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atyfb: Properly save PCI state before changing PCI PM level
[deliverable/linux.git] / drivers / serial / 8250_pci.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 13 */
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
1da177e4
LT		 17#include <linux/string.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
21#include <linux/tty.h>
22#include <linux/serial_core.h>
23#include <linux/8250_pci.h>
24#include <linux/bitops.h>
25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
29#include "8250.h"
30
31#undef SERIAL_DEBUG_PCI
32
1da177e4
LT		 33/*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
05caac58 47 struct uart_port *, int);
1da177e4
LT		 48 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
70db3d91 54 struct pci_dev *dev;
1da177e4
LT		 55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59};
60
61static void moan_device(const char *str, struct pci_dev *dev)
62{
63 printk(KERN_WARNING "%s: %s\n"
64 KERN_WARNING "Please send the output of lspci -vv, this\n"
65 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
66 KERN_WARNING "manufacturer and name of serial board or\n"
67 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
68 pci_name(dev), str, dev->vendor, dev->device,
69 dev->subsystem_vendor, dev->subsystem_device);
70}
71
72static int
70db3d91 73setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 74 int bar, int offset, int regshift)
75{
70db3d91 76 struct pci_dev *dev = priv->dev;
1da177e4
LT		 77 unsigned long base, len;
78
79 if (bar >= PCI_NUM_BAR_RESOURCES)
80 return -EINVAL;
81
72ce9a83
RK		 82 base = pci_resource_start(dev, bar);
83
1da177e4 84 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 85 len = pci_resource_len(dev, bar);
86
87 if (!priv->remapped_bar[bar])
6f441fe9 88 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 89 if (!priv->remapped_bar[bar])
90 return -ENOMEM;
91
92 port->iotype = UPIO_MEM;
72ce9a83 93 port->iobase = 0;
1da177e4
LT		 94 port->mapbase = base + offset;
95 port->membase = priv->remapped_bar[bar] + offset;
96 port->regshift = regshift;
97 } else {
1da177e4 98 port->iotype = UPIO_PORT;
72ce9a83
RK		 99 port->iobase = base + offset;
100 port->mapbase = 0;
101 port->membase = NULL;
102 port->regshift = 0;
1da177e4
LT		 103 }
104 return 0;
105}
106
02c9b5cf
KJ		 107/*
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 */
110static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 111 const struct pciserial_board *board,
02c9b5cf
KJ		 112 struct uart_port *port, int idx)
113{
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
116
117 if (idx < 2) {
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
120 bar += 1;
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
123 bar += 2;
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
126 bar += 3;
127 offset += ((idx - 6) * board->uart_offset);
128 }
129
130 return setup_port(priv, port, bar, offset, board->reg_shift);
131}
132
1da177e4
LT		 133/*
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
136 */
137static int
975a1a7d 138afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 139 struct uart_port *port, int idx)
140{
141 unsigned int bar, offset = board->first_offset;
5756ee99 142
1da177e4
LT		 143 bar = FL_GET_BASE(board->flags);
144 if (idx < 4)
145 bar += idx;
146 else {
147 bar = 4;
148 offset += (idx - 4) * board->uart_offset;
149 }
150
70db3d91 151 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 152}
153
154/*
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
160 */
61a116ef 161static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 162{
163 int rc = 0;
164
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
170 rc = 3;
171 break;
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
173 rc = 2;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 rc = 4;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 180 rc = 1;
181 break;
182 }
183
184 return rc;
185}
186
187/*
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
190 */
191static int
975a1a7d
RK		 192pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
194 struct uart_port *port, int idx)
1da177e4
LT		 195{
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
70db3d91 199 switch (priv->dev->subsystem_device) {
1da177e4
LT		 200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
70db3d91 216 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 217}
218
219/*
220 * Added for EKF Intel i960 serial boards
221 */
61a116ef 222static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 223{
224 unsigned long oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
5756ee99
AC		 230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 232 printk(KERN_DEBUG "Local i960 firmware missing");
233 return -ENODEV;
234 }
235 return 0;
236}
237
238/*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
61a116ef 244static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 245{
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
add7b58e 255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 257 irq_config = 0x43;
5756ee99 258
1da177e4 259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 261 /*
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
267 * deep FIFOs
268 */
269 irq_config = 0x5b;
1da177e4
LT		 270 /*
271 * enable/disable interrupts
272 */
6f441fe9 273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285}
286
287static void __devexit pci_plx9050_exit(struct pci_dev *dev)
288{
289 u8 __iomem *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
6f441fe9 297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307}
308
309/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
310static int
975a1a7d 311sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 312 struct uart_port *port, int idx)
313{
314 unsigned int bar, offset = board->first_offset;
315
316 bar = 0;
317
318 if (idx < 4) {
319 /* first four channels map to 0, 0x100, 0x200, 0x300 */
320 offset += idx * board->uart_offset;
321 } else if (idx < 8) {
322 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
323 offset += idx * board->uart_offset + 0xC00;
324 } else /* we have only 8 ports on PMC-OCTALPRO */
325 return 1;
326
70db3d91 327 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 328}
329
330/*
331* This does initialization for PMC OCTALPRO cards:
332* maps the device memory, resets the UARTs (needed, bc
333* if the module is removed and inserted again, the card
334* is in the sleep mode) and enables global interrupt.
335*/
336
337/* global control register offset for SBS PMC-OctalPro */
338#define OCT_REG_CR_OFF 0x500
339
61a116ef 340static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 341{
342 u8 __iomem *p;
343
6f441fe9
AC		 344 p = ioremap_nocache(pci_resource_start(dev, 0),
345 pci_resource_len(dev, 0));
1da177e4
LT		 346
347 if (p == NULL)
348 return -ENOMEM;
349 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 350 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 351 udelay(50);
5756ee99 352 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 353
354 /* Set bit-2 (INTENABLE) of Control Register */
355 writeb(0x4, p + OCT_REG_CR_OFF);
356 iounmap(p);
357
358 return 0;
359}
360
361/*
362 * Disables the global interrupt of PMC-OctalPro
363 */
364
365static void __devexit sbs_exit(struct pci_dev *dev)
366{
367 u8 __iomem *p;
368
6f441fe9
AC		 369 p = ioremap_nocache(pci_resource_start(dev, 0),
370 pci_resource_len(dev, 0));
5756ee99
AC		 371 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
372 if (p != NULL)
1da177e4 373 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 374 iounmap(p);
375}
376
377/*
378 * SIIG serial cards have an PCI interface chip which also controls
379 * the UART clocking frequency. Each UART can be clocked independently
380 * (except cards equiped with 4 UARTs) and initial clocking settings
381 * are stored in the EEPROM chip. It can cause problems because this
382 * version of serial driver doesn't support differently clocked UART's
383 * on single PCI card. To prevent this, initialization functions set
384 * high frequency clocking for all UART's on given card. It is safe (I
385 * hope) because it doesn't touch EEPROM settings to prevent conflicts
386 * with other OSes (like M$ DOS).
387 *
388 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 389 *
1da177e4
LT		 390 * There is two family of SIIG serial cards with different PCI
391 * interface chip and different configuration methods:
392 * - 10x cards have control registers in IO and/or memory space;
393 * - 20x cards have control registers in standard PCI configuration space.
394 *
67d74b87
RK		 395 * Note: all 10x cards have PCI device ids 0x10..
396 * all 20x cards have PCI device ids 0x20..
397 *
fbc0dc0d
AP		 398 * There are also Quartet Serial cards which use Oxford Semiconductor
399 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
400 *
1da177e4
LT		 401 * Note: some SIIG cards are probed by the parport_serial object.
402 */
403
404#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
405#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
406
407static int pci_siig10x_init(struct pci_dev *dev)
408{
409 u16 data;
410 void __iomem *p;
411
412 switch (dev->device & 0xfff8) {
413 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
414 data = 0xffdf;
415 break;
416 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
417 data = 0xf7ff;
418 break;
419 default: /* 1S1P, 4S */
420 data = 0xfffb;
421 break;
422 }
423
6f441fe9 424 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 425 if (p == NULL)
426 return -ENOMEM;
427
428 writew(readw(p + 0x28) & data, p + 0x28);
429 readw(p + 0x28);
430 iounmap(p);
431 return 0;
432}
433
434#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
435#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
436
437static int pci_siig20x_init(struct pci_dev *dev)
438{
439 u8 data;
440
441 /* Change clock frequency for the first UART. */
442 pci_read_config_byte(dev, 0x6f, &data);
443 pci_write_config_byte(dev, 0x6f, data & 0xef);
444
445 /* If this card has 2 UART, we have to do the same with second UART. */
446 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
447 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
448 pci_read_config_byte(dev, 0x73, &data);
449 pci_write_config_byte(dev, 0x73, data & 0xef);
450 }
451 return 0;
452}
453
67d74b87
RK		 454static int pci_siig_init(struct pci_dev *dev)
455{
456 unsigned int type = dev->device & 0xff00;
457
458 if (type == 0x1000)
459 return pci_siig10x_init(dev);
460 else if (type == 0x2000)
461 return pci_siig20x_init(dev);
462
463 moan_device("Unknown SIIG card", dev);
464 return -ENODEV;
465}
466
3ec9c594 467static int pci_siig_setup(struct serial_private *priv,
975a1a7d 468 const struct pciserial_board *board,
3ec9c594
AP		 469 struct uart_port *port, int idx)
470{
471 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
472
473 if (idx > 3) {
474 bar = 4;
475 offset = (idx - 4) * 8;
476 }
477
478 return setup_port(priv, port, bar, offset, 0);
479}
480
1da177e4
LT		 481/*
482 * Timedia has an explosion of boards, and to avoid the PCI table from
483 * growing *huge*, we use this function to collapse some 70 entries
484 * in the PCI table into one, for sanity's and compactness's sake.
485 */
e9422e09 486static const unsigned short timedia_single_port[] = {
1da177e4
LT		 487 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
488};
489
e9422e09 490static const unsigned short timedia_dual_port[] = {
1da177e4 491 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 492 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
493 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 494 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
495 0xD079, 0
496};
497
e9422e09 498static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 499 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
500 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 501 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
502 0xB157, 0
503};
504
e9422e09 505static const unsigned short timedia_eight_port[] = {
5756ee99 506 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 507 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
508};
509
cb3592be 510static const struct timedia_struct {
1da177e4 511 int num;
e9422e09 512 const unsigned short *ids;
1da177e4
LT		 513} timedia_data[] = {
514 { 1, timedia_single_port },
515 { 2, timedia_dual_port },
516 { 4, timedia_quad_port },
e9422e09 517 { 8, timedia_eight_port }
1da177e4
LT		 518};
519
61a116ef 520static int pci_timedia_init(struct pci_dev *dev)
1da177e4 521{
e9422e09 522 const unsigned short *ids;
1da177e4
LT		 523 int i, j;
524
e9422e09 525 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 526 ids = timedia_data[i].ids;
527 for (j = 0; ids[j]; j++)
528 if (dev->subsystem_device == ids[j])
529 return timedia_data[i].num;
530 }
531 return 0;
532}
533
534/*
535 * Timedia/SUNIX uses a mixture of BARs and offsets
536 * Ugh, this is ugly as all hell --- TYT
537 */
538static int
975a1a7d
RK		 539pci_timedia_setup(struct serial_private *priv,
540 const struct pciserial_board *board,
1da177e4
LT		 541 struct uart_port *port, int idx)
542{
543 unsigned int bar = 0, offset = board->first_offset;
544
545 switch (idx) {
546 case 0:
547 bar = 0;
548 break;
549 case 1:
550 offset = board->uart_offset;
551 bar = 0;
552 break;
553 case 2:
554 bar = 1;
555 break;
556 case 3:
557 offset = board->uart_offset;
c2cd6d3c 558 /* FALLTHROUGH */
1da177e4
LT		 559 case 4: /* BAR 2 */
560 case 5: /* BAR 3 */
561 case 6: /* BAR 4 */
562 case 7: /* BAR 5 */
563 bar = idx - 2;
564 }
565
70db3d91 566 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 567}
568
569/*
570 * Some Titan cards are also a little weird
571 */
572static int
70db3d91 573titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 574 const struct pciserial_board *board,
1da177e4
LT		 575 struct uart_port *port, int idx)
576{
577 unsigned int bar, offset = board->first_offset;
578
579 switch (idx) {
580 case 0:
581 bar = 1;
582 break;
583 case 1:
584 bar = 2;
585 break;
586 default:
587 bar = 4;
588 offset = (idx - 2) * board->uart_offset;
589 }
590
70db3d91 591 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 592}
593
61a116ef 594static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 595{
596 msleep(100);
597 return 0;
598}
599
61a116ef 600static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 601{
602 /* subdevice 0x00PS means <P> parallel, <S> serial */
603 unsigned int num_serial = dev->subsystem_device & 0xf;
604
25cf9bc1
JS		 605 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
606 dev->subsystem_device == 0x0299)
607 return 0;
608
1da177e4
LT		 609 if (num_serial == 0)
610 return -ENODEV;
611 return num_serial;
612}
613
84f8c6fc
NV		 614/*
615 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
616 *
617 * These chips are available with optionally one parallel port and up to
618 * two serial ports. Unfortunately they all have the same product id.
619 *
620 * Basic configuration is done over a region of 32 I/O ports. The base
621 * ioport is called INTA or INTC, depending on docs/other drivers.
622 *
623 * The region of the 32 I/O ports is configured in POSIO0R...
624 */
625
626/* registers */
627#define ITE_887x_MISCR 0x9c
628#define ITE_887x_INTCBAR 0x78
629#define ITE_887x_UARTBAR 0x7c
630#define ITE_887x_PS0BAR 0x10
631#define ITE_887x_POSIO0 0x60
632
633/* I/O space size */
634#define ITE_887x_IOSIZE 32
635/* I/O space size (bits 26-24; 8 bytes = 011b) */
636#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
637/* I/O space size (bits 26-24; 32 bytes = 101b) */
638#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
639/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
640#define ITE_887x_POSIO_SPEED (3 << 29)
641/* enable IO_Space bit */
642#define ITE_887x_POSIO_ENABLE (1 << 31)
643
f79abb82 644static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 645{
646 /* inta_addr are the configuration addresses of the ITE */
647 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
648 0x200, 0x280, 0 };
649 int ret, i, type;
650 struct resource *iobase = NULL;
651 u32 miscr, uartbar, ioport;
652
653 /* search for the base-ioport */
654 i = 0;
655 while (inta_addr[i] && iobase == NULL) {
656 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
657 "ite887x");
658 if (iobase != NULL) {
659 /* write POSIO0R - speed | size | ioport */
660 pci_write_config_dword(dev, ITE_887x_POSIO0,
661 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
662 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
663 /* write INTCBAR - ioport */
5756ee99
AC		 664 pci_write_config_dword(dev, ITE_887x_INTCBAR,
665 inta_addr[i]);
84f8c6fc
NV		 666 ret = inb(inta_addr[i]);
667 if (ret != 0xff) {
668 /* ioport connected */
669 break;
670 }
671 release_region(iobase->start, ITE_887x_IOSIZE);
672 iobase = NULL;
673 }
674 i++;
675 }
676
677 if (!inta_addr[i]) {
678 printk(KERN_ERR "ite887x: could not find iobase\n");
679 return -ENODEV;
680 }
681
682 /* start of undocumented type checking (see parport_pc.c) */
683 type = inb(iobase->start + 0x18) & 0x0f;
684
685 switch (type) {
686 case 0x2: /* ITE8871 (1P) */
687 case 0xa: /* ITE8875 (1P) */
688 ret = 0;
689 break;
690 case 0xe: /* ITE8872 (2S1P) */
691 ret = 2;
692 break;
693 case 0x6: /* ITE8873 (1S) */
694 ret = 1;
695 break;
696 case 0x8: /* ITE8874 (2S) */
697 ret = 2;
698 break;
699 default:
700 moan_device("Unknown ITE887x", dev);
701 ret = -ENODEV;
702 }
703
704 /* configure all serial ports */
705 for (i = 0; i < ret; i++) {
706 /* read the I/O port from the device */
707 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
708 &ioport);
709 ioport &= 0x0000FF00; /* the actual base address */
710 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
711 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
712 ITE_887x_POSIO_IOSIZE_8 | ioport);
713
714 /* write the ioport to the UARTBAR */
715 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
716 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
717 uartbar |= (ioport << (16 * i)); /* set the ioport */
718 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
719
720 /* get current config */
721 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
722 /* disable interrupts (UARTx_Routing[3:0]) */
723 miscr &= ~(0xf << (12 - 4 * i));
724 /* activate the UART (UARTx_En) */
725 miscr |= 1 << (23 - i);
726 /* write new config with activated UART */
727 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
728 }
729
730 if (ret <= 0) {
731 /* the device has no UARTs if we get here */
732 release_region(iobase->start, ITE_887x_IOSIZE);
733 }
734
735 return ret;
736}
737
738static void __devexit pci_ite887x_exit(struct pci_dev *dev)
739{
740 u32 ioport;
741 /* the ioport is bit 0-15 in POSIO0R */
742 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
743 ioport &= 0xffff;
744 release_region(ioport, ITE_887x_IOSIZE);
745}
746
9f2a036a
RK		 747/*
748 * Oxford Semiconductor Inc.
749 * Check that device is part of the Tornado range of devices, then determine
750 * the number of ports available on the device.
751 */
752static int pci_oxsemi_tornado_init(struct pci_dev *dev)
753{
754 u8 __iomem *p;
755 unsigned long deviceID;
756 unsigned int number_uarts = 0;
757
758 /* OxSemi Tornado devices are all 0xCxxx */
759 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
760 (dev->device & 0xF000) != 0xC000)
761 return 0;
762
763 p = pci_iomap(dev, 0, 5);
764 if (p == NULL)
765 return -ENOMEM;
766
767 deviceID = ioread32(p);
768 /* Tornado device */
769 if (deviceID == 0x07000200) {
770 number_uarts = ioread8(p + 4);
771 printk(KERN_DEBUG
772 "%d ports detected on Oxford PCI Express device\n",
773 number_uarts);
774 }
775 pci_iounmap(dev, p);
776 return number_uarts;
777}
778
1da177e4 779static int
975a1a7d
RK		 780pci_default_setup(struct serial_private *priv,
781 const struct pciserial_board *board,
1da177e4
LT		 782 struct uart_port *port, int idx)
783{
784 unsigned int bar, offset = board->first_offset, maxnr;
785
786 bar = FL_GET_BASE(board->flags);
787 if (board->flags & FL_BASE_BARS)
788 bar += idx;
789 else
790 offset += idx * board->uart_offset;
791
2427ddd8
GKH		 792 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
793 (board->reg_shift + 3);
1da177e4
LT		 794
795 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
796 return 1;
5756ee99 797
70db3d91 798 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 799}
800
801/* This should be in linux/pci_ids.h */
802#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
803#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
804#define PCI_DEVICE_ID_OCTPRO 0x0001
805#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
806#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
807#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
808#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
78d70d48
MB		 809#define PCI_VENDOR_ID_ADVANTECH 0x13fe
810#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1da177e4 811
b76c5a07
CB		 812/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
813#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
814
1da177e4
LT		 815/*
816 * Master list of serial port init/setup/exit quirks.
817 * This does not describe the general nature of the port.
818 * (ie, baud base, number and location of ports, etc)
819 *
820 * This list is ordered alphabetically by vendor then device.
821 * Specific entries must come before more generic entries.
822 */
7a63ce5a 823static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 824 /*
825 * ADDI-DATA GmbH communication cards <info@addi-data.com>
826 */
827 {
828 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
829 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
830 .subvendor = PCI_ANY_ID,
831 .subdevice = PCI_ANY_ID,
832 .setup = addidata_apci7800_setup,
833 },
1da177e4 834 /*
61a116ef 835 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 836 * It is not clear whether this applies to all products.
837 */
838 {
839 .vendor = PCI_VENDOR_ID_AFAVLAB,
840 .device = PCI_ANY_ID,
841 .subvendor = PCI_ANY_ID,
842 .subdevice = PCI_ANY_ID,
843 .setup = afavlab_setup,
844 },
845 /*
846 * HP Diva
847 */
848 {
849 .vendor = PCI_VENDOR_ID_HP,
850 .device = PCI_DEVICE_ID_HP_DIVA,
851 .subvendor = PCI_ANY_ID,
852 .subdevice = PCI_ANY_ID,
853 .init = pci_hp_diva_init,
854 .setup = pci_hp_diva_setup,
855 },
856 /*
857 * Intel
858 */
859 {
860 .vendor = PCI_VENDOR_ID_INTEL,
861 .device = PCI_DEVICE_ID_INTEL_80960_RP,
862 .subvendor = 0xe4bf,
863 .subdevice = PCI_ANY_ID,
864 .init = pci_inteli960ni_init,
865 .setup = pci_default_setup,
866 },
84f8c6fc
NV		 867 /*
868 * ITE
869 */
870 {
871 .vendor = PCI_VENDOR_ID_ITE,
872 .device = PCI_DEVICE_ID_ITE_8872,
873 .subvendor = PCI_ANY_ID,
874 .subdevice = PCI_ANY_ID,
875 .init = pci_ite887x_init,
876 .setup = pci_default_setup,
877 .exit = __devexit_p(pci_ite887x_exit),
878 },
1da177e4
LT		 879 /*
880 * Panacom
881 */
882 {
883 .vendor = PCI_VENDOR_ID_PANACOM,
884 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
885 .subvendor = PCI_ANY_ID,
886 .subdevice = PCI_ANY_ID,
887 .init = pci_plx9050_init,
888 .setup = pci_default_setup,
889 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 890 },
1da177e4
LT		 891 {
892 .vendor = PCI_VENDOR_ID_PANACOM,
893 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
894 .subvendor = PCI_ANY_ID,
895 .subdevice = PCI_ANY_ID,
896 .init = pci_plx9050_init,
897 .setup = pci_default_setup,
898 .exit = __devexit_p(pci_plx9050_exit),
899 },
900 /*
901 * PLX
902 */
48212008
TH		 903 {
904 .vendor = PCI_VENDOR_ID_PLX,
905 .device = PCI_DEVICE_ID_PLX_9030,
906 .subvendor = PCI_SUBVENDOR_ID_PERLE,
907 .subdevice = PCI_ANY_ID,
908 .setup = pci_default_setup,
909 },
add7b58e
BH		 910 {
911 .vendor = PCI_VENDOR_ID_PLX,
912 .device = PCI_DEVICE_ID_PLX_9050,
913 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
914 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
915 .init = pci_plx9050_init,
916 .setup = pci_default_setup,
917 .exit = __devexit_p(pci_plx9050_exit),
918 },
1da177e4
LT		 919 {
920 .vendor = PCI_VENDOR_ID_PLX,
921 .device = PCI_DEVICE_ID_PLX_9050,
922 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
923 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
924 .init = pci_plx9050_init,
925 .setup = pci_default_setup,
926 .exit = __devexit_p(pci_plx9050_exit),
927 },
b76c5a07
CB		 928 {
929 .vendor = PCI_VENDOR_ID_PLX,
930 .device = PCI_DEVICE_ID_PLX_9050,
931 .subvendor = PCI_VENDOR_ID_PLX,
932 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
933 .init = pci_plx9050_init,
934 .setup = pci_default_setup,
935 .exit = __devexit_p(pci_plx9050_exit),
936 },
1da177e4
LT		 937 {
938 .vendor = PCI_VENDOR_ID_PLX,
939 .device = PCI_DEVICE_ID_PLX_ROMULUS,
940 .subvendor = PCI_VENDOR_ID_PLX,
941 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
942 .init = pci_plx9050_init,
943 .setup = pci_default_setup,
944 .exit = __devexit_p(pci_plx9050_exit),
945 },
946 /*
947 * SBS Technologies, Inc., PMC-OCTALPRO 232
948 */
949 {
950 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
951 .device = PCI_DEVICE_ID_OCTPRO,
952 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
953 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
954 .init = sbs_init,
955 .setup = sbs_setup,
956 .exit = __devexit_p(sbs_exit),
957 },
958 /*
959 * SBS Technologies, Inc., PMC-OCTALPRO 422
960 */
961 {
962 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
963 .device = PCI_DEVICE_ID_OCTPRO,
964 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
965 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
966 .init = sbs_init,
967 .setup = sbs_setup,
968 .exit = __devexit_p(sbs_exit),
969 },
970 /*
971 * SBS Technologies, Inc., P-Octal 232
972 */
973 {
974 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
975 .device = PCI_DEVICE_ID_OCTPRO,
976 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
977 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
978 .init = sbs_init,
979 .setup = sbs_setup,
980 .exit = __devexit_p(sbs_exit),
981 },
982 /*
983 * SBS Technologies, Inc., P-Octal 422
984 */
985 {
986 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
987 .device = PCI_DEVICE_ID_OCTPRO,
988 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
989 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
990 .init = sbs_init,
991 .setup = sbs_setup,
992 .exit = __devexit_p(sbs_exit),
993 },
1da177e4 994 /*
61a116ef 995 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 996 */
997 {
998 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 999 .device = PCI_ANY_ID,
1da177e4
LT		 1000 .subvendor = PCI_ANY_ID,
1001 .subdevice = PCI_ANY_ID,
67d74b87 1002 .init = pci_siig_init,
3ec9c594 1003 .setup = pci_siig_setup,
1da177e4
LT		 1004 },
1005 /*
1006 * Titan cards
1007 */
1008 {
1009 .vendor = PCI_VENDOR_ID_TITAN,
1010 .device = PCI_DEVICE_ID_TITAN_400L,
1011 .subvendor = PCI_ANY_ID,
1012 .subdevice = PCI_ANY_ID,
1013 .setup = titan_400l_800l_setup,
1014 },
1015 {
1016 .vendor = PCI_VENDOR_ID_TITAN,
1017 .device = PCI_DEVICE_ID_TITAN_800L,
1018 .subvendor = PCI_ANY_ID,
1019 .subdevice = PCI_ANY_ID,
1020 .setup = titan_400l_800l_setup,
1021 },
1022 /*
1023 * Timedia cards
1024 */
1025 {
1026 .vendor = PCI_VENDOR_ID_TIMEDIA,
1027 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1028 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1029 .subdevice = PCI_ANY_ID,
1030 .init = pci_timedia_init,
1031 .setup = pci_timedia_setup,
1032 },
1033 {
1034 .vendor = PCI_VENDOR_ID_TIMEDIA,
1035 .device = PCI_ANY_ID,
1036 .subvendor = PCI_ANY_ID,
1037 .subdevice = PCI_ANY_ID,
1038 .setup = pci_timedia_setup,
1039 },
1040 /*
1041 * Xircom cards
1042 */
1043 {
1044 .vendor = PCI_VENDOR_ID_XIRCOM,
1045 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1046 .subvendor = PCI_ANY_ID,
1047 .subdevice = PCI_ANY_ID,
1048 .init = pci_xircom_init,
1049 .setup = pci_default_setup,
1050 },
1051 /*
61a116ef 1052 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1053 */
1054 {
1055 .vendor = PCI_VENDOR_ID_NETMOS,
1056 .device = PCI_ANY_ID,
1057 .subvendor = PCI_ANY_ID,
1058 .subdevice = PCI_ANY_ID,
1059 .init = pci_netmos_init,
1060 .setup = pci_default_setup,
1061 },
9f2a036a
RK		 1062 /*
1063 * For Oxford Semiconductor and Mainpine
1064 */
1065 {
1066 .vendor = PCI_VENDOR_ID_OXSEMI,
1067 .device = PCI_ANY_ID,
1068 .subvendor = PCI_ANY_ID,
1069 .subdevice = PCI_ANY_ID,
1070 .init = pci_oxsemi_tornado_init,
1071 .setup = pci_default_setup,
1072 },
1073 {
1074 .vendor = PCI_VENDOR_ID_MAINPINE,
1075 .device = PCI_ANY_ID,
1076 .subvendor = PCI_ANY_ID,
1077 .subdevice = PCI_ANY_ID,
1078 .init = pci_oxsemi_tornado_init,
1079 .setup = pci_default_setup,
1080 },
1da177e4
LT		 1081 /*
1082 * Default "match everything" terminator entry
1083 */
1084 {
1085 .vendor = PCI_ANY_ID,
1086 .device = PCI_ANY_ID,
1087 .subvendor = PCI_ANY_ID,
1088 .subdevice = PCI_ANY_ID,
1089 .setup = pci_default_setup,
1090 }
1091};
1092
1093static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1094{
1095 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1096}
1097
1098static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1099{
1100 struct pci_serial_quirk *quirk;
1101
1102 for (quirk = pci_serial_quirks; ; quirk++)
1103 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1104 quirk_id_matches(quirk->device, dev->device) &&
1105 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1106 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1107 break;
1da177e4
LT		 1108 return quirk;
1109}
1110
dd68e88c 1111static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1112 const struct pciserial_board *board)
1da177e4
LT		 1113{
1114 if (board->flags & FL_NOIRQ)
1115 return 0;
1116 else
1117 return dev->irq;
1118}
1119
1120/*
1121 * This is the configuration table for all of the PCI serial boards
1122 * which we support. It is directly indexed by the pci_board_num_t enum
1123 * value, which is encoded in the pci_device_id PCI probe table's
1124 * driver_data member.
1125 *
1126 * The makeup of these names are:
26e92861 1127 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1128 *
26e92861
GH		 1129 * bn = PCI BAR number
1130 * bt = Index using PCI BARs
1131 * n = number of serial ports
1132 * baud = baud rate
1133 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1134 *
26e92861 1135 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1136 *
1da177e4
LT		 1137 * Please note: in theory if n = 1, _bt infix should make no difference.
1138 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1139 */
1140enum pci_board_num_t {
1141 pbn_default = 0,
1142
1143 pbn_b0_1_115200,
1144 pbn_b0_2_115200,
1145 pbn_b0_4_115200,
1146 pbn_b0_5_115200,
bf0df636 1147 pbn_b0_8_115200,
1da177e4
LT		 1148
1149 pbn_b0_1_921600,
1150 pbn_b0_2_921600,
1151 pbn_b0_4_921600,
1152
db1de159
DR		 1153 pbn_b0_2_1130000,
1154
fbc0dc0d
AP		 1155 pbn_b0_4_1152000,
1156
26e92861
GH		 1157 pbn_b0_2_1843200,
1158 pbn_b0_4_1843200,
1159
1160 pbn_b0_2_1843200_200,
1161 pbn_b0_4_1843200_200,
1162 pbn_b0_8_1843200_200,
1163
7106b4e3
LH		 1164 pbn_b0_1_4000000,
1165
1da177e4
LT		 1166 pbn_b0_bt_1_115200,
1167 pbn_b0_bt_2_115200,
1168 pbn_b0_bt_8_115200,
1169
1170 pbn_b0_bt_1_460800,
1171 pbn_b0_bt_2_460800,
1172 pbn_b0_bt_4_460800,
1173
1174 pbn_b0_bt_1_921600,
1175 pbn_b0_bt_2_921600,
1176 pbn_b0_bt_4_921600,
1177 pbn_b0_bt_8_921600,
1178
1179 pbn_b1_1_115200,
1180 pbn_b1_2_115200,
1181 pbn_b1_4_115200,
1182 pbn_b1_8_115200,
1183
1184 pbn_b1_1_921600,
1185 pbn_b1_2_921600,
1186 pbn_b1_4_921600,
1187 pbn_b1_8_921600,
1188
26e92861
GH		 1189 pbn_b1_2_1250000,
1190
84f8c6fc 1191 pbn_b1_bt_1_115200,
1da177e4
LT		 1192 pbn_b1_bt_2_921600,
1193
1194 pbn_b1_1_1382400,
1195 pbn_b1_2_1382400,
1196 pbn_b1_4_1382400,
1197 pbn_b1_8_1382400,
1198
1199 pbn_b2_1_115200,
737c1756 1200 pbn_b2_2_115200,
a9cccd34 1201 pbn_b2_4_115200,
1da177e4
LT		 1202 pbn_b2_8_115200,
1203
1204 pbn_b2_1_460800,
1205 pbn_b2_4_460800,
1206 pbn_b2_8_460800,
1207 pbn_b2_16_460800,
1208
1209 pbn_b2_1_921600,
1210 pbn_b2_4_921600,
1211 pbn_b2_8_921600,
1212
1213 pbn_b2_bt_1_115200,
1214 pbn_b2_bt_2_115200,
1215 pbn_b2_bt_4_115200,
1216
1217 pbn_b2_bt_2_921600,
1218 pbn_b2_bt_4_921600,
1219
d9004eb4 1220 pbn_b3_2_115200,
1da177e4
LT		 1221 pbn_b3_4_115200,
1222 pbn_b3_8_115200,
1223
1224 /*
1225 * Board-specific versions.
1226 */
1227 pbn_panacom,
1228 pbn_panacom2,
1229 pbn_panacom4,
add7b58e 1230 pbn_exsys_4055,
1da177e4
LT		 1231 pbn_plx_romulus,
1232 pbn_oxsemi,
7106b4e3
LH		 1233 pbn_oxsemi_1_4000000,
1234 pbn_oxsemi_2_4000000,
1235 pbn_oxsemi_4_4000000,
1236 pbn_oxsemi_8_4000000,
1da177e4
LT		 1237 pbn_intel_i960,
1238 pbn_sgi_ioc3,
1da177e4
LT		 1239 pbn_computone_4,
1240 pbn_computone_6,
1241 pbn_computone_8,
1242 pbn_sbsxrsio,
1243 pbn_exar_XR17C152,
1244 pbn_exar_XR17C154,
1245 pbn_exar_XR17C158,
aa798505 1246 pbn_pasemi_1682M,
1da177e4
LT		 1247};
1248
1249/*
1250 * uart_offset - the space between channels
1251 * reg_shift - describes how the UART registers are mapped
1252 * to PCI memory by the card.
1253 * For example IER register on SBS, Inc. PMC-OctPro is located at
1254 * offset 0x10 from the UART base, while UART_IER is defined as 1
1255 * in include/linux/serial_reg.h,
1256 * see first lines of serial_in() and serial_out() in 8250.c
1257*/
1258
1c7c1fe5 1259static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1260 [pbn_default] = {
1261 .flags = FL_BASE0,
1262 .num_ports = 1,
1263 .base_baud = 115200,
1264 .uart_offset = 8,
1265 },
1266 [pbn_b0_1_115200] = {
1267 .flags = FL_BASE0,
1268 .num_ports = 1,
1269 .base_baud = 115200,
1270 .uart_offset = 8,
1271 },
1272 [pbn_b0_2_115200] = {
1273 .flags = FL_BASE0,
1274 .num_ports = 2,
1275 .base_baud = 115200,
1276 .uart_offset = 8,
1277 },
1278 [pbn_b0_4_115200] = {
1279 .flags = FL_BASE0,
1280 .num_ports = 4,
1281 .base_baud = 115200,
1282 .uart_offset = 8,
1283 },
1284 [pbn_b0_5_115200] = {
1285 .flags = FL_BASE0,
1286 .num_ports = 5,
1287 .base_baud = 115200,
1288 .uart_offset = 8,
1289 },
bf0df636
AC		 1290 [pbn_b0_8_115200] = {
1291 .flags = FL_BASE0,
1292 .num_ports = 8,
1293 .base_baud = 115200,
1294 .uart_offset = 8,
1295 },
1da177e4
LT		 1296 [pbn_b0_1_921600] = {
1297 .flags = FL_BASE0,
1298 .num_ports = 1,
1299 .base_baud = 921600,
1300 .uart_offset = 8,
1301 },
1302 [pbn_b0_2_921600] = {
1303 .flags = FL_BASE0,
1304 .num_ports = 2,
1305 .base_baud = 921600,
1306 .uart_offset = 8,
1307 },
1308 [pbn_b0_4_921600] = {
1309 .flags = FL_BASE0,
1310 .num_ports = 4,
1311 .base_baud = 921600,
1312 .uart_offset = 8,
1313 },
db1de159
DR		 1314
1315 [pbn_b0_2_1130000] = {
1316 .flags = FL_BASE0,
1317 .num_ports = 2,
1318 .base_baud = 1130000,
1319 .uart_offset = 8,
1320 },
1321
fbc0dc0d
AP		 1322 [pbn_b0_4_1152000] = {
1323 .flags = FL_BASE0,
1324 .num_ports = 4,
1325 .base_baud = 1152000,
1326 .uart_offset = 8,
1327 },
1da177e4 1328
26e92861
GH		 1329 [pbn_b0_2_1843200] = {
1330 .flags = FL_BASE0,
1331 .num_ports = 2,
1332 .base_baud = 1843200,
1333 .uart_offset = 8,
1334 },
1335 [pbn_b0_4_1843200] = {
1336 .flags = FL_BASE0,
1337 .num_ports = 4,
1338 .base_baud = 1843200,
1339 .uart_offset = 8,
1340 },
1341
1342 [pbn_b0_2_1843200_200] = {
1343 .flags = FL_BASE0,
1344 .num_ports = 2,
1345 .base_baud = 1843200,
1346 .uart_offset = 0x200,
1347 },
1348 [pbn_b0_4_1843200_200] = {
1349 .flags = FL_BASE0,
1350 .num_ports = 4,
1351 .base_baud = 1843200,
1352 .uart_offset = 0x200,
1353 },
1354 [pbn_b0_8_1843200_200] = {
1355 .flags = FL_BASE0,
1356 .num_ports = 8,
1357 .base_baud = 1843200,
1358 .uart_offset = 0x200,
1359 },
7106b4e3
LH		 1360 [pbn_b0_1_4000000] = {
1361 .flags = FL_BASE0,
1362 .num_ports = 1,
1363 .base_baud = 4000000,
1364 .uart_offset = 8,
1365 },
26e92861 1366
1da177e4
LT		 1367 [pbn_b0_bt_1_115200] = {
1368 .flags = FL_BASE0|FL_BASE_BARS,
1369 .num_ports = 1,
1370 .base_baud = 115200,
1371 .uart_offset = 8,
1372 },
1373 [pbn_b0_bt_2_115200] = {
1374 .flags = FL_BASE0|FL_BASE_BARS,
1375 .num_ports = 2,
1376 .base_baud = 115200,
1377 .uart_offset = 8,
1378 },
1379 [pbn_b0_bt_8_115200] = {
1380 .flags = FL_BASE0|FL_BASE_BARS,
1381 .num_ports = 8,
1382 .base_baud = 115200,
1383 .uart_offset = 8,
1384 },
1385
1386 [pbn_b0_bt_1_460800] = {
1387 .flags = FL_BASE0|FL_BASE_BARS,
1388 .num_ports = 1,
1389 .base_baud = 460800,
1390 .uart_offset = 8,
1391 },
1392 [pbn_b0_bt_2_460800] = {
1393 .flags = FL_BASE0|FL_BASE_BARS,
1394 .num_ports = 2,
1395 .base_baud = 460800,
1396 .uart_offset = 8,
1397 },
1398 [pbn_b0_bt_4_460800] = {
1399 .flags = FL_BASE0|FL_BASE_BARS,
1400 .num_ports = 4,
1401 .base_baud = 460800,
1402 .uart_offset = 8,
1403 },
1404
1405 [pbn_b0_bt_1_921600] = {
1406 .flags = FL_BASE0|FL_BASE_BARS,
1407 .num_ports = 1,
1408 .base_baud = 921600,
1409 .uart_offset = 8,
1410 },
1411 [pbn_b0_bt_2_921600] = {
1412 .flags = FL_BASE0|FL_BASE_BARS,
1413 .num_ports = 2,
1414 .base_baud = 921600,
1415 .uart_offset = 8,
1416 },
1417 [pbn_b0_bt_4_921600] = {
1418 .flags = FL_BASE0|FL_BASE_BARS,
1419 .num_ports = 4,
1420 .base_baud = 921600,
1421 .uart_offset = 8,
1422 },
1423 [pbn_b0_bt_8_921600] = {
1424 .flags = FL_BASE0|FL_BASE_BARS,
1425 .num_ports = 8,
1426 .base_baud = 921600,
1427 .uart_offset = 8,
1428 },
1429
1430 [pbn_b1_1_115200] = {
1431 .flags = FL_BASE1,
1432 .num_ports = 1,
1433 .base_baud = 115200,
1434 .uart_offset = 8,
1435 },
1436 [pbn_b1_2_115200] = {
1437 .flags = FL_BASE1,
1438 .num_ports = 2,
1439 .base_baud = 115200,
1440 .uart_offset = 8,
1441 },
1442 [pbn_b1_4_115200] = {
1443 .flags = FL_BASE1,
1444 .num_ports = 4,
1445 .base_baud = 115200,
1446 .uart_offset = 8,
1447 },
1448 [pbn_b1_8_115200] = {
1449 .flags = FL_BASE1,
1450 .num_ports = 8,
1451 .base_baud = 115200,
1452 .uart_offset = 8,
1453 },
1454
1455 [pbn_b1_1_921600] = {
1456 .flags = FL_BASE1,
1457 .num_ports = 1,
1458 .base_baud = 921600,
1459 .uart_offset = 8,
1460 },
1461 [pbn_b1_2_921600] = {
1462 .flags = FL_BASE1,
1463 .num_ports = 2,
1464 .base_baud = 921600,
1465 .uart_offset = 8,
1466 },
1467 [pbn_b1_4_921600] = {
1468 .flags = FL_BASE1,
1469 .num_ports = 4,
1470 .base_baud = 921600,
1471 .uart_offset = 8,
1472 },
1473 [pbn_b1_8_921600] = {
1474 .flags = FL_BASE1,
1475 .num_ports = 8,
1476 .base_baud = 921600,
1477 .uart_offset = 8,
1478 },
26e92861
GH		 1479 [pbn_b1_2_1250000] = {
1480 .flags = FL_BASE1,
1481 .num_ports = 2,
1482 .base_baud = 1250000,
1483 .uart_offset = 8,
1484 },
1da177e4 1485
84f8c6fc
NV		 1486 [pbn_b1_bt_1_115200] = {
1487 .flags = FL_BASE1|FL_BASE_BARS,
1488 .num_ports = 1,
1489 .base_baud = 115200,
1490 .uart_offset = 8,
1491 },
1492
1da177e4
LT		 1493 [pbn_b1_bt_2_921600] = {
1494 .flags = FL_BASE1|FL_BASE_BARS,
1495 .num_ports = 2,
1496 .base_baud = 921600,
1497 .uart_offset = 8,
1498 },
1499
1500 [pbn_b1_1_1382400] = {
1501 .flags = FL_BASE1,
1502 .num_ports = 1,
1503 .base_baud = 1382400,
1504 .uart_offset = 8,
1505 },
1506 [pbn_b1_2_1382400] = {
1507 .flags = FL_BASE1,
1508 .num_ports = 2,
1509 .base_baud = 1382400,
1510 .uart_offset = 8,
1511 },
1512 [pbn_b1_4_1382400] = {
1513 .flags = FL_BASE1,
1514 .num_ports = 4,
1515 .base_baud = 1382400,
1516 .uart_offset = 8,
1517 },
1518 [pbn_b1_8_1382400] = {
1519 .flags = FL_BASE1,
1520 .num_ports = 8,
1521 .base_baud = 1382400,
1522 .uart_offset = 8,
1523 },
1524
1525 [pbn_b2_1_115200] = {
1526 .flags = FL_BASE2,
1527 .num_ports = 1,
1528 .base_baud = 115200,
1529 .uart_offset = 8,
1530 },
737c1756
PH		 1531 [pbn_b2_2_115200] = {
1532 .flags = FL_BASE2,
1533 .num_ports = 2,
1534 .base_baud = 115200,
1535 .uart_offset = 8,
1536 },
a9cccd34
MF		 1537 [pbn_b2_4_115200] = {
1538 .flags = FL_BASE2,
1539 .num_ports = 4,
1540 .base_baud = 115200,
1541 .uart_offset = 8,
1542 },
1da177e4
LT		 1543 [pbn_b2_8_115200] = {
1544 .flags = FL_BASE2,
1545 .num_ports = 8,
1546 .base_baud = 115200,
1547 .uart_offset = 8,
1548 },
1549
1550 [pbn_b2_1_460800] = {
1551 .flags = FL_BASE2,
1552 .num_ports = 1,
1553 .base_baud = 460800,
1554 .uart_offset = 8,
1555 },
1556 [pbn_b2_4_460800] = {
1557 .flags = FL_BASE2,
1558 .num_ports = 4,
1559 .base_baud = 460800,
1560 .uart_offset = 8,
1561 },
1562 [pbn_b2_8_460800] = {
1563 .flags = FL_BASE2,
1564 .num_ports = 8,
1565 .base_baud = 460800,
1566 .uart_offset = 8,
1567 },
1568 [pbn_b2_16_460800] = {
1569 .flags = FL_BASE2,
1570 .num_ports = 16,
1571 .base_baud = 460800,
1572 .uart_offset = 8,
1573 },
1574
1575 [pbn_b2_1_921600] = {
1576 .flags = FL_BASE2,
1577 .num_ports = 1,
1578 .base_baud = 921600,
1579 .uart_offset = 8,
1580 },
1581 [pbn_b2_4_921600] = {
1582 .flags = FL_BASE2,
1583 .num_ports = 4,
1584 .base_baud = 921600,
1585 .uart_offset = 8,
1586 },
1587 [pbn_b2_8_921600] = {
1588 .flags = FL_BASE2,
1589 .num_ports = 8,
1590 .base_baud = 921600,
1591 .uart_offset = 8,
1592 },
1593
1594 [pbn_b2_bt_1_115200] = {
1595 .flags = FL_BASE2|FL_BASE_BARS,
1596 .num_ports = 1,
1597 .base_baud = 115200,
1598 .uart_offset = 8,
1599 },
1600 [pbn_b2_bt_2_115200] = {
1601 .flags = FL_BASE2|FL_BASE_BARS,
1602 .num_ports = 2,
1603 .base_baud = 115200,
1604 .uart_offset = 8,
1605 },
1606 [pbn_b2_bt_4_115200] = {
1607 .flags = FL_BASE2|FL_BASE_BARS,
1608 .num_ports = 4,
1609 .base_baud = 115200,
1610 .uart_offset = 8,
1611 },
1612
1613 [pbn_b2_bt_2_921600] = {
1614 .flags = FL_BASE2|FL_BASE_BARS,
1615 .num_ports = 2,
1616 .base_baud = 921600,
1617 .uart_offset = 8,
1618 },
1619 [pbn_b2_bt_4_921600] = {
1620 .flags = FL_BASE2|FL_BASE_BARS,
1621 .num_ports = 4,
1622 .base_baud = 921600,
1623 .uart_offset = 8,
1624 },
1625
d9004eb4
ABL		 1626 [pbn_b3_2_115200] = {
1627 .flags = FL_BASE3,
1628 .num_ports = 2,
1629 .base_baud = 115200,
1630 .uart_offset = 8,
1631 },
1da177e4
LT		 1632 [pbn_b3_4_115200] = {
1633 .flags = FL_BASE3,
1634 .num_ports = 4,
1635 .base_baud = 115200,
1636 .uart_offset = 8,
1637 },
1638 [pbn_b3_8_115200] = {
1639 .flags = FL_BASE3,
1640 .num_ports = 8,
1641 .base_baud = 115200,
1642 .uart_offset = 8,
1643 },
1644
1645 /*
1646 * Entries following this are board-specific.
1647 */
1648
1649 /*
1650 * Panacom - IOMEM
1651 */
1652 [pbn_panacom] = {
1653 .flags = FL_BASE2,
1654 .num_ports = 2,
1655 .base_baud = 921600,
1656 .uart_offset = 0x400,
1657 .reg_shift = 7,
1658 },
1659 [pbn_panacom2] = {
1660 .flags = FL_BASE2|FL_BASE_BARS,
1661 .num_ports = 2,
1662 .base_baud = 921600,
1663 .uart_offset = 0x400,
1664 .reg_shift = 7,
1665 },
1666 [pbn_panacom4] = {
1667 .flags = FL_BASE2|FL_BASE_BARS,
1668 .num_ports = 4,
1669 .base_baud = 921600,
1670 .uart_offset = 0x400,
1671 .reg_shift = 7,
1672 },
1673
add7b58e
BH		 1674 [pbn_exsys_4055] = {
1675 .flags = FL_BASE2,
1676 .num_ports = 4,
1677 .base_baud = 115200,
1678 .uart_offset = 8,
1679 },
1680
1da177e4
LT		 1681 /* I think this entry is broken - the first_offset looks wrong --rmk */
1682 [pbn_plx_romulus] = {
1683 .flags = FL_BASE2,
1684 .num_ports = 4,
1685 .base_baud = 921600,
1686 .uart_offset = 8 << 2,
1687 .reg_shift = 2,
1688 .first_offset = 0x03,
1689 },
1690
1691 /*
1692 * This board uses the size of PCI Base region 0 to
1693 * signal now many ports are available
1694 */
1695 [pbn_oxsemi] = {
1696 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1697 .num_ports = 32,
1698 .base_baud = 115200,
1699 .uart_offset = 8,
1700 },
7106b4e3
LH		 1701 [pbn_oxsemi_1_4000000] = {
1702 .flags = FL_BASE0,
1703 .num_ports = 1,
1704 .base_baud = 4000000,
1705 .uart_offset = 0x200,
1706 .first_offset = 0x1000,
1707 },
1708 [pbn_oxsemi_2_4000000] = {
1709 .flags = FL_BASE0,
1710 .num_ports = 2,
1711 .base_baud = 4000000,
1712 .uart_offset = 0x200,
1713 .first_offset = 0x1000,
1714 },
1715 [pbn_oxsemi_4_4000000] = {
1716 .flags = FL_BASE0,
1717 .num_ports = 4,
1718 .base_baud = 4000000,
1719 .uart_offset = 0x200,
1720 .first_offset = 0x1000,
1721 },
1722 [pbn_oxsemi_8_4000000] = {
1723 .flags = FL_BASE0,
1724 .num_ports = 8,
1725 .base_baud = 4000000,
1726 .uart_offset = 0x200,
1727 .first_offset = 0x1000,
1728 },
1729
1da177e4
LT		 1730
1731 /*
1732 * EKF addition for i960 Boards form EKF with serial port.
1733 * Max 256 ports.
1734 */
1735 [pbn_intel_i960] = {
1736 .flags = FL_BASE0,
1737 .num_ports = 32,
1738 .base_baud = 921600,
1739 .uart_offset = 8 << 2,
1740 .reg_shift = 2,
1741 .first_offset = 0x10000,
1742 },
1743 [pbn_sgi_ioc3] = {
1744 .flags = FL_BASE0|FL_NOIRQ,
1745 .num_ports = 1,
1746 .base_baud = 458333,
1747 .uart_offset = 8,
1748 .reg_shift = 0,
1749 .first_offset = 0x20178,
1750 },
1751
1da177e4
LT		 1752 /*
1753 * Computone - uses IOMEM.
1754 */
1755 [pbn_computone_4] = {
1756 .flags = FL_BASE0,
1757 .num_ports = 4,
1758 .base_baud = 921600,
1759 .uart_offset = 0x40,
1760 .reg_shift = 2,
1761 .first_offset = 0x200,
1762 },
1763 [pbn_computone_6] = {
1764 .flags = FL_BASE0,
1765 .num_ports = 6,
1766 .base_baud = 921600,
1767 .uart_offset = 0x40,
1768 .reg_shift = 2,
1769 .first_offset = 0x200,
1770 },
1771 [pbn_computone_8] = {
1772 .flags = FL_BASE0,
1773 .num_ports = 8,
1774 .base_baud = 921600,
1775 .uart_offset = 0x40,
1776 .reg_shift = 2,
1777 .first_offset = 0x200,
1778 },
1779 [pbn_sbsxrsio] = {
1780 .flags = FL_BASE0,
1781 .num_ports = 8,
1782 .base_baud = 460800,
1783 .uart_offset = 256,
1784 .reg_shift = 4,
1785 },
1786 /*
1787 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1788 * Only basic 16550A support.
1789 * XR17C15[24] are not tested, but they should work.
1790 */
1791 [pbn_exar_XR17C152] = {
1792 .flags = FL_BASE0,
1793 .num_ports = 2,
1794 .base_baud = 921600,
1795 .uart_offset = 0x200,
1796 },
1797 [pbn_exar_XR17C154] = {
1798 .flags = FL_BASE0,
1799 .num_ports = 4,
1800 .base_baud = 921600,
1801 .uart_offset = 0x200,
1802 },
1803 [pbn_exar_XR17C158] = {
1804 .flags = FL_BASE0,
1805 .num_ports = 8,
1806 .base_baud = 921600,
1807 .uart_offset = 0x200,
1808 },
aa798505
OJ		 1809 /*
1810 * PA Semi PWRficient PA6T-1682M on-chip UART
1811 */
1812 [pbn_pasemi_1682M] = {
1813 .flags = FL_BASE0,
1814 .num_ports = 1,
1815 .base_baud = 8333333,
1816 },
1da177e4
LT		 1817};
1818
436bbd43 1819static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 1820 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
436bbd43
CS		 1821};
1822
1da177e4
LT		 1823/*
1824 * Given a complete unknown PCI device, try to use some heuristics to
1825 * guess what the configuration might be, based on the pitiful PCI
1826 * serial specs. Returns 0 on success, 1 on failure.
1827 */
1828static int __devinit
1c7c1fe5 1829serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 1830{
436bbd43 1831 const struct pci_device_id *blacklist;
1da177e4 1832 int num_iomem, num_port, first_port = -1, i;
5756ee99 1833
1da177e4
LT		 1834 /*
1835 * If it is not a communications device or the programming
1836 * interface is greater than 6, give up.
1837 *
1838 * (Should we try to make guesses for multiport serial devices
5756ee99 1839 * later?)
1da177e4
LT		 1840 */
1841 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1842 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1843 (dev->class & 0xff) > 6)
1844 return -ENODEV;
1845
436bbd43
CS		 1846 /*
1847 * Do not access blacklisted devices that are known not to
1848 * feature serial ports.
1849 */
1850 for (blacklist = softmodem_blacklist;
1851 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1852 blacklist++) {
1853 if (dev->vendor == blacklist->vendor &&
1854 dev->device == blacklist->device)
1855 return -ENODEV;
1856 }
1857
1da177e4
LT		 1858 num_iomem = num_port = 0;
1859 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1860 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1861 num_port++;
1862 if (first_port == -1)
1863 first_port = i;
1864 }
1865 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1866 num_iomem++;
1867 }
1868
1869 /*
1870 * If there is 1 or 0 iomem regions, and exactly one port,
1871 * use it. We guess the number of ports based on the IO
1872 * region size.
1873 */
1874 if (num_iomem <= 1 && num_port == 1) {
1875 board->flags = first_port;
1876 board->num_ports = pci_resource_len(dev, first_port) / 8;
1877 return 0;
1878 }
1879
1880 /*
1881 * Now guess if we've got a board which indexes by BARs.
1882 * Each IO BAR should be 8 bytes, and they should follow
1883 * consecutively.
1884 */
1885 first_port = -1;
1886 num_port = 0;
1887 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1888 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1889 pci_resource_len(dev, i) == 8 &&
1890 (first_port == -1 || (first_port + num_port) == i)) {
1891 num_port++;
1892 if (first_port == -1)
1893 first_port = i;
1894 }
1895 }
1896
1897 if (num_port > 1) {
1898 board->flags = first_port | FL_BASE_BARS;
1899 board->num_ports = num_port;
1900 return 0;
1901 }
1902
1903 return -ENODEV;
1904}
1905
1906static inline int
975a1a7d
RK		 1907serial_pci_matches(const struct pciserial_board *board,
1908 const struct pciserial_board *guessed)
1da177e4
LT		 1909{
1910 return
1911 board->num_ports == guessed->num_ports &&
1912 board->base_baud == guessed->base_baud &&
1913 board->uart_offset == guessed->uart_offset &&
1914 board->reg_shift == guessed->reg_shift &&
1915 board->first_offset == guessed->first_offset;
1916}
1917
241fc436 1918struct serial_private *
975a1a7d 1919pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 1920{
72ce9a83 1921 struct uart_port serial_port;
1da177e4 1922 struct serial_private *priv;
1da177e4
LT		 1923 struct pci_serial_quirk *quirk;
1924 int rc, nr_ports, i;
1925
1da177e4
LT		 1926 nr_ports = board->num_ports;
1927
1928 /*
1929 * Find an init and setup quirks.
1930 */
1931 quirk = find_quirk(dev);
1932
1933 /*
1934 * Run the new-style initialization function.
1935 * The initialization function returns:
1936 * <0 - error
1937 * 0 - use board->num_ports
1938 * >0 - number of ports
1939 */
1940 if (quirk->init) {
1941 rc = quirk->init(dev);
241fc436
RK		 1942 if (rc < 0) {
1943 priv = ERR_PTR(rc);
1944 goto err_out;
1945 }
1da177e4
LT		 1946 if (rc)
1947 nr_ports = rc;
1948 }
1949
8f31bb39 1950 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 1951 sizeof(unsigned int) * nr_ports,
1952 GFP_KERNEL);
1953 if (!priv) {
241fc436
RK		 1954 priv = ERR_PTR(-ENOMEM);
1955 goto err_deinit;
1da177e4
LT		 1956 }
1957
70db3d91 1958 priv->dev = dev;
1da177e4 1959 priv->quirk = quirk;
1da177e4 1960
72ce9a83
RK		 1961 memset(&serial_port, 0, sizeof(struct uart_port));
1962 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1963 serial_port.uartclk = board->base_baud * 16;
1964 serial_port.irq = get_pci_irq(dev, board);
1965 serial_port.dev = &dev->dev;
1966
1da177e4 1967 for (i = 0; i < nr_ports; i++) {
70db3d91 1968 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 1969 break;
72ce9a83 1970
1da177e4 1971#ifdef SERIAL_DEBUG_PCI
5756ee99 1972 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
1da177e4
LT		 1973 serial_port.iobase, serial_port.irq, serial_port.iotype);
1974#endif
5756ee99 1975
1da177e4
LT		 1976 priv->line[i] = serial8250_register_port(&serial_port);
1977 if (priv->line[i] < 0) {
1978 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1979 break;
1980 }
1981 }
1da177e4 1982 priv->nr = i;
241fc436 1983 return priv;
1da177e4 1984
5756ee99 1985err_deinit:
1da177e4
LT		 1986 if (quirk->exit)
1987 quirk->exit(dev);
5756ee99 1988err_out:
241fc436 1989 return priv;
1da177e4 1990}
241fc436 1991EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 1992
241fc436 1993void pciserial_remove_ports(struct serial_private *priv)
1da177e4 1994{
056a8763
RK		 1995 struct pci_serial_quirk *quirk;
1996 int i;
1da177e4 1997
056a8763
RK		 1998 for (i = 0; i < priv->nr; i++)
1999 serial8250_unregister_port(priv->line[i]);
1da177e4 2000
056a8763
RK		 2001 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2002 if (priv->remapped_bar[i])
2003 iounmap(priv->remapped_bar[i]);
2004 priv->remapped_bar[i] = NULL;
2005 }
1da177e4 2006
056a8763
RK		 2007 /*
2008 * Find the exit quirks.
2009 */
241fc436 2010 quirk = find_quirk(priv->dev);
056a8763 2011 if (quirk->exit)
241fc436
RK		 2012 quirk->exit(priv->dev);
2013
2014 kfree(priv);
2015}
2016EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2017
2018void pciserial_suspend_ports(struct serial_private *priv)
2019{
2020 int i;
2021
2022 for (i = 0; i < priv->nr; i++)
2023 if (priv->line[i] >= 0)
2024 serial8250_suspend_port(priv->line[i]);
2025}
2026EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2027
2028void pciserial_resume_ports(struct serial_private *priv)
2029{
2030 int i;
2031
2032 /*
2033 * Ensure that the board is correctly configured.
2034 */
2035 if (priv->quirk->init)
2036 priv->quirk->init(priv->dev);
2037
2038 for (i = 0; i < priv->nr; i++)
2039 if (priv->line[i] >= 0)
2040 serial8250_resume_port(priv->line[i]);
2041}
2042EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2043
2044/*
2045 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2046 * to the arrangement of serial ports on a PCI card.
2047 */
2048static int __devinit
2049pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2050{
2051 struct serial_private *priv;
975a1a7d
RK		 2052 const struct pciserial_board *board;
2053 struct pciserial_board tmp;
241fc436
RK		 2054 int rc;
2055
2056 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2057 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2058 ent->driver_data);
2059 return -EINVAL;
2060 }
2061
2062 board = &pci_boards[ent->driver_data];
2063
2064 rc = pci_enable_device(dev);
2065 if (rc)
2066 return rc;
2067
2068 if (ent->driver_data == pbn_default) {
2069 /*
2070 * Use a copy of the pci_board entry for this;
2071 * avoid changing entries in the table.
2072 */
2073 memcpy(&tmp, board, sizeof(struct pciserial_board));
2074 board = &tmp;
2075
2076 /*
2077 * We matched one of our class entries. Try to
2078 * determine the parameters of this board.
2079 */
975a1a7d 2080 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2081 if (rc)
2082 goto disable;
2083 } else {
2084 /*
2085 * We matched an explicit entry. If we are able to
2086 * detect this boards settings with our heuristic,
2087 * then we no longer need this entry.
2088 */
2089 memcpy(&tmp, &pci_boards[pbn_default],
2090 sizeof(struct pciserial_board));
2091 rc = serial_pci_guess_board(dev, &tmp);
2092 if (rc == 0 && serial_pci_matches(board, &tmp))
2093 moan_device("Redundant entry in serial pci_table.",
2094 dev);
2095 }
2096
2097 priv = pciserial_init_ports(dev, board);
2098 if (!IS_ERR(priv)) {
2099 pci_set_drvdata(dev, priv);
2100 return 0;
2101 }
2102
2103 rc = PTR_ERR(priv);
1da177e4 2104
241fc436 2105 disable:
056a8763 2106 pci_disable_device(dev);
241fc436
RK		 2107 return rc;
2108}
1da177e4 2109
241fc436
RK		 2110static void __devexit pciserial_remove_one(struct pci_dev *dev)
2111{
2112 struct serial_private *priv = pci_get_drvdata(dev);
2113
2114 pci_set_drvdata(dev, NULL);
2115
2116 pciserial_remove_ports(priv);
2117
2118 pci_disable_device(dev);
1da177e4
LT		 2119}
2120
1d5e7996 2121#ifdef CONFIG_PM
1da177e4
LT		 2122static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2123{
2124 struct serial_private *priv = pci_get_drvdata(dev);
2125
241fc436
RK		 2126 if (priv)
2127 pciserial_suspend_ports(priv);
1da177e4 2128
1da177e4
LT		 2129 pci_save_state(dev);
2130 pci_set_power_state(dev, pci_choose_state(dev, state));
2131 return 0;
2132}
2133
2134static int pciserial_resume_one(struct pci_dev *dev)
2135{
ccb9d59e 2136 int err;
1da177e4
LT		 2137 struct serial_private *priv = pci_get_drvdata(dev);
2138
2139 pci_set_power_state(dev, PCI_D0);
2140 pci_restore_state(dev);
2141
2142 if (priv) {
1da177e4
LT		 2143 /*
2144 * The device may have been disabled. Re-enable it.
2145 */
ccb9d59e 2146 err = pci_enable_device(dev);
40836c48 2147 /* FIXME: We cannot simply error out here */
ccb9d59e 2148 if (err)
40836c48 2149 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2150 pciserial_resume_ports(priv);
1da177e4
LT		 2151 }
2152 return 0;
2153}
1d5e7996 2154#endif
1da177e4
LT		 2155
2156static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 2157 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2158 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2159 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2160 pbn_b2_8_921600 },
1da177e4
LT		 2161 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2162 PCI_SUBVENDOR_ID_CONNECT_TECH,
2163 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2164 pbn_b1_8_1382400 },
2165 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2166 PCI_SUBVENDOR_ID_CONNECT_TECH,
2167 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2168 pbn_b1_4_1382400 },
2169 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2170 PCI_SUBVENDOR_ID_CONNECT_TECH,
2171 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2172 pbn_b1_2_1382400 },
2173 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2174 PCI_SUBVENDOR_ID_CONNECT_TECH,
2175 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2176 pbn_b1_8_1382400 },
2177 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2178 PCI_SUBVENDOR_ID_CONNECT_TECH,
2179 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2180 pbn_b1_4_1382400 },
2181 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2182 PCI_SUBVENDOR_ID_CONNECT_TECH,
2183 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2184 pbn_b1_2_1382400 },
2185 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2186 PCI_SUBVENDOR_ID_CONNECT_TECH,
2187 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2188 pbn_b1_8_921600 },
2189 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2190 PCI_SUBVENDOR_ID_CONNECT_TECH,
2191 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2192 pbn_b1_8_921600 },
2193 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2194 PCI_SUBVENDOR_ID_CONNECT_TECH,
2195 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2196 pbn_b1_4_921600 },
2197 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2198 PCI_SUBVENDOR_ID_CONNECT_TECH,
2199 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2200 pbn_b1_4_921600 },
2201 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2202 PCI_SUBVENDOR_ID_CONNECT_TECH,
2203 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2204 pbn_b1_2_921600 },
2205 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2206 PCI_SUBVENDOR_ID_CONNECT_TECH,
2207 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2208 pbn_b1_8_921600 },
2209 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2210 PCI_SUBVENDOR_ID_CONNECT_TECH,
2211 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2212 pbn_b1_8_921600 },
2213 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2214 PCI_SUBVENDOR_ID_CONNECT_TECH,
2215 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2216 pbn_b1_4_921600 },
26e92861
GH		 2217 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2218 PCI_SUBVENDOR_ID_CONNECT_TECH,
2219 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2220 pbn_b1_2_1250000 },
2221 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2222 PCI_SUBVENDOR_ID_CONNECT_TECH,
2223 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2224 pbn_b0_2_1843200 },
2225 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2226 PCI_SUBVENDOR_ID_CONNECT_TECH,
2227 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2228 pbn_b0_4_1843200 },
85d1494e
YY		 2229 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2230 PCI_VENDOR_ID_AFAVLAB,
2231 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2232 pbn_b0_4_1152000 },
26e92861
GH		 2233 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2234 PCI_SUBVENDOR_ID_CONNECT_TECH,
2235 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2236 pbn_b0_2_1843200_200 },
2237 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2238 PCI_SUBVENDOR_ID_CONNECT_TECH,
2239 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2240 pbn_b0_4_1843200_200 },
2241 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2242 PCI_SUBVENDOR_ID_CONNECT_TECH,
2243 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2244 pbn_b0_8_1843200_200 },
2245 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2246 PCI_SUBVENDOR_ID_CONNECT_TECH,
2247 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2248 pbn_b0_2_1843200_200 },
2249 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2250 PCI_SUBVENDOR_ID_CONNECT_TECH,
2251 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2252 pbn_b0_4_1843200_200 },
2253 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2254 PCI_SUBVENDOR_ID_CONNECT_TECH,
2255 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2256 pbn_b0_8_1843200_200 },
2257 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2258 PCI_SUBVENDOR_ID_CONNECT_TECH,
2259 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2260 pbn_b0_2_1843200_200 },
2261 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2262 PCI_SUBVENDOR_ID_CONNECT_TECH,
2263 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2264 pbn_b0_4_1843200_200 },
2265 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2266 PCI_SUBVENDOR_ID_CONNECT_TECH,
2267 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2268 pbn_b0_8_1843200_200 },
2269 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2270 PCI_SUBVENDOR_ID_CONNECT_TECH,
2271 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2272 pbn_b0_2_1843200_200 },
2273 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2274 PCI_SUBVENDOR_ID_CONNECT_TECH,
2275 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2276 pbn_b0_4_1843200_200 },
2277 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2278 PCI_SUBVENDOR_ID_CONNECT_TECH,
2279 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2280 pbn_b0_8_1843200_200 },
1da177e4
LT		 2281
2282 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 2283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2284 pbn_b2_bt_1_115200 },
2285 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 2286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2287 pbn_b2_bt_2_115200 },
2288 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 2289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2290 pbn_b2_bt_4_115200 },
2291 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 2292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2293 pbn_b2_bt_2_115200 },
2294 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 2295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2296 pbn_b2_bt_4_115200 },
2297 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 2298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2299 pbn_b2_8_115200 },
e65f0f82
FL		 2300 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2302 pbn_b2_8_460800 },
1da177e4
LT		 2303 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2305 pbn_b2_8_115200 },
2306
2307 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2309 pbn_b2_bt_2_115200 },
2310 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2312 pbn_b2_bt_2_921600 },
2313 /*
2314 * VScom SPCOM800, from sl@s.pl
2315 */
5756ee99
AC		 2316 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2318 pbn_b2_8_921600 },
2319 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 2320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2321 pbn_b2_4_921600 },
b76c5a07
CB		 2322 /* Unknown card - subdevice 0x1584 */
2323 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2324 PCI_VENDOR_ID_PLX,
2325 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2326 pbn_b0_4_115200 },
1da177e4
LT		 2327 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2328 PCI_SUBVENDOR_ID_KEYSPAN,
2329 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2330 pbn_panacom },
2331 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2333 pbn_panacom4 },
2334 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2336 pbn_panacom2 },
a9cccd34
MF		 2337 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2338 PCI_VENDOR_ID_ESDGMBH,
2339 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2340 pbn_b2_4_115200 },
1da177e4
LT		 2341 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2342 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2343 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 2344 pbn_b2_4_460800 },
2345 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2346 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2347 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 2348 pbn_b2_8_460800 },
2349 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2350 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2351 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 2352 pbn_b2_16_460800 },
2353 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2354 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2355 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 2356 pbn_b2_16_460800 },
2357 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2358 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2359 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 2360 pbn_b2_4_460800 },
2361 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2362 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2363 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 2364 pbn_b2_8_460800 },
add7b58e
BH		 2365 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2366 PCI_SUBVENDOR_ID_EXSYS,
2367 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2368 pbn_exsys_4055 },
1da177e4
LT		 2369 /*
2370 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2371 * (Exoray@isys.ca)
2372 */
2373 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2374 0x10b5, 0x106a, 0, 0,
2375 pbn_plx_romulus },
2376 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2378 pbn_b1_4_115200 },
2379 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2381 pbn_b1_2_115200 },
2382 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2384 pbn_b1_8_115200 },
2385 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2387 pbn_b1_8_115200 },
2388 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2389 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2390 0, 0,
1da177e4 2391 pbn_b0_4_921600 },
fbc0dc0d 2392 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2393 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2394 0, 0,
fbc0dc0d 2395 pbn_b0_4_1152000 },
db1de159
DR		 2396
2397 /*
2398 * The below card is a little controversial since it is the
2399 * subject of a PCI vendor/device ID clash. (See
2400 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2401 * For now just used the hex ID 0x950a.
2402 */
39aced68
NV		 2403 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2404 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2405 pbn_b0_2_115200 },
db1de159
DR		 2406 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2408 pbn_b0_2_1130000 },
1da177e4
LT		 2409 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2411 pbn_b0_4_115200 },
2412 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2414 pbn_b0_bt_2_921600 },
2415
7106b4e3
LH		 2416 /*
2417 * Oxford Semiconductor Inc. Tornado PCI express device range.
2418 */
2419 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2421 pbn_b0_1_4000000 },
2422 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2424 pbn_b0_1_4000000 },
2425 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2427 pbn_oxsemi_1_4000000 },
2428 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2430 pbn_oxsemi_1_4000000 },
2431 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2433 pbn_b0_1_4000000 },
2434 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2436 pbn_b0_1_4000000 },
2437 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2439 pbn_oxsemi_1_4000000 },
2440 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2442 pbn_oxsemi_1_4000000 },
2443 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2445 pbn_b0_1_4000000 },
2446 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2448 pbn_b0_1_4000000 },
2449 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2451 pbn_b0_1_4000000 },
2452 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2454 pbn_b0_1_4000000 },
2455 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2457 pbn_oxsemi_2_4000000 },
2458 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2460 pbn_oxsemi_2_4000000 },
2461 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2463 pbn_oxsemi_4_4000000 },
2464 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2466 pbn_oxsemi_4_4000000 },
2467 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2469 pbn_oxsemi_8_4000000 },
2470 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2472 pbn_oxsemi_8_4000000 },
2473 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2475 pbn_oxsemi_1_4000000 },
2476 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2478 pbn_oxsemi_1_4000000 },
2479 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2481 pbn_oxsemi_1_4000000 },
2482 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2484 pbn_oxsemi_1_4000000 },
2485 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2487 pbn_oxsemi_1_4000000 },
2488 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2490 pbn_oxsemi_1_4000000 },
2491 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2493 pbn_oxsemi_1_4000000 },
2494 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2496 pbn_oxsemi_1_4000000 },
2497 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2499 pbn_oxsemi_1_4000000 },
2500 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2502 pbn_oxsemi_1_4000000 },
2503 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2505 pbn_oxsemi_1_4000000 },
2506 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2508 pbn_oxsemi_1_4000000 },
2509 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2511 pbn_oxsemi_1_4000000 },
2512 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2514 pbn_oxsemi_1_4000000 },
2515 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2517 pbn_oxsemi_1_4000000 },
2518 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2520 pbn_oxsemi_1_4000000 },
2521 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2523 pbn_oxsemi_1_4000000 },
2524 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2526 pbn_oxsemi_1_4000000 },
2527 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2529 pbn_oxsemi_1_4000000 },
2530 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2532 pbn_oxsemi_1_4000000 },
2533 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2535 pbn_oxsemi_1_4000000 },
2536 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
2537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2538 pbn_oxsemi_1_4000000 },
2539 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
2540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2541 pbn_oxsemi_1_4000000 },
2542 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
2543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2544 pbn_oxsemi_1_4000000 },
2545 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
2546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2547 pbn_oxsemi_1_4000000 },
2548 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
2549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2550 pbn_oxsemi_1_4000000 },
b80de369
LH		 2551 /*
2552 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2553 */
2554 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2555 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2556 pbn_oxsemi_1_4000000 },
2557 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2558 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2559 pbn_oxsemi_2_4000000 },
2560 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2561 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2562 pbn_oxsemi_4_4000000 },
2563 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2564 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2565 pbn_oxsemi_8_4000000 },
1da177e4
LT		 2566 /*
2567 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2568 * from skokodyn@yahoo.com
2569 */
2570 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2571 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2572 pbn_sbsxrsio },
2573 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2574 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2575 pbn_sbsxrsio },
2576 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2577 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2578 pbn_sbsxrsio },
2579 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2580 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2581 pbn_sbsxrsio },
2582
2583 /*
2584 * Digitan DS560-558, from jimd@esoft.com
2585 */
2586 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 2587 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2588 pbn_b1_1_115200 },
2589
2590 /*
2591 * Titan Electronic cards
2592 * The 400L and 800L have a custom setup quirk.
2593 */
2594 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 2595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2596 pbn_b0_1_921600 },
2597 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 2598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2599 pbn_b0_2_921600 },
2600 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 2601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2602 pbn_b0_4_921600 },
2603 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 2604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2605 pbn_b0_4_921600 },
2606 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2608 pbn_b1_1_921600 },
2609 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2611 pbn_b1_bt_2_921600 },
2612 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2614 pbn_b0_bt_4_921600 },
2615 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2617 pbn_b0_bt_8_921600 },
2618
2619 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2621 pbn_b2_1_460800 },
2622 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2624 pbn_b2_1_460800 },
2625 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2627 pbn_b2_1_460800 },
2628 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2630 pbn_b2_bt_2_921600 },
2631 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2633 pbn_b2_bt_2_921600 },
2634 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2636 pbn_b2_bt_2_921600 },
2637 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2639 pbn_b2_bt_4_921600 },
2640 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2642 pbn_b2_bt_4_921600 },
2643 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2645 pbn_b2_bt_4_921600 },
2646 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2648 pbn_b0_1_921600 },
2649 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2651 pbn_b0_1_921600 },
2652 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2654 pbn_b0_1_921600 },
2655 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2657 pbn_b0_bt_2_921600 },
2658 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2660 pbn_b0_bt_2_921600 },
2661 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2663 pbn_b0_bt_2_921600 },
2664 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2666 pbn_b0_bt_4_921600 },
2667 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2669 pbn_b0_bt_4_921600 },
2670 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2672 pbn_b0_bt_4_921600 },
3ec9c594
AP		 2673 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2675 pbn_b0_bt_8_921600 },
2676 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2678 pbn_b0_bt_8_921600 },
2679 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2681 pbn_b0_bt_8_921600 },
1da177e4
LT		 2682
2683 /*
2684 * Computone devices submitted by Doug McNash dmcnash@computone.com
2685 */
2686 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2687 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2688 0, 0, pbn_computone_4 },
2689 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2690 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2691 0, 0, pbn_computone_8 },
2692 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2693 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2694 0, 0, pbn_computone_6 },
2695
2696 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2698 pbn_oxsemi },
2699 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2700 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2701 pbn_b0_bt_1_921600 },
2702
2703 /*
2704 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2705 */
2706 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2708 pbn_b0_bt_8_115200 },
2709 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2711 pbn_b0_bt_8_115200 },
2712
2713 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2715 pbn_b0_bt_2_115200 },
2716 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2718 pbn_b0_bt_2_115200 },
2719 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2721 pbn_b0_bt_2_115200 },
2722 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2724 pbn_b0_bt_4_460800 },
2725 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2727 pbn_b0_bt_4_460800 },
2728 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2730 pbn_b0_bt_2_460800 },
2731 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2733 pbn_b0_bt_2_460800 },
2734 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2736 pbn_b0_bt_2_460800 },
2737 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2739 pbn_b0_bt_1_115200 },
2740 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2742 pbn_b0_bt_1_460800 },
2743
1fb8cacc
RK		 2744 /*
2745 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2746 * Cards are identified by their subsystem vendor IDs, which
2747 * (in hex) match the model number.
2748 *
2749 * Note that JC140x are RS422/485 cards which require ox950
2750 * ACR = 0x10, and as such are not currently fully supported.
2751 */
2752 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2753 0x1204, 0x0004, 0, 0,
2754 pbn_b0_4_921600 },
2755 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2756 0x1208, 0x0004, 0, 0,
2757 pbn_b0_4_921600 },
2758/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2759 0x1402, 0x0002, 0, 0,
2760 pbn_b0_2_921600 }, */
2761/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2762 0x1404, 0x0004, 0, 0,
2763 pbn_b0_4_921600 }, */
2764 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2765 0x1208, 0x0004, 0, 0,
2766 pbn_b0_4_921600 },
2767
1da177e4
LT		 2768 /*
2769 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2770 */
2771 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2773 pbn_b1_1_1382400 },
2774
2775 /*
2776 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2777 */
2778 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2780 pbn_b1_1_1382400 },
2781
2782 /*
2783 * RAStel 2 port modem, gerg@moreton.com.au
2784 */
2785 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2787 pbn_b2_bt_2_115200 },
2788
2789 /*
2790 * EKF addition for i960 Boards form EKF with serial port
2791 */
2792 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2793 0xE4BF, PCI_ANY_ID, 0, 0,
2794 pbn_intel_i960 },
2795
2796 /*
2797 * Xircom Cardbus/Ethernet combos
2798 */
2799 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2801 pbn_b0_1_115200 },
2802 /*
2803 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2804 */
2805 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2807 pbn_b0_1_115200 },
2808
2809 /*
2810 * Untested PCI modems, sent in from various folks...
2811 */
2812
2813 /*
2814 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2815 */
2816 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2817 0x1048, 0x1500, 0, 0,
2818 pbn_b1_1_115200 },
2819
2820 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2821 0xFF00, 0, 0, 0,
2822 pbn_sgi_ioc3 },
2823
2824 /*
2825 * HP Diva card
2826 */
2827 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2828 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2829 pbn_b1_1_115200 },
2830 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2832 pbn_b0_5_115200 },
2833 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2834 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2835 pbn_b2_1_115200 },
2836
d9004eb4
ABL		 2837 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2839 pbn_b3_2_115200 },
1da177e4
LT		 2840 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2842 pbn_b3_4_115200 },
2843 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2845 pbn_b3_8_115200 },
2846
2847 /*
2848 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2849 */
2850 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2851 PCI_ANY_ID, PCI_ANY_ID,
2852 0,
2853 0, pbn_exar_XR17C152 },
2854 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2855 PCI_ANY_ID, PCI_ANY_ID,
2856 0,
2857 0, pbn_exar_XR17C154 },
2858 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2859 PCI_ANY_ID, PCI_ANY_ID,
2860 0,
2861 0, pbn_exar_XR17C158 },
2862
2863 /*
2864 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2865 */
2866 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2868 pbn_b0_1_115200 },
84f8c6fc
NV		 2869 /*
2870 * ITE
2871 */
2872 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2873 PCI_ANY_ID, PCI_ANY_ID,
2874 0, 0,
2875 pbn_b1_bt_1_115200 },
1da177e4 2876
737c1756
PH		 2877 /*
2878 * IntaShield IS-200
2879 */
2880 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2881 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2882 pbn_b2_2_115200 },
4b6f6ce9
IGP		 2883 /*
2884 * IntaShield IS-400
2885 */
2886 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
2887 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
2888 pbn_b2_4_115200 },
48212008
TH		 2889 /*
2890 * Perle PCI-RAS cards
2891 */
2892 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2893 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2894 0, 0, pbn_b2_4_921600 },
2895 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2896 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2897 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 2898
2899 /*
2900 * Mainpine series cards: Fairly standard layout but fools
2901 * parts of the autodetect in some cases and uses otherwise
2902 * unmatched communications subclasses in the PCI Express case
2903 */
2904
2905 { /* RockForceDUO */
2906 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2907 PCI_VENDOR_ID_MAINPINE, 0x0200,
2908 0, 0, pbn_b0_2_115200 },
2909 { /* RockForceQUATRO */
2910 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2911 PCI_VENDOR_ID_MAINPINE, 0x0300,
2912 0, 0, pbn_b0_4_115200 },
2913 { /* RockForceDUO+ */
2914 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2915 PCI_VENDOR_ID_MAINPINE, 0x0400,
2916 0, 0, pbn_b0_2_115200 },
2917 { /* RockForceQUATRO+ */
2918 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2919 PCI_VENDOR_ID_MAINPINE, 0x0500,
2920 0, 0, pbn_b0_4_115200 },
2921 { /* RockForce+ */
2922 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2923 PCI_VENDOR_ID_MAINPINE, 0x0600,
2924 0, 0, pbn_b0_2_115200 },
2925 { /* RockForce+ */
2926 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2927 PCI_VENDOR_ID_MAINPINE, 0x0700,
2928 0, 0, pbn_b0_4_115200 },
2929 { /* RockForceOCTO+ */
2930 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2931 PCI_VENDOR_ID_MAINPINE, 0x0800,
2932 0, 0, pbn_b0_8_115200 },
2933 { /* RockForceDUO+ */
2934 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2935 PCI_VENDOR_ID_MAINPINE, 0x0C00,
2936 0, 0, pbn_b0_2_115200 },
2937 { /* RockForceQUARTRO+ */
2938 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2939 PCI_VENDOR_ID_MAINPINE, 0x0D00,
2940 0, 0, pbn_b0_4_115200 },
2941 { /* RockForceOCTO+ */
2942 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2943 PCI_VENDOR_ID_MAINPINE, 0x1D00,
2944 0, 0, pbn_b0_8_115200 },
2945 { /* RockForceD1 */
2946 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2947 PCI_VENDOR_ID_MAINPINE, 0x2000,
2948 0, 0, pbn_b0_1_115200 },
2949 { /* RockForceF1 */
2950 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2951 PCI_VENDOR_ID_MAINPINE, 0x2100,
2952 0, 0, pbn_b0_1_115200 },
2953 { /* RockForceD2 */
2954 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2955 PCI_VENDOR_ID_MAINPINE, 0x2200,
2956 0, 0, pbn_b0_2_115200 },
2957 { /* RockForceF2 */
2958 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2959 PCI_VENDOR_ID_MAINPINE, 0x2300,
2960 0, 0, pbn_b0_2_115200 },
2961 { /* RockForceD4 */
2962 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2963 PCI_VENDOR_ID_MAINPINE, 0x2400,
2964 0, 0, pbn_b0_4_115200 },
2965 { /* RockForceF4 */
2966 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2967 PCI_VENDOR_ID_MAINPINE, 0x2500,
2968 0, 0, pbn_b0_4_115200 },
2969 { /* RockForceD8 */
2970 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2971 PCI_VENDOR_ID_MAINPINE, 0x2600,
2972 0, 0, pbn_b0_8_115200 },
2973 { /* RockForceF8 */
2974 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2975 PCI_VENDOR_ID_MAINPINE, 0x2700,
2976 0, 0, pbn_b0_8_115200 },
2977 { /* IQ Express D1 */
2978 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2979 PCI_VENDOR_ID_MAINPINE, 0x3000,
2980 0, 0, pbn_b0_1_115200 },
2981 { /* IQ Express F1 */
2982 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2983 PCI_VENDOR_ID_MAINPINE, 0x3100,
2984 0, 0, pbn_b0_1_115200 },
2985 { /* IQ Express D2 */
2986 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2987 PCI_VENDOR_ID_MAINPINE, 0x3200,
2988 0, 0, pbn_b0_2_115200 },
2989 { /* IQ Express F2 */
2990 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2991 PCI_VENDOR_ID_MAINPINE, 0x3300,
2992 0, 0, pbn_b0_2_115200 },
2993 { /* IQ Express D4 */
2994 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2995 PCI_VENDOR_ID_MAINPINE, 0x3400,
2996 0, 0, pbn_b0_4_115200 },
2997 { /* IQ Express F4 */
2998 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2999 PCI_VENDOR_ID_MAINPINE, 0x3500,
3000 0, 0, pbn_b0_4_115200 },
3001 { /* IQ Express D8 */
3002 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3003 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3004 0, 0, pbn_b0_8_115200 },
3005 { /* IQ Express F8 */
3006 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3007 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3008 0, 0, pbn_b0_8_115200 },
3009
3010
aa798505
OJ		 3011 /*
3012 * PA Semi PA6T-1682M on-chip UART
3013 */
3014 { PCI_VENDOR_ID_PASEMI, 0xa004,
3015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3016 pbn_pasemi_1682M },
3017
02c9b5cf
KJ		 3018 /*
3019 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3020 */
3021 { PCI_VENDOR_ID_ADDIDATA,
3022 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3023 PCI_ANY_ID,
3024 PCI_ANY_ID,
3025 0,
3026 0,
3027 pbn_b0_4_115200 },
3028
3029 { PCI_VENDOR_ID_ADDIDATA,
3030 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3031 PCI_ANY_ID,
3032 PCI_ANY_ID,
3033 0,
3034 0,
3035 pbn_b0_2_115200 },
3036
3037 { PCI_VENDOR_ID_ADDIDATA,
3038 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3039 PCI_ANY_ID,
3040 PCI_ANY_ID,
3041 0,
3042 0,
3043 pbn_b0_1_115200 },
3044
3045 { PCI_VENDOR_ID_ADDIDATA_OLD,
3046 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3047 PCI_ANY_ID,
3048 PCI_ANY_ID,
3049 0,
3050 0,
3051 pbn_b1_8_115200 },
3052
3053 { PCI_VENDOR_ID_ADDIDATA,
3054 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3055 PCI_ANY_ID,
3056 PCI_ANY_ID,
3057 0,
3058 0,
3059 pbn_b0_4_115200 },
3060
3061 { PCI_VENDOR_ID_ADDIDATA,
3062 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3063 PCI_ANY_ID,
3064 PCI_ANY_ID,
3065 0,
3066 0,
3067 pbn_b0_2_115200 },
3068
3069 { PCI_VENDOR_ID_ADDIDATA,
3070 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3071 PCI_ANY_ID,
3072 PCI_ANY_ID,
3073 0,
3074 0,
3075 pbn_b0_1_115200 },
3076
3077 { PCI_VENDOR_ID_ADDIDATA,
3078 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3079 PCI_ANY_ID,
3080 PCI_ANY_ID,
3081 0,
3082 0,
3083 pbn_b0_4_115200 },
3084
3085 { PCI_VENDOR_ID_ADDIDATA,
3086 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3087 PCI_ANY_ID,
3088 PCI_ANY_ID,
3089 0,
3090 0,
3091 pbn_b0_2_115200 },
3092
3093 { PCI_VENDOR_ID_ADDIDATA,
3094 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3095 PCI_ANY_ID,
3096 PCI_ANY_ID,
3097 0,
3098 0,
3099 pbn_b0_1_115200 },
3100
3101 { PCI_VENDOR_ID_ADDIDATA,
3102 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3103 PCI_ANY_ID,
3104 PCI_ANY_ID,
3105 0,
3106 0,
3107 pbn_b0_8_115200 },
3108
25cf9bc1
JS		 3109 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3110 PCI_VENDOR_ID_IBM, 0x0299,
3111 0, 0, pbn_b0_bt_2_115200 },
3112
1da177e4
LT		 3113 /*
3114 * These entries match devices with class COMMUNICATION_SERIAL,
3115 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3116 */
3117 { PCI_ANY_ID, PCI_ANY_ID,
3118 PCI_ANY_ID, PCI_ANY_ID,
3119 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3120 0xffff00, pbn_default },
3121 { PCI_ANY_ID, PCI_ANY_ID,
3122 PCI_ANY_ID, PCI_ANY_ID,
3123 PCI_CLASS_COMMUNICATION_MODEM << 8,
3124 0xffff00, pbn_default },
3125 { PCI_ANY_ID, PCI_ANY_ID,
3126 PCI_ANY_ID, PCI_ANY_ID,
3127 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3128 0xffff00, pbn_default },
3129 { 0, }
3130};
3131
3132static struct pci_driver serial_pci_driver = {
3133 .name = "serial",
3134 .probe = pciserial_init_one,
3135 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 3136#ifdef CONFIG_PM
1da177e4
LT		 3137 .suspend = pciserial_suspend_one,
3138 .resume = pciserial_resume_one,
1d5e7996 3139#endif
1da177e4
LT		 3140 .id_table = serial_pci_tbl,
3141};
3142
3143static int __init serial8250_pci_init(void)
3144{
3145 return pci_register_driver(&serial_pci_driver);
3146}
3147
3148static void __exit serial8250_pci_exit(void)
3149{
3150 pci_unregister_driver(&serial_pci_driver);
3151}
3152
3153module_init(serial8250_pci_init);
3154module_exit(serial8250_pci_exit);
3155
3156MODULE_LICENSE("GPL");
3157MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3158MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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