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[SERIAL] support the Exsys EX-4055 4S four-port card
[deliverable/linux.git] / drivers / serial / 8250_pci.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include <linux/sched.h>
20#include <linux/string.h>
21#include <linux/kernel.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24#include <linux/tty.h>
25#include <linux/serial_core.h>
26#include <linux/8250_pci.h>
27#include <linux/bitops.h>
28
29#include <asm/byteorder.h>
30#include <asm/io.h>
31
32#include "8250.h"
33
34#undef SERIAL_DEBUG_PCI
35
1da177e4
LT		 36/*
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
40 * < 0 - error
41 */
42struct pci_serial_quirk {
43 u32 vendor;
44 u32 device;
45 u32 subvendor;
46 u32 subdevice;
47 int (*init)(struct pci_dev *dev);
70db3d91 48 int (*setup)(struct serial_private *, struct pciserial_board *,
05caac58 49 struct uart_port *, int);
1da177e4
LT		 50 void (*exit)(struct pci_dev *dev);
51};
52
53#define PCI_NUM_BAR_RESOURCES 6
54
55struct serial_private {
70db3d91 56 struct pci_dev *dev;
1da177e4
LT		 57 unsigned int nr;
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
60 int line[0];
61};
62
63static void moan_device(const char *str, struct pci_dev *dev)
64{
65 printk(KERN_WARNING "%s: %s\n"
66 KERN_WARNING "Please send the output of lspci -vv, this\n"
67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING "manufacturer and name of serial board or\n"
69 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
72}
73
74static int
70db3d91 75setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 76 int bar, int offset, int regshift)
77{
70db3d91 78 struct pci_dev *dev = priv->dev;
1da177e4
LT		 79 unsigned long base, len;
80
81 if (bar >= PCI_NUM_BAR_RESOURCES)
82 return -EINVAL;
83
72ce9a83
RK		 84 base = pci_resource_start(dev, bar);
85
1da177e4 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 87 len = pci_resource_len(dev, bar);
88
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap(base, len);
91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
94 port->iotype = UPIO_MEM;
72ce9a83 95 port->iobase = 0;
1da177e4
LT		 96 port->mapbase = base + offset;
97 port->membase = priv->remapped_bar[bar] + offset;
98 port->regshift = regshift;
99 } else {
1da177e4 100 port->iotype = UPIO_PORT;
72ce9a83
RK		 101 port->iobase = base + offset;
102 port->mapbase = 0;
103 port->membase = NULL;
104 port->regshift = 0;
1da177e4
LT		 105 }
106 return 0;
107}
108
109/*
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
112 */
113static int
70db3d91 114afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 115 struct uart_port *port, int idx)
116{
117 unsigned int bar, offset = board->first_offset;
118
119 bar = FL_GET_BASE(board->flags);
120 if (idx < 4)
121 bar += idx;
122 else {
123 bar = 4;
124 offset += (idx - 4) * board->uart_offset;
125 }
126
70db3d91 127 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 128}
129
130/*
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
136 */
137static int __devinit pci_hp_diva_init(struct pci_dev *dev)
138{
139 int rc = 0;
140
141 switch (dev->subsystem_device) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
146 rc = 3;
147 break;
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
149 rc = 2;
150 break;
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
152 rc = 4;
153 break;
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
155 rc = 1;
156 break;
157 }
158
159 return rc;
160}
161
162/*
163 * HP's Diva chip puts the 4th/5th serial port further out, and
164 * some serial ports are supposed to be hidden on certain models.
165 */
166static int
70db3d91 167pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 168 struct uart_port *port, int idx)
169{
170 unsigned int offset = board->first_offset;
171 unsigned int bar = FL_GET_BASE(board->flags);
172
70db3d91 173 switch (priv->dev->subsystem_device) {
1da177e4
LT		 174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
175 if (idx == 3)
176 idx++;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
179 if (idx > 0)
180 idx++;
181 if (idx > 2)
182 idx++;
183 break;
184 }
185 if (idx > 2)
186 offset = 0x18;
187
188 offset += idx * board->uart_offset;
189
70db3d91 190 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 191}
192
193/*
194 * Added for EKF Intel i960 serial boards
195 */
196static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
197{
198 unsigned long oldval;
199
200 if (!(dev->subsystem_device & 0x1000))
201 return -ENODEV;
202
203 /* is firmware started? */
204 pci_read_config_dword(dev, 0x44, (void*) &oldval);
205 if (oldval == 0x00001000L) { /* RESET value */
206 printk(KERN_DEBUG "Local i960 firmware missing");
207 return -ENODEV;
208 }
209 return 0;
210}
211
212/*
213 * Some PCI serial cards using the PLX 9050 PCI interface chip require
214 * that the card interrupt be explicitly enabled or disabled. This
215 * seems to be mainly needed on card using the PLX which also use I/O
216 * mapped memory.
217 */
218static int __devinit pci_plx9050_init(struct pci_dev *dev)
219{
220 u8 irq_config;
221 void __iomem *p;
222
223 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
224 moan_device("no memory in bar 0", dev);
225 return 0;
226 }
227
228 irq_config = 0x41;
add7b58e
BH		 229 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
230 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
1da177e4 231 irq_config = 0x43;
add7b58e 232 }
1da177e4
LT		 233 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
234 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
235 /*
236 * As the megawolf cards have the int pins active
237 * high, and have 2 UART chips, both ints must be
238 * enabled on the 9050. Also, the UARTS are set in
239 * 16450 mode by default, so we have to enable the
240 * 16C950 'enhanced' mode so that we can use the
241 * deep FIFOs
242 */
243 irq_config = 0x5b;
244 }
245
246 /*
247 * enable/disable interrupts
248 */
249 p = ioremap(pci_resource_start(dev, 0), 0x80);
250 if (p == NULL)
251 return -ENOMEM;
252 writel(irq_config, p + 0x4c);
253
254 /*
255 * Read the register back to ensure that it took effect.
256 */
257 readl(p + 0x4c);
258 iounmap(p);
259
260 return 0;
261}
262
263static void __devexit pci_plx9050_exit(struct pci_dev *dev)
264{
265 u8 __iomem *p;
266
267 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
268 return;
269
270 /*
271 * disable interrupts
272 */
273 p = ioremap(pci_resource_start(dev, 0), 0x80);
274 if (p != NULL) {
275 writel(0, p + 0x4c);
276
277 /*
278 * Read the register back to ensure that it took effect.
279 */
280 readl(p + 0x4c);
281 iounmap(p);
282 }
283}
284
285/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
286static int
70db3d91 287sbs_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 288 struct uart_port *port, int idx)
289{
290 unsigned int bar, offset = board->first_offset;
291
292 bar = 0;
293
294 if (idx < 4) {
295 /* first four channels map to 0, 0x100, 0x200, 0x300 */
296 offset += idx * board->uart_offset;
297 } else if (idx < 8) {
298 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
299 offset += idx * board->uart_offset + 0xC00;
300 } else /* we have only 8 ports on PMC-OCTALPRO */
301 return 1;
302
70db3d91 303 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 304}
305
306/*
307* This does initialization for PMC OCTALPRO cards:
308* maps the device memory, resets the UARTs (needed, bc
309* if the module is removed and inserted again, the card
310* is in the sleep mode) and enables global interrupt.
311*/
312
313/* global control register offset for SBS PMC-OctalPro */
314#define OCT_REG_CR_OFF 0x500
315
316static int __devinit sbs_init(struct pci_dev *dev)
317{
318 u8 __iomem *p;
319
320 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
321
322 if (p == NULL)
323 return -ENOMEM;
324 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
325 writeb(0x10,p + OCT_REG_CR_OFF);
326 udelay(50);
327 writeb(0x0,p + OCT_REG_CR_OFF);
328
329 /* Set bit-2 (INTENABLE) of Control Register */
330 writeb(0x4, p + OCT_REG_CR_OFF);
331 iounmap(p);
332
333 return 0;
334}
335
336/*
337 * Disables the global interrupt of PMC-OctalPro
338 */
339
340static void __devexit sbs_exit(struct pci_dev *dev)
341{
342 u8 __iomem *p;
343
344 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
345 if (p != NULL) {
346 writeb(0, p + OCT_REG_CR_OFF);
347 }
348 iounmap(p);
349}
350
351/*
352 * SIIG serial cards have an PCI interface chip which also controls
353 * the UART clocking frequency. Each UART can be clocked independently
354 * (except cards equiped with 4 UARTs) and initial clocking settings
355 * are stored in the EEPROM chip. It can cause problems because this
356 * version of serial driver doesn't support differently clocked UART's
357 * on single PCI card. To prevent this, initialization functions set
358 * high frequency clocking for all UART's on given card. It is safe (I
359 * hope) because it doesn't touch EEPROM settings to prevent conflicts
360 * with other OSes (like M$ DOS).
361 *
362 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
363 *
364 * There is two family of SIIG serial cards with different PCI
365 * interface chip and different configuration methods:
366 * - 10x cards have control registers in IO and/or memory space;
367 * - 20x cards have control registers in standard PCI configuration space.
368 *
67d74b87
RK		 369 * Note: all 10x cards have PCI device ids 0x10..
370 * all 20x cards have PCI device ids 0x20..
371 *
fbc0dc0d
AP		 372 * There are also Quartet Serial cards which use Oxford Semiconductor
373 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
374 *
1da177e4
LT		 375 * Note: some SIIG cards are probed by the parport_serial object.
376 */
377
378#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
379#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
380
381static int pci_siig10x_init(struct pci_dev *dev)
382{
383 u16 data;
384 void __iomem *p;
385
386 switch (dev->device & 0xfff8) {
387 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
388 data = 0xffdf;
389 break;
390 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
391 data = 0xf7ff;
392 break;
393 default: /* 1S1P, 4S */
394 data = 0xfffb;
395 break;
396 }
397
398 p = ioremap(pci_resource_start(dev, 0), 0x80);
399 if (p == NULL)
400 return -ENOMEM;
401
402 writew(readw(p + 0x28) & data, p + 0x28);
403 readw(p + 0x28);
404 iounmap(p);
405 return 0;
406}
407
408#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
409#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
410
411static int pci_siig20x_init(struct pci_dev *dev)
412{
413 u8 data;
414
415 /* Change clock frequency for the first UART. */
416 pci_read_config_byte(dev, 0x6f, &data);
417 pci_write_config_byte(dev, 0x6f, data & 0xef);
418
419 /* If this card has 2 UART, we have to do the same with second UART. */
420 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
421 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
422 pci_read_config_byte(dev, 0x73, &data);
423 pci_write_config_byte(dev, 0x73, data & 0xef);
424 }
425 return 0;
426}
427
67d74b87
RK		 428static int pci_siig_init(struct pci_dev *dev)
429{
430 unsigned int type = dev->device & 0xff00;
431
432 if (type == 0x1000)
433 return pci_siig10x_init(dev);
434 else if (type == 0x2000)
435 return pci_siig20x_init(dev);
436
437 moan_device("Unknown SIIG card", dev);
438 return -ENODEV;
439}
440
1da177e4
LT		 441/*
442 * Timedia has an explosion of boards, and to avoid the PCI table from
443 * growing *huge*, we use this function to collapse some 70 entries
444 * in the PCI table into one, for sanity's and compactness's sake.
445 */
446static unsigned short timedia_single_port[] = {
447 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
448};
449
450static unsigned short timedia_dual_port[] = {
451 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
452 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
453 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
454 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
455 0xD079, 0
456};
457
458static unsigned short timedia_quad_port[] = {
459 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
460 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
461 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
462 0xB157, 0
463};
464
465static unsigned short timedia_eight_port[] = {
466 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
467 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
468};
469
470static struct timedia_struct {
471 int num;
472 unsigned short *ids;
473} timedia_data[] = {
474 { 1, timedia_single_port },
475 { 2, timedia_dual_port },
476 { 4, timedia_quad_port },
477 { 8, timedia_eight_port },
478 { 0, NULL }
479};
480
481static int __devinit pci_timedia_init(struct pci_dev *dev)
482{
483 unsigned short *ids;
484 int i, j;
485
486 for (i = 0; timedia_data[i].num; i++) {
487 ids = timedia_data[i].ids;
488 for (j = 0; ids[j]; j++)
489 if (dev->subsystem_device == ids[j])
490 return timedia_data[i].num;
491 }
492 return 0;
493}
494
495/*
496 * Timedia/SUNIX uses a mixture of BARs and offsets
497 * Ugh, this is ugly as all hell --- TYT
498 */
499static int
70db3d91 500pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 501 struct uart_port *port, int idx)
502{
503 unsigned int bar = 0, offset = board->first_offset;
504
505 switch (idx) {
506 case 0:
507 bar = 0;
508 break;
509 case 1:
510 offset = board->uart_offset;
511 bar = 0;
512 break;
513 case 2:
514 bar = 1;
515 break;
516 case 3:
517 offset = board->uart_offset;
518 bar = 1;
519 case 4: /* BAR 2 */
520 case 5: /* BAR 3 */
521 case 6: /* BAR 4 */
522 case 7: /* BAR 5 */
523 bar = idx - 2;
524 }
525
70db3d91 526 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 527}
528
529/*
530 * Some Titan cards are also a little weird
531 */
532static int
70db3d91 533titan_400l_800l_setup(struct serial_private *priv,
1c7c1fe5 534 struct pciserial_board *board,
1da177e4
LT		 535 struct uart_port *port, int idx)
536{
537 unsigned int bar, offset = board->first_offset;
538
539 switch (idx) {
540 case 0:
541 bar = 1;
542 break;
543 case 1:
544 bar = 2;
545 break;
546 default:
547 bar = 4;
548 offset = (idx - 2) * board->uart_offset;
549 }
550
70db3d91 551 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 552}
553
554static int __devinit pci_xircom_init(struct pci_dev *dev)
555{
556 msleep(100);
557 return 0;
558}
559
560static int __devinit pci_netmos_init(struct pci_dev *dev)
561{
562 /* subdevice 0x00PS means <P> parallel, <S> serial */
563 unsigned int num_serial = dev->subsystem_device & 0xf;
564
565 if (num_serial == 0)
566 return -ENODEV;
567 return num_serial;
568}
569
570static int
70db3d91 571pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 572 struct uart_port *port, int idx)
573{
574 unsigned int bar, offset = board->first_offset, maxnr;
575
576 bar = FL_GET_BASE(board->flags);
577 if (board->flags & FL_BASE_BARS)
578 bar += idx;
579 else
580 offset += idx * board->uart_offset;
581
70db3d91 582 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) /
1da177e4
LT		 583 (8 << board->reg_shift);
584
585 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
586 return 1;
587
70db3d91 588 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 589}
590
591/* This should be in linux/pci_ids.h */
592#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
593#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
594#define PCI_DEVICE_ID_OCTPRO 0x0001
595#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
596#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
597#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
598#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
599
600/*
601 * Master list of serial port init/setup/exit quirks.
602 * This does not describe the general nature of the port.
603 * (ie, baud base, number and location of ports, etc)
604 *
605 * This list is ordered alphabetically by vendor then device.
606 * Specific entries must come before more generic entries.
607 */
608static struct pci_serial_quirk pci_serial_quirks[] = {
609 /*
610 * AFAVLAB cards.
611 * It is not clear whether this applies to all products.
612 */
613 {
614 .vendor = PCI_VENDOR_ID_AFAVLAB,
615 .device = PCI_ANY_ID,
616 .subvendor = PCI_ANY_ID,
617 .subdevice = PCI_ANY_ID,
618 .setup = afavlab_setup,
619 },
620 /*
621 * HP Diva
622 */
623 {
624 .vendor = PCI_VENDOR_ID_HP,
625 .device = PCI_DEVICE_ID_HP_DIVA,
626 .subvendor = PCI_ANY_ID,
627 .subdevice = PCI_ANY_ID,
628 .init = pci_hp_diva_init,
629 .setup = pci_hp_diva_setup,
630 },
631 /*
632 * Intel
633 */
634 {
635 .vendor = PCI_VENDOR_ID_INTEL,
636 .device = PCI_DEVICE_ID_INTEL_80960_RP,
637 .subvendor = 0xe4bf,
638 .subdevice = PCI_ANY_ID,
639 .init = pci_inteli960ni_init,
640 .setup = pci_default_setup,
641 },
642 /*
643 * Panacom
644 */
645 {
646 .vendor = PCI_VENDOR_ID_PANACOM,
647 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
648 .subvendor = PCI_ANY_ID,
649 .subdevice = PCI_ANY_ID,
650 .init = pci_plx9050_init,
651 .setup = pci_default_setup,
652 .exit = __devexit_p(pci_plx9050_exit),
653 },
654 {
655 .vendor = PCI_VENDOR_ID_PANACOM,
656 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
657 .subvendor = PCI_ANY_ID,
658 .subdevice = PCI_ANY_ID,
659 .init = pci_plx9050_init,
660 .setup = pci_default_setup,
661 .exit = __devexit_p(pci_plx9050_exit),
662 },
663 /*
664 * PLX
665 */
add7b58e
BH		 666 {
667 .vendor = PCI_VENDOR_ID_PLX,
668 .device = PCI_DEVICE_ID_PLX_9050,
669 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
670 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
671 .init = pci_plx9050_init,
672 .setup = pci_default_setup,
673 .exit = __devexit_p(pci_plx9050_exit),
674 },
1da177e4
LT		 675 {
676 .vendor = PCI_VENDOR_ID_PLX,
677 .device = PCI_DEVICE_ID_PLX_9050,
678 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
679 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
680 .init = pci_plx9050_init,
681 .setup = pci_default_setup,
682 .exit = __devexit_p(pci_plx9050_exit),
683 },
684 {
685 .vendor = PCI_VENDOR_ID_PLX,
686 .device = PCI_DEVICE_ID_PLX_ROMULUS,
687 .subvendor = PCI_VENDOR_ID_PLX,
688 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
689 .init = pci_plx9050_init,
690 .setup = pci_default_setup,
691 .exit = __devexit_p(pci_plx9050_exit),
692 },
693 /*
694 * SBS Technologies, Inc., PMC-OCTALPRO 232
695 */
696 {
697 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
698 .device = PCI_DEVICE_ID_OCTPRO,
699 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
700 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
701 .init = sbs_init,
702 .setup = sbs_setup,
703 .exit = __devexit_p(sbs_exit),
704 },
705 /*
706 * SBS Technologies, Inc., PMC-OCTALPRO 422
707 */
708 {
709 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
710 .device = PCI_DEVICE_ID_OCTPRO,
711 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
712 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
713 .init = sbs_init,
714 .setup = sbs_setup,
715 .exit = __devexit_p(sbs_exit),
716 },
717 /*
718 * SBS Technologies, Inc., P-Octal 232
719 */
720 {
721 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
722 .device = PCI_DEVICE_ID_OCTPRO,
723 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
724 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
725 .init = sbs_init,
726 .setup = sbs_setup,
727 .exit = __devexit_p(sbs_exit),
728 },
729 /*
730 * SBS Technologies, Inc., P-Octal 422
731 */
732 {
733 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
734 .device = PCI_DEVICE_ID_OCTPRO,
735 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
736 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
737 .init = sbs_init,
738 .setup = sbs_setup,
739 .exit = __devexit_p(sbs_exit),
740 },
1da177e4
LT		 741 /*
742 * SIIG cards.
1da177e4
LT		 743 */
744 {
745 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 746 .device = PCI_ANY_ID,
1da177e4
LT		 747 .subvendor = PCI_ANY_ID,
748 .subdevice = PCI_ANY_ID,
67d74b87 749 .init = pci_siig_init,
1da177e4
LT		 750 .setup = pci_default_setup,
751 },
752 /*
753 * Titan cards
754 */
755 {
756 .vendor = PCI_VENDOR_ID_TITAN,
757 .device = PCI_DEVICE_ID_TITAN_400L,
758 .subvendor = PCI_ANY_ID,
759 .subdevice = PCI_ANY_ID,
760 .setup = titan_400l_800l_setup,
761 },
762 {
763 .vendor = PCI_VENDOR_ID_TITAN,
764 .device = PCI_DEVICE_ID_TITAN_800L,
765 .subvendor = PCI_ANY_ID,
766 .subdevice = PCI_ANY_ID,
767 .setup = titan_400l_800l_setup,
768 },
769 /*
770 * Timedia cards
771 */
772 {
773 .vendor = PCI_VENDOR_ID_TIMEDIA,
774 .device = PCI_DEVICE_ID_TIMEDIA_1889,
775 .subvendor = PCI_VENDOR_ID_TIMEDIA,
776 .subdevice = PCI_ANY_ID,
777 .init = pci_timedia_init,
778 .setup = pci_timedia_setup,
779 },
780 {
781 .vendor = PCI_VENDOR_ID_TIMEDIA,
782 .device = PCI_ANY_ID,
783 .subvendor = PCI_ANY_ID,
784 .subdevice = PCI_ANY_ID,
785 .setup = pci_timedia_setup,
786 },
787 /*
788 * Xircom cards
789 */
790 {
791 .vendor = PCI_VENDOR_ID_XIRCOM,
792 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
793 .subvendor = PCI_ANY_ID,
794 .subdevice = PCI_ANY_ID,
795 .init = pci_xircom_init,
796 .setup = pci_default_setup,
797 },
798 /*
799 * Netmos cards
800 */
801 {
802 .vendor = PCI_VENDOR_ID_NETMOS,
803 .device = PCI_ANY_ID,
804 .subvendor = PCI_ANY_ID,
805 .subdevice = PCI_ANY_ID,
806 .init = pci_netmos_init,
807 .setup = pci_default_setup,
808 },
809 /*
810 * Default "match everything" terminator entry
811 */
812 {
813 .vendor = PCI_ANY_ID,
814 .device = PCI_ANY_ID,
815 .subvendor = PCI_ANY_ID,
816 .subdevice = PCI_ANY_ID,
817 .setup = pci_default_setup,
818 }
819};
820
821static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
822{
823 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
824}
825
826static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
827{
828 struct pci_serial_quirk *quirk;
829
830 for (quirk = pci_serial_quirks; ; quirk++)
831 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
832 quirk_id_matches(quirk->device, dev->device) &&
833 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
834 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
835 break;
836 return quirk;
837}
838
839static _INLINE_ int
72ce9a83 840get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
1da177e4
LT		 841{
842 if (board->flags & FL_NOIRQ)
843 return 0;
844 else
845 return dev->irq;
846}
847
848/*
849 * This is the configuration table for all of the PCI serial boards
850 * which we support. It is directly indexed by the pci_board_num_t enum
851 * value, which is encoded in the pci_device_id PCI probe table's
852 * driver_data member.
853 *
854 * The makeup of these names are:
855 * pbn_bn{_bt}_n_baud
856 *
857 * bn = PCI BAR number
858 * bt = Index using PCI BARs
859 * n = number of serial ports
860 * baud = baud rate
861 *
f1690f37
RK		 862 * This table is sorted by (in order): baud, bt, bn, n.
863 *
1da177e4
LT		 864 * Please note: in theory if n = 1, _bt infix should make no difference.
865 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
866 */
867enum pci_board_num_t {
868 pbn_default = 0,
869
870 pbn_b0_1_115200,
871 pbn_b0_2_115200,
872 pbn_b0_4_115200,
873 pbn_b0_5_115200,
874
875 pbn_b0_1_921600,
876 pbn_b0_2_921600,
877 pbn_b0_4_921600,
878
db1de159
DR		 879 pbn_b0_2_1130000,
880
fbc0dc0d
AP		 881 pbn_b0_4_1152000,
882
1da177e4
LT		 883 pbn_b0_bt_1_115200,
884 pbn_b0_bt_2_115200,
885 pbn_b0_bt_8_115200,
886
887 pbn_b0_bt_1_460800,
888 pbn_b0_bt_2_460800,
889 pbn_b0_bt_4_460800,
890
891 pbn_b0_bt_1_921600,
892 pbn_b0_bt_2_921600,
893 pbn_b0_bt_4_921600,
894 pbn_b0_bt_8_921600,
895
896 pbn_b1_1_115200,
897 pbn_b1_2_115200,
898 pbn_b1_4_115200,
899 pbn_b1_8_115200,
900
901 pbn_b1_1_921600,
902 pbn_b1_2_921600,
903 pbn_b1_4_921600,
904 pbn_b1_8_921600,
905
906 pbn_b1_bt_2_921600,
907
908 pbn_b1_1_1382400,
909 pbn_b1_2_1382400,
910 pbn_b1_4_1382400,
911 pbn_b1_8_1382400,
912
913 pbn_b2_1_115200,
914 pbn_b2_8_115200,
915
916 pbn_b2_1_460800,
917 pbn_b2_4_460800,
918 pbn_b2_8_460800,
919 pbn_b2_16_460800,
920
921 pbn_b2_1_921600,
922 pbn_b2_4_921600,
923 pbn_b2_8_921600,
924
925 pbn_b2_bt_1_115200,
926 pbn_b2_bt_2_115200,
927 pbn_b2_bt_4_115200,
928
929 pbn_b2_bt_2_921600,
930 pbn_b2_bt_4_921600,
931
932 pbn_b3_4_115200,
933 pbn_b3_8_115200,
934
935 /*
936 * Board-specific versions.
937 */
938 pbn_panacom,
939 pbn_panacom2,
940 pbn_panacom4,
add7b58e 941 pbn_exsys_4055,
1da177e4
LT		 942 pbn_plx_romulus,
943 pbn_oxsemi,
944 pbn_intel_i960,
945 pbn_sgi_ioc3,
946 pbn_nec_nile4,
947 pbn_computone_4,
948 pbn_computone_6,
949 pbn_computone_8,
950 pbn_sbsxrsio,
951 pbn_exar_XR17C152,
952 pbn_exar_XR17C154,
953 pbn_exar_XR17C158,
954};
955
956/*
957 * uart_offset - the space between channels
958 * reg_shift - describes how the UART registers are mapped
959 * to PCI memory by the card.
960 * For example IER register on SBS, Inc. PMC-OctPro is located at
961 * offset 0x10 from the UART base, while UART_IER is defined as 1
962 * in include/linux/serial_reg.h,
963 * see first lines of serial_in() and serial_out() in 8250.c
964*/
965
1c7c1fe5 966static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 967 [pbn_default] = {
968 .flags = FL_BASE0,
969 .num_ports = 1,
970 .base_baud = 115200,
971 .uart_offset = 8,
972 },
973 [pbn_b0_1_115200] = {
974 .flags = FL_BASE0,
975 .num_ports = 1,
976 .base_baud = 115200,
977 .uart_offset = 8,
978 },
979 [pbn_b0_2_115200] = {
980 .flags = FL_BASE0,
981 .num_ports = 2,
982 .base_baud = 115200,
983 .uart_offset = 8,
984 },
985 [pbn_b0_4_115200] = {
986 .flags = FL_BASE0,
987 .num_ports = 4,
988 .base_baud = 115200,
989 .uart_offset = 8,
990 },
991 [pbn_b0_5_115200] = {
992 .flags = FL_BASE0,
993 .num_ports = 5,
994 .base_baud = 115200,
995 .uart_offset = 8,
996 },
997
998 [pbn_b0_1_921600] = {
999 .flags = FL_BASE0,
1000 .num_ports = 1,
1001 .base_baud = 921600,
1002 .uart_offset = 8,
1003 },
1004 [pbn_b0_2_921600] = {
1005 .flags = FL_BASE0,
1006 .num_ports = 2,
1007 .base_baud = 921600,
1008 .uart_offset = 8,
1009 },
1010 [pbn_b0_4_921600] = {
1011 .flags = FL_BASE0,
1012 .num_ports = 4,
1013 .base_baud = 921600,
1014 .uart_offset = 8,
1015 },
db1de159
DR		 1016
1017 [pbn_b0_2_1130000] = {
1018 .flags = FL_BASE0,
1019 .num_ports = 2,
1020 .base_baud = 1130000,
1021 .uart_offset = 8,
1022 },
1023
fbc0dc0d
AP		 1024 [pbn_b0_4_1152000] = {
1025 .flags = FL_BASE0,
1026 .num_ports = 4,
1027 .base_baud = 1152000,
1028 .uart_offset = 8,
1029 },
1da177e4
LT		 1030
1031 [pbn_b0_bt_1_115200] = {
1032 .flags = FL_BASE0|FL_BASE_BARS,
1033 .num_ports = 1,
1034 .base_baud = 115200,
1035 .uart_offset = 8,
1036 },
1037 [pbn_b0_bt_2_115200] = {
1038 .flags = FL_BASE0|FL_BASE_BARS,
1039 .num_ports = 2,
1040 .base_baud = 115200,
1041 .uart_offset = 8,
1042 },
1043 [pbn_b0_bt_8_115200] = {
1044 .flags = FL_BASE0|FL_BASE_BARS,
1045 .num_ports = 8,
1046 .base_baud = 115200,
1047 .uart_offset = 8,
1048 },
1049
1050 [pbn_b0_bt_1_460800] = {
1051 .flags = FL_BASE0|FL_BASE_BARS,
1052 .num_ports = 1,
1053 .base_baud = 460800,
1054 .uart_offset = 8,
1055 },
1056 [pbn_b0_bt_2_460800] = {
1057 .flags = FL_BASE0|FL_BASE_BARS,
1058 .num_ports = 2,
1059 .base_baud = 460800,
1060 .uart_offset = 8,
1061 },
1062 [pbn_b0_bt_4_460800] = {
1063 .flags = FL_BASE0|FL_BASE_BARS,
1064 .num_ports = 4,
1065 .base_baud = 460800,
1066 .uart_offset = 8,
1067 },
1068
1069 [pbn_b0_bt_1_921600] = {
1070 .flags = FL_BASE0|FL_BASE_BARS,
1071 .num_ports = 1,
1072 .base_baud = 921600,
1073 .uart_offset = 8,
1074 },
1075 [pbn_b0_bt_2_921600] = {
1076 .flags = FL_BASE0|FL_BASE_BARS,
1077 .num_ports = 2,
1078 .base_baud = 921600,
1079 .uart_offset = 8,
1080 },
1081 [pbn_b0_bt_4_921600] = {
1082 .flags = FL_BASE0|FL_BASE_BARS,
1083 .num_ports = 4,
1084 .base_baud = 921600,
1085 .uart_offset = 8,
1086 },
1087 [pbn_b0_bt_8_921600] = {
1088 .flags = FL_BASE0|FL_BASE_BARS,
1089 .num_ports = 8,
1090 .base_baud = 921600,
1091 .uart_offset = 8,
1092 },
1093
1094 [pbn_b1_1_115200] = {
1095 .flags = FL_BASE1,
1096 .num_ports = 1,
1097 .base_baud = 115200,
1098 .uart_offset = 8,
1099 },
1100 [pbn_b1_2_115200] = {
1101 .flags = FL_BASE1,
1102 .num_ports = 2,
1103 .base_baud = 115200,
1104 .uart_offset = 8,
1105 },
1106 [pbn_b1_4_115200] = {
1107 .flags = FL_BASE1,
1108 .num_ports = 4,
1109 .base_baud = 115200,
1110 .uart_offset = 8,
1111 },
1112 [pbn_b1_8_115200] = {
1113 .flags = FL_BASE1,
1114 .num_ports = 8,
1115 .base_baud = 115200,
1116 .uart_offset = 8,
1117 },
1118
1119 [pbn_b1_1_921600] = {
1120 .flags = FL_BASE1,
1121 .num_ports = 1,
1122 .base_baud = 921600,
1123 .uart_offset = 8,
1124 },
1125 [pbn_b1_2_921600] = {
1126 .flags = FL_BASE1,
1127 .num_ports = 2,
1128 .base_baud = 921600,
1129 .uart_offset = 8,
1130 },
1131 [pbn_b1_4_921600] = {
1132 .flags = FL_BASE1,
1133 .num_ports = 4,
1134 .base_baud = 921600,
1135 .uart_offset = 8,
1136 },
1137 [pbn_b1_8_921600] = {
1138 .flags = FL_BASE1,
1139 .num_ports = 8,
1140 .base_baud = 921600,
1141 .uart_offset = 8,
1142 },
1143
1144 [pbn_b1_bt_2_921600] = {
1145 .flags = FL_BASE1|FL_BASE_BARS,
1146 .num_ports = 2,
1147 .base_baud = 921600,
1148 .uart_offset = 8,
1149 },
1150
1151 [pbn_b1_1_1382400] = {
1152 .flags = FL_BASE1,
1153 .num_ports = 1,
1154 .base_baud = 1382400,
1155 .uart_offset = 8,
1156 },
1157 [pbn_b1_2_1382400] = {
1158 .flags = FL_BASE1,
1159 .num_ports = 2,
1160 .base_baud = 1382400,
1161 .uart_offset = 8,
1162 },
1163 [pbn_b1_4_1382400] = {
1164 .flags = FL_BASE1,
1165 .num_ports = 4,
1166 .base_baud = 1382400,
1167 .uart_offset = 8,
1168 },
1169 [pbn_b1_8_1382400] = {
1170 .flags = FL_BASE1,
1171 .num_ports = 8,
1172 .base_baud = 1382400,
1173 .uart_offset = 8,
1174 },
1175
1176 [pbn_b2_1_115200] = {
1177 .flags = FL_BASE2,
1178 .num_ports = 1,
1179 .base_baud = 115200,
1180 .uart_offset = 8,
1181 },
1182 [pbn_b2_8_115200] = {
1183 .flags = FL_BASE2,
1184 .num_ports = 8,
1185 .base_baud = 115200,
1186 .uart_offset = 8,
1187 },
1188
1189 [pbn_b2_1_460800] = {
1190 .flags = FL_BASE2,
1191 .num_ports = 1,
1192 .base_baud = 460800,
1193 .uart_offset = 8,
1194 },
1195 [pbn_b2_4_460800] = {
1196 .flags = FL_BASE2,
1197 .num_ports = 4,
1198 .base_baud = 460800,
1199 .uart_offset = 8,
1200 },
1201 [pbn_b2_8_460800] = {
1202 .flags = FL_BASE2,
1203 .num_ports = 8,
1204 .base_baud = 460800,
1205 .uart_offset = 8,
1206 },
1207 [pbn_b2_16_460800] = {
1208 .flags = FL_BASE2,
1209 .num_ports = 16,
1210 .base_baud = 460800,
1211 .uart_offset = 8,
1212 },
1213
1214 [pbn_b2_1_921600] = {
1215 .flags = FL_BASE2,
1216 .num_ports = 1,
1217 .base_baud = 921600,
1218 .uart_offset = 8,
1219 },
1220 [pbn_b2_4_921600] = {
1221 .flags = FL_BASE2,
1222 .num_ports = 4,
1223 .base_baud = 921600,
1224 .uart_offset = 8,
1225 },
1226 [pbn_b2_8_921600] = {
1227 .flags = FL_BASE2,
1228 .num_ports = 8,
1229 .base_baud = 921600,
1230 .uart_offset = 8,
1231 },
1232
1233 [pbn_b2_bt_1_115200] = {
1234 .flags = FL_BASE2|FL_BASE_BARS,
1235 .num_ports = 1,
1236 .base_baud = 115200,
1237 .uart_offset = 8,
1238 },
1239 [pbn_b2_bt_2_115200] = {
1240 .flags = FL_BASE2|FL_BASE_BARS,
1241 .num_ports = 2,
1242 .base_baud = 115200,
1243 .uart_offset = 8,
1244 },
1245 [pbn_b2_bt_4_115200] = {
1246 .flags = FL_BASE2|FL_BASE_BARS,
1247 .num_ports = 4,
1248 .base_baud = 115200,
1249 .uart_offset = 8,
1250 },
1251
1252 [pbn_b2_bt_2_921600] = {
1253 .flags = FL_BASE2|FL_BASE_BARS,
1254 .num_ports = 2,
1255 .base_baud = 921600,
1256 .uart_offset = 8,
1257 },
1258 [pbn_b2_bt_4_921600] = {
1259 .flags = FL_BASE2|FL_BASE_BARS,
1260 .num_ports = 4,
1261 .base_baud = 921600,
1262 .uart_offset = 8,
1263 },
1264
1265 [pbn_b3_4_115200] = {
1266 .flags = FL_BASE3,
1267 .num_ports = 4,
1268 .base_baud = 115200,
1269 .uart_offset = 8,
1270 },
1271 [pbn_b3_8_115200] = {
1272 .flags = FL_BASE3,
1273 .num_ports = 8,
1274 .base_baud = 115200,
1275 .uart_offset = 8,
1276 },
1277
1278 /*
1279 * Entries following this are board-specific.
1280 */
1281
1282 /*
1283 * Panacom - IOMEM
1284 */
1285 [pbn_panacom] = {
1286 .flags = FL_BASE2,
1287 .num_ports = 2,
1288 .base_baud = 921600,
1289 .uart_offset = 0x400,
1290 .reg_shift = 7,
1291 },
1292 [pbn_panacom2] = {
1293 .flags = FL_BASE2|FL_BASE_BARS,
1294 .num_ports = 2,
1295 .base_baud = 921600,
1296 .uart_offset = 0x400,
1297 .reg_shift = 7,
1298 },
1299 [pbn_panacom4] = {
1300 .flags = FL_BASE2|FL_BASE_BARS,
1301 .num_ports = 4,
1302 .base_baud = 921600,
1303 .uart_offset = 0x400,
1304 .reg_shift = 7,
1305 },
1306
add7b58e
BH		 1307 [pbn_exsys_4055] = {
1308 .flags = FL_BASE2,
1309 .num_ports = 4,
1310 .base_baud = 115200,
1311 .uart_offset = 8,
1312 },
1313
1da177e4
LT		 1314 /* I think this entry is broken - the first_offset looks wrong --rmk */
1315 [pbn_plx_romulus] = {
1316 .flags = FL_BASE2,
1317 .num_ports = 4,
1318 .base_baud = 921600,
1319 .uart_offset = 8 << 2,
1320 .reg_shift = 2,
1321 .first_offset = 0x03,
1322 },
1323
1324 /*
1325 * This board uses the size of PCI Base region 0 to
1326 * signal now many ports are available
1327 */
1328 [pbn_oxsemi] = {
1329 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1330 .num_ports = 32,
1331 .base_baud = 115200,
1332 .uart_offset = 8,
1333 },
1334
1335 /*
1336 * EKF addition for i960 Boards form EKF with serial port.
1337 * Max 256 ports.
1338 */
1339 [pbn_intel_i960] = {
1340 .flags = FL_BASE0,
1341 .num_ports = 32,
1342 .base_baud = 921600,
1343 .uart_offset = 8 << 2,
1344 .reg_shift = 2,
1345 .first_offset = 0x10000,
1346 },
1347 [pbn_sgi_ioc3] = {
1348 .flags = FL_BASE0|FL_NOIRQ,
1349 .num_ports = 1,
1350 .base_baud = 458333,
1351 .uart_offset = 8,
1352 .reg_shift = 0,
1353 .first_offset = 0x20178,
1354 },
1355
1356 /*
1357 * NEC Vrc-5074 (Nile 4) builtin UART.
1358 */
1359 [pbn_nec_nile4] = {
1360 .flags = FL_BASE0,
1361 .num_ports = 1,
1362 .base_baud = 520833,
1363 .uart_offset = 8 << 3,
1364 .reg_shift = 3,
1365 .first_offset = 0x300,
1366 },
1367
1368 /*
1369 * Computone - uses IOMEM.
1370 */
1371 [pbn_computone_4] = {
1372 .flags = FL_BASE0,
1373 .num_ports = 4,
1374 .base_baud = 921600,
1375 .uart_offset = 0x40,
1376 .reg_shift = 2,
1377 .first_offset = 0x200,
1378 },
1379 [pbn_computone_6] = {
1380 .flags = FL_BASE0,
1381 .num_ports = 6,
1382 .base_baud = 921600,
1383 .uart_offset = 0x40,
1384 .reg_shift = 2,
1385 .first_offset = 0x200,
1386 },
1387 [pbn_computone_8] = {
1388 .flags = FL_BASE0,
1389 .num_ports = 8,
1390 .base_baud = 921600,
1391 .uart_offset = 0x40,
1392 .reg_shift = 2,
1393 .first_offset = 0x200,
1394 },
1395 [pbn_sbsxrsio] = {
1396 .flags = FL_BASE0,
1397 .num_ports = 8,
1398 .base_baud = 460800,
1399 .uart_offset = 256,
1400 .reg_shift = 4,
1401 },
1402 /*
1403 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1404 * Only basic 16550A support.
1405 * XR17C15[24] are not tested, but they should work.
1406 */
1407 [pbn_exar_XR17C152] = {
1408 .flags = FL_BASE0,
1409 .num_ports = 2,
1410 .base_baud = 921600,
1411 .uart_offset = 0x200,
1412 },
1413 [pbn_exar_XR17C154] = {
1414 .flags = FL_BASE0,
1415 .num_ports = 4,
1416 .base_baud = 921600,
1417 .uart_offset = 0x200,
1418 },
1419 [pbn_exar_XR17C158] = {
1420 .flags = FL_BASE0,
1421 .num_ports = 8,
1422 .base_baud = 921600,
1423 .uart_offset = 0x200,
1424 },
1425};
1426
1427/*
1428 * Given a complete unknown PCI device, try to use some heuristics to
1429 * guess what the configuration might be, based on the pitiful PCI
1430 * serial specs. Returns 0 on success, 1 on failure.
1431 */
1432static int __devinit
1c7c1fe5 1433serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4
LT		 1434{
1435 int num_iomem, num_port, first_port = -1, i;
1436
1437 /*
1438 * If it is not a communications device or the programming
1439 * interface is greater than 6, give up.
1440 *
1441 * (Should we try to make guesses for multiport serial devices
1442 * later?)
1443 */
1444 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1445 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1446 (dev->class & 0xff) > 6)
1447 return -ENODEV;
1448
1449 num_iomem = num_port = 0;
1450 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1451 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1452 num_port++;
1453 if (first_port == -1)
1454 first_port = i;
1455 }
1456 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1457 num_iomem++;
1458 }
1459
1460 /*
1461 * If there is 1 or 0 iomem regions, and exactly one port,
1462 * use it. We guess the number of ports based on the IO
1463 * region size.
1464 */
1465 if (num_iomem <= 1 && num_port == 1) {
1466 board->flags = first_port;
1467 board->num_ports = pci_resource_len(dev, first_port) / 8;
1468 return 0;
1469 }
1470
1471 /*
1472 * Now guess if we've got a board which indexes by BARs.
1473 * Each IO BAR should be 8 bytes, and they should follow
1474 * consecutively.
1475 */
1476 first_port = -1;
1477 num_port = 0;
1478 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1479 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1480 pci_resource_len(dev, i) == 8 &&
1481 (first_port == -1 || (first_port + num_port) == i)) {
1482 num_port++;
1483 if (first_port == -1)
1484 first_port = i;
1485 }
1486 }
1487
1488 if (num_port > 1) {
1489 board->flags = first_port | FL_BASE_BARS;
1490 board->num_ports = num_port;
1491 return 0;
1492 }
1493
1494 return -ENODEV;
1495}
1496
1497static inline int
1c7c1fe5
RK		 1498serial_pci_matches(struct pciserial_board *board,
1499 struct pciserial_board *guessed)
1da177e4
LT		 1500{
1501 return
1502 board->num_ports == guessed->num_ports &&
1503 board->base_baud == guessed->base_baud &&
1504 board->uart_offset == guessed->uart_offset &&
1505 board->reg_shift == guessed->reg_shift &&
1506 board->first_offset == guessed->first_offset;
1507}
1508
241fc436
RK		 1509struct serial_private *
1510pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 1511{
72ce9a83 1512 struct uart_port serial_port;
1da177e4 1513 struct serial_private *priv;
1da177e4
LT		 1514 struct pci_serial_quirk *quirk;
1515 int rc, nr_ports, i;
1516
1da177e4
LT		 1517 nr_ports = board->num_ports;
1518
1519 /*
1520 * Find an init and setup quirks.
1521 */
1522 quirk = find_quirk(dev);
1523
1524 /*
1525 * Run the new-style initialization function.
1526 * The initialization function returns:
1527 * <0 - error
1528 * 0 - use board->num_ports
1529 * >0 - number of ports
1530 */
1531 if (quirk->init) {
1532 rc = quirk->init(dev);
241fc436
RK		 1533 if (rc < 0) {
1534 priv = ERR_PTR(rc);
1535 goto err_out;
1536 }
1da177e4
LT		 1537 if (rc)
1538 nr_ports = rc;
1539 }
1540
1541 priv = kmalloc(sizeof(struct serial_private) +
1542 sizeof(unsigned int) * nr_ports,
1543 GFP_KERNEL);
1544 if (!priv) {
241fc436
RK		 1545 priv = ERR_PTR(-ENOMEM);
1546 goto err_deinit;
1da177e4
LT		 1547 }
1548
1549 memset(priv, 0, sizeof(struct serial_private) +
1550 sizeof(unsigned int) * nr_ports);
1551
70db3d91 1552 priv->dev = dev;
1da177e4 1553 priv->quirk = quirk;
1da177e4 1554
72ce9a83
RK		 1555 memset(&serial_port, 0, sizeof(struct uart_port));
1556 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1557 serial_port.uartclk = board->base_baud * 16;
1558 serial_port.irq = get_pci_irq(dev, board);
1559 serial_port.dev = &dev->dev;
1560
1da177e4 1561 for (i = 0; i < nr_ports; i++) {
70db3d91 1562 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 1563 break;
72ce9a83 1564
1da177e4
LT		 1565#ifdef SERIAL_DEBUG_PCI
1566 printk("Setup PCI port: port %x, irq %d, type %d\n",
1567 serial_port.iobase, serial_port.irq, serial_port.iotype);
1568#endif
1569
1570 priv->line[i] = serial8250_register_port(&serial_port);
1571 if (priv->line[i] < 0) {
1572 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1573 break;
1574 }
1575 }
1576
1577 priv->nr = i;
1578
241fc436 1579 return priv;
1da177e4 1580
241fc436 1581 err_deinit:
1da177e4
LT		 1582 if (quirk->exit)
1583 quirk->exit(dev);
241fc436
RK		 1584 err_out:
1585 return priv;
1da177e4 1586}
241fc436 1587EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 1588
241fc436 1589void pciserial_remove_ports(struct serial_private *priv)
1da177e4 1590{
056a8763
RK		 1591 struct pci_serial_quirk *quirk;
1592 int i;
1da177e4 1593
056a8763
RK		 1594 for (i = 0; i < priv->nr; i++)
1595 serial8250_unregister_port(priv->line[i]);
1da177e4 1596
056a8763
RK		 1597 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1598 if (priv->remapped_bar[i])
1599 iounmap(priv->remapped_bar[i]);
1600 priv->remapped_bar[i] = NULL;
1601 }
1da177e4 1602
056a8763
RK		 1603 /*
1604 * Find the exit quirks.
1605 */
241fc436 1606 quirk = find_quirk(priv->dev);
056a8763 1607 if (quirk->exit)
241fc436
RK		 1608 quirk->exit(priv->dev);
1609
1610 kfree(priv);
1611}
1612EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1613
1614void pciserial_suspend_ports(struct serial_private *priv)
1615{
1616 int i;
1617
1618 for (i = 0; i < priv->nr; i++)
1619 if (priv->line[i] >= 0)
1620 serial8250_suspend_port(priv->line[i]);
1621}
1622EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1623
1624void pciserial_resume_ports(struct serial_private *priv)
1625{
1626 int i;
1627
1628 /*
1629 * Ensure that the board is correctly configured.
1630 */
1631 if (priv->quirk->init)
1632 priv->quirk->init(priv->dev);
1633
1634 for (i = 0; i < priv->nr; i++)
1635 if (priv->line[i] >= 0)
1636 serial8250_resume_port(priv->line[i]);
1637}
1638EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1639
1640/*
1641 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1642 * to the arrangement of serial ports on a PCI card.
1643 */
1644static int __devinit
1645pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1646{
1647 struct serial_private *priv;
1648 struct pciserial_board *board, tmp;
1649 int rc;
1650
1651 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1652 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1653 ent->driver_data);
1654 return -EINVAL;
1655 }
1656
1657 board = &pci_boards[ent->driver_data];
1658
1659 rc = pci_enable_device(dev);
1660 if (rc)
1661 return rc;
1662
1663 if (ent->driver_data == pbn_default) {
1664 /*
1665 * Use a copy of the pci_board entry for this;
1666 * avoid changing entries in the table.
1667 */
1668 memcpy(&tmp, board, sizeof(struct pciserial_board));
1669 board = &tmp;
1670
1671 /*
1672 * We matched one of our class entries. Try to
1673 * determine the parameters of this board.
1674 */
1675 rc = serial_pci_guess_board(dev, board);
1676 if (rc)
1677 goto disable;
1678 } else {
1679 /*
1680 * We matched an explicit entry. If we are able to
1681 * detect this boards settings with our heuristic,
1682 * then we no longer need this entry.
1683 */
1684 memcpy(&tmp, &pci_boards[pbn_default],
1685 sizeof(struct pciserial_board));
1686 rc = serial_pci_guess_board(dev, &tmp);
1687 if (rc == 0 && serial_pci_matches(board, &tmp))
1688 moan_device("Redundant entry in serial pci_table.",
1689 dev);
1690 }
1691
1692 priv = pciserial_init_ports(dev, board);
1693 if (!IS_ERR(priv)) {
1694 pci_set_drvdata(dev, priv);
1695 return 0;
1696 }
1697
1698 rc = PTR_ERR(priv);
1da177e4 1699
241fc436 1700 disable:
056a8763 1701 pci_disable_device(dev);
241fc436
RK		 1702 return rc;
1703}
1da177e4 1704
241fc436
RK		 1705static void __devexit pciserial_remove_one(struct pci_dev *dev)
1706{
1707 struct serial_private *priv = pci_get_drvdata(dev);
1708
1709 pci_set_drvdata(dev, NULL);
1710
1711 pciserial_remove_ports(priv);
1712
1713 pci_disable_device(dev);
1da177e4
LT		 1714}
1715
1716static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1717{
1718 struct serial_private *priv = pci_get_drvdata(dev);
1719
241fc436
RK		 1720 if (priv)
1721 pciserial_suspend_ports(priv);
1da177e4 1722
1da177e4
LT		 1723 pci_save_state(dev);
1724 pci_set_power_state(dev, pci_choose_state(dev, state));
1725 return 0;
1726}
1727
1728static int pciserial_resume_one(struct pci_dev *dev)
1729{
1730 struct serial_private *priv = pci_get_drvdata(dev);
1731
1732 pci_set_power_state(dev, PCI_D0);
1733 pci_restore_state(dev);
1734
1735 if (priv) {
1da177e4
LT		 1736 /*
1737 * The device may have been disabled. Re-enable it.
1738 */
1739 pci_enable_device(dev);
1740
241fc436 1741 pciserial_resume_ports(priv);
1da177e4
LT		 1742 }
1743 return 0;
1744}
1745
1746static struct pci_device_id serial_pci_tbl[] = {
1747 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1748 PCI_SUBVENDOR_ID_CONNECT_TECH,
1749 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1750 pbn_b1_8_1382400 },
1751 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1752 PCI_SUBVENDOR_ID_CONNECT_TECH,
1753 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1754 pbn_b1_4_1382400 },
1755 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1756 PCI_SUBVENDOR_ID_CONNECT_TECH,
1757 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1758 pbn_b1_2_1382400 },
1759 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1760 PCI_SUBVENDOR_ID_CONNECT_TECH,
1761 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1762 pbn_b1_8_1382400 },
1763 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1764 PCI_SUBVENDOR_ID_CONNECT_TECH,
1765 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1766 pbn_b1_4_1382400 },
1767 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1768 PCI_SUBVENDOR_ID_CONNECT_TECH,
1769 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1770 pbn_b1_2_1382400 },
1771 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1772 PCI_SUBVENDOR_ID_CONNECT_TECH,
1773 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1774 pbn_b1_8_921600 },
1775 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1776 PCI_SUBVENDOR_ID_CONNECT_TECH,
1777 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1778 pbn_b1_8_921600 },
1779 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1780 PCI_SUBVENDOR_ID_CONNECT_TECH,
1781 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1782 pbn_b1_4_921600 },
1783 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1784 PCI_SUBVENDOR_ID_CONNECT_TECH,
1785 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1786 pbn_b1_4_921600 },
1787 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1788 PCI_SUBVENDOR_ID_CONNECT_TECH,
1789 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1790 pbn_b1_2_921600 },
1791 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1792 PCI_SUBVENDOR_ID_CONNECT_TECH,
1793 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1794 pbn_b1_8_921600 },
1795 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1796 PCI_SUBVENDOR_ID_CONNECT_TECH,
1797 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1798 pbn_b1_8_921600 },
1799 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1800 PCI_SUBVENDOR_ID_CONNECT_TECH,
1801 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1802 pbn_b1_4_921600 },
1803
1804 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1806 pbn_b2_bt_1_115200 },
1807 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1809 pbn_b2_bt_2_115200 },
1810 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1812 pbn_b2_bt_4_115200 },
1813 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1815 pbn_b2_bt_2_115200 },
1816 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1818 pbn_b2_bt_4_115200 },
1819 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1821 pbn_b2_8_115200 },
1822 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1824 pbn_b2_8_115200 },
1825
1826 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1828 pbn_b2_bt_2_115200 },
1829 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1831 pbn_b2_bt_2_921600 },
1832 /*
1833 * VScom SPCOM800, from sl@s.pl
1834 */
1835 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1837 pbn_b2_8_921600 },
1838 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1840 pbn_b2_4_921600 },
1841 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1842 PCI_SUBVENDOR_ID_KEYSPAN,
1843 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1844 pbn_panacom },
1845 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1847 pbn_panacom4 },
1848 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1849 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1850 pbn_panacom2 },
1851 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1852 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1853 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1854 pbn_b2_4_460800 },
1855 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1856 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1857 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1858 pbn_b2_8_460800 },
1859 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1860 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1861 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1862 pbn_b2_16_460800 },
1863 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1864 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1865 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1866 pbn_b2_16_460800 },
1867 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1868 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1869 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1870 pbn_b2_4_460800 },
1871 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1872 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1873 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1874 pbn_b2_8_460800 },
add7b58e
BH		 1875 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1876 PCI_SUBVENDOR_ID_EXSYS,
1877 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
1878 pbn_exsys_4055 },
1da177e4
LT		 1879 /*
1880 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1881 * (Exoray@isys.ca)
1882 */
1883 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1884 0x10b5, 0x106a, 0, 0,
1885 pbn_plx_romulus },
1886 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1888 pbn_b1_4_115200 },
1889 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1891 pbn_b1_2_115200 },
1892 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1894 pbn_b1_8_115200 },
1895 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1897 pbn_b1_8_115200 },
1898 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1899 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1900 pbn_b0_4_921600 },
fbc0dc0d
AP		 1901 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1902 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
1903 pbn_b0_4_1152000 },
db1de159
DR		 1904
1905 /*
1906 * The below card is a little controversial since it is the
1907 * subject of a PCI vendor/device ID clash. (See
1908 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
1909 * For now just used the hex ID 0x950a.
1910 */
1911 { PCI_VENDOR_ID_OXSEMI, 0x950a,
1912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1913 pbn_b0_2_1130000 },
1da177e4
LT		 1914 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1916 pbn_b0_4_115200 },
1917 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1919 pbn_b0_bt_2_921600 },
1920
1921 /*
1922 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1923 * from skokodyn@yahoo.com
1924 */
1925 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1926 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1927 pbn_sbsxrsio },
1928 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1929 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1930 pbn_sbsxrsio },
1931 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1932 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1933 pbn_sbsxrsio },
1934 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1935 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1936 pbn_sbsxrsio },
1937
1938 /*
1939 * Digitan DS560-558, from jimd@esoft.com
1940 */
1941 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1943 pbn_b1_1_115200 },
1944
1945 /*
1946 * Titan Electronic cards
1947 * The 400L and 800L have a custom setup quirk.
1948 */
1949 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1951 pbn_b0_1_921600 },
1952 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1954 pbn_b0_2_921600 },
1955 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1957 pbn_b0_4_921600 },
1958 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1960 pbn_b0_4_921600 },
1961 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1963 pbn_b1_1_921600 },
1964 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1966 pbn_b1_bt_2_921600 },
1967 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1969 pbn_b0_bt_4_921600 },
1970 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1972 pbn_b0_bt_8_921600 },
1973
1974 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1976 pbn_b2_1_460800 },
1977 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1979 pbn_b2_1_460800 },
1980 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1982 pbn_b2_1_460800 },
1983 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1985 pbn_b2_bt_2_921600 },
1986 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1988 pbn_b2_bt_2_921600 },
1989 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1991 pbn_b2_bt_2_921600 },
1992 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1994 pbn_b2_bt_4_921600 },
1995 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1997 pbn_b2_bt_4_921600 },
1998 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
1999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2000 pbn_b2_bt_4_921600 },
2001 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2003 pbn_b0_1_921600 },
2004 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2006 pbn_b0_1_921600 },
2007 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2009 pbn_b0_1_921600 },
2010 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2012 pbn_b0_bt_2_921600 },
2013 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2015 pbn_b0_bt_2_921600 },
2016 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2018 pbn_b0_bt_2_921600 },
2019 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2021 pbn_b0_bt_4_921600 },
2022 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2024 pbn_b0_bt_4_921600 },
2025 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2027 pbn_b0_bt_4_921600 },
2028
2029 /*
2030 * Computone devices submitted by Doug McNash dmcnash@computone.com
2031 */
2032 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2033 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2034 0, 0, pbn_computone_4 },
2035 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2036 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2037 0, 0, pbn_computone_8 },
2038 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2039 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2040 0, 0, pbn_computone_6 },
2041
2042 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2044 pbn_oxsemi },
2045 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2046 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2047 pbn_b0_bt_1_921600 },
2048
2049 /*
2050 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2051 */
2052 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2054 pbn_b0_bt_8_115200 },
2055 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2057 pbn_b0_bt_8_115200 },
2058
2059 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2061 pbn_b0_bt_2_115200 },
2062 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2064 pbn_b0_bt_2_115200 },
2065 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2067 pbn_b0_bt_2_115200 },
2068 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2070 pbn_b0_bt_4_460800 },
2071 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2073 pbn_b0_bt_4_460800 },
2074 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2076 pbn_b0_bt_2_460800 },
2077 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2079 pbn_b0_bt_2_460800 },
2080 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2082 pbn_b0_bt_2_460800 },
2083 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2085 pbn_b0_bt_1_115200 },
2086 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2088 pbn_b0_bt_1_460800 },
2089
2090 /*
2091 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2092 */
2093 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2095 pbn_b1_1_1382400 },
2096
2097 /*
2098 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2099 */
2100 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2102 pbn_b1_1_1382400 },
2103
2104 /*
2105 * RAStel 2 port modem, gerg@moreton.com.au
2106 */
2107 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2109 pbn_b2_bt_2_115200 },
2110
2111 /*
2112 * EKF addition for i960 Boards form EKF with serial port
2113 */
2114 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2115 0xE4BF, PCI_ANY_ID, 0, 0,
2116 pbn_intel_i960 },
2117
2118 /*
2119 * Xircom Cardbus/Ethernet combos
2120 */
2121 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2123 pbn_b0_1_115200 },
2124 /*
2125 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2126 */
2127 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2129 pbn_b0_1_115200 },
2130
2131 /*
2132 * Untested PCI modems, sent in from various folks...
2133 */
2134
2135 /*
2136 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2137 */
2138 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2139 0x1048, 0x1500, 0, 0,
2140 pbn_b1_1_115200 },
2141
2142 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2143 0xFF00, 0, 0, 0,
2144 pbn_sgi_ioc3 },
2145
2146 /*
2147 * HP Diva card
2148 */
2149 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2150 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2151 pbn_b1_1_115200 },
2152 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2154 pbn_b0_5_115200 },
2155 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2157 pbn_b2_1_115200 },
2158
2159 /*
2160 * NEC Vrc-5074 (Nile 4) builtin UART.
2161 */
2162 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2164 pbn_nec_nile4 },
2165
2166 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2168 pbn_b3_4_115200 },
2169 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2171 pbn_b3_8_115200 },
2172
2173 /*
2174 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2175 */
2176 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2177 PCI_ANY_ID, PCI_ANY_ID,
2178 0,
2179 0, pbn_exar_XR17C152 },
2180 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2181 PCI_ANY_ID, PCI_ANY_ID,
2182 0,
2183 0, pbn_exar_XR17C154 },
2184 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2185 PCI_ANY_ID, PCI_ANY_ID,
2186 0,
2187 0, pbn_exar_XR17C158 },
2188
2189 /*
2190 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2191 */
2192 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2194 pbn_b0_1_115200 },
2195
2196 /*
2197 * These entries match devices with class COMMUNICATION_SERIAL,
2198 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2199 */
2200 { PCI_ANY_ID, PCI_ANY_ID,
2201 PCI_ANY_ID, PCI_ANY_ID,
2202 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2203 0xffff00, pbn_default },
2204 { PCI_ANY_ID, PCI_ANY_ID,
2205 PCI_ANY_ID, PCI_ANY_ID,
2206 PCI_CLASS_COMMUNICATION_MODEM << 8,
2207 0xffff00, pbn_default },
2208 { PCI_ANY_ID, PCI_ANY_ID,
2209 PCI_ANY_ID, PCI_ANY_ID,
2210 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2211 0xffff00, pbn_default },
2212 { 0, }
2213};
2214
2215static struct pci_driver serial_pci_driver = {
2216 .name = "serial",
2217 .probe = pciserial_init_one,
2218 .remove = __devexit_p(pciserial_remove_one),
2219 .suspend = pciserial_suspend_one,
2220 .resume = pciserial_resume_one,
2221 .id_table = serial_pci_tbl,
2222};
2223
2224static int __init serial8250_pci_init(void)
2225{
2226 return pci_register_driver(&serial_pci_driver);
2227}
2228
2229static void __exit serial8250_pci_exit(void)
2230{
2231 pci_unregister_driver(&serial_pci_driver);
2232}
2233
2234module_init(serial8250_pci_init);
2235module_exit(serial8250_pci_exit);
2236
2237MODULE_LICENSE("GPL");
2238MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2239MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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