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ALSA: aaci - Fix alignment faults on ARM Cortex introduced by commit 29a4f2d3
[deliverable/linux.git] / drivers / serial / amba-pl011.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
1da177e4
LT		 25 * This is a generic driver for ARM AMBA-type serial ports. They
26 * have a lot of 16550-like features, but are not register compatible.
27 * Note that although they do have CTS, DCD and DSR inputs, they do
28 * not have an RI input, nor do they have DTR or RTS outputs. If
29 * required, these have to be supplied via some other means (eg, GPIO)
30 * and hooked into this driver.
31 */
1da177e4
LT		 32
33#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
a62c80e5
RK		 47#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
f8ce2547 49#include <linux/clk.h>
1da177e4
LT		 50
51#include <asm/io.h>
c6b8fdad 52#include <asm/sizes.h>
1da177e4
LT		 53
54#define UART_NR 14
55
56#define SERIAL_AMBA_MAJOR 204
57#define SERIAL_AMBA_MINOR 64
58#define SERIAL_AMBA_NR UART_NR
59
60#define AMBA_ISR_PASS_LIMIT 256
61
b63d4f0f
RK		 62#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
63#define UART_DUMMY_DR_RX (1 << 16)
1da177e4
LT		 64
65/*
66 * We wrap our port structure around the generic uart_port.
67 */
68struct uart_amba_port {
69 struct uart_port port;
70 struct clk *clk;
71 unsigned int im; /* interrupt mask */
72 unsigned int old_status;
5926a295 73 unsigned int ifls; /* vendor-specific */
3b43816f 74 bool autorts;
5926a295
AR		 75};
76
77/* There is by now at least one vendor with differing details, so handle it */
78struct vendor_data {
79 unsigned int ifls;
80 unsigned int fifosize;
81};
82
83static struct vendor_data vendor_arm = {
84 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
85 .fifosize = 16,
86};
87
88static struct vendor_data vendor_st = {
89 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
90 .fifosize = 64,
1da177e4
LT		 91};
92
b129a8cc 93static void pl011_stop_tx(struct uart_port *port)
1da177e4
LT		 94{
95 struct uart_amba_port *uap = (struct uart_amba_port *)port;
96
97 uap->im &= ~UART011_TXIM;
98 writew(uap->im, uap->port.membase + UART011_IMSC);
99}
100
b129a8cc 101static void pl011_start_tx(struct uart_port *port)
1da177e4
LT		 102{
103 struct uart_amba_port *uap = (struct uart_amba_port *)port;
104
105 uap->im |= UART011_TXIM;
106 writew(uap->im, uap->port.membase + UART011_IMSC);
107}
108
109static void pl011_stop_rx(struct uart_port *port)
110{
111 struct uart_amba_port *uap = (struct uart_amba_port *)port;
112
113 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
114 UART011_PEIM|UART011_BEIM|UART011_OEIM);
115 writew(uap->im, uap->port.membase + UART011_IMSC);
116}
117
118static void pl011_enable_ms(struct uart_port *port)
119{
120 struct uart_amba_port *uap = (struct uart_amba_port *)port;
121
122 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
123 writew(uap->im, uap->port.membase + UART011_IMSC);
124}
125
7d12e780 126static void pl011_rx_chars(struct uart_amba_port *uap)
1da177e4 127{
ebd2c8f6 128 struct tty_struct *tty = uap->port.state->port.tty;
b63d4f0f 129 unsigned int status, ch, flag, max_count = 256;
1da177e4
LT		 130
131 status = readw(uap->port.membase + UART01x_FR);
132 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
b63d4f0f 133 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
1da177e4
LT		 134 flag = TTY_NORMAL;
135 uap->port.icount.rx++;
136
137 /*
138 * Note that the error handling code is
139 * out of the main execution path
140 */
b63d4f0f
RK		 141 if (unlikely(ch & UART_DR_ERROR)) {
142 if (ch & UART011_DR_BE) {
143 ch &= ~(UART011_DR_FE | UART011_DR_PE);
1da177e4
LT		 144 uap->port.icount.brk++;
145 if (uart_handle_break(&uap->port))
146 goto ignore_char;
b63d4f0f 147 } else if (ch & UART011_DR_PE)
1da177e4 148 uap->port.icount.parity++;
b63d4f0f 149 else if (ch & UART011_DR_FE)
1da177e4 150 uap->port.icount.frame++;
b63d4f0f 151 if (ch & UART011_DR_OE)
1da177e4
LT		 152 uap->port.icount.overrun++;
153
b63d4f0f 154 ch &= uap->port.read_status_mask;
1da177e4 155
b63d4f0f 156 if (ch & UART011_DR_BE)
1da177e4 157 flag = TTY_BREAK;
b63d4f0f 158 else if (ch & UART011_DR_PE)
1da177e4 159 flag = TTY_PARITY;
b63d4f0f 160 else if (ch & UART011_DR_FE)
1da177e4
LT		 161 flag = TTY_FRAME;
162 }
163
7d12e780 164 if (uart_handle_sysrq_char(&uap->port, ch & 255))
1da177e4
LT		 165 goto ignore_char;
166
b63d4f0f 167 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
05ab3014 168
1da177e4
LT		 169 ignore_char:
170 status = readw(uap->port.membase + UART01x_FR);
171 }
2389b272 172 spin_unlock(&uap->port.lock);
1da177e4 173 tty_flip_buffer_push(tty);
2389b272 174 spin_lock(&uap->port.lock);
1da177e4
LT		 175}
176
177static void pl011_tx_chars(struct uart_amba_port *uap)
178{
ebd2c8f6 179 struct circ_buf *xmit = &uap->port.state->xmit;
1da177e4
LT		 180 int count;
181
182 if (uap->port.x_char) {
183 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
184 uap->port.icount.tx++;
185 uap->port.x_char = 0;
186 return;
187 }
188 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
b129a8cc 189 pl011_stop_tx(&uap->port);
1da177e4
LT		 190 return;
191 }
192
193 count = uap->port.fifosize >> 1;
194 do {
195 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
196 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
197 uap->port.icount.tx++;
198 if (uart_circ_empty(xmit))
199 break;
200 } while (--count > 0);
201
202 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
203 uart_write_wakeup(&uap->port);
204
205 if (uart_circ_empty(xmit))
b129a8cc 206 pl011_stop_tx(&uap->port);
1da177e4
LT		 207}
208
209static void pl011_modem_status(struct uart_amba_port *uap)
210{
211 unsigned int status, delta;
212
213 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
214
215 delta = status ^ uap->old_status;
216 uap->old_status = status;
217
218 if (!delta)
219 return;
220
221 if (delta & UART01x_FR_DCD)
222 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
223
224 if (delta & UART01x_FR_DSR)
225 uap->port.icount.dsr++;
226
227 if (delta & UART01x_FR_CTS)
228 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
229
bdc04e31 230 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 231}
232
7d12e780 233static irqreturn_t pl011_int(int irq, void *dev_id)
1da177e4
LT		 234{
235 struct uart_amba_port *uap = dev_id;
236 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
237 int handled = 0;
238
239 spin_lock(&uap->port.lock);
240
241 status = readw(uap->port.membase + UART011_MIS);
242 if (status) {
243 do {
244 writew(status & ~(UART011_TXIS|UART011_RTIS|
245 UART011_RXIS),
246 uap->port.membase + UART011_ICR);
247
248 if (status & (UART011_RTIS|UART011_RXIS))
1da177e4 249 pl011_rx_chars(uap);
1da177e4
LT		 250 if (status & (UART011_DSRMIS|UART011_DCDMIS|
251 UART011_CTSMIS|UART011_RIMIS))
252 pl011_modem_status(uap);
253 if (status & UART011_TXIS)
254 pl011_tx_chars(uap);
255
256 if (pass_counter-- == 0)
257 break;
258
259 status = readw(uap->port.membase + UART011_MIS);
260 } while (status != 0);
261 handled = 1;
262 }
263
264 spin_unlock(&uap->port.lock);
265
266 return IRQ_RETVAL(handled);
267}
268
269static unsigned int pl01x_tx_empty(struct uart_port *port)
270{
271 struct uart_amba_port *uap = (struct uart_amba_port *)port;
272 unsigned int status = readw(uap->port.membase + UART01x_FR);
273 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
274}
275
276static unsigned int pl01x_get_mctrl(struct uart_port *port)
277{
278 struct uart_amba_port *uap = (struct uart_amba_port *)port;
279 unsigned int result = 0;
280 unsigned int status = readw(uap->port.membase + UART01x_FR);
281
5159f407 282#define TIOCMBIT(uartbit, tiocmbit) \
1da177e4
LT		 283 if (status & uartbit) \
284 result |= tiocmbit
285
5159f407
JS		 286 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
287 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
288 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
289 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
290#undef TIOCMBIT
1da177e4
LT		 291 return result;
292}
293
294static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
295{
296 struct uart_amba_port *uap = (struct uart_amba_port *)port;
297 unsigned int cr;
298
299 cr = readw(uap->port.membase + UART011_CR);
300
5159f407 301#define TIOCMBIT(tiocmbit, uartbit) \
1da177e4
LT		 302 if (mctrl & tiocmbit) \
303 cr |= uartbit; \
304 else \
305 cr &= ~uartbit
306
5159f407
JS		 307 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
308 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
309 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
310 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
311 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
3b43816f
RV		 312
313 if (uap->autorts) {
314 /* We need to disable auto-RTS if we want to turn RTS off */
315 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
316 }
5159f407 317#undef TIOCMBIT
1da177e4
LT		 318
319 writew(cr, uap->port.membase + UART011_CR);
320}
321
322static void pl011_break_ctl(struct uart_port *port, int break_state)
323{
324 struct uart_amba_port *uap = (struct uart_amba_port *)port;
325 unsigned long flags;
326 unsigned int lcr_h;
327
328 spin_lock_irqsave(&uap->port.lock, flags);
329 lcr_h = readw(uap->port.membase + UART011_LCRH);
330 if (break_state == -1)
331 lcr_h |= UART01x_LCRH_BRK;
332 else
333 lcr_h &= ~UART01x_LCRH_BRK;
334 writew(lcr_h, uap->port.membase + UART011_LCRH);
335 spin_unlock_irqrestore(&uap->port.lock, flags);
336}
337
84b5ae15
JW		 338#ifdef CONFIG_CONSOLE_POLL
339static int pl010_get_poll_char(struct uart_port *port)
340{
341 struct uart_amba_port *uap = (struct uart_amba_port *)port;
342 unsigned int status;
343
344 do {
345 status = readw(uap->port.membase + UART01x_FR);
346 } while (status & UART01x_FR_RXFE);
347
348 return readw(uap->port.membase + UART01x_DR);
349}
350
351static void pl010_put_poll_char(struct uart_port *port,
352 unsigned char ch)
353{
354 struct uart_amba_port *uap = (struct uart_amba_port *)port;
355
356 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
357 barrier();
358
359 writew(ch, uap->port.membase + UART01x_DR);
360}
361
362#endif /* CONFIG_CONSOLE_POLL */
363
1da177e4
LT		 364static int pl011_startup(struct uart_port *port)
365{
366 struct uart_amba_port *uap = (struct uart_amba_port *)port;
367 unsigned int cr;
368 int retval;
369
370 /*
371 * Try to enable the clock producer.
372 */
373 retval = clk_enable(uap->clk);
374 if (retval)
375 goto out;
376
377 uap->port.uartclk = clk_get_rate(uap->clk);
378
379 /*
380 * Allocate the IRQ
381 */
382 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
383 if (retval)
384 goto clk_dis;
385
5926a295 386 writew(uap->ifls, uap->port.membase + UART011_IFLS);
1da177e4
LT		 387
388 /*
389 * Provoke TX FIFO interrupt into asserting.
390 */
391 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
392 writew(cr, uap->port.membase + UART011_CR);
393 writew(0, uap->port.membase + UART011_FBRD);
394 writew(1, uap->port.membase + UART011_IBRD);
395 writew(0, uap->port.membase + UART011_LCRH);
396 writew(0, uap->port.membase + UART01x_DR);
397 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
398 barrier();
399
400 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
401 writew(cr, uap->port.membase + UART011_CR);
402
403 /*
404 * initialise the old status of the modem signals
405 */
406 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
407
408 /*
409 * Finally, enable interrupts
410 */
411 spin_lock_irq(&uap->port.lock);
412 uap->im = UART011_RXIM | UART011_RTIM;
413 writew(uap->im, uap->port.membase + UART011_IMSC);
414 spin_unlock_irq(&uap->port.lock);
415
416 return 0;
417
418 clk_dis:
419 clk_disable(uap->clk);
420 out:
421 return retval;
422}
423
424static void pl011_shutdown(struct uart_port *port)
425{
426 struct uart_amba_port *uap = (struct uart_amba_port *)port;
427 unsigned long val;
428
429 /*
430 * disable all interrupts
431 */
432 spin_lock_irq(&uap->port.lock);
433 uap->im = 0;
434 writew(uap->im, uap->port.membase + UART011_IMSC);
435 writew(0xffff, uap->port.membase + UART011_ICR);
436 spin_unlock_irq(&uap->port.lock);
437
438 /*
439 * Free the interrupt
440 */
441 free_irq(uap->port.irq, uap);
442
443 /*
444 * disable the port
445 */
3b43816f 446 uap->autorts = false;
1da177e4
LT		 447 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
448
449 /*
450 * disable break condition and fifos
451 */
452 val = readw(uap->port.membase + UART011_LCRH);
453 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
454 writew(val, uap->port.membase + UART011_LCRH);
455
456 /*
457 * Shut down the clock producer
458 */
459 clk_disable(uap->clk);
460}
461
462static void
606d099c
AC		 463pl011_set_termios(struct uart_port *port, struct ktermios *termios,
464 struct ktermios *old)
1da177e4 465{
3b43816f 466 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4
LT		 467 unsigned int lcr_h, old_cr;
468 unsigned long flags;
469 unsigned int baud, quot;
470
471 /*
472 * Ask the core to calculate the divisor for us.
473 */
474 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
475 quot = port->uartclk * 4 / baud;
476
477 switch (termios->c_cflag & CSIZE) {
478 case CS5:
479 lcr_h = UART01x_LCRH_WLEN_5;
480 break;
481 case CS6:
482 lcr_h = UART01x_LCRH_WLEN_6;
483 break;
484 case CS7:
485 lcr_h = UART01x_LCRH_WLEN_7;
486 break;
487 default: // CS8
488 lcr_h = UART01x_LCRH_WLEN_8;
489 break;
490 }
491 if (termios->c_cflag & CSTOPB)
492 lcr_h |= UART01x_LCRH_STP2;
493 if (termios->c_cflag & PARENB) {
494 lcr_h |= UART01x_LCRH_PEN;
495 if (!(termios->c_cflag & PARODD))
496 lcr_h |= UART01x_LCRH_EPS;
497 }
498 if (port->fifosize > 1)
499 lcr_h |= UART01x_LCRH_FEN;
500
501 spin_lock_irqsave(&port->lock, flags);
502
503 /*
504 * Update the per-port timeout.
505 */
506 uart_update_timeout(port, termios->c_cflag, baud);
507
b63d4f0f 508 port->read_status_mask = UART011_DR_OE | 255;
1da177e4 509 if (termios->c_iflag & INPCK)
b63d4f0f 510 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1da177e4 511 if (termios->c_iflag & (BRKINT | PARMRK))
b63d4f0f 512 port->read_status_mask |= UART011_DR_BE;
1da177e4
LT		 513
514 /*
515 * Characters to ignore
516 */
517 port->ignore_status_mask = 0;
518 if (termios->c_iflag & IGNPAR)
b63d4f0f 519 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1da177e4 520 if (termios->c_iflag & IGNBRK) {
b63d4f0f 521 port->ignore_status_mask |= UART011_DR_BE;
1da177e4
LT		 522 /*
523 * If we're ignoring parity and break indicators,
524 * ignore overruns too (for real raw support).
525 */
526 if (termios->c_iflag & IGNPAR)
b63d4f0f 527 port->ignore_status_mask |= UART011_DR_OE;
1da177e4
LT		 528 }
529
530 /*
531 * Ignore all characters if CREAD is not set.
532 */
533 if ((termios->c_cflag & CREAD) == 0)
b63d4f0f 534 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1da177e4
LT		 535
536 if (UART_ENABLE_MS(port, termios->c_cflag))
537 pl011_enable_ms(port);
538
539 /* first, disable everything */
540 old_cr = readw(port->membase + UART011_CR);
541 writew(0, port->membase + UART011_CR);
542
3b43816f
RV		 543 if (termios->c_cflag & CRTSCTS) {
544 if (old_cr & UART011_CR_RTS)
545 old_cr |= UART011_CR_RTSEN;
546
547 old_cr |= UART011_CR_CTSEN;
548 uap->autorts = true;
549 } else {
550 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
551 uap->autorts = false;
552 }
553
1da177e4
LT		 554 /* Set baud rate */
555 writew(quot & 0x3f, port->membase + UART011_FBRD);
556 writew(quot >> 6, port->membase + UART011_IBRD);
557
558 /*
559 * ----------v----------v----------v----------v-----
560 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
561 * ----------^----------^----------^----------^-----
562 */
563 writew(lcr_h, port->membase + UART011_LCRH);
564 writew(old_cr, port->membase + UART011_CR);
565
566 spin_unlock_irqrestore(&port->lock, flags);
567}
568
569static const char *pl011_type(struct uart_port *port)
570{
571 return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
572}
573
574/*
575 * Release the memory region(s) being used by 'port'
576 */
577static void pl010_release_port(struct uart_port *port)
578{
579 release_mem_region(port->mapbase, SZ_4K);
580}
581
582/*
583 * Request the memory region(s) being used by 'port'
584 */
585static int pl010_request_port(struct uart_port *port)
586{
587 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
588 != NULL ? 0 : -EBUSY;
589}
590
591/*
592 * Configure/autoconfigure the port.
593 */
594static void pl010_config_port(struct uart_port *port, int flags)
595{
596 if (flags & UART_CONFIG_TYPE) {
597 port->type = PORT_AMBA;
598 pl010_request_port(port);
599 }
600}
601
602/*
603 * verify the new serial_struct (for TIOCSSERIAL).
604 */
605static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
606{
607 int ret = 0;
608 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
609 ret = -EINVAL;
a62c4133 610 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 611 ret = -EINVAL;
612 if (ser->baud_base < 9600)
613 ret = -EINVAL;
614 return ret;
615}
616
617static struct uart_ops amba_pl011_pops = {
618 .tx_empty = pl01x_tx_empty,
619 .set_mctrl = pl011_set_mctrl,
620 .get_mctrl = pl01x_get_mctrl,
621 .stop_tx = pl011_stop_tx,
622 .start_tx = pl011_start_tx,
623 .stop_rx = pl011_stop_rx,
624 .enable_ms = pl011_enable_ms,
625 .break_ctl = pl011_break_ctl,
626 .startup = pl011_startup,
627 .shutdown = pl011_shutdown,
628 .set_termios = pl011_set_termios,
629 .type = pl011_type,
630 .release_port = pl010_release_port,
631 .request_port = pl010_request_port,
632 .config_port = pl010_config_port,
633 .verify_port = pl010_verify_port,
84b5ae15
JW		 634#ifdef CONFIG_CONSOLE_POLL
635 .poll_get_char = pl010_get_poll_char,
636 .poll_put_char = pl010_put_poll_char,
637#endif
1da177e4
LT		 638};
639
640static struct uart_amba_port *amba_ports[UART_NR];
641
642#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
643
d358788f 644static void pl011_console_putchar(struct uart_port *port, int ch)
1da177e4 645{
d358788f 646 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1da177e4 647
d358788f
RK		 648 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
649 barrier();
1da177e4
LT		 650 writew(ch, uap->port.membase + UART01x_DR);
651}
652
653static void
654pl011_console_write(struct console *co, const char *s, unsigned int count)
655{
656 struct uart_amba_port *uap = amba_ports[co->index];
657 unsigned int status, old_cr, new_cr;
1da177e4
LT		 658
659 clk_enable(uap->clk);
660
661 /*
662 * First save the CR then disable the interrupts
663 */
664 old_cr = readw(uap->port.membase + UART011_CR);
665 new_cr = old_cr & ~UART011_CR_CTSEN;
666 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
667 writew(new_cr, uap->port.membase + UART011_CR);
668
d358788f 669 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1da177e4
LT		 670
671 /*
672 * Finally, wait for transmitter to become empty
673 * and restore the TCR
674 */
675 do {
676 status = readw(uap->port.membase + UART01x_FR);
677 } while (status & UART01x_FR_BUSY);
678 writew(old_cr, uap->port.membase + UART011_CR);
679
680 clk_disable(uap->clk);
681}
682
683static void __init
684pl011_console_get_options(struct uart_amba_port *uap, int *baud,
685 int *parity, int *bits)
686{
687 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
688 unsigned int lcr_h, ibrd, fbrd;
689
690 lcr_h = readw(uap->port.membase + UART011_LCRH);
691
692 *parity = 'n';
693 if (lcr_h & UART01x_LCRH_PEN) {
694 if (lcr_h & UART01x_LCRH_EPS)
695 *parity = 'e';
696 else
697 *parity = 'o';
698 }
699
700 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
701 *bits = 7;
702 else
703 *bits = 8;
704
705 ibrd = readw(uap->port.membase + UART011_IBRD);
706 fbrd = readw(uap->port.membase + UART011_FBRD);
707
708 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
709 }
710}
711
712static int __init pl011_console_setup(struct console *co, char *options)
713{
714 struct uart_amba_port *uap;
715 int baud = 38400;
716 int bits = 8;
717 int parity = 'n';
718 int flow = 'n';
719
720 /*
721 * Check whether an invalid uart number has been specified, and
722 * if so, search for the first available port that does have
723 * console support.
724 */
725 if (co->index >= UART_NR)
726 co->index = 0;
727 uap = amba_ports[co->index];
d28122a5
RK		 728 if (!uap)
729 return -ENODEV;
1da177e4
LT		 730
731 uap->port.uartclk = clk_get_rate(uap->clk);
732
733 if (options)
734 uart_parse_options(options, &baud, &parity, &bits, &flow);
735 else
736 pl011_console_get_options(uap, &baud, &parity, &bits);
737
738 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
739}
740
2d93486c 741static struct uart_driver amba_reg;
1da177e4
LT		 742static struct console amba_console = {
743 .name = "ttyAMA",
744 .write = pl011_console_write,
745 .device = uart_console_device,
746 .setup = pl011_console_setup,
747 .flags = CON_PRINTBUFFER,
748 .index = -1,
749 .data = &amba_reg,
750};
751
752#define AMBA_CONSOLE (&amba_console)
753#else
754#define AMBA_CONSOLE NULL
755#endif
756
757static struct uart_driver amba_reg = {
758 .owner = THIS_MODULE,
759 .driver_name = "ttyAMA",
760 .dev_name = "ttyAMA",
761 .major = SERIAL_AMBA_MAJOR,
762 .minor = SERIAL_AMBA_MINOR,
763 .nr = UART_NR,
764 .cons = AMBA_CONSOLE,
765};
766
03fbdb15 767static int pl011_probe(struct amba_device *dev, struct amba_id *id)
1da177e4
LT		 768{
769 struct uart_amba_port *uap;
5926a295 770 struct vendor_data *vendor = id->data;
1da177e4
LT		 771 void __iomem *base;
772 int i, ret;
773
774 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
775 if (amba_ports[i] == NULL)
776 break;
777
778 if (i == ARRAY_SIZE(amba_ports)) {
779 ret = -EBUSY;
780 goto out;
781 }
782
dd00cc48 783 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1da177e4
LT		 784 if (uap == NULL) {
785 ret = -ENOMEM;
786 goto out;
787 }
788
dc890c2d 789 base = ioremap(dev->res.start, resource_size(&dev->res));
1da177e4
LT		 790 if (!base) {
791 ret = -ENOMEM;
792 goto free;
793 }
794
ee569c43 795 uap->clk = clk_get(&dev->dev, NULL);
1da177e4
LT		 796 if (IS_ERR(uap->clk)) {
797 ret = PTR_ERR(uap->clk);
798 goto unmap;
799 }
800
5926a295 801 uap->ifls = vendor->ifls;
1da177e4
LT		 802 uap->port.dev = &dev->dev;
803 uap->port.mapbase = dev->res.start;
804 uap->port.membase = base;
805 uap->port.iotype = UPIO_MEM;
806 uap->port.irq = dev->irq[0];
5926a295 807 uap->port.fifosize = vendor->fifosize;
1da177e4
LT		 808 uap->port.ops = &amba_pl011_pops;
809 uap->port.flags = UPF_BOOT_AUTOCONF;
810 uap->port.line = i;
811
812 amba_ports[i] = uap;
813
814 amba_set_drvdata(dev, uap);
815 ret = uart_add_one_port(&amba_reg, &uap->port);
816 if (ret) {
817 amba_set_drvdata(dev, NULL);
818 amba_ports[i] = NULL;
1da177e4
LT		 819 clk_put(uap->clk);
820 unmap:
821 iounmap(base);
822 free:
823 kfree(uap);
824 }
825 out:
826 return ret;
827}
828
829static int pl011_remove(struct amba_device *dev)
830{
831 struct uart_amba_port *uap = amba_get_drvdata(dev);
832 int i;
833
834 amba_set_drvdata(dev, NULL);
835
836 uart_remove_one_port(&amba_reg, &uap->port);
837
838 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
839 if (amba_ports[i] == uap)
840 amba_ports[i] = NULL;
841
842 iounmap(uap->port.membase);
1da177e4
LT		 843 clk_put(uap->clk);
844 kfree(uap);
845 return 0;
846}
847
b736b89f
LC		 848#ifdef CONFIG_PM
849static int pl011_suspend(struct amba_device *dev, pm_message_t state)
850{
851 struct uart_amba_port *uap = amba_get_drvdata(dev);
852
853 if (!uap)
854 return -EINVAL;
855
856 return uart_suspend_port(&amba_reg, &uap->port);
857}
858
859static int pl011_resume(struct amba_device *dev)
860{
861 struct uart_amba_port *uap = amba_get_drvdata(dev);
862
863 if (!uap)
864 return -EINVAL;
865
866 return uart_resume_port(&amba_reg, &uap->port);
867}
868#endif
869
1da177e4
LT		 870static struct amba_id pl011_ids[] __initdata = {
871 {
872 .id = 0x00041011,
873 .mask = 0x000fffff,
5926a295
AR		 874 .data = &vendor_arm,
875 },
876 {
877 .id = 0x00380802,
878 .mask = 0x00ffffff,
879 .data = &vendor_st,
1da177e4
LT		 880 },
881 { 0, 0 },
882};
883
884static struct amba_driver pl011_driver = {
885 .drv = {
886 .name = "uart-pl011",
887 },
888 .id_table = pl011_ids,
889 .probe = pl011_probe,
890 .remove = pl011_remove,
b736b89f
LC		 891#ifdef CONFIG_PM
892 .suspend = pl011_suspend,
893 .resume = pl011_resume,
894#endif
1da177e4
LT		 895};
896
897static int __init pl011_init(void)
898{
899 int ret;
900 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
901
902 ret = uart_register_driver(&amba_reg);
903 if (ret == 0) {
904 ret = amba_driver_register(&pl011_driver);
905 if (ret)
906 uart_unregister_driver(&amba_reg);
907 }
908 return ret;
909}
910
911static void __exit pl011_exit(void)
912{
913 amba_driver_unregister(&pl011_driver);
914 uart_unregister_driver(&amba_reg);
915}
916
4dd9e742
AR		 917/*
918 * While this can be a module, if builtin it's most likely the console
919 * So let's leave module_exit but move module_init to an earlier place
920 */
921arch_initcall(pl011_init);
1da177e4
LT		 922module_exit(pl011_exit);
923
924MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
925MODULE_DESCRIPTION("ARM AMBA serial port driver");
926MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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