Commit | Line | Data |
---|---|---|
1e6c9c28 | 1 | /* |
c2f5ccfb | 2 | * linux/drivers/char/atmel_serial.c |
1e6c9c28 | 3 | * |
7192f92c | 4 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
5 | * Copyright (C) 2003 Rick Bronson |
6 | * | |
7 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
8 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
9 | * | |
a6670615 CC |
10 | * DMA support added by Chip Coldwell. |
11 | * | |
1e6c9c28 AV |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | */ | |
1e6c9c28 AV |
27 | #include <linux/module.h> |
28 | #include <linux/tty.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/serial.h> | |
afefc415 | 33 | #include <linux/clk.h> |
1e6c9c28 AV |
34 | #include <linux/console.h> |
35 | #include <linux/sysrq.h> | |
36 | #include <linux/tty_flip.h> | |
afefc415 | 37 | #include <linux/platform_device.h> |
a6670615 | 38 | #include <linux/dma-mapping.h> |
93a3ddc2 | 39 | #include <linux/atmel_pdc.h> |
fa3218d8 | 40 | #include <linux/atmel_serial.h> |
1e6c9c28 AV |
41 | |
42 | #include <asm/io.h> | |
43 | ||
afefc415 | 44 | #include <asm/mach/serial_at91.h> |
1e6c9c28 | 45 | #include <asm/arch/board.h> |
93a3ddc2 | 46 | |
acca9b83 | 47 | #ifdef CONFIG_ARM |
c2f5ccfb | 48 | #include <asm/arch/cpu.h> |
20e65276 | 49 | #include <asm/arch/gpio.h> |
acca9b83 | 50 | #endif |
1e6c9c28 | 51 | |
a6670615 CC |
52 | #define PDC_BUFFER_SIZE 512 |
53 | /* Revisit: We should calculate this based on the actual port settings */ | |
54 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ | |
55 | ||
749c4e60 | 56 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
57 | #define SUPPORT_SYSRQ |
58 | #endif | |
59 | ||
60 | #include <linux/serial_core.h> | |
61 | ||
749c4e60 | 62 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
63 | |
64 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
65 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
66 | * UART. */ | |
7192f92c | 67 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 68 | #define MINOR_START 154 |
7192f92c | 69 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
70 | |
71 | #else | |
72 | ||
73 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
74 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 75 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 76 | #define MINOR_START 64 |
7192f92c | 77 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
78 | |
79 | #endif | |
80 | ||
7192f92c | 81 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 82 | |
b843aa21 | 83 | /* UART registers. CR is write-only, hence no GET macro */ |
544fc728 HS |
84 | #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) |
85 | #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) | |
86 | #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) | |
87 | #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) | |
88 | #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) | |
89 | #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) | |
90 | #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) | |
91 | #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) | |
92 | #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) | |
93 | #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) | |
94 | #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) | |
95 | #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) | |
96 | ||
1e6c9c28 | 97 | /* PDC registers */ |
544fc728 HS |
98 | #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) |
99 | #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) | |
100 | ||
101 | #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) | |
102 | #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) | |
103 | #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) | |
104 | #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) | |
105 | #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) | |
106 | ||
107 | #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) | |
108 | #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) | |
39d4c922 | 109 | #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) |
1e6c9c28 | 110 | |
71f2e2b8 HS |
111 | static int (*atmel_open_hook)(struct uart_port *); |
112 | static void (*atmel_close_hook)(struct uart_port *); | |
1e6c9c28 | 113 | |
a6670615 CC |
114 | struct atmel_dma_buffer { |
115 | unsigned char *buf; | |
116 | dma_addr_t dma_addr; | |
117 | unsigned int dma_size; | |
118 | unsigned int ofs; | |
119 | }; | |
120 | ||
1ecc26bd RB |
121 | struct atmel_uart_char { |
122 | u16 status; | |
123 | u16 ch; | |
124 | }; | |
125 | ||
126 | #define ATMEL_SERIAL_RINGSIZE 1024 | |
127 | ||
afefc415 AV |
128 | /* |
129 | * We wrap our port structure around the generic uart_port. | |
130 | */ | |
7192f92c | 131 | struct atmel_uart_port { |
afefc415 AV |
132 | struct uart_port uart; /* uart */ |
133 | struct clk *clk; /* uart clock */ | |
134 | unsigned short suspended; /* is port suspended? */ | |
9e6077bd | 135 | int break_active; /* break being received */ |
1ecc26bd | 136 | |
a6670615 CC |
137 | short use_dma_rx; /* enable PDC receiver */ |
138 | short pdc_rx_idx; /* current PDC RX buffer */ | |
139 | struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ | |
140 | ||
141 | short use_dma_tx; /* enable PDC transmitter */ | |
142 | struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ | |
143 | ||
1ecc26bd RB |
144 | struct tasklet_struct tasklet; |
145 | unsigned int irq_status; | |
146 | unsigned int irq_status_prev; | |
147 | ||
148 | struct circ_buf rx_ring; | |
afefc415 AV |
149 | }; |
150 | ||
7192f92c | 151 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
afefc415 | 152 | |
1e6c9c28 | 153 | #ifdef SUPPORT_SYSRQ |
7192f92c | 154 | static struct console atmel_console; |
1e6c9c28 AV |
155 | #endif |
156 | ||
c811ab8c HS |
157 | static inline struct atmel_uart_port * |
158 | to_atmel_uart_port(struct uart_port *uart) | |
159 | { | |
160 | return container_of(uart, struct atmel_uart_port, uart); | |
161 | } | |
162 | ||
a6670615 CC |
163 | #ifdef CONFIG_SERIAL_ATMEL_PDC |
164 | static bool atmel_use_dma_rx(struct uart_port *port) | |
165 | { | |
c811ab8c | 166 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
167 | |
168 | return atmel_port->use_dma_rx; | |
169 | } | |
170 | ||
171 | static bool atmel_use_dma_tx(struct uart_port *port) | |
172 | { | |
c811ab8c | 173 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
174 | |
175 | return atmel_port->use_dma_tx; | |
176 | } | |
177 | #else | |
178 | static bool atmel_use_dma_rx(struct uart_port *port) | |
179 | { | |
180 | return false; | |
181 | } | |
182 | ||
183 | static bool atmel_use_dma_tx(struct uart_port *port) | |
184 | { | |
185 | return false; | |
186 | } | |
187 | #endif | |
188 | ||
1e6c9c28 AV |
189 | /* |
190 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
191 | */ | |
7192f92c | 192 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 193 | { |
7192f92c | 194 | return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; |
1e6c9c28 AV |
195 | } |
196 | ||
197 | /* | |
198 | * Set state of the modem control output lines | |
199 | */ | |
7192f92c | 200 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
201 | { |
202 | unsigned int control = 0; | |
afefc415 | 203 | unsigned int mode; |
1e6c9c28 | 204 | |
c2f5ccfb | 205 | #ifdef CONFIG_ARCH_AT91RM9200 |
79da7a61 | 206 | if (cpu_is_at91rm9200()) { |
afefc415 | 207 | /* |
b843aa21 RB |
208 | * AT91RM9200 Errata #39: RTS0 is not internally connected |
209 | * to PA21. We need to drive the pin manually. | |
afefc415 | 210 | */ |
72729910 | 211 | if (port->mapbase == AT91RM9200_BASE_US0) { |
afefc415 | 212 | if (mctrl & TIOCM_RTS) |
20e65276 | 213 | at91_set_gpio_value(AT91_PIN_PA21, 0); |
afefc415 | 214 | else |
20e65276 | 215 | at91_set_gpio_value(AT91_PIN_PA21, 1); |
afefc415 | 216 | } |
1e6c9c28 | 217 | } |
acca9b83 | 218 | #endif |
1e6c9c28 AV |
219 | |
220 | if (mctrl & TIOCM_RTS) | |
7192f92c | 221 | control |= ATMEL_US_RTSEN; |
1e6c9c28 | 222 | else |
7192f92c | 223 | control |= ATMEL_US_RTSDIS; |
1e6c9c28 AV |
224 | |
225 | if (mctrl & TIOCM_DTR) | |
7192f92c | 226 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 227 | else |
7192f92c | 228 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 229 | |
afefc415 AV |
230 | UART_PUT_CR(port, control); |
231 | ||
232 | /* Local loopback mode? */ | |
7192f92c | 233 | mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; |
afefc415 | 234 | if (mctrl & TIOCM_LOOP) |
7192f92c | 235 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 236 | else |
7192f92c | 237 | mode |= ATMEL_US_CHMODE_NORMAL; |
afefc415 | 238 | UART_PUT_MR(port, mode); |
1e6c9c28 AV |
239 | } |
240 | ||
241 | /* | |
242 | * Get state of the modem control input lines | |
243 | */ | |
7192f92c | 244 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 AV |
245 | { |
246 | unsigned int status, ret = 0; | |
247 | ||
248 | status = UART_GET_CSR(port); | |
249 | ||
250 | /* | |
251 | * The control signals are active low. | |
252 | */ | |
7192f92c | 253 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 254 | ret |= TIOCM_CD; |
7192f92c | 255 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 256 | ret |= TIOCM_CTS; |
7192f92c | 257 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 258 | ret |= TIOCM_DSR; |
7192f92c | 259 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
260 | ret |= TIOCM_RI; |
261 | ||
262 | return ret; | |
263 | } | |
264 | ||
265 | /* | |
266 | * Stop transmitting. | |
267 | */ | |
7192f92c | 268 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 269 | { |
a6670615 CC |
270 | if (atmel_use_dma_tx(port)) { |
271 | /* disable PDC transmit */ | |
272 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
273 | UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); | |
274 | } else | |
275 | UART_PUT_IDR(port, ATMEL_US_TXRDY); | |
1e6c9c28 AV |
276 | } |
277 | ||
278 | /* | |
279 | * Start transmitting. | |
280 | */ | |
7192f92c | 281 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 282 | { |
a6670615 CC |
283 | if (atmel_use_dma_tx(port)) { |
284 | if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) | |
285 | /* The transmitter is already running. Yes, we | |
286 | really need this.*/ | |
287 | return; | |
288 | ||
289 | UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); | |
290 | /* re-enable PDC transmit */ | |
291 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
292 | } else | |
293 | UART_PUT_IER(port, ATMEL_US_TXRDY); | |
1e6c9c28 AV |
294 | } |
295 | ||
296 | /* | |
297 | * Stop receiving - port is in process of being closed. | |
298 | */ | |
7192f92c | 299 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 300 | { |
a6670615 CC |
301 | if (atmel_use_dma_rx(port)) { |
302 | /* disable PDC receive */ | |
303 | UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); | |
304 | UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
305 | } else | |
306 | UART_PUT_IDR(port, ATMEL_US_RXRDY); | |
1e6c9c28 AV |
307 | } |
308 | ||
309 | /* | |
310 | * Enable modem status interrupts | |
311 | */ | |
7192f92c | 312 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 313 | { |
b843aa21 RB |
314 | UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC |
315 | | ATMEL_US_DCDIC | ATMEL_US_CTSIC); | |
1e6c9c28 AV |
316 | } |
317 | ||
318 | /* | |
319 | * Control the transmission of a break signal | |
320 | */ | |
7192f92c | 321 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
322 | { |
323 | if (break_state != 0) | |
7192f92c | 324 | UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ |
1e6c9c28 | 325 | else |
7192f92c | 326 | UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ |
1e6c9c28 AV |
327 | } |
328 | ||
1ecc26bd RB |
329 | /* |
330 | * Stores the incoming character in the ring buffer | |
331 | */ | |
332 | static void | |
333 | atmel_buffer_rx_char(struct uart_port *port, unsigned int status, | |
334 | unsigned int ch) | |
335 | { | |
c811ab8c | 336 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
337 | struct circ_buf *ring = &atmel_port->rx_ring; |
338 | struct atmel_uart_char *c; | |
339 | ||
340 | if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) | |
341 | /* Buffer overflow, ignore char */ | |
342 | return; | |
343 | ||
344 | c = &((struct atmel_uart_char *)ring->buf)[ring->head]; | |
345 | c->status = status; | |
346 | c->ch = ch; | |
347 | ||
348 | /* Make sure the character is stored before we update head. */ | |
349 | smp_wmb(); | |
350 | ||
351 | ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
352 | } | |
353 | ||
a6670615 CC |
354 | /* |
355 | * Deal with parity, framing and overrun errors. | |
356 | */ | |
357 | static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) | |
358 | { | |
359 | /* clear error */ | |
360 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
361 | ||
362 | if (status & ATMEL_US_RXBRK) { | |
363 | /* ignore side-effect */ | |
364 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
365 | port->icount.brk++; | |
366 | } | |
367 | if (status & ATMEL_US_PARE) | |
368 | port->icount.parity++; | |
369 | if (status & ATMEL_US_FRAME) | |
370 | port->icount.frame++; | |
371 | if (status & ATMEL_US_OVRE) | |
372 | port->icount.overrun++; | |
373 | } | |
374 | ||
1e6c9c28 AV |
375 | /* |
376 | * Characters received (called from interrupt handler) | |
377 | */ | |
7d12e780 | 378 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 379 | { |
c811ab8c | 380 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 381 | unsigned int status, ch; |
1e6c9c28 | 382 | |
afefc415 | 383 | status = UART_GET_CSR(port); |
7192f92c | 384 | while (status & ATMEL_US_RXRDY) { |
1e6c9c28 AV |
385 | ch = UART_GET_CHAR(port); |
386 | ||
1e6c9c28 AV |
387 | /* |
388 | * note that the error handling code is | |
389 | * out of the main execution path | |
390 | */ | |
9e6077bd HS |
391 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
392 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
393 | || atmel_port->break_active)) { | |
1ecc26bd | 394 | |
b843aa21 RB |
395 | /* clear error */ |
396 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
1ecc26bd | 397 | |
9e6077bd HS |
398 | if (status & ATMEL_US_RXBRK |
399 | && !atmel_port->break_active) { | |
9e6077bd HS |
400 | atmel_port->break_active = 1; |
401 | UART_PUT_IER(port, ATMEL_US_RXBRK); | |
9e6077bd HS |
402 | } else { |
403 | /* | |
404 | * This is either the end-of-break | |
405 | * condition or we've received at | |
406 | * least one character without RXBRK | |
407 | * being set. In both cases, the next | |
408 | * RXBRK will indicate start-of-break. | |
409 | */ | |
410 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
411 | status &= ~ATMEL_US_RXBRK; | |
412 | atmel_port->break_active = 0; | |
afefc415 | 413 | } |
1e6c9c28 AV |
414 | } |
415 | ||
1ecc26bd | 416 | atmel_buffer_rx_char(port, status, ch); |
afefc415 | 417 | status = UART_GET_CSR(port); |
1e6c9c28 AV |
418 | } |
419 | ||
1ecc26bd | 420 | tasklet_schedule(&atmel_port->tasklet); |
1e6c9c28 AV |
421 | } |
422 | ||
423 | /* | |
1ecc26bd RB |
424 | * Transmit characters (called from tasklet with TXRDY interrupt |
425 | * disabled) | |
1e6c9c28 | 426 | */ |
7192f92c | 427 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 AV |
428 | { |
429 | struct circ_buf *xmit = &port->info->xmit; | |
430 | ||
1ecc26bd | 431 | if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) { |
1e6c9c28 AV |
432 | UART_PUT_CHAR(port, port->x_char); |
433 | port->icount.tx++; | |
434 | port->x_char = 0; | |
1e6c9c28 | 435 | } |
1ecc26bd | 436 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
1e6c9c28 | 437 | return; |
1e6c9c28 | 438 | |
7192f92c | 439 | while (UART_GET_CSR(port) & ATMEL_US_TXRDY) { |
1e6c9c28 AV |
440 | UART_PUT_CHAR(port, xmit->buf[xmit->tail]); |
441 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
442 | port->icount.tx++; | |
443 | if (uart_circ_empty(xmit)) | |
444 | break; | |
445 | } | |
446 | ||
447 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
448 | uart_write_wakeup(port); | |
449 | ||
1ecc26bd RB |
450 | if (!uart_circ_empty(xmit)) |
451 | UART_PUT_IER(port, ATMEL_US_TXRDY); | |
1e6c9c28 AV |
452 | } |
453 | ||
b843aa21 RB |
454 | /* |
455 | * receive interrupt handler. | |
456 | */ | |
457 | static void | |
458 | atmel_handle_receive(struct uart_port *port, unsigned int pending) | |
459 | { | |
c811ab8c | 460 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b843aa21 | 461 | |
a6670615 CC |
462 | if (atmel_use_dma_rx(port)) { |
463 | /* | |
464 | * PDC receive. Just schedule the tasklet and let it | |
465 | * figure out the details. | |
466 | * | |
467 | * TODO: We're not handling error flags correctly at | |
468 | * the moment. | |
469 | */ | |
470 | if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { | |
471 | UART_PUT_IDR(port, (ATMEL_US_ENDRX | |
472 | | ATMEL_US_TIMEOUT)); | |
473 | tasklet_schedule(&atmel_port->tasklet); | |
474 | } | |
475 | ||
476 | if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | | |
477 | ATMEL_US_FRAME | ATMEL_US_PARE)) | |
478 | atmel_pdc_rxerr(port, pending); | |
479 | } | |
480 | ||
b843aa21 RB |
481 | /* Interrupt receive */ |
482 | if (pending & ATMEL_US_RXRDY) | |
483 | atmel_rx_chars(port); | |
484 | else if (pending & ATMEL_US_RXBRK) { | |
485 | /* | |
486 | * End of break detected. If it came along with a | |
487 | * character, atmel_rx_chars will handle it. | |
488 | */ | |
489 | UART_PUT_CR(port, ATMEL_US_RSTSTA); | |
490 | UART_PUT_IDR(port, ATMEL_US_RXBRK); | |
491 | atmel_port->break_active = 0; | |
492 | } | |
493 | } | |
494 | ||
495 | /* | |
1ecc26bd | 496 | * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) |
b843aa21 RB |
497 | */ |
498 | static void | |
499 | atmel_handle_transmit(struct uart_port *port, unsigned int pending) | |
500 | { | |
c811ab8c | 501 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 502 | |
a6670615 CC |
503 | if (atmel_use_dma_tx(port)) { |
504 | /* PDC transmit */ | |
505 | if (pending & (ATMEL_US_ENDTX | ATMEL_US_TXBUFE)) { | |
506 | UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); | |
507 | tasklet_schedule(&atmel_port->tasklet); | |
508 | } | |
509 | } else { | |
510 | /* Interrupt transmit */ | |
511 | if (pending & ATMEL_US_TXRDY) { | |
512 | UART_PUT_IDR(port, ATMEL_US_TXRDY); | |
513 | tasklet_schedule(&atmel_port->tasklet); | |
514 | } | |
1ecc26bd | 515 | } |
b843aa21 RB |
516 | } |
517 | ||
518 | /* | |
519 | * status flags interrupt handler. | |
520 | */ | |
521 | static void | |
522 | atmel_handle_status(struct uart_port *port, unsigned int pending, | |
523 | unsigned int status) | |
524 | { | |
c811ab8c | 525 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 526 | |
b843aa21 | 527 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC |
1ecc26bd RB |
528 | | ATMEL_US_CTSIC)) { |
529 | atmel_port->irq_status = status; | |
530 | tasklet_schedule(&atmel_port->tasklet); | |
531 | } | |
b843aa21 RB |
532 | } |
533 | ||
1e6c9c28 AV |
534 | /* |
535 | * Interrupt handler | |
536 | */ | |
7d12e780 | 537 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
538 | { |
539 | struct uart_port *port = dev_id; | |
540 | unsigned int status, pending, pass_counter = 0; | |
541 | ||
a6670615 CC |
542 | do { |
543 | status = UART_GET_CSR(port); | |
544 | pending = status & UART_GET_IMR(port); | |
545 | if (!pending) | |
546 | break; | |
547 | ||
b843aa21 RB |
548 | atmel_handle_receive(port, pending); |
549 | atmel_handle_status(port, pending, status); | |
550 | atmel_handle_transmit(port, pending); | |
a6670615 | 551 | } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); |
afefc415 | 552 | |
0400b697 | 553 | return pass_counter ? IRQ_HANDLED : IRQ_NONE; |
a6670615 | 554 | } |
1e6c9c28 | 555 | |
a6670615 CC |
556 | /* |
557 | * Called from tasklet with ENDTX and TXBUFE interrupts disabled. | |
558 | */ | |
559 | static void atmel_tx_dma(struct uart_port *port) | |
560 | { | |
c811ab8c | 561 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
562 | struct circ_buf *xmit = &port->info->xmit; |
563 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
564 | int count; | |
565 | ||
ba0657ff MT |
566 | /* nothing left to transmit? */ |
567 | if (UART_GET_TCR(port)) | |
568 | return; | |
569 | ||
a6670615 CC |
570 | xmit->tail += pdc->ofs; |
571 | xmit->tail &= UART_XMIT_SIZE - 1; | |
572 | ||
573 | port->icount.tx += pdc->ofs; | |
574 | pdc->ofs = 0; | |
575 | ||
ba0657ff | 576 | /* more to transmit - setup next transfer */ |
a6670615 | 577 | |
ba0657ff MT |
578 | /* disable PDC transmit */ |
579 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
580 | ||
581 | if (!uart_circ_empty(xmit)) { | |
a6670615 CC |
582 | dma_sync_single_for_device(port->dev, |
583 | pdc->dma_addr, | |
584 | pdc->dma_size, | |
585 | DMA_TO_DEVICE); | |
586 | ||
587 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
588 | pdc->ofs = count; | |
589 | ||
590 | UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); | |
591 | UART_PUT_TCR(port, count); | |
592 | /* re-enable PDC transmit and interrupts */ | |
593 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
594 | UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE); | |
1e6c9c28 | 595 | } |
a6670615 CC |
596 | |
597 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
598 | uart_write_wakeup(port); | |
1e6c9c28 AV |
599 | } |
600 | ||
1ecc26bd RB |
601 | static void atmel_rx_from_ring(struct uart_port *port) |
602 | { | |
c811ab8c | 603 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
604 | struct circ_buf *ring = &atmel_port->rx_ring; |
605 | unsigned int flg; | |
606 | unsigned int status; | |
607 | ||
608 | while (ring->head != ring->tail) { | |
609 | struct atmel_uart_char c; | |
610 | ||
611 | /* Make sure c is loaded after head. */ | |
612 | smp_rmb(); | |
613 | ||
614 | c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; | |
615 | ||
616 | ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
617 | ||
618 | port->icount.rx++; | |
619 | status = c.status; | |
620 | flg = TTY_NORMAL; | |
621 | ||
622 | /* | |
623 | * note that the error handling code is | |
624 | * out of the main execution path | |
625 | */ | |
626 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | |
627 | | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { | |
628 | if (status & ATMEL_US_RXBRK) { | |
629 | /* ignore side-effect */ | |
630 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
631 | ||
632 | port->icount.brk++; | |
633 | if (uart_handle_break(port)) | |
634 | continue; | |
635 | } | |
636 | if (status & ATMEL_US_PARE) | |
637 | port->icount.parity++; | |
638 | if (status & ATMEL_US_FRAME) | |
639 | port->icount.frame++; | |
640 | if (status & ATMEL_US_OVRE) | |
641 | port->icount.overrun++; | |
642 | ||
643 | status &= port->read_status_mask; | |
644 | ||
645 | if (status & ATMEL_US_RXBRK) | |
646 | flg = TTY_BREAK; | |
647 | else if (status & ATMEL_US_PARE) | |
648 | flg = TTY_PARITY; | |
649 | else if (status & ATMEL_US_FRAME) | |
650 | flg = TTY_FRAME; | |
651 | } | |
652 | ||
653 | ||
654 | if (uart_handle_sysrq_char(port, c.ch)) | |
655 | continue; | |
656 | ||
657 | uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); | |
658 | } | |
659 | ||
660 | /* | |
661 | * Drop the lock here since it might end up calling | |
662 | * uart_start(), which takes the lock. | |
663 | */ | |
664 | spin_unlock(&port->lock); | |
665 | tty_flip_buffer_push(port->info->tty); | |
666 | spin_lock(&port->lock); | |
667 | } | |
668 | ||
a6670615 CC |
669 | static void atmel_rx_from_dma(struct uart_port *port) |
670 | { | |
c811ab8c | 671 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
672 | struct tty_struct *tty = port->info->tty; |
673 | struct atmel_dma_buffer *pdc; | |
674 | int rx_idx = atmel_port->pdc_rx_idx; | |
675 | unsigned int head; | |
676 | unsigned int tail; | |
677 | unsigned int count; | |
678 | ||
679 | do { | |
680 | /* Reset the UART timeout early so that we don't miss one */ | |
681 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
682 | ||
683 | pdc = &atmel_port->pdc_rx[rx_idx]; | |
684 | head = UART_GET_RPR(port) - pdc->dma_addr; | |
685 | tail = pdc->ofs; | |
686 | ||
687 | /* If the PDC has switched buffers, RPR won't contain | |
688 | * any address within the current buffer. Since head | |
689 | * is unsigned, we just need a one-way comparison to | |
690 | * find out. | |
691 | * | |
692 | * In this case, we just need to consume the entire | |
693 | * buffer and resubmit it for DMA. This will clear the | |
694 | * ENDRX bit as well, so that we can safely re-enable | |
695 | * all interrupts below. | |
696 | */ | |
697 | head = min(head, pdc->dma_size); | |
698 | ||
699 | if (likely(head != tail)) { | |
700 | dma_sync_single_for_cpu(port->dev, pdc->dma_addr, | |
701 | pdc->dma_size, DMA_FROM_DEVICE); | |
702 | ||
703 | /* | |
704 | * head will only wrap around when we recycle | |
705 | * the DMA buffer, and when that happens, we | |
706 | * explicitly set tail to 0. So head will | |
707 | * always be greater than tail. | |
708 | */ | |
709 | count = head - tail; | |
710 | ||
711 | tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count); | |
712 | ||
713 | dma_sync_single_for_device(port->dev, pdc->dma_addr, | |
714 | pdc->dma_size, DMA_FROM_DEVICE); | |
715 | ||
716 | port->icount.rx += count; | |
717 | pdc->ofs = head; | |
718 | } | |
719 | ||
720 | /* | |
721 | * If the current buffer is full, we need to check if | |
722 | * the next one contains any additional data. | |
723 | */ | |
724 | if (head >= pdc->dma_size) { | |
725 | pdc->ofs = 0; | |
726 | UART_PUT_RNPR(port, pdc->dma_addr); | |
727 | UART_PUT_RNCR(port, pdc->dma_size); | |
728 | ||
729 | rx_idx = !rx_idx; | |
730 | atmel_port->pdc_rx_idx = rx_idx; | |
731 | } | |
732 | } while (head >= pdc->dma_size); | |
733 | ||
734 | /* | |
735 | * Drop the lock here since it might end up calling | |
736 | * uart_start(), which takes the lock. | |
737 | */ | |
738 | spin_unlock(&port->lock); | |
739 | tty_flip_buffer_push(tty); | |
740 | spin_lock(&port->lock); | |
741 | ||
742 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
743 | } | |
744 | ||
1ecc26bd RB |
745 | /* |
746 | * tasklet handling tty stuff outside the interrupt handler. | |
747 | */ | |
748 | static void atmel_tasklet_func(unsigned long data) | |
749 | { | |
750 | struct uart_port *port = (struct uart_port *)data; | |
c811ab8c | 751 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
752 | unsigned int status; |
753 | unsigned int status_change; | |
754 | ||
755 | /* The interrupt handler does not take the lock */ | |
756 | spin_lock(&port->lock); | |
757 | ||
a6670615 CC |
758 | if (atmel_use_dma_tx(port)) |
759 | atmel_tx_dma(port); | |
760 | else | |
761 | atmel_tx_chars(port); | |
1ecc26bd RB |
762 | |
763 | status = atmel_port->irq_status; | |
764 | status_change = status ^ atmel_port->irq_status_prev; | |
765 | ||
766 | if (status_change & (ATMEL_US_RI | ATMEL_US_DSR | |
767 | | ATMEL_US_DCD | ATMEL_US_CTS)) { | |
768 | /* TODO: All reads to CSR will clear these interrupts! */ | |
769 | if (status_change & ATMEL_US_RI) | |
770 | port->icount.rng++; | |
771 | if (status_change & ATMEL_US_DSR) | |
772 | port->icount.dsr++; | |
773 | if (status_change & ATMEL_US_DCD) | |
774 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
775 | if (status_change & ATMEL_US_CTS) | |
776 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
777 | ||
778 | wake_up_interruptible(&port->info->delta_msr_wait); | |
779 | ||
780 | atmel_port->irq_status_prev = status; | |
781 | } | |
782 | ||
a6670615 CC |
783 | if (atmel_use_dma_rx(port)) |
784 | atmel_rx_from_dma(port); | |
785 | else | |
786 | atmel_rx_from_ring(port); | |
1ecc26bd RB |
787 | |
788 | spin_unlock(&port->lock); | |
789 | } | |
790 | ||
1e6c9c28 AV |
791 | /* |
792 | * Perform initialization and enable port for reception | |
793 | */ | |
7192f92c | 794 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 795 | { |
c811ab8c | 796 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ae161068 | 797 | struct tty_struct *tty = port->info->tty; |
1e6c9c28 AV |
798 | int retval; |
799 | ||
800 | /* | |
801 | * Ensure that no interrupts are enabled otherwise when | |
802 | * request_irq() is called we could get stuck trying to | |
803 | * handle an unexpected interrupt | |
804 | */ | |
805 | UART_PUT_IDR(port, -1); | |
806 | ||
807 | /* | |
808 | * Allocate the IRQ | |
809 | */ | |
b843aa21 | 810 | retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, |
ae161068 | 811 | tty ? tty->name : "atmel_serial", port); |
1e6c9c28 | 812 | if (retval) { |
7192f92c | 813 | printk("atmel_serial: atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
814 | return retval; |
815 | } | |
816 | ||
a6670615 CC |
817 | /* |
818 | * Initialize DMA (if necessary) | |
819 | */ | |
820 | if (atmel_use_dma_rx(port)) { | |
821 | int i; | |
822 | ||
823 | for (i = 0; i < 2; i++) { | |
824 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
825 | ||
826 | pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); | |
827 | if (pdc->buf == NULL) { | |
828 | if (i != 0) { | |
829 | dma_unmap_single(port->dev, | |
830 | atmel_port->pdc_rx[0].dma_addr, | |
831 | PDC_BUFFER_SIZE, | |
832 | DMA_FROM_DEVICE); | |
833 | kfree(atmel_port->pdc_rx[0].buf); | |
834 | } | |
835 | free_irq(port->irq, port); | |
836 | return -ENOMEM; | |
837 | } | |
838 | pdc->dma_addr = dma_map_single(port->dev, | |
839 | pdc->buf, | |
840 | PDC_BUFFER_SIZE, | |
841 | DMA_FROM_DEVICE); | |
842 | pdc->dma_size = PDC_BUFFER_SIZE; | |
843 | pdc->ofs = 0; | |
844 | } | |
845 | ||
846 | atmel_port->pdc_rx_idx = 0; | |
847 | ||
848 | UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); | |
849 | UART_PUT_RCR(port, PDC_BUFFER_SIZE); | |
850 | ||
851 | UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); | |
852 | UART_PUT_RNCR(port, PDC_BUFFER_SIZE); | |
853 | } | |
854 | if (atmel_use_dma_tx(port)) { | |
855 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
856 | struct circ_buf *xmit = &port->info->xmit; | |
857 | ||
858 | pdc->buf = xmit->buf; | |
859 | pdc->dma_addr = dma_map_single(port->dev, | |
860 | pdc->buf, | |
861 | UART_XMIT_SIZE, | |
862 | DMA_TO_DEVICE); | |
863 | pdc->dma_size = UART_XMIT_SIZE; | |
864 | pdc->ofs = 0; | |
865 | } | |
866 | ||
1e6c9c28 AV |
867 | /* |
868 | * If there is a specific "open" function (to register | |
869 | * control line interrupts) | |
870 | */ | |
71f2e2b8 HS |
871 | if (atmel_open_hook) { |
872 | retval = atmel_open_hook(port); | |
1e6c9c28 AV |
873 | if (retval) { |
874 | free_irq(port->irq, port); | |
875 | return retval; | |
876 | } | |
877 | } | |
878 | ||
1e6c9c28 AV |
879 | /* |
880 | * Finally, enable the serial port | |
881 | */ | |
7192f92c | 882 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
b843aa21 RB |
883 | /* enable xmit & rcvr */ |
884 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
afefc415 | 885 | |
a6670615 CC |
886 | if (atmel_use_dma_rx(port)) { |
887 | /* set UART timeout */ | |
888 | UART_PUT_RTOR(port, PDC_RX_TIMEOUT); | |
889 | UART_PUT_CR(port, ATMEL_US_STTTO); | |
890 | ||
891 | UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
892 | /* enable PDC controller */ | |
893 | UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); | |
894 | } else { | |
895 | /* enable receive only */ | |
896 | UART_PUT_IER(port, ATMEL_US_RXRDY); | |
897 | } | |
afefc415 | 898 | |
1e6c9c28 AV |
899 | return 0; |
900 | } | |
901 | ||
902 | /* | |
903 | * Disable the port | |
904 | */ | |
7192f92c | 905 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 906 | { |
c811ab8c | 907 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 CC |
908 | /* |
909 | * Ensure everything is stopped. | |
910 | */ | |
911 | atmel_stop_rx(port); | |
912 | atmel_stop_tx(port); | |
913 | ||
914 | /* | |
915 | * Shut-down the DMA. | |
916 | */ | |
917 | if (atmel_use_dma_rx(port)) { | |
918 | int i; | |
919 | ||
920 | for (i = 0; i < 2; i++) { | |
921 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
922 | ||
923 | dma_unmap_single(port->dev, | |
924 | pdc->dma_addr, | |
925 | pdc->dma_size, | |
926 | DMA_FROM_DEVICE); | |
927 | kfree(pdc->buf); | |
928 | } | |
929 | } | |
930 | if (atmel_use_dma_tx(port)) { | |
931 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
932 | ||
933 | dma_unmap_single(port->dev, | |
934 | pdc->dma_addr, | |
935 | pdc->dma_size, | |
936 | DMA_TO_DEVICE); | |
937 | } | |
938 | ||
1e6c9c28 AV |
939 | /* |
940 | * Disable all interrupts, port and break condition. | |
941 | */ | |
7192f92c | 942 | UART_PUT_CR(port, ATMEL_US_RSTSTA); |
1e6c9c28 AV |
943 | UART_PUT_IDR(port, -1); |
944 | ||
945 | /* | |
946 | * Free the interrupt | |
947 | */ | |
948 | free_irq(port->irq, port); | |
949 | ||
950 | /* | |
951 | * If there is a specific "close" function (to unregister | |
952 | * control line interrupts) | |
953 | */ | |
71f2e2b8 HS |
954 | if (atmel_close_hook) |
955 | atmel_close_hook(port); | |
1e6c9c28 AV |
956 | } |
957 | ||
958 | /* | |
959 | * Power / Clock management. | |
960 | */ | |
b843aa21 RB |
961 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, |
962 | unsigned int oldstate) | |
1e6c9c28 | 963 | { |
c811ab8c | 964 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 965 | |
1e6c9c28 | 966 | switch (state) { |
b843aa21 RB |
967 | case 0: |
968 | /* | |
969 | * Enable the peripheral clock for this serial port. | |
970 | * This is called on uart_open() or a resume event. | |
971 | */ | |
972 | clk_enable(atmel_port->clk); | |
973 | break; | |
974 | case 3: | |
975 | /* | |
976 | * Disable the peripheral clock for this serial port. | |
977 | * This is called on uart_close() or a suspend event. | |
978 | */ | |
979 | clk_disable(atmel_port->clk); | |
980 | break; | |
981 | default: | |
982 | printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); | |
1e6c9c28 AV |
983 | } |
984 | } | |
985 | ||
986 | /* | |
987 | * Change the port parameters | |
988 | */ | |
b843aa21 RB |
989 | static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, |
990 | struct ktermios *old) | |
1e6c9c28 AV |
991 | { |
992 | unsigned long flags; | |
993 | unsigned int mode, imr, quot, baud; | |
994 | ||
03abeac0 | 995 | /* Get current mode register */ |
b843aa21 RB |
996 | mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL |
997 | | ATMEL_US_NBSTOP | ATMEL_US_PAR); | |
03abeac0 | 998 | |
b843aa21 | 999 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
1e6c9c28 AV |
1000 | quot = uart_get_divisor(port, baud); |
1001 | ||
b843aa21 | 1002 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
03abeac0 AV |
1003 | quot /= 8; |
1004 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
1005 | } | |
1e6c9c28 AV |
1006 | |
1007 | /* byte size */ | |
1008 | switch (termios->c_cflag & CSIZE) { | |
1009 | case CS5: | |
7192f92c | 1010 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
1011 | break; |
1012 | case CS6: | |
7192f92c | 1013 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
1014 | break; |
1015 | case CS7: | |
7192f92c | 1016 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
1017 | break; |
1018 | default: | |
7192f92c | 1019 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
1020 | break; |
1021 | } | |
1022 | ||
1023 | /* stop bits */ | |
1024 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 1025 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
1026 | |
1027 | /* parity */ | |
1028 | if (termios->c_cflag & PARENB) { | |
b843aa21 RB |
1029 | /* Mark or Space parity */ |
1030 | if (termios->c_cflag & CMSPAR) { | |
1e6c9c28 | 1031 | if (termios->c_cflag & PARODD) |
7192f92c | 1032 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 1033 | else |
7192f92c | 1034 | mode |= ATMEL_US_PAR_SPACE; |
b843aa21 | 1035 | } else if (termios->c_cflag & PARODD) |
7192f92c | 1036 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 1037 | else |
7192f92c | 1038 | mode |= ATMEL_US_PAR_EVEN; |
b843aa21 | 1039 | } else |
7192f92c | 1040 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 AV |
1041 | |
1042 | spin_lock_irqsave(&port->lock, flags); | |
1043 | ||
7192f92c | 1044 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 1045 | if (termios->c_iflag & INPCK) |
7192f92c | 1046 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1047 | if (termios->c_iflag & (BRKINT | PARMRK)) |
7192f92c | 1048 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 | 1049 | |
a6670615 CC |
1050 | if (atmel_use_dma_rx(port)) |
1051 | /* need to enable error interrupts */ | |
1052 | UART_PUT_IER(port, port->read_status_mask); | |
1053 | ||
1e6c9c28 AV |
1054 | /* |
1055 | * Characters to ignore | |
1056 | */ | |
1057 | port->ignore_status_mask = 0; | |
1058 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1059 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 1060 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 1061 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
1062 | /* |
1063 | * If we're ignoring parity and break indicators, | |
1064 | * ignore overruns too (for real raw support). | |
1065 | */ | |
1066 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 1067 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 | 1068 | } |
b843aa21 | 1069 | /* TODO: Ignore all characters if CREAD is set.*/ |
1e6c9c28 AV |
1070 | |
1071 | /* update the per-port timeout */ | |
1072 | uart_update_timeout(port, termios->c_cflag, baud); | |
1073 | ||
b843aa21 RB |
1074 | /* save/disable interrupts and drain transmitter */ |
1075 | imr = UART_GET_IMR(port); | |
1076 | UART_PUT_IDR(port, -1); | |
1077 | while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) | |
829dd811 | 1078 | cpu_relax(); |
1e6c9c28 AV |
1079 | |
1080 | /* disable receiver and transmitter */ | |
7192f92c | 1081 | UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 AV |
1082 | |
1083 | /* set the parity, stop bits and data size */ | |
1084 | UART_PUT_MR(port, mode); | |
1085 | ||
1086 | /* set the baud rate */ | |
1087 | UART_PUT_BRGR(port, quot); | |
7192f92c HS |
1088 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1089 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1090 | |
1091 | /* restore interrupts */ | |
1092 | UART_PUT_IER(port, imr); | |
1093 | ||
1094 | /* CTS flow-control and modem-status interrupts */ | |
1095 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1096 | port->ops->enable_ms(port); | |
1097 | ||
1098 | spin_unlock_irqrestore(&port->lock, flags); | |
1099 | } | |
1100 | ||
1101 | /* | |
1102 | * Return string describing the specified port | |
1103 | */ | |
7192f92c | 1104 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 1105 | { |
9ab4f88b | 1106 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
1107 | } |
1108 | ||
1109 | /* | |
1110 | * Release the memory region(s) being used by 'port'. | |
1111 | */ | |
7192f92c | 1112 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 1113 | { |
afefc415 AV |
1114 | struct platform_device *pdev = to_platform_device(port->dev); |
1115 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
1116 | ||
1117 | release_mem_region(port->mapbase, size); | |
1118 | ||
1119 | if (port->flags & UPF_IOREMAP) { | |
1120 | iounmap(port->membase); | |
1121 | port->membase = NULL; | |
1122 | } | |
1e6c9c28 AV |
1123 | } |
1124 | ||
1125 | /* | |
1126 | * Request the memory region(s) being used by 'port'. | |
1127 | */ | |
7192f92c | 1128 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 1129 | { |
afefc415 AV |
1130 | struct platform_device *pdev = to_platform_device(port->dev); |
1131 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
1132 | ||
7192f92c | 1133 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
1134 | return -EBUSY; |
1135 | ||
1136 | if (port->flags & UPF_IOREMAP) { | |
1137 | port->membase = ioremap(port->mapbase, size); | |
1138 | if (port->membase == NULL) { | |
1139 | release_mem_region(port->mapbase, size); | |
1140 | return -ENOMEM; | |
1141 | } | |
1142 | } | |
1e6c9c28 | 1143 | |
afefc415 | 1144 | return 0; |
1e6c9c28 AV |
1145 | } |
1146 | ||
1147 | /* | |
1148 | * Configure/autoconfigure the port. | |
1149 | */ | |
7192f92c | 1150 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
1151 | { |
1152 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 1153 | port->type = PORT_ATMEL; |
7192f92c | 1154 | atmel_request_port(port); |
1e6c9c28 AV |
1155 | } |
1156 | } | |
1157 | ||
1158 | /* | |
1159 | * Verify the new serial_struct (for TIOCSSERIAL). | |
1160 | */ | |
7192f92c | 1161 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
1162 | { |
1163 | int ret = 0; | |
9ab4f88b | 1164 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
1165 | ret = -EINVAL; |
1166 | if (port->irq != ser->irq) | |
1167 | ret = -EINVAL; | |
1168 | if (ser->io_type != SERIAL_IO_MEM) | |
1169 | ret = -EINVAL; | |
1170 | if (port->uartclk / 16 != ser->baud_base) | |
1171 | ret = -EINVAL; | |
1172 | if ((void *)port->mapbase != ser->iomem_base) | |
1173 | ret = -EINVAL; | |
1174 | if (port->iobase != ser->port) | |
1175 | ret = -EINVAL; | |
1176 | if (ser->hub6 != 0) | |
1177 | ret = -EINVAL; | |
1178 | return ret; | |
1179 | } | |
1180 | ||
7192f92c HS |
1181 | static struct uart_ops atmel_pops = { |
1182 | .tx_empty = atmel_tx_empty, | |
1183 | .set_mctrl = atmel_set_mctrl, | |
1184 | .get_mctrl = atmel_get_mctrl, | |
1185 | .stop_tx = atmel_stop_tx, | |
1186 | .start_tx = atmel_start_tx, | |
1187 | .stop_rx = atmel_stop_rx, | |
1188 | .enable_ms = atmel_enable_ms, | |
1189 | .break_ctl = atmel_break_ctl, | |
1190 | .startup = atmel_startup, | |
1191 | .shutdown = atmel_shutdown, | |
1192 | .set_termios = atmel_set_termios, | |
1193 | .type = atmel_type, | |
1194 | .release_port = atmel_release_port, | |
1195 | .request_port = atmel_request_port, | |
1196 | .config_port = atmel_config_port, | |
1197 | .verify_port = atmel_verify_port, | |
1198 | .pm = atmel_serial_pm, | |
1e6c9c28 AV |
1199 | }; |
1200 | ||
afefc415 AV |
1201 | /* |
1202 | * Configure the port from the platform device resource info. | |
1203 | */ | |
b843aa21 RB |
1204 | static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, |
1205 | struct platform_device *pdev) | |
1e6c9c28 | 1206 | { |
7192f92c | 1207 | struct uart_port *port = &atmel_port->uart; |
73e2798b | 1208 | struct atmel_uart_data *data = pdev->dev.platform_data; |
afefc415 AV |
1209 | |
1210 | port->iotype = UPIO_MEM; | |
a14d5273 | 1211 | port->flags = UPF_BOOT_AUTOCONF; |
7192f92c | 1212 | port->ops = &atmel_pops; |
a14d5273 | 1213 | port->fifosize = 1; |
afefc415 AV |
1214 | port->line = pdev->id; |
1215 | port->dev = &pdev->dev; | |
1216 | ||
1217 | port->mapbase = pdev->resource[0].start; | |
1218 | port->irq = pdev->resource[1].start; | |
1219 | ||
1ecc26bd RB |
1220 | tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, |
1221 | (unsigned long)port); | |
1222 | ||
1223 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); | |
1224 | ||
75d35213 HS |
1225 | if (data->regs) |
1226 | /* Already mapped by setup code */ | |
1227 | port->membase = data->regs; | |
afefc415 AV |
1228 | else { |
1229 | port->flags |= UPF_IOREMAP; | |
1230 | port->membase = NULL; | |
1231 | } | |
1e6c9c28 | 1232 | |
b843aa21 RB |
1233 | /* for console, the clock could already be configured */ |
1234 | if (!atmel_port->clk) { | |
7192f92c HS |
1235 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
1236 | clk_enable(atmel_port->clk); | |
1237 | port->uartclk = clk_get_rate(atmel_port->clk); | |
afefc415 | 1238 | } |
a6670615 CC |
1239 | |
1240 | atmel_port->use_dma_rx = data->use_dma_rx; | |
1241 | atmel_port->use_dma_tx = data->use_dma_tx; | |
1242 | if (atmel_use_dma_tx(port)) | |
1243 | port->fifosize = PDC_BUFFER_SIZE; | |
1e6c9c28 AV |
1244 | } |
1245 | ||
afefc415 AV |
1246 | /* |
1247 | * Register board-specific modem-control line handlers. | |
1248 | */ | |
71f2e2b8 | 1249 | void __init atmel_register_uart_fns(struct atmel_port_fns *fns) |
1e6c9c28 AV |
1250 | { |
1251 | if (fns->enable_ms) | |
7192f92c | 1252 | atmel_pops.enable_ms = fns->enable_ms; |
1e6c9c28 | 1253 | if (fns->get_mctrl) |
7192f92c | 1254 | atmel_pops.get_mctrl = fns->get_mctrl; |
1e6c9c28 | 1255 | if (fns->set_mctrl) |
7192f92c | 1256 | atmel_pops.set_mctrl = fns->set_mctrl; |
71f2e2b8 HS |
1257 | atmel_open_hook = fns->open; |
1258 | atmel_close_hook = fns->close; | |
7192f92c HS |
1259 | atmel_pops.pm = fns->pm; |
1260 | atmel_pops.set_wake = fns->set_wake; | |
1e6c9c28 AV |
1261 | } |
1262 | ||
749c4e60 | 1263 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 1264 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 1265 | { |
7192f92c | 1266 | while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) |
829dd811 | 1267 | cpu_relax(); |
d358788f RK |
1268 | UART_PUT_CHAR(port, ch); |
1269 | } | |
1e6c9c28 AV |
1270 | |
1271 | /* | |
1272 | * Interrupts are disabled on entering | |
1273 | */ | |
7192f92c | 1274 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 1275 | { |
7192f92c | 1276 | struct uart_port *port = &atmel_ports[co->index].uart; |
d358788f | 1277 | unsigned int status, imr; |
39d4c922 | 1278 | unsigned int pdc_tx; |
1e6c9c28 AV |
1279 | |
1280 | /* | |
b843aa21 | 1281 | * First, save IMR and then disable interrupts |
1e6c9c28 | 1282 | */ |
b843aa21 | 1283 | imr = UART_GET_IMR(port); |
7192f92c | 1284 | UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY); |
1e6c9c28 | 1285 | |
39d4c922 MP |
1286 | /* Store PDC transmit status and disable it */ |
1287 | pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; | |
1288 | UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); | |
1289 | ||
7192f92c | 1290 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
1291 | |
1292 | /* | |
b843aa21 RB |
1293 | * Finally, wait for transmitter to become empty |
1294 | * and restore IMR | |
1e6c9c28 AV |
1295 | */ |
1296 | do { | |
1297 | status = UART_GET_CSR(port); | |
7192f92c | 1298 | } while (!(status & ATMEL_US_TXRDY)); |
39d4c922 MP |
1299 | |
1300 | /* Restore PDC transmit status */ | |
1301 | if (pdc_tx) | |
1302 | UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); | |
1303 | ||
b843aa21 RB |
1304 | /* set interrupts back the way they were */ |
1305 | UART_PUT_IER(port, imr); | |
1e6c9c28 AV |
1306 | } |
1307 | ||
1308 | /* | |
b843aa21 RB |
1309 | * If the port was already initialised (eg, by a boot loader), |
1310 | * try to determine the current setup. | |
1e6c9c28 | 1311 | */ |
b843aa21 RB |
1312 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, |
1313 | int *parity, int *bits) | |
1e6c9c28 AV |
1314 | { |
1315 | unsigned int mr, quot; | |
1316 | ||
1c0fd82f HS |
1317 | /* |
1318 | * If the baud rate generator isn't running, the port wasn't | |
1319 | * initialized by the boot loader. | |
1320 | */ | |
9c81c5c9 | 1321 | quot = UART_GET_BRGR(port) & ATMEL_US_CD; |
1c0fd82f HS |
1322 | if (!quot) |
1323 | return; | |
1e6c9c28 | 1324 | |
7192f92c HS |
1325 | mr = UART_GET_MR(port) & ATMEL_US_CHRL; |
1326 | if (mr == ATMEL_US_CHRL_8) | |
1e6c9c28 AV |
1327 | *bits = 8; |
1328 | else | |
1329 | *bits = 7; | |
1330 | ||
7192f92c HS |
1331 | mr = UART_GET_MR(port) & ATMEL_US_PAR; |
1332 | if (mr == ATMEL_US_PAR_EVEN) | |
1e6c9c28 | 1333 | *parity = 'e'; |
7192f92c | 1334 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
1335 | *parity = 'o'; |
1336 | ||
4d5e392c HS |
1337 | /* |
1338 | * The serial core only rounds down when matching this to a | |
1339 | * supported baud rate. Make sure we don't end up slightly | |
1340 | * lower than one of those, as it would make us fall through | |
1341 | * to a much lower baud rate than we really want. | |
1342 | */ | |
4d5e392c | 1343 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
1344 | } |
1345 | ||
7192f92c | 1346 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 1347 | { |
7192f92c | 1348 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
1349 | int baud = 115200; |
1350 | int bits = 8; | |
1351 | int parity = 'n'; | |
1352 | int flow = 'n'; | |
1353 | ||
b843aa21 RB |
1354 | if (port->membase == NULL) { |
1355 | /* Port not initialized yet - delay setup */ | |
afefc415 | 1356 | return -ENODEV; |
b843aa21 | 1357 | } |
1e6c9c28 | 1358 | |
b843aa21 | 1359 | UART_PUT_IDR(port, -1); |
7192f92c HS |
1360 | UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
1361 | UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
1362 | |
1363 | if (options) | |
1364 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1365 | else | |
7192f92c | 1366 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
1367 | |
1368 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1369 | } | |
1370 | ||
7192f92c | 1371 | static struct uart_driver atmel_uart; |
1e6c9c28 | 1372 | |
7192f92c HS |
1373 | static struct console atmel_console = { |
1374 | .name = ATMEL_DEVICENAME, | |
1375 | .write = atmel_console_write, | |
1e6c9c28 | 1376 | .device = uart_console_device, |
7192f92c | 1377 | .setup = atmel_console_setup, |
1e6c9c28 AV |
1378 | .flags = CON_PRINTBUFFER, |
1379 | .index = -1, | |
7192f92c | 1380 | .data = &atmel_uart, |
1e6c9c28 AV |
1381 | }; |
1382 | ||
7192f92c | 1383 | #define ATMEL_CONSOLE_DEVICE &atmel_console |
1e6c9c28 | 1384 | |
afefc415 AV |
1385 | /* |
1386 | * Early console initialization (before VM subsystem initialized). | |
1387 | */ | |
7192f92c | 1388 | static int __init atmel_console_init(void) |
1e6c9c28 | 1389 | { |
73e2798b | 1390 | if (atmel_default_console_device) { |
b843aa21 RB |
1391 | add_preferred_console(ATMEL_DEVICENAME, |
1392 | atmel_default_console_device->id, NULL); | |
1393 | atmel_init_port(&atmel_ports[atmel_default_console_device->id], | |
1394 | atmel_default_console_device); | |
7192f92c | 1395 | register_console(&atmel_console); |
afefc415 | 1396 | } |
1e6c9c28 | 1397 | |
1e6c9c28 AV |
1398 | return 0; |
1399 | } | |
b843aa21 | 1400 | |
7192f92c | 1401 | console_initcall(atmel_console_init); |
1e6c9c28 | 1402 | |
afefc415 AV |
1403 | /* |
1404 | * Late console initialization. | |
1405 | */ | |
7192f92c | 1406 | static int __init atmel_late_console_init(void) |
afefc415 | 1407 | { |
b843aa21 RB |
1408 | if (atmel_default_console_device |
1409 | && !(atmel_console.flags & CON_ENABLED)) | |
7192f92c | 1410 | register_console(&atmel_console); |
afefc415 AV |
1411 | |
1412 | return 0; | |
1413 | } | |
b843aa21 | 1414 | |
7192f92c | 1415 | core_initcall(atmel_late_console_init); |
afefc415 | 1416 | |
dfa7f343 HS |
1417 | static inline bool atmel_is_console_port(struct uart_port *port) |
1418 | { | |
1419 | return port->cons && port->cons->index == port->line; | |
1420 | } | |
1421 | ||
1e6c9c28 | 1422 | #else |
7192f92c | 1423 | #define ATMEL_CONSOLE_DEVICE NULL |
dfa7f343 HS |
1424 | |
1425 | static inline bool atmel_is_console_port(struct uart_port *port) | |
1426 | { | |
1427 | return false; | |
1428 | } | |
1e6c9c28 AV |
1429 | #endif |
1430 | ||
7192f92c | 1431 | static struct uart_driver atmel_uart = { |
b843aa21 RB |
1432 | .owner = THIS_MODULE, |
1433 | .driver_name = "atmel_serial", | |
1434 | .dev_name = ATMEL_DEVICENAME, | |
1435 | .major = SERIAL_ATMEL_MAJOR, | |
1436 | .minor = MINOR_START, | |
1437 | .nr = ATMEL_MAX_UART, | |
1438 | .cons = ATMEL_CONSOLE_DEVICE, | |
1e6c9c28 AV |
1439 | }; |
1440 | ||
afefc415 | 1441 | #ifdef CONFIG_PM |
b843aa21 RB |
1442 | static int atmel_serial_suspend(struct platform_device *pdev, |
1443 | pm_message_t state) | |
1e6c9c28 | 1444 | { |
afefc415 | 1445 | struct uart_port *port = platform_get_drvdata(pdev); |
c811ab8c | 1446 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 1447 | |
b843aa21 RB |
1448 | if (device_may_wakeup(&pdev->dev) |
1449 | && !at91_suspend_entering_slow_clock()) | |
afefc415 AV |
1450 | enable_irq_wake(port->irq); |
1451 | else { | |
7192f92c HS |
1452 | uart_suspend_port(&atmel_uart, port); |
1453 | atmel_port->suspended = 1; | |
afefc415 | 1454 | } |
1e6c9c28 | 1455 | |
afefc415 AV |
1456 | return 0; |
1457 | } | |
1e6c9c28 | 1458 | |
7192f92c | 1459 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
1460 | { |
1461 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 1462 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 1463 | |
7192f92c HS |
1464 | if (atmel_port->suspended) { |
1465 | uart_resume_port(&atmel_uart, port); | |
1466 | atmel_port->suspended = 0; | |
b843aa21 | 1467 | } else |
9b938166 | 1468 | disable_irq_wake(port->irq); |
1e6c9c28 AV |
1469 | |
1470 | return 0; | |
1471 | } | |
afefc415 | 1472 | #else |
7192f92c HS |
1473 | #define atmel_serial_suspend NULL |
1474 | #define atmel_serial_resume NULL | |
afefc415 | 1475 | #endif |
1e6c9c28 | 1476 | |
7192f92c | 1477 | static int __devinit atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 1478 | { |
7192f92c | 1479 | struct atmel_uart_port *port; |
1ecc26bd | 1480 | void *data; |
afefc415 | 1481 | int ret; |
1e6c9c28 | 1482 | |
1ecc26bd RB |
1483 | BUILD_BUG_ON(!is_power_of_2(ATMEL_SERIAL_RINGSIZE)); |
1484 | ||
7192f92c HS |
1485 | port = &atmel_ports[pdev->id]; |
1486 | atmel_init_port(port, pdev); | |
1e6c9c28 | 1487 | |
a6670615 CC |
1488 | if (!atmel_use_dma_rx(&port->uart)) { |
1489 | ret = -ENOMEM; | |
6433471d HS |
1490 | data = kmalloc(sizeof(struct atmel_uart_char) |
1491 | * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); | |
a6670615 CC |
1492 | if (!data) |
1493 | goto err_alloc_ring; | |
1494 | port->rx_ring.buf = data; | |
1495 | } | |
1ecc26bd | 1496 | |
7192f92c | 1497 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
dfa7f343 HS |
1498 | if (ret) |
1499 | goto err_add_port; | |
1500 | ||
1501 | device_init_wakeup(&pdev->dev, 1); | |
1502 | platform_set_drvdata(pdev, port); | |
1503 | ||
1504 | return 0; | |
1505 | ||
1506 | err_add_port: | |
1ecc26bd RB |
1507 | kfree(port->rx_ring.buf); |
1508 | port->rx_ring.buf = NULL; | |
1509 | err_alloc_ring: | |
dfa7f343 HS |
1510 | if (!atmel_is_console_port(&port->uart)) { |
1511 | clk_disable(port->clk); | |
1512 | clk_put(port->clk); | |
1513 | port->clk = NULL; | |
afefc415 AV |
1514 | } |
1515 | ||
1516 | return ret; | |
1517 | } | |
1518 | ||
7192f92c | 1519 | static int __devexit atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
1520 | { |
1521 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 1522 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 AV |
1523 | int ret = 0; |
1524 | ||
afefc415 AV |
1525 | device_init_wakeup(&pdev->dev, 0); |
1526 | platform_set_drvdata(pdev, NULL); | |
1527 | ||
dfa7f343 HS |
1528 | ret = uart_remove_one_port(&atmel_uart, port); |
1529 | ||
1ecc26bd RB |
1530 | tasklet_kill(&atmel_port->tasklet); |
1531 | kfree(atmel_port->rx_ring.buf); | |
1532 | ||
dfa7f343 HS |
1533 | /* "port" is allocated statically, so we shouldn't free it */ |
1534 | ||
1535 | clk_disable(atmel_port->clk); | |
1536 | clk_put(atmel_port->clk); | |
afefc415 AV |
1537 | |
1538 | return ret; | |
1539 | } | |
1540 | ||
7192f92c HS |
1541 | static struct platform_driver atmel_serial_driver = { |
1542 | .probe = atmel_serial_probe, | |
1543 | .remove = __devexit_p(atmel_serial_remove), | |
1544 | .suspend = atmel_serial_suspend, | |
1545 | .resume = atmel_serial_resume, | |
afefc415 | 1546 | .driver = { |
1e8ea802 | 1547 | .name = "atmel_usart", |
afefc415 AV |
1548 | .owner = THIS_MODULE, |
1549 | }, | |
1550 | }; | |
1551 | ||
7192f92c | 1552 | static int __init atmel_serial_init(void) |
afefc415 AV |
1553 | { |
1554 | int ret; | |
1555 | ||
7192f92c | 1556 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
1557 | if (ret) |
1558 | return ret; | |
1559 | ||
7192f92c | 1560 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 1561 | if (ret) |
7192f92c | 1562 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
1563 | |
1564 | return ret; | |
1565 | } | |
1566 | ||
7192f92c | 1567 | static void __exit atmel_serial_exit(void) |
afefc415 | 1568 | { |
7192f92c HS |
1569 | platform_driver_unregister(&atmel_serial_driver); |
1570 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
1571 | } |
1572 | ||
7192f92c HS |
1573 | module_init(atmel_serial_init); |
1574 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
1575 | |
1576 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 1577 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 1578 | MODULE_LICENSE("GPL"); |
e169c139 | 1579 | MODULE_ALIAS("platform:atmel_usart"); |