[deliverable/linux.git] / drivers / serial / clps711x.c

/*
 *  linux/drivers/char/clps711x.c
 *
 *  Driver for CLPS711x serial ports
 *
 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
 *
 *  Copyright 1999 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *  $Id: clps711x.c,v 1.42 2002/07/28 10:03:28 rmk Exp $
 *
 */
#include <linux/config.h>

#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif

#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/hardware/clps7111.h>

#define UART_NR		2

#define SERIAL_CLPS711X_MAJOR	204
#define SERIAL_CLPS711X_MINOR	40
#define SERIAL_CLPS711X_NR	UART_NR

/*
 * We use the relevant SYSCON register as a base address for these ports.
 */
#define UBRLCR(port)		((port)->iobase + UBRLCR1 - SYSCON1)
#define UARTDR(port)		((port)->iobase + UARTDR1 - SYSCON1)
#define SYSFLG(port)		((port)->iobase + SYSFLG1 - SYSCON1)
#define SYSCON(port)		((port)->iobase + SYSCON1 - SYSCON1)

#define TX_IRQ(port)		((port)->irq)
#define RX_IRQ(port)		((port)->irq + 1)

#define UART_ANY_ERR		(UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR)

#define tx_enabled(port)	((port)->unused[0])

static void clps711xuart_stop_tx(struct uart_port *port)
{
	if (tx_enabled(port)) {
		disable_irq(TX_IRQ(port));
		tx_enabled(port) = 0;
	}
}

static void clps711xuart_start_tx(struct uart_port *port)
{
	if (!tx_enabled(port)) {
		enable_irq(TX_IRQ(port));
		tx_enabled(port) = 1;
	}
}

static void clps711xuart_stop_rx(struct uart_port *port)
{
	disable_irq(RX_IRQ(port));
}

static void clps711xuart_enable_ms(struct uart_port *port)
{
}

static irqreturn_t clps711xuart_int_rx(int irq, void *dev_id, struct pt_regs *regs)
{
	struct uart_port *port = dev_id;
	struct tty_struct *tty = port->info->tty;
	unsigned int status, ch, flg;

	status = clps_readl(SYSFLG(port));
	while (!(status & SYSFLG_URXFE)) {
		ch = clps_readl(UARTDR(port));

		if (tty->flip.count >= TTY_FLIPBUF_SIZE)
			goto ignore_char;
		port->icount.rx++;

		flg = TTY_NORMAL;

		/*
		 * Note that the error handling code is
		 * out of the main execution path
		 */
		if (unlikely(ch & UART_ANY_ERR)) {
			if (ch & UARTDR_PARERR)
				port->icount.parity++;
			else if (ch & UARTDR_FRMERR)
				port->icount.frame++;
			if (ch & UARTDR_OVERR)
				port->icount.overrun++;

			ch &= port->read_status_mask;

			if (ch & UARTDR_PARERR)
				flg = TTY_PARITY;
			else if (ch & UARTDR_FRMERR)
				flg = TTY_FRAME;

#ifdef SUPPORT_SYSRQ
			port->sysrq = 0;
#endif
		}

		if (uart_handle_sysrq_char(port, ch, regs))
			goto ignore_char;

		/*
		 * CHECK: does overrun affect the current character?
		 * ASSUMPTION: it does not.
		 */
		uart_insert_char(port, ch, UARTDR_OVERR, ch, flg);

	ignore_char:
		status = clps_readl(SYSFLG(port));
	}
	tty_flip_buffer_push(tty);
	return IRQ_HANDLED;
}

static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id, struct pt_regs *regs)
{
	struct uart_port *port = dev_id;
	struct circ_buf *xmit = &port->info->xmit;
	int count;

	if (port->x_char) {
		clps_writel(port->x_char, UARTDR(port));
		port->icount.tx++;
		port->x_char = 0;
		return IRQ_HANDLED;
	}
	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		clps711xuart_stop_tx(port);
		return IRQ_HANDLED;
	}

	count = port->fifosize >> 1;
	do {
		clps_writel(xmit->buf[xmit->tail], UARTDR(port));
		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		port->icount.tx++;
		if (uart_circ_empty(xmit))
			break;
	} while (--count > 0);

	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	if (uart_circ_empty(xmit))
		clps711xuart_stop_tx(port);

	return IRQ_HANDLED;
}

static unsigned int clps711xuart_tx_empty(struct uart_port *port)
{
	unsigned int status = clps_readl(SYSFLG(port));
	return status & SYSFLG_UBUSY ? 0 : TIOCSER_TEMT;
}

static unsigned int clps711xuart_get_mctrl(struct uart_port *port)
{
	unsigned int port_addr;
	unsigned int result = 0;
	unsigned int status;

	port_addr = SYSFLG(port);
	if (port_addr == SYSFLG1) {
		status = clps_readl(SYSFLG1);
		if (status & SYSFLG1_DCD)
			result |= TIOCM_CAR;
		if (status & SYSFLG1_DSR)
			result |= TIOCM_DSR;
		if (status & SYSFLG1_CTS)
			result |= TIOCM_CTS;
	}

	return result;
}

static void
clps711xuart_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
{
}

static void clps711xuart_break_ctl(struct uart_port *port, int break_state)
{
	unsigned long flags;
	unsigned int ubrlcr;

	spin_lock_irqsave(&port->lock, flags);
	ubrlcr = clps_readl(UBRLCR(port));
	if (break_state == -1)
		ubrlcr |= UBRLCR_BREAK;
	else
		ubrlcr &= ~UBRLCR_BREAK;
	clps_writel(ubrlcr, UBRLCR(port));
	spin_unlock_irqrestore(&port->lock, flags);
}

static int clps711xuart_startup(struct uart_port *port)
{
	unsigned int syscon;
	int retval;

	tx_enabled(port) = 1;

	/*
	 * Allocate the IRQs
	 */
	retval = request_irq(TX_IRQ(port), clps711xuart_int_tx, 0,
			     "clps711xuart_tx", port);
	if (retval)
		return retval;

	retval = request_irq(RX_IRQ(port), clps711xuart_int_rx, 0,
			     "clps711xuart_rx", port);
	if (retval) {
		free_irq(TX_IRQ(port), port);
		return retval;
	}

	/*
	 * enable the port
	 */
	syscon = clps_readl(SYSCON(port));
	syscon |= SYSCON_UARTEN;
	clps_writel(syscon, SYSCON(port));

	return 0;
}

static void clps711xuart_shutdown(struct uart_port *port)
{
	unsigned int ubrlcr, syscon;

	/*
	 * Free the interrupt
	 */
	free_irq(TX_IRQ(port), port);	/* TX interrupt */
	free_irq(RX_IRQ(port), port);	/* RX interrupt */

	/*
	 * disable the port
	 */
	syscon = clps_readl(SYSCON(port));
	syscon &= ~SYSCON_UARTEN;
	clps_writel(syscon, SYSCON(port));

	/*
	 * disable break condition and fifos
	 */
	ubrlcr = clps_readl(UBRLCR(port));
	ubrlcr &= ~(UBRLCR_FIFOEN | UBRLCR_BREAK);
	clps_writel(ubrlcr, UBRLCR(port));
}

static void
clps711xuart_set_termios(struct uart_port *port, struct termios *termios,
			 struct termios *old)
{
	unsigned int ubrlcr, baud, quot;
	unsigned long flags;

	/*
	 * We don't implement CREAD.
	 */
	termios->c_cflag |= CREAD;

	/*
	 * Ask the core to calculate the divisor for us.
	 */
	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 
	quot = uart_get_divisor(port, baud);

	switch (termios->c_cflag & CSIZE) {
	case CS5:
		ubrlcr = UBRLCR_WRDLEN5;
		break;
	case CS6:
		ubrlcr = UBRLCR_WRDLEN6;
		break;
	case CS7:
		ubrlcr = UBRLCR_WRDLEN7;
		break;
	default: // CS8
		ubrlcr = UBRLCR_WRDLEN8;
		break;
	}
	if (termios->c_cflag & CSTOPB)
		ubrlcr |= UBRLCR_XSTOP;
	if (termios->c_cflag & PARENB) {
		ubrlcr |= UBRLCR_PRTEN;
		if (!(termios->c_cflag & PARODD))
			ubrlcr |= UBRLCR_EVENPRT;
	}
	if (port->fifosize > 1)
		ubrlcr |= UBRLCR_FIFOEN;

	spin_lock_irqsave(&port->lock, flags);

	/*
	 * Update the per-port timeout.
	 */
	uart_update_timeout(port, termios->c_cflag, baud);

	port->read_status_mask = UARTDR_OVERR;
	if (termios->c_iflag & INPCK)
		port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;

	/*
	 * Characters to ignore
	 */
	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= UARTDR_FRMERR | UARTDR_PARERR;
	if (termios->c_iflag & IGNBRK) {
		/*
		 * If we're ignoring parity and break indicators,
		 * ignore overruns to (for real raw support).
		 */
		if (termios->c_iflag & IGNPAR)
			port->ignore_status_mask |= UARTDR_OVERR;
	}

	quot -= 1;

	clps_writel(ubrlcr | quot, UBRLCR(port));

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *clps711xuart_type(struct uart_port *port)
{
	return port->type == PORT_CLPS711X ? "CLPS711x" : NULL;
}

/*
 * Configure/autoconfigure the port.
 */
static void clps711xuart_config_port(struct uart_port *port, int flags)
{
	if (flags & UART_CONFIG_TYPE)
		port->type = PORT_CLPS711X;
}

static void clps711xuart_release_port(struct uart_port *port)
{
}

static int clps711xuart_request_port(struct uart_port *port)
{
	return 0;
}

static struct uart_ops clps711x_pops = {
	.tx_empty	= clps711xuart_tx_empty,
	.set_mctrl	= clps711xuart_set_mctrl_null,
	.get_mctrl	= clps711xuart_get_mctrl,
	.stop_tx	= clps711xuart_stop_tx,
	.start_tx	= clps711xuart_start_tx,
	.stop_rx	= clps711xuart_stop_rx,
	.enable_ms	= clps711xuart_enable_ms,
	.break_ctl	= clps711xuart_break_ctl,
	.startup	= clps711xuart_startup,
	.shutdown	= clps711xuart_shutdown,
	.set_termios	= clps711xuart_set_termios,
	.type		= clps711xuart_type,
	.config_port	= clps711xuart_config_port,
	.release_port	= clps711xuart_release_port,
	.request_port	= clps711xuart_request_port,
};

static struct uart_port clps711x_ports[UART_NR] = {
	{
		.iobase		= SYSCON1,
		.irq		= IRQ_UTXINT1, /* IRQ_URXINT1, IRQ_UMSINT */
#ifdef CONFIG_MP1000_90MHZ
		.uartclk	= 4515840,
#else
		.uartclk	= 3686400,
#endif
		.fifosize	= 16,
		.ops		= &clps711x_pops,
		.line		= 0,
		.flags		= ASYNC_BOOT_AUTOCONF,
	},
	{
		.iobase		= SYSCON2,
		.irq		= IRQ_UTXINT2, /* IRQ_URXINT2 */
#ifdef CONFIG_MP1000_90MHZ
		.uartclk	= 4515840,
#else
		.uartclk	= 3686400,
#endif
		.fifosize	= 16,
		.ops		= &clps711x_pops,
		.line		= 1,
		.flags		= ASYNC_BOOT_AUTOCONF,
	}
};

#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
/*
 *	Print a string to the serial port trying not to disturb
 *	any possible real use of the port...
 *
 *	The console_lock must be held when we get here.
 *
 *	Note that this is called with interrupts already disabled
 */
static void
clps711xuart_console_write(struct console *co, const char *s,
			   unsigned int count)
{
	struct uart_port *port = clps711x_ports + co->index;
	unsigned int status, syscon;
	int i;

	/*
	 *	Ensure that the port is enabled.
	 */
	syscon = clps_readl(SYSCON(port));
	clps_writel(syscon | SYSCON_UARTEN, SYSCON(port));

	/*
	 *	Now, do each character
	 */
	for (i = 0; i < count; i++) {
		do {
			status = clps_readl(SYSFLG(port));
		} while (status & SYSFLG_UTXFF);
		clps_writel(s[i], UARTDR(port));
		if (s[i] == '\n') {
			do {
				status = clps_readl(SYSFLG(port));
			} while (status & SYSFLG_UTXFF);
			clps_writel('\r', UARTDR(port));
		}
	}

	/*
	 *	Finally, wait for transmitter to become empty
	 *	and restore the uart state.
	 */
	do {
		status = clps_readl(SYSFLG(port));
	} while (status & SYSFLG_UBUSY);

	clps_writel(syscon, SYSCON(port));
}

static void __init
clps711xuart_console_get_options(struct uart_port *port, int *baud,
				 int *parity, int *bits)
{
	if (clps_readl(SYSCON(port)) & SYSCON_UARTEN) {
		unsigned int ubrlcr, quot;

		ubrlcr = clps_readl(UBRLCR(port));

		*parity = 'n';
		if (ubrlcr & UBRLCR_PRTEN) {
			if (ubrlcr & UBRLCR_EVENPRT)
				*parity = 'e';
			else
				*parity = 'o';
		}

		if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
			*bits = 7;
		else
			*bits = 8;

		quot = ubrlcr & UBRLCR_BAUD_MASK;
		*baud = port->uartclk / (16 * (quot + 1));
	}
}

static int __init clps711xuart_console_setup(struct console *co, char *options)
{
	struct uart_port *port;
	int baud = 38400;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	/*
	 * Check whether an invalid uart number has been specified, and
	 * if so, search for the first available port that does have
	 * console support.
	 */
	port = uart_get_console(clps711x_ports, UART_NR, co);

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);
	else
		clps711xuart_console_get_options(port, &baud, &parity, &bits);

	return uart_set_options(port, co, baud, parity, bits, flow);
}

static struct uart_driver clps711x_reg;
static struct console clps711x_console = {
	.name		= "ttyCL",
	.write		= clps711xuart_console_write,
	.device		= uart_console_device,
	.setup		= clps711xuart_console_setup,
	.flags		= CON_PRINTBUFFER,
	.index		= -1,
	.data		= &clps711x_reg,
};

static int __init clps711xuart_console_init(void)
{
	register_console(&clps711x_console);
	return 0;
}
console_initcall(clps711xuart_console_init);

#define CLPS711X_CONSOLE	&clps711x_console
#else
#define CLPS711X_CONSOLE	NULL
#endif

static struct uart_driver clps711x_reg = {
	.driver_name		= "ttyCL",
	.dev_name		= "ttyCL",
	.devfs_name		= "ttyCL",
	.major			= SERIAL_CLPS711X_MAJOR,
	.minor			= SERIAL_CLPS711X_MINOR,
	.nr			= UART_NR,

	.cons			= CLPS711X_CONSOLE,
};

static int __init clps711xuart_init(void)
{
	int ret, i;

	printk(KERN_INFO "Serial: CLPS711x driver $Revision: 1.42 $\n");

	ret = uart_register_driver(&clps711x_reg);
	if (ret)
		return ret;

	for (i = 0; i < UART_NR; i++)
		uart_add_one_port(&clps711x_reg, &clps711x_ports[i]);

	return 0;
}

static void __exit clps711xuart_exit(void)
{
	int i;

	for (i = 0; i < UART_NR; i++)
		uart_remove_one_port(&clps711x_reg, &clps711x_ports[i]);

	uart_unregister_driver(&clps711x_reg);
}

module_init(clps711xuart_init);
module_exit(clps711xuart_exit);

MODULE_AUTHOR("Deep Blue Solutions Ltd");
MODULE_DESCRIPTION("CLPS-711x generic serial driver $Revision: 1.42 $");
MODULE_LICENSE("GPL");
MODULE_ALIAS_CHARDEV(SERIAL_CLPS711X_MAJOR, SERIAL_CLPS711X_MINOR);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/char/clps711x.c
	3	*
	4	* Driver for CLPS711x serial ports
	5	*
	6	* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
	7	*
	8	* Copyright 1999 ARM Limited
	9	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	24	*
	25	* $Id: clps711x.c,v 1.42 2002/07/28 10:03:28 rmk Exp $
	26	*
	27	*/
	28	#include <linux/config.h>
	29
	30	#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
	31	#define SUPPORT_SYSRQ
	32	#endif
	33
	34	#include <linux/module.h>
	35	#include <linux/ioport.h>
	36	#include <linux/init.h>
	37	#include <linux/console.h>
	38	#include <linux/sysrq.h>
	39	#include <linux/spinlock.h>
	40	#include <linux/device.h>
	41	#include <linux/tty.h>
	42	#include <linux/tty_flip.h>
	43	#include <linux/serial_core.h>
	44	#include <linux/serial.h>
	45
	46	#include <asm/hardware.h>
	47	#include <asm/io.h>
	48	#include <asm/irq.h>
	49	#include <asm/hardware/clps7111.h>
	50
	51	#define UART_NR 2
	52
	53	#define SERIAL_CLPS711X_MAJOR 204
	54	#define SERIAL_CLPS711X_MINOR 40
	55	#define SERIAL_CLPS711X_NR UART_NR
	56
	57	/*
	58	* We use the relevant SYSCON register as a base address for these ports.
	59	*/
	60	#define UBRLCR(port) ((port)->iobase + UBRLCR1 - SYSCON1)
	61	#define UARTDR(port) ((port)->iobase + UARTDR1 - SYSCON1)
	62	#define SYSFLG(port) ((port)->iobase + SYSFLG1 - SYSCON1)
	63	#define SYSCON(port) ((port)->iobase + SYSCON1 - SYSCON1)
	64
65	#define TX_IRQ(port) ((port)->irq)
66	#define RX_IRQ(port) ((port)->irq + 1)
67
68	#define UART_ANY_ERR (UARTDR_FRMERR \| UARTDR_PARERR \| UARTDR_OVERR)
69
70	#define tx_enabled(port) ((port)->unused[0])
71
b129a8cc	72	static void clps711xuart_stop_tx(struct uart_port *port)
1da177e4 LT	73	{
	74	if (tx_enabled(port)) {
	75	disable_irq(TX_IRQ(port));
	76	tx_enabled(port) = 0;
	77	}
	78	}
	79
b129a8cc	80	static void clps711xuart_start_tx(struct uart_port *port)
1da177e4 LT	81	{
	82	if (!tx_enabled(port)) {
	83	enable_irq(TX_IRQ(port));
	84	tx_enabled(port) = 1;
	85	}
	86	}
	87
	88	static void clps711xuart_stop_rx(struct uart_port *port)
	89	{
	90	disable_irq(RX_IRQ(port));
	91	}
	92
	93	static void clps711xuart_enable_ms(struct uart_port *port)
	94	{
	95	}
	96
	97	static irqreturn_t clps711xuart_int_rx(int irq, void dev_id, struct pt_regs regs)
	98	{
	99	struct uart_port *port = dev_id;
	100	struct tty_struct *tty = port->info->tty;
f9937242	101	unsigned int status, ch, flg;
1da177e4 LT	102
	103	status = clps_readl(SYSFLG(port));
	104	while (!(status & SYSFLG_URXFE)) {
	105	ch = clps_readl(UARTDR(port));
	106
	107	if (tty->flip.count >= TTY_FLIPBUF_SIZE)
	108	goto ignore_char;
	109	port->icount.rx++;
	110
	111	flg = TTY_NORMAL;
	112
	113	/*
	114	* Note that the error handling code is
	115	* out of the main execution path
	116	*/
2a9604b8 RK	117	if (unlikely(ch & UART_ANY_ERR)) {
	118	if (ch & UARTDR_PARERR)
	119	port->icount.parity++;
	120	else if (ch & UARTDR_FRMERR)
	121	port->icount.frame++;
	122	if (ch & UARTDR_OVERR)
	123	port->icount.overrun++;
1da177e4	124
2a9604b8	125	ch &= port->read_status_mask;
1da177e4	126
2a9604b8 RK	127	if (ch & UARTDR_PARERR)
	128	flg = TTY_PARITY;
	129	else if (ch & UARTDR_FRMERR)
	130	flg = TTY_FRAME;
1da177e4	131
2a9604b8 RK	132	#ifdef SUPPORT_SYSRQ
	133	port->sysrq = 0;
	134	#endif
	135	}
1da177e4	136
2a9604b8 RK	137	if (uart_handle_sysrq_char(port, ch, regs))
2a9604b8 RK	138	goto ignore_char;
1da177e4	139
1da177e4 LT	140	/*
	141	* CHECK: does overrun affect the current character?
	142	* ASSUMPTION: it does not.
	143	*/
05ab3014	144	uart_insert_char(port, ch, UARTDR_OVERR, ch, flg);
2a9604b8 RK	145
	146	ignore_char:
	147	status = clps_readl(SYSFLG(port));
1da177e4	148	}
2a9604b8 RK	149	tty_flip_buffer_push(tty);
2a9604b8 RK	150	return IRQ_HANDLED;
1da177e4 LT	151	}
	152
	153	static irqreturn_t clps711xuart_int_tx(int irq, void dev_id, struct pt_regs regs)
	154	{
	155	struct uart_port *port = dev_id;
	156	struct circ_buf *xmit = &port->info->xmit;
	157	int count;
	158
	159	if (port->x_char) {
	160	clps_writel(port->x_char, UARTDR(port));
	161	port->icount.tx++;
	162	port->x_char = 0;
	163	return IRQ_HANDLED;
	164	}
	165	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
b129a8cc	166	clps711xuart_stop_tx(port);
1da177e4 LT	167	return IRQ_HANDLED;
	168	}
	169
	170	count = port->fifosize >> 1;
	171	do {
	172	clps_writel(xmit->buf[xmit->tail], UARTDR(port));
	173	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
	174	port->icount.tx++;
	175	if (uart_circ_empty(xmit))
	176	break;
	177	} while (--count > 0);
	178
	179	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	180	uart_write_wakeup(port);
	181
	182	if (uart_circ_empty(xmit))
b129a8cc	183	clps711xuart_stop_tx(port);
1da177e4 LT	184
	185	return IRQ_HANDLED;
	186	}
	187
	188	static unsigned int clps711xuart_tx_empty(struct uart_port *port)
	189	{
	190	unsigned int status = clps_readl(SYSFLG(port));
	191	return status & SYSFLG_UBUSY ? 0 : TIOCSER_TEMT;
	192	}
	193
	194	static unsigned int clps711xuart_get_mctrl(struct uart_port *port)
	195	{
	196	unsigned int port_addr;
	197	unsigned int result = 0;
	198	unsigned int status;
	199
	200	port_addr = SYSFLG(port);
	201	if (port_addr == SYSFLG1) {
	202	status = clps_readl(SYSFLG1);
	203	if (status & SYSFLG1_DCD)
	204	result \|= TIOCM_CAR;
	205	if (status & SYSFLG1_DSR)
	206	result \|= TIOCM_DSR;
	207	if (status & SYSFLG1_CTS)
	208	result \|= TIOCM_CTS;
	209	}
	210
	211	return result;
	212	}
	213
	214	static void
	215	clps711xuart_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
	216	{
	217	}
	218
	219	static void clps711xuart_break_ctl(struct uart_port *port, int break_state)
	220	{
	221	unsigned long flags;
	222	unsigned int ubrlcr;
	223
	224	spin_lock_irqsave(&port->lock, flags);
	225	ubrlcr = clps_readl(UBRLCR(port));
	226	if (break_state == -1)
	227	ubrlcr \|= UBRLCR_BREAK;
	228	else
	229	ubrlcr &= ~UBRLCR_BREAK;
	230	clps_writel(ubrlcr, UBRLCR(port));
	231	spin_unlock_irqrestore(&port->lock, flags);
	232	}
	233
	234	static int clps711xuart_startup(struct uart_port *port)
	235	{
	236	unsigned int syscon;
	237	int retval;
	238
	239	tx_enabled(port) = 1;
	240
	241	/*
	242	* Allocate the IRQs
	243	*/
	244	retval = request_irq(TX_IRQ(port), clps711xuart_int_tx, 0,
	245	"clps711xuart_tx", port);
	246	if (retval)
	247	return retval;
248
249	retval = request_irq(RX_IRQ(port), clps711xuart_int_rx, 0,
250	"clps711xuart_rx", port);
251	if (retval) {
252	free_irq(TX_IRQ(port), port);
253	return retval;
254	}
255
256	/*
257	* enable the port
258	*/
259	syscon = clps_readl(SYSCON(port));
260	syscon \|= SYSCON_UARTEN;
261	clps_writel(syscon, SYSCON(port));
262
263	return 0;
264	}
265
266	static void clps711xuart_shutdown(struct uart_port *port)
267	{
268	unsigned int ubrlcr, syscon;
269
270	/*
271	* Free the interrupt
272	*/
273	free_irq(TX_IRQ(port), port); /* TX interrupt */
274	free_irq(RX_IRQ(port), port); /* RX interrupt */
275
276	/*
277	* disable the port
278	*/
279	syscon = clps_readl(SYSCON(port));
280	syscon &= ~SYSCON_UARTEN;
281	clps_writel(syscon, SYSCON(port));
282
283	/*
284	* disable break condition and fifos
285	*/
286	ubrlcr = clps_readl(UBRLCR(port));
287	ubrlcr &= ~(UBRLCR_FIFOEN \| UBRLCR_BREAK);
288	clps_writel(ubrlcr, UBRLCR(port));
289	}
290
291	static void
292	clps711xuart_set_termios(struct uart_port port, struct termios termios,
293	struct termios *old)
294	{
295	unsigned int ubrlcr, baud, quot;
296	unsigned long flags;
297
298	/*
299	* We don't implement CREAD.
300	*/
301	termios->c_cflag \|= CREAD;
302
303	/*
304	* Ask the core to calculate the divisor for us.
305	*/
306	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
307	quot = uart_get_divisor(port, baud);
308
309	switch (termios->c_cflag & CSIZE) {
310	case CS5:
311	ubrlcr = UBRLCR_WRDLEN5;
312	break;
313	case CS6:
314	ubrlcr = UBRLCR_WRDLEN6;
315	break;
316	case CS7:
317	ubrlcr = UBRLCR_WRDLEN7;
318	break;
319	default: // CS8
320	ubrlcr = UBRLCR_WRDLEN8;
321	break;
322	}
323	if (termios->c_cflag & CSTOPB)
324	ubrlcr \|= UBRLCR_XSTOP;
325	if (termios->c_cflag & PARENB) {
326	ubrlcr \|= UBRLCR_PRTEN;
327	if (!(termios->c_cflag & PARODD))
328	ubrlcr \|= UBRLCR_EVENPRT;
329	}
330	if (port->fifosize > 1)
331	ubrlcr \|= UBRLCR_FIFOEN;
332
333	spin_lock_irqsave(&port->lock, flags);
334
335	/*
336	* Update the per-port timeout.
337	*/
338	uart_update_timeout(port, termios->c_cflag, baud);
339
340	port->read_status_mask = UARTDR_OVERR;
341	if (termios->c_iflag & INPCK)
342	port->read_status_mask \|= UARTDR_PARERR \| UARTDR_FRMERR;
343
344	/*
345	* Characters to ignore
346	*/
347	port->ignore_status_mask = 0;
348	if (termios->c_iflag & IGNPAR)
349	port->ignore_status_mask \|= UARTDR_FRMERR \| UARTDR_PARERR;
350	if (termios->c_iflag & IGNBRK) {
351	/*
352	* If we're ignoring parity and break indicators,
353	* ignore overruns to (for real raw support).
354	*/
355	if (termios->c_iflag & IGNPAR)
356	port->ignore_status_mask \|= UARTDR_OVERR;
357	}
358
359	quot -= 1;
360
361	clps_writel(ubrlcr \| quot, UBRLCR(port));
362
363	spin_unlock_irqrestore(&port->lock, flags);
364	}
365
366	static const char clps711xuart_type(struct uart_port port)
367	{
368	return port->type == PORT_CLPS711X ? "CLPS711x" : NULL;
369	}
370
371	/*
372	* Configure/autoconfigure the port.
373	*/
374	static void clps711xuart_config_port(struct uart_port *port, int flags)
375	{
376	if (flags & UART_CONFIG_TYPE)
377	port->type = PORT_CLPS711X;
378	}
379
380	static void clps711xuart_release_port(struct uart_port *port)
381	{
382	}
383
384	static int clps711xuart_request_port(struct uart_port *port)
385	{
386	return 0;
387	}
388
389	static struct uart_ops clps711x_pops = {
390	.tx_empty = clps711xuart_tx_empty,
391	.set_mctrl = clps711xuart_set_mctrl_null,
392	.get_mctrl = clps711xuart_get_mctrl,
393	.stop_tx = clps711xuart_stop_tx,
394	.start_tx = clps711xuart_start_tx,
395	.stop_rx = clps711xuart_stop_rx,
396	.enable_ms = clps711xuart_enable_ms,
397	.break_ctl = clps711xuart_break_ctl,
398	.startup = clps711xuart_startup,
399	.shutdown = clps711xuart_shutdown,
400	.set_termios = clps711xuart_set_termios,
401	.type = clps711xuart_type,
402	.config_port = clps711xuart_config_port,
403	.release_port = clps711xuart_release_port,
404	.request_port = clps711xuart_request_port,
405	};
406
407	static struct uart_port clps711x_ports[UART_NR] = {
408	{
409	.iobase = SYSCON1,
410	.irq = IRQ_UTXINT1, /* IRQ_URXINT1, IRQ_UMSINT */
0b83f140 JR	411	#ifdef CONFIG_MP1000_90MHZ
	412	.uartclk = 4515840,
	413	#else
1da177e4	414	.uartclk = 3686400,
0b83f140	415	#endif
1da177e4 LT	416	.fifosize = 16,
	417	.ops = &clps711x_pops,
	418	.line = 0,
	419	.flags = ASYNC_BOOT_AUTOCONF,
	420	},
	421	{
	422	.iobase = SYSCON2,
	423	.irq = IRQ_UTXINT2, /* IRQ_URXINT2 */
0b83f140 JR	424	#ifdef CONFIG_MP1000_90MHZ
	425	.uartclk = 4515840,
	426	#else
1da177e4	427	.uartclk = 3686400,
0b83f140	428	#endif
1da177e4 LT	429	.fifosize = 16,
	430	.ops = &clps711x_pops,
	431	.line = 1,
	432	.flags = ASYNC_BOOT_AUTOCONF,
	433	}
	434	};
	435
	436	#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
	437	/*
	438	* Print a string to the serial port trying not to disturb
	439	* any possible real use of the port...
	440	*
	441	* The console_lock must be held when we get here.
	442	*
	443	* Note that this is called with interrupts already disabled
	444	*/
	445	static void
	446	clps711xuart_console_write(struct console co, const char s,
	447	unsigned int count)
	448	{
	449	struct uart_port *port = clps711x_ports + co->index;
	450	unsigned int status, syscon;
	451	int i;
	452
	453	/*
	454	* Ensure that the port is enabled.
	455	*/
	456	syscon = clps_readl(SYSCON(port));
	457	clps_writel(syscon \| SYSCON_UARTEN, SYSCON(port));
	458
	459	/*
	460	* Now, do each character
	461	*/
	462	for (i = 0; i < count; i++) {
	463	do {
	464	status = clps_readl(SYSFLG(port));
	465	} while (status & SYSFLG_UTXFF);
	466	clps_writel(s[i], UARTDR(port));
	467	if (s[i] == '\n') {
	468	do {
	469	status = clps_readl(SYSFLG(port));
	470	} while (status & SYSFLG_UTXFF);
	471	clps_writel('\r', UARTDR(port));
	472	}
	473	}
	474
	475	/*
	476	* Finally, wait for transmitter to become empty
	477	* and restore the uart state.
	478	*/
	479	do {
	480	status = clps_readl(SYSFLG(port));
	481	} while (status & SYSFLG_UBUSY);
	482
	483	clps_writel(syscon, SYSCON(port));
	484	}
	485
	486	static void __init
	487	clps711xuart_console_get_options(struct uart_port port, int baud,
	488	int parity, int bits)
	489	{
	490	if (clps_readl(SYSCON(port)) & SYSCON_UARTEN) {
	491	unsigned int ubrlcr, quot;
	492
493	ubrlcr = clps_readl(UBRLCR(port));
494
495	*parity = 'n';
496	if (ubrlcr & UBRLCR_PRTEN) {
497	if (ubrlcr & UBRLCR_EVENPRT)
498	*parity = 'e';
499	else
500	*parity = 'o';
501	}
502
503	if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
504	*bits = 7;
505	else
506	*bits = 8;
507
508	quot = ubrlcr & UBRLCR_BAUD_MASK;
509	baud = port->uartclk / (16 (quot + 1));
510	}
511	}
512
513	static int __init clps711xuart_console_setup(struct console co, char options)
514	{
515	struct uart_port *port;
516	int baud = 38400;
517	int bits = 8;
518	int parity = 'n';
519	int flow = 'n';
520
521	/*
522	* Check whether an invalid uart number has been specified, and
523	* if so, search for the first available port that does have
524	* console support.
525	*/
526	port = uart_get_console(clps711x_ports, UART_NR, co);
527
528	if (options)
529	uart_parse_options(options, &baud, &parity, &bits, &flow);
530	else
531	clps711xuart_console_get_options(port, &baud, &parity, &bits);
532
533	return uart_set_options(port, co, baud, parity, bits, flow);
534	}
535
2d93486c	536	static struct uart_driver clps711x_reg;
1da177e4 LT	537	static struct console clps711x_console = {
	538	.name = "ttyCL",
	539	.write = clps711xuart_console_write,
	540	.device = uart_console_device,
	541	.setup = clps711xuart_console_setup,
	542	.flags = CON_PRINTBUFFER,
	543	.index = -1,
	544	.data = &clps711x_reg,
	545	};
	546
	547	static int __init clps711xuart_console_init(void)
	548	{
	549	register_console(&clps711x_console);
	550	return 0;
	551	}
	552	console_initcall(clps711xuart_console_init);
	553
	554	#define CLPS711X_CONSOLE &clps711x_console
	555	#else
	556	#define CLPS711X_CONSOLE NULL
	557	#endif
	558
	559	static struct uart_driver clps711x_reg = {
	560	.driver_name = "ttyCL",
	561	.dev_name = "ttyCL",
0b83f140	562	.devfs_name = "ttyCL",
1da177e4 LT	563	.major = SERIAL_CLPS711X_MAJOR,
	564	.minor = SERIAL_CLPS711X_MINOR,
	565	.nr = UART_NR,
	566
	567	.cons = CLPS711X_CONSOLE,
	568	};
	569
	570	static int __init clps711xuart_init(void)
	571	{
	572	int ret, i;
	573
	574	printk(KERN_INFO "Serial: CLPS711x driver $Revision: 1.42 $\n");
	575
	576	ret = uart_register_driver(&clps711x_reg);
	577	if (ret)
	578	return ret;
	579
	580	for (i = 0; i < UART_NR; i++)
	581	uart_add_one_port(&clps711x_reg, &clps711x_ports[i]);
	582
	583	return 0;
	584	}
	585
	586	static void __exit clps711xuart_exit(void)
	587	{
	588	int i;
	589
	590	for (i = 0; i < UART_NR; i++)
	591	uart_remove_one_port(&clps711x_reg, &clps711x_ports[i]);
	592
	593	uart_unregister_driver(&clps711x_reg);
	594	}
	595
	596	module_init(clps711xuart_init);
	597	module_exit(clps711xuart_exit);
	598
	599	MODULE_AUTHOR("Deep Blue Solutions Ltd");
	600	MODULE_DESCRIPTION("CLPS-711x generic serial driver $Revision: 1.42 $");
	601	MODULE_LICENSE("GPL");
	602	MODULE_ALIAS_CHARDEV(SERIAL_CLPS711X_MAJOR, SERIAL_CLPS711X_MINOR);