Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/cpm_uart.c | |
3 | * | |
4 | * Driver for CPM (SCC/SMC) serial ports; CPM1 definitions | |
5 | * | |
4c8d3d99 | 6 | * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) |
1da177e4 | 7 | * Pantelis Antoniou (panto@intracom.gr) (CPM1) |
311c4627 | 8 | * |
1da177e4 LT |
9 | * Copyright (C) 2004 Freescale Semiconductor, Inc. |
10 | * (C) 2004 Intracom, S.A. | |
6e197696 VB |
11 | * (C) 2006 MontaVista Software, Inc. |
12 | * Vitaly Bordug <vbordug@ru.mvista.com> | |
1da177e4 LT |
13 | * |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
27 | * | |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/module.h> |
31 | #include <linux/tty.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/console.h> | |
36 | #include <linux/sysrq.h> | |
37 | #include <linux/device.h> | |
38 | #include <linux/bootmem.h> | |
39 | #include <linux/dma-mapping.h> | |
40 | ||
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | ||
44 | #include <linux/serial_core.h> | |
45 | #include <linux/kernel.h> | |
46 | ||
47 | #include "cpm_uart.h" | |
48 | ||
49 | /**************************************************************/ | |
50 | ||
51 | void cpm_line_cr_cmd(int line, int cmd) | |
52 | { | |
53 | ushort val; | |
54 | volatile cpm8xx_t *cp = cpmp; | |
55 | ||
56 | switch (line) { | |
57 | case UART_SMC1: | |
58 | val = mk_cr_cmd(CPM_CR_CH_SMC1, cmd) | CPM_CR_FLG; | |
59 | break; | |
60 | case UART_SMC2: | |
61 | val = mk_cr_cmd(CPM_CR_CH_SMC2, cmd) | CPM_CR_FLG; | |
62 | break; | |
63 | case UART_SCC1: | |
64 | val = mk_cr_cmd(CPM_CR_CH_SCC1, cmd) | CPM_CR_FLG; | |
65 | break; | |
66 | case UART_SCC2: | |
67 | val = mk_cr_cmd(CPM_CR_CH_SCC2, cmd) | CPM_CR_FLG; | |
68 | break; | |
69 | case UART_SCC3: | |
70 | val = mk_cr_cmd(CPM_CR_CH_SCC3, cmd) | CPM_CR_FLG; | |
71 | break; | |
72 | case UART_SCC4: | |
73 | val = mk_cr_cmd(CPM_CR_CH_SCC4, cmd) | CPM_CR_FLG; | |
74 | break; | |
75 | default: | |
76 | return; | |
77 | ||
78 | } | |
79 | cp->cp_cpcr = val; | |
80 | while (cp->cp_cpcr & CPM_CR_FLG) ; | |
81 | } | |
82 | ||
83 | void smc1_lineif(struct uart_cpm_port *pinfo) | |
84 | { | |
1da177e4 LT |
85 | pinfo->brg = 1; |
86 | } | |
87 | ||
88 | void smc2_lineif(struct uart_cpm_port *pinfo) | |
89 | { | |
1da177e4 LT |
90 | pinfo->brg = 2; |
91 | } | |
92 | ||
93 | void scc1_lineif(struct uart_cpm_port *pinfo) | |
94 | { | |
95 | /* XXX SCC1: insert port configuration here */ | |
96 | pinfo->brg = 1; | |
97 | } | |
98 | ||
99 | void scc2_lineif(struct uart_cpm_port *pinfo) | |
100 | { | |
101 | /* XXX SCC2: insert port configuration here */ | |
102 | pinfo->brg = 2; | |
103 | } | |
104 | ||
105 | void scc3_lineif(struct uart_cpm_port *pinfo) | |
106 | { | |
107 | /* XXX SCC3: insert port configuration here */ | |
108 | pinfo->brg = 3; | |
109 | } | |
110 | ||
111 | void scc4_lineif(struct uart_cpm_port *pinfo) | |
112 | { | |
113 | /* XXX SCC4: insert port configuration here */ | |
114 | pinfo->brg = 4; | |
115 | } | |
116 | ||
117 | /* | |
311c4627 | 118 | * Allocate DP-Ram and memory buffers. We need to allocate a transmit and |
1da177e4 LT |
119 | * receive buffer descriptors from dual port ram, and a character |
120 | * buffer area from host mem. If we are allocating for the console we need | |
121 | * to do it from bootmem | |
122 | */ | |
123 | int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con) | |
124 | { | |
125 | int dpmemsz, memsz; | |
126 | u8 *dp_mem; | |
127 | uint dp_offset; | |
128 | u8 *mem_addr; | |
129 | dma_addr_t dma_addr = 0; | |
130 | ||
131 | pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line); | |
132 | ||
133 | dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos); | |
134 | dp_offset = cpm_dpalloc(dpmemsz, 8); | |
135 | if (IS_DPERR(dp_offset)) { | |
136 | printk(KERN_ERR | |
137 | "cpm_uart_cpm1.c: could not allocate buffer descriptors\n"); | |
138 | return -ENOMEM; | |
139 | } | |
140 | dp_mem = cpm_dpram_addr(dp_offset); | |
141 | ||
142 | memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) + | |
143 | L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize); | |
144 | if (is_con) { | |
311c4627 KG |
145 | /* was hostalloc but changed cause it blows away the */ |
146 | /* large tlb mapping when pinning the kernel area */ | |
4e4b7952 | 147 | mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8)); |
09b03b6c | 148 | dma_addr = (u32)mem_addr; |
1da177e4 LT |
149 | } else |
150 | mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr, | |
151 | GFP_KERNEL); | |
152 | ||
153 | if (mem_addr == NULL) { | |
154 | cpm_dpfree(dp_offset); | |
155 | printk(KERN_ERR | |
156 | "cpm_uart_cpm1.c: could not allocate coherent memory\n"); | |
157 | return -ENOMEM; | |
158 | } | |
159 | ||
160 | pinfo->dp_addr = dp_offset; | |
09b03b6c VB |
161 | pinfo->mem_addr = mem_addr; /* virtual address*/ |
162 | pinfo->dma_addr = dma_addr; /* physical address*/ | |
163 | pinfo->mem_size = memsz; | |
1da177e4 LT |
164 | |
165 | pinfo->rx_buf = mem_addr; | |
166 | pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos | |
167 | * pinfo->rx_fifosize); | |
168 | ||
169 | pinfo->rx_bd_base = (volatile cbd_t *)dp_mem; | |
170 | pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos; | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
175 | void cpm_uart_freebuf(struct uart_cpm_port *pinfo) | |
176 | { | |
177 | dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos * | |
178 | pinfo->rx_fifosize) + | |
179 | L1_CACHE_ALIGN(pinfo->tx_nrfifos * | |
180 | pinfo->tx_fifosize), pinfo->mem_addr, | |
181 | pinfo->dma_addr); | |
182 | ||
183 | cpm_dpfree(pinfo->dp_addr); | |
184 | } | |
185 | ||
186 | /* Setup any dynamic params in the uart desc */ | |
0091cf5a | 187 | int __init cpm_uart_init_portdesc(void) |
1da177e4 LT |
188 | { |
189 | pr_debug("CPM uart[-]:init portdesc\n"); | |
190 | ||
191 | cpm_uart_nr = 0; | |
192 | #ifdef CONFIG_SERIAL_CPM_SMC1 | |
193 | cpm_uart_ports[UART_SMC1].smcp = &cpmp->cp_smc[0]; | |
194 | /* | |
195 | * Is SMC1 being relocated? | |
196 | */ | |
197 | # ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH | |
198 | cpm_uart_ports[UART_SMC1].smcup = | |
199 | (smc_uart_t *) & cpmp->cp_dparam[0x3C0]; | |
200 | # else | |
201 | cpm_uart_ports[UART_SMC1].smcup = | |
202 | (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC1]; | |
203 | # endif | |
204 | cpm_uart_ports[UART_SMC1].port.mapbase = | |
205 | (unsigned long)&cpmp->cp_smc[0]; | |
206 | cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX); | |
207 | cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); | |
208 | cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
209 | cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1; | |
210 | #endif | |
211 | ||
212 | #ifdef CONFIG_SERIAL_CPM_SMC2 | |
213 | cpm_uart_ports[UART_SMC2].smcp = &cpmp->cp_smc[1]; | |
214 | cpm_uart_ports[UART_SMC2].smcup = | |
215 | (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC2]; | |
216 | cpm_uart_ports[UART_SMC2].port.mapbase = | |
217 | (unsigned long)&cpmp->cp_smc[1]; | |
218 | cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX); | |
219 | cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); | |
220 | cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
221 | cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2; | |
222 | #endif | |
223 | ||
224 | #ifdef CONFIG_SERIAL_CPM_SCC1 | |
225 | cpm_uart_ports[UART_SCC1].sccp = &cpmp->cp_scc[0]; | |
226 | cpm_uart_ports[UART_SCC1].sccup = | |
227 | (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC1]; | |
228 | cpm_uart_ports[UART_SCC1].port.mapbase = | |
229 | (unsigned long)&cpmp->cp_scc[0]; | |
230 | cpm_uart_ports[UART_SCC1].sccp->scc_sccm &= | |
231 | ~(UART_SCCM_TX | UART_SCCM_RX); | |
232 | cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &= | |
233 | ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
234 | cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
235 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1; | |
236 | #endif | |
237 | ||
238 | #ifdef CONFIG_SERIAL_CPM_SCC2 | |
239 | cpm_uart_ports[UART_SCC2].sccp = &cpmp->cp_scc[1]; | |
240 | cpm_uart_ports[UART_SCC2].sccup = | |
241 | (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC2]; | |
242 | cpm_uart_ports[UART_SCC2].port.mapbase = | |
243 | (unsigned long)&cpmp->cp_scc[1]; | |
244 | cpm_uart_ports[UART_SCC2].sccp->scc_sccm &= | |
245 | ~(UART_SCCM_TX | UART_SCCM_RX); | |
246 | cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &= | |
247 | ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
248 | cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
249 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2; | |
250 | #endif | |
251 | ||
252 | #ifdef CONFIG_SERIAL_CPM_SCC3 | |
253 | cpm_uart_ports[UART_SCC3].sccp = &cpmp->cp_scc[2]; | |
254 | cpm_uart_ports[UART_SCC3].sccup = | |
255 | (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC3]; | |
256 | cpm_uart_ports[UART_SCC3].port.mapbase = | |
257 | (unsigned long)&cpmp->cp_scc[2]; | |
258 | cpm_uart_ports[UART_SCC3].sccp->scc_sccm &= | |
259 | ~(UART_SCCM_TX | UART_SCCM_RX); | |
260 | cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &= | |
261 | ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
262 | cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
263 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3; | |
264 | #endif | |
265 | ||
266 | #ifdef CONFIG_SERIAL_CPM_SCC4 | |
267 | cpm_uart_ports[UART_SCC4].sccp = &cpmp->cp_scc[3]; | |
268 | cpm_uart_ports[UART_SCC4].sccup = | |
269 | (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC4]; | |
270 | cpm_uart_ports[UART_SCC4].port.mapbase = | |
271 | (unsigned long)&cpmp->cp_scc[3]; | |
272 | cpm_uart_ports[UART_SCC4].sccp->scc_sccm &= | |
273 | ~(UART_SCCM_TX | UART_SCCM_RX); | |
274 | cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &= | |
275 | ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
276 | cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq); | |
277 | cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4; | |
278 | #endif | |
279 | return 0; | |
280 | } |