Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
9399575d | 2 | * dz.c: Serial port driver for DECstations equipped |
1da177e4 LT |
3 | * with the DZ chipset. |
4 | * | |
fd8c5972 RB |
5 | * Copyright (C) 1998 Olivier A. D. Lebaillif |
6 | * | |
1da177e4 LT |
7 | * Email: olivier.lebaillif@ifrsys.com |
8 | * | |
87cff7fb | 9 | * Copyright (C) 2004, 2006, 2007 Maciej W. Rozycki |
9399575d | 10 | * |
1da177e4 LT |
11 | * [31-AUG-98] triemer |
12 | * Changed IRQ to use Harald's dec internals interrupts.h | |
13 | * removed base_addr code - moving address assignment to setup.c | |
14 | * Changed name of dz_init to rs_init to be consistent with tc code | |
15 | * [13-NOV-98] triemer fixed code to receive characters | |
fd8c5972 | 16 | * after patches by harald to irq code. |
1da177e4 LT |
17 | * [09-JAN-99] triemer minor fix for schedule - due to removal of timeout |
18 | * field from "current" - somewhere between 2.1.121 and 2.1.131 | |
19 | Qua Jun 27 15:02:26 BRT 2001 | |
20 | * [27-JUN-2001] Arnaldo Carvalho de Melo <acme@conectiva.com.br> - cleanups | |
fd8c5972 RB |
21 | * |
22 | * Parts (C) 1999 David Airlie, airlied@linux.ie | |
23 | * [07-SEP-99] Bugfixes | |
1da177e4 LT |
24 | * |
25 | * [06-Jan-2002] Russell King <rmk@arm.linux.org.uk> | |
26 | * Converted to new serial core | |
27 | */ | |
28 | ||
29 | #undef DEBUG_DZ | |
30 | ||
9399575d MR |
31 | #if defined(CONFIG_SERIAL_DZ_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
32 | #define SUPPORT_SYSRQ | |
33 | #endif | |
34 | ||
87cff7fb MR |
35 | #include <linux/bitops.h> |
36 | #include <linux/compiler.h> | |
37 | #include <linux/console.h> | |
9399575d | 38 | #include <linux/delay.h> |
87cff7fb | 39 | #include <linux/errno.h> |
1da177e4 | 40 | #include <linux/init.h> |
87cff7fb MR |
41 | #include <linux/interrupt.h> |
42 | #include <linux/kernel.h> | |
43 | #include <linux/major.h> | |
44 | #include <linux/module.h> | |
45 | #include <linux/serial.h> | |
46 | #include <linux/serial_core.h> | |
9399575d | 47 | #include <linux/sysrq.h> |
1da177e4 | 48 | #include <linux/tty.h> |
1da177e4 LT |
49 | |
50 | #include <asm/bootinfo.h> | |
87cff7fb MR |
51 | #include <asm/system.h> |
52 | ||
1da177e4 LT |
53 | #include <asm/dec/interrupts.h> |
54 | #include <asm/dec/kn01.h> | |
55 | #include <asm/dec/kn02.h> | |
56 | #include <asm/dec/machtype.h> | |
57 | #include <asm/dec/prom.h> | |
1da177e4 | 58 | |
1da177e4 LT |
59 | #include "dz.h" |
60 | ||
1da177e4 | 61 | static char *dz_name = "DECstation DZ serial driver version "; |
9399575d | 62 | static char *dz_version = "1.03"; |
1da177e4 LT |
63 | |
64 | struct dz_port { | |
65 | struct uart_port port; | |
66 | unsigned int cflag; | |
67 | }; | |
68 | ||
69 | static struct dz_port dz_ports[DZ_NB_PORT]; | |
70 | ||
1da177e4 LT |
71 | /* |
72 | * ------------------------------------------------------------ | |
73 | * dz_in () and dz_out () | |
74 | * | |
fd8c5972 | 75 | * These routines are used to access the registers of the DZ |
1da177e4 LT |
76 | * chip, hiding relocation differences between implementation. |
77 | * ------------------------------------------------------------ | |
78 | */ | |
79 | ||
80 | static inline unsigned short dz_in(struct dz_port *dport, unsigned offset) | |
81 | { | |
82 | volatile unsigned short *addr = | |
83 | (volatile unsigned short *) (dport->port.membase + offset); | |
9399575d | 84 | |
1da177e4 LT |
85 | return *addr; |
86 | } | |
87 | ||
88 | static inline void dz_out(struct dz_port *dport, unsigned offset, | |
89 | unsigned short value) | |
90 | { | |
91 | volatile unsigned short *addr = | |
92 | (volatile unsigned short *) (dport->port.membase + offset); | |
9399575d | 93 | |
1da177e4 LT |
94 | *addr = value; |
95 | } | |
96 | ||
97 | /* | |
98 | * ------------------------------------------------------------ | |
99 | * rs_stop () and rs_start () | |
100 | * | |
fd8c5972 RB |
101 | * These routines are called before setting or resetting |
102 | * tty->stopped. They enable or disable transmitter interrupts, | |
1da177e4 LT |
103 | * as necessary. |
104 | * ------------------------------------------------------------ | |
105 | */ | |
106 | ||
b129a8cc | 107 | static void dz_stop_tx(struct uart_port *uport) |
1da177e4 LT |
108 | { |
109 | struct dz_port *dport = (struct dz_port *)uport; | |
110 | unsigned short tmp, mask = 1 << dport->port.line; | |
111 | unsigned long flags; | |
112 | ||
113 | spin_lock_irqsave(&dport->port.lock, flags); | |
114 | tmp = dz_in(dport, DZ_TCR); /* read the TX flag */ | |
115 | tmp &= ~mask; /* clear the TX flag */ | |
116 | dz_out(dport, DZ_TCR, tmp); | |
117 | spin_unlock_irqrestore(&dport->port.lock, flags); | |
118 | } | |
119 | ||
b129a8cc | 120 | static void dz_start_tx(struct uart_port *uport) |
1da177e4 LT |
121 | { |
122 | struct dz_port *dport = (struct dz_port *)uport; | |
123 | unsigned short tmp, mask = 1 << dport->port.line; | |
124 | unsigned long flags; | |
125 | ||
126 | spin_lock_irqsave(&dport->port.lock, flags); | |
127 | tmp = dz_in(dport, DZ_TCR); /* read the TX flag */ | |
128 | tmp |= mask; /* set the TX flag */ | |
129 | dz_out(dport, DZ_TCR, tmp); | |
130 | spin_unlock_irqrestore(&dport->port.lock, flags); | |
131 | } | |
132 | ||
133 | static void dz_stop_rx(struct uart_port *uport) | |
134 | { | |
135 | struct dz_port *dport = (struct dz_port *)uport; | |
136 | unsigned long flags; | |
137 | ||
138 | spin_lock_irqsave(&dport->port.lock, flags); | |
139 | dport->cflag &= ~DZ_CREAD; | |
9399575d | 140 | dz_out(dport, DZ_LPR, dport->cflag | dport->port.line); |
1da177e4 LT |
141 | spin_unlock_irqrestore(&dport->port.lock, flags); |
142 | } | |
143 | ||
144 | static void dz_enable_ms(struct uart_port *port) | |
145 | { | |
146 | /* nothing to do */ | |
147 | } | |
148 | ||
149 | /* | |
150 | * ------------------------------------------------------------ | |
1da177e4 | 151 | * |
9399575d MR |
152 | * Here start the interrupt handling routines. All of the following |
153 | * subroutines are declared as inline and are folded into | |
154 | * dz_interrupt. They were separated out for readability's sake. | |
155 | * | |
156 | * Note: dz_interrupt() is a "fast" interrupt, which means that it | |
1da177e4 | 157 | * runs with interrupts turned off. People who may want to modify |
9399575d | 158 | * dz_interrupt() should try to keep the interrupt handler as fast as |
1da177e4 LT |
159 | * possible. After you are done making modifications, it is not a bad |
160 | * idea to do: | |
fd8c5972 | 161 | * |
1da177e4 LT |
162 | * make drivers/serial/dz.s |
163 | * | |
164 | * and look at the resulting assemble code in dz.s. | |
165 | * | |
166 | * ------------------------------------------------------------ | |
167 | */ | |
168 | ||
169 | /* | |
170 | * ------------------------------------------------------------ | |
171 | * receive_char () | |
172 | * | |
173 | * This routine deals with inputs from any lines. | |
174 | * ------------------------------------------------------------ | |
175 | */ | |
de320199 | 176 | static inline void dz_receive_chars(struct dz_port *dport_in) |
1da177e4 | 177 | { |
9399575d | 178 | struct dz_port *dport; |
1da177e4 LT |
179 | struct tty_struct *tty = NULL; |
180 | struct uart_icount *icount; | |
9399575d MR |
181 | int lines_rx[DZ_NB_PORT] = { [0 ... DZ_NB_PORT - 1] = 0 }; |
182 | unsigned short status; | |
1da177e4 | 183 | unsigned char ch, flag; |
9399575d | 184 | int i; |
1da177e4 | 185 | |
9399575d MR |
186 | while ((status = dz_in(dport_in, DZ_RBUF)) & DZ_DVAL) { |
187 | dport = &dz_ports[LINE(status)]; | |
188 | tty = dport->port.info->tty; /* point to the proper dev */ | |
1da177e4 | 189 | |
9399575d | 190 | ch = UCHAR(status); /* grab the char */ |
1da177e4 | 191 | |
1da177e4 | 192 | icount = &dport->port.icount; |
1da177e4 LT |
193 | icount->rx++; |
194 | ||
9399575d MR |
195 | flag = TTY_NORMAL; |
196 | if (status & DZ_FERR) { /* frame error */ | |
197 | /* | |
198 | * There is no separate BREAK status bit, so | |
199 | * treat framing errors as BREAKs for Magic SysRq | |
200 | * and SAK; normally, otherwise. | |
1da177e4 | 201 | */ |
9399575d MR |
202 | if (uart_handle_break(&dport->port)) |
203 | continue; | |
204 | if (dport->port.flags & UPF_SAK) | |
205 | flag = TTY_BREAK; | |
206 | else | |
1da177e4 | 207 | flag = TTY_FRAME; |
9399575d MR |
208 | } else if (status & DZ_OERR) /* overrun error */ |
209 | flag = TTY_OVERRUN; | |
210 | else if (status & DZ_PERR) /* parity error */ | |
211 | flag = TTY_PARITY; | |
212 | ||
213 | /* keep track of the statistics */ | |
214 | switch (flag) { | |
215 | case TTY_FRAME: | |
216 | icount->frame++; | |
217 | break; | |
218 | case TTY_PARITY: | |
219 | icount->parity++; | |
220 | break; | |
221 | case TTY_OVERRUN: | |
222 | icount->overrun++; | |
223 | break; | |
224 | case TTY_BREAK: | |
225 | icount->brk++; | |
226 | break; | |
227 | default: | |
228 | break; | |
1da177e4 | 229 | } |
1da177e4 | 230 | |
de320199 | 231 | if (uart_handle_sysrq_char(&dport->port, ch)) |
9399575d MR |
232 | continue; |
233 | ||
234 | if ((status & dport->port.ignore_status_mask) == 0) { | |
235 | uart_insert_char(&dport->port, | |
236 | status, DZ_OERR, ch, flag); | |
237 | lines_rx[LINE(status)] = 1; | |
238 | } | |
239 | } | |
240 | for (i = 0; i < DZ_NB_PORT; i++) | |
241 | if (lines_rx[i]) | |
242 | tty_flip_buffer_push(dz_ports[i].port.info->tty); | |
1da177e4 LT |
243 | } |
244 | ||
245 | /* | |
246 | * ------------------------------------------------------------ | |
247 | * transmit_char () | |
248 | * | |
249 | * This routine deals with outputs to any lines. | |
250 | * ------------------------------------------------------------ | |
251 | */ | |
9399575d | 252 | static inline void dz_transmit_chars(struct dz_port *dport_in) |
1da177e4 | 253 | { |
9399575d MR |
254 | struct dz_port *dport; |
255 | struct circ_buf *xmit; | |
256 | unsigned short status; | |
1da177e4 LT |
257 | unsigned char tmp; |
258 | ||
9399575d MR |
259 | status = dz_in(dport_in, DZ_CSR); |
260 | dport = &dz_ports[LINE(status)]; | |
261 | xmit = &dport->port.info->xmit; | |
262 | ||
263 | if (dport->port.x_char) { /* XON/XOFF chars */ | |
1da177e4 LT |
264 | dz_out(dport, DZ_TDR, dport->port.x_char); |
265 | dport->port.icount.tx++; | |
266 | dport->port.x_char = 0; | |
267 | return; | |
268 | } | |
9399575d | 269 | /* If nothing to do or stopped or hardware stopped. */ |
1da177e4 | 270 | if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) { |
b129a8cc | 271 | dz_stop_tx(&dport->port); |
1da177e4 LT |
272 | return; |
273 | } | |
274 | ||
275 | /* | |
9399575d MR |
276 | * If something to do... (remember the dz has no output fifo, |
277 | * so we go one char at a time) :-< | |
1da177e4 LT |
278 | */ |
279 | tmp = xmit->buf[xmit->tail]; | |
280 | xmit->tail = (xmit->tail + 1) & (DZ_XMIT_SIZE - 1); | |
281 | dz_out(dport, DZ_TDR, tmp); | |
282 | dport->port.icount.tx++; | |
283 | ||
284 | if (uart_circ_chars_pending(xmit) < DZ_WAKEUP_CHARS) | |
285 | uart_write_wakeup(&dport->port); | |
286 | ||
9399575d | 287 | /* Are we are done. */ |
1da177e4 | 288 | if (uart_circ_empty(xmit)) |
b129a8cc | 289 | dz_stop_tx(&dport->port); |
1da177e4 LT |
290 | } |
291 | ||
292 | /* | |
293 | * ------------------------------------------------------------ | |
9399575d | 294 | * check_modem_status() |
1da177e4 | 295 | * |
9399575d MR |
296 | * DS 3100 & 5100: Only valid for the MODEM line, duh! |
297 | * DS 5000/200: Valid for the MODEM and PRINTER line. | |
1da177e4 LT |
298 | * ------------------------------------------------------------ |
299 | */ | |
300 | static inline void check_modem_status(struct dz_port *dport) | |
301 | { | |
9399575d MR |
302 | /* |
303 | * FIXME: | |
304 | * 1. No status change interrupt; use a timer. | |
305 | * 2. Handle the 3100/5000 as appropriate. --macro | |
306 | */ | |
1da177e4 LT |
307 | unsigned short status; |
308 | ||
9399575d | 309 | /* If not the modem line just return. */ |
1da177e4 LT |
310 | if (dport->port.line != DZ_MODEM) |
311 | return; | |
312 | ||
313 | status = dz_in(dport, DZ_MSR); | |
314 | ||
315 | /* it's easy, since DSR2 is the only bit in the register */ | |
316 | if (status) | |
317 | dport->port.icount.dsr++; | |
318 | } | |
319 | ||
320 | /* | |
321 | * ------------------------------------------------------------ | |
322 | * dz_interrupt () | |
323 | * | |
324 | * this is the main interrupt routine for the DZ chip. | |
325 | * It deals with the multiple ports. | |
326 | * ------------------------------------------------------------ | |
327 | */ | |
7d12e780 | 328 | static irqreturn_t dz_interrupt(int irq, void *dev) |
1da177e4 | 329 | { |
15aafa2f | 330 | struct dz_port *dport = dev; |
1da177e4 LT |
331 | unsigned short status; |
332 | ||
333 | /* get the reason why we just got an irq */ | |
9399575d | 334 | status = dz_in(dport, DZ_CSR); |
1da177e4 | 335 | |
9399575d | 336 | if ((status & (DZ_RDONE | DZ_RIE)) == (DZ_RDONE | DZ_RIE)) |
de320199 | 337 | dz_receive_chars(dport); |
1da177e4 | 338 | |
9399575d | 339 | if ((status & (DZ_TRDY | DZ_TIE)) == (DZ_TRDY | DZ_TIE)) |
1da177e4 LT |
340 | dz_transmit_chars(dport); |
341 | ||
1da177e4 LT |
342 | return IRQ_HANDLED; |
343 | } | |
344 | ||
345 | /* | |
346 | * ------------------------------------------------------------------- | |
347 | * Here ends the DZ interrupt routines. | |
348 | * ------------------------------------------------------------------- | |
349 | */ | |
350 | ||
351 | static unsigned int dz_get_mctrl(struct uart_port *uport) | |
352 | { | |
9399575d MR |
353 | /* |
354 | * FIXME: Handle the 3100/5000 as appropriate. --macro | |
355 | */ | |
1da177e4 LT |
356 | struct dz_port *dport = (struct dz_port *)uport; |
357 | unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | |
358 | ||
359 | if (dport->port.line == DZ_MODEM) { | |
1da177e4 LT |
360 | if (dz_in(dport, DZ_MSR) & DZ_MODEM_DSR) |
361 | mctrl &= ~TIOCM_DSR; | |
362 | } | |
363 | ||
364 | return mctrl; | |
365 | } | |
366 | ||
367 | static void dz_set_mctrl(struct uart_port *uport, unsigned int mctrl) | |
368 | { | |
9399575d MR |
369 | /* |
370 | * FIXME: Handle the 3100/5000 as appropriate. --macro | |
371 | */ | |
1da177e4 LT |
372 | struct dz_port *dport = (struct dz_port *)uport; |
373 | unsigned short tmp; | |
374 | ||
375 | if (dport->port.line == DZ_MODEM) { | |
376 | tmp = dz_in(dport, DZ_TCR); | |
377 | if (mctrl & TIOCM_DTR) | |
378 | tmp &= ~DZ_MODEM_DTR; | |
379 | else | |
380 | tmp |= DZ_MODEM_DTR; | |
381 | dz_out(dport, DZ_TCR, tmp); | |
382 | } | |
383 | } | |
384 | ||
385 | /* | |
386 | * ------------------------------------------------------------------- | |
387 | * startup () | |
388 | * | |
389 | * various initialization tasks | |
fd8c5972 | 390 | * ------------------------------------------------------------------- |
1da177e4 LT |
391 | */ |
392 | static int dz_startup(struct uart_port *uport) | |
393 | { | |
394 | struct dz_port *dport = (struct dz_port *)uport; | |
395 | unsigned long flags; | |
396 | unsigned short tmp; | |
397 | ||
1da177e4 LT |
398 | spin_lock_irqsave(&dport->port.lock, flags); |
399 | ||
400 | /* enable the interrupt and the scanning */ | |
401 | tmp = dz_in(dport, DZ_CSR); | |
402 | tmp |= DZ_RIE | DZ_TIE | DZ_MSE; | |
403 | dz_out(dport, DZ_CSR, tmp); | |
404 | ||
405 | spin_unlock_irqrestore(&dport->port.lock, flags); | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
fd8c5972 | 410 | /* |
1da177e4 LT |
411 | * ------------------------------------------------------------------- |
412 | * shutdown () | |
413 | * | |
414 | * This routine will shutdown a serial port; interrupts are disabled, and | |
415 | * DTR is dropped if the hangup on close termio flag is on. | |
fd8c5972 | 416 | * ------------------------------------------------------------------- |
1da177e4 LT |
417 | */ |
418 | static void dz_shutdown(struct uart_port *uport) | |
419 | { | |
b129a8cc | 420 | dz_stop_tx(uport); |
1da177e4 LT |
421 | } |
422 | ||
423 | /* | |
9399575d MR |
424 | * ------------------------------------------------------------------- |
425 | * dz_tx_empty() -- get the transmitter empty status | |
1da177e4 LT |
426 | * |
427 | * Purpose: Let user call ioctl() to get info when the UART physically | |
428 | * is emptied. On bus types like RS485, the transmitter must | |
429 | * release the bus after transmitting. This must be done when | |
430 | * the transmit shift register is empty, not be done when the | |
431 | * transmit holding register is empty. This functionality | |
fd8c5972 | 432 | * allows an RS485 driver to be written in user space. |
9399575d | 433 | * ------------------------------------------------------------------- |
1da177e4 LT |
434 | */ |
435 | static unsigned int dz_tx_empty(struct uart_port *uport) | |
436 | { | |
437 | struct dz_port *dport = (struct dz_port *)uport; | |
9399575d | 438 | unsigned short tmp, mask = 1 << dport->port.line; |
1da177e4 | 439 | |
9399575d MR |
440 | tmp = dz_in(dport, DZ_TCR); |
441 | tmp &= mask; | |
442 | ||
443 | return tmp ? 0 : TIOCSER_TEMT; | |
1da177e4 LT |
444 | } |
445 | ||
446 | static void dz_break_ctl(struct uart_port *uport, int break_state) | |
447 | { | |
9399575d MR |
448 | /* |
449 | * FIXME: Can't access BREAK bits in TDR easily; | |
450 | * reuse the code for polled TX. --macro | |
451 | */ | |
1da177e4 LT |
452 | struct dz_port *dport = (struct dz_port *)uport; |
453 | unsigned long flags; | |
9399575d | 454 | unsigned short tmp, mask = 1 << dport->port.line; |
1da177e4 LT |
455 | |
456 | spin_lock_irqsave(&uport->lock, flags); | |
457 | tmp = dz_in(dport, DZ_TCR); | |
458 | if (break_state) | |
459 | tmp |= mask; | |
460 | else | |
461 | tmp &= ~mask; | |
462 | dz_out(dport, DZ_TCR, tmp); | |
463 | spin_unlock_irqrestore(&uport->lock, flags); | |
464 | } | |
465 | ||
606d099c AC |
466 | static void dz_set_termios(struct uart_port *uport, struct ktermios *termios, |
467 | struct ktermios *old_termios) | |
1da177e4 LT |
468 | { |
469 | struct dz_port *dport = (struct dz_port *)uport; | |
470 | unsigned long flags; | |
471 | unsigned int cflag, baud; | |
472 | ||
473 | cflag = dport->port.line; | |
474 | ||
475 | switch (termios->c_cflag & CSIZE) { | |
476 | case CS5: | |
477 | cflag |= DZ_CS5; | |
478 | break; | |
479 | case CS6: | |
480 | cflag |= DZ_CS6; | |
481 | break; | |
482 | case CS7: | |
483 | cflag |= DZ_CS7; | |
484 | break; | |
485 | case CS8: | |
486 | default: | |
487 | cflag |= DZ_CS8; | |
488 | } | |
489 | ||
490 | if (termios->c_cflag & CSTOPB) | |
491 | cflag |= DZ_CSTOPB; | |
492 | if (termios->c_cflag & PARENB) | |
493 | cflag |= DZ_PARENB; | |
494 | if (termios->c_cflag & PARODD) | |
495 | cflag |= DZ_PARODD; | |
496 | ||
497 | baud = uart_get_baud_rate(uport, termios, old_termios, 50, 9600); | |
498 | switch (baud) { | |
499 | case 50: | |
500 | cflag |= DZ_B50; | |
501 | break; | |
502 | case 75: | |
503 | cflag |= DZ_B75; | |
504 | break; | |
505 | case 110: | |
506 | cflag |= DZ_B110; | |
507 | break; | |
508 | case 134: | |
509 | cflag |= DZ_B134; | |
510 | break; | |
511 | case 150: | |
512 | cflag |= DZ_B150; | |
513 | break; | |
514 | case 300: | |
515 | cflag |= DZ_B300; | |
516 | break; | |
517 | case 600: | |
518 | cflag |= DZ_B600; | |
519 | break; | |
520 | case 1200: | |
521 | cflag |= DZ_B1200; | |
522 | break; | |
523 | case 1800: | |
524 | cflag |= DZ_B1800; | |
525 | break; | |
526 | case 2000: | |
527 | cflag |= DZ_B2000; | |
528 | break; | |
529 | case 2400: | |
530 | cflag |= DZ_B2400; | |
531 | break; | |
532 | case 3600: | |
533 | cflag |= DZ_B3600; | |
534 | break; | |
535 | case 4800: | |
536 | cflag |= DZ_B4800; | |
537 | break; | |
538 | case 7200: | |
539 | cflag |= DZ_B7200; | |
540 | break; | |
541 | case 9600: | |
542 | default: | |
543 | cflag |= DZ_B9600; | |
544 | } | |
545 | ||
546 | if (termios->c_cflag & CREAD) | |
547 | cflag |= DZ_RXENAB; | |
548 | ||
549 | spin_lock_irqsave(&dport->port.lock, flags); | |
550 | ||
9399575d | 551 | dz_out(dport, DZ_LPR, cflag | dport->port.line); |
1da177e4 LT |
552 | dport->cflag = cflag; |
553 | ||
554 | /* setup accept flag */ | |
555 | dport->port.read_status_mask = DZ_OERR; | |
556 | if (termios->c_iflag & INPCK) | |
557 | dport->port.read_status_mask |= DZ_FERR | DZ_PERR; | |
558 | ||
559 | /* characters to ignore */ | |
560 | uport->ignore_status_mask = 0; | |
561 | if (termios->c_iflag & IGNPAR) | |
562 | dport->port.ignore_status_mask |= DZ_FERR | DZ_PERR; | |
563 | ||
564 | spin_unlock_irqrestore(&dport->port.lock, flags); | |
565 | } | |
566 | ||
567 | static const char *dz_type(struct uart_port *port) | |
568 | { | |
569 | return "DZ"; | |
570 | } | |
571 | ||
572 | static void dz_release_port(struct uart_port *port) | |
573 | { | |
574 | /* nothing to do */ | |
575 | } | |
576 | ||
577 | static int dz_request_port(struct uart_port *port) | |
578 | { | |
579 | return 0; | |
580 | } | |
581 | ||
582 | static void dz_config_port(struct uart_port *port, int flags) | |
583 | { | |
584 | if (flags & UART_CONFIG_TYPE) | |
585 | port->type = PORT_DZ; | |
586 | } | |
587 | ||
588 | /* | |
589 | * verify the new serial_struct (for TIOCSSERIAL). | |
590 | */ | |
591 | static int dz_verify_port(struct uart_port *port, struct serial_struct *ser) | |
592 | { | |
593 | int ret = 0; | |
594 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_DZ) | |
595 | ret = -EINVAL; | |
596 | if (ser->irq != port->irq) | |
597 | ret = -EINVAL; | |
598 | return ret; | |
599 | } | |
600 | ||
601 | static struct uart_ops dz_ops = { | |
602 | .tx_empty = dz_tx_empty, | |
603 | .get_mctrl = dz_get_mctrl, | |
604 | .set_mctrl = dz_set_mctrl, | |
605 | .stop_tx = dz_stop_tx, | |
606 | .start_tx = dz_start_tx, | |
607 | .stop_rx = dz_stop_rx, | |
608 | .enable_ms = dz_enable_ms, | |
609 | .break_ctl = dz_break_ctl, | |
610 | .startup = dz_startup, | |
611 | .shutdown = dz_shutdown, | |
612 | .set_termios = dz_set_termios, | |
613 | .type = dz_type, | |
614 | .release_port = dz_release_port, | |
615 | .request_port = dz_request_port, | |
616 | .config_port = dz_config_port, | |
617 | .verify_port = dz_verify_port, | |
618 | }; | |
619 | ||
620 | static void __init dz_init_ports(void) | |
621 | { | |
622 | static int first = 1; | |
623 | struct dz_port *dport; | |
624 | unsigned long base; | |
625 | int i; | |
626 | ||
627 | if (!first) | |
628 | return; | |
629 | first = 0; | |
630 | ||
631 | if (mips_machtype == MACH_DS23100 || | |
632 | mips_machtype == MACH_DS5100) | |
46677736 | 633 | base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_DZ11); |
1da177e4 | 634 | else |
46677736 | 635 | base = CKSEG1ADDR(KN02_SLOT_BASE + KN02_DZ11); |
1da177e4 LT |
636 | |
637 | for (i = 0, dport = dz_ports; i < DZ_NB_PORT; i++, dport++) { | |
638 | spin_lock_init(&dport->port.lock); | |
639 | dport->port.membase = (char *) base; | |
9399575d | 640 | dport->port.iotype = UPIO_MEM; |
1da177e4 LT |
641 | dport->port.irq = dec_interrupt[DEC_IRQ_DZ11]; |
642 | dport->port.line = i; | |
643 | dport->port.fifosize = 1; | |
644 | dport->port.ops = &dz_ops; | |
645 | dport->port.flags = UPF_BOOT_AUTOCONF; | |
646 | } | |
647 | } | |
648 | ||
649 | static void dz_reset(struct dz_port *dport) | |
650 | { | |
651 | dz_out(dport, DZ_CSR, DZ_CLR); | |
1da177e4 | 652 | while (dz_in(dport, DZ_CSR) & DZ_CLR); |
1da177e4 LT |
653 | iob(); |
654 | ||
655 | /* enable scanning */ | |
656 | dz_out(dport, DZ_CSR, DZ_MSE); | |
657 | } | |
658 | ||
659 | #ifdef CONFIG_SERIAL_DZ_CONSOLE | |
9399575d MR |
660 | /* |
661 | * ------------------------------------------------------------------- | |
662 | * dz_console_putchar() -- transmit a character | |
663 | * | |
664 | * Polled transmission. This is tricky. We need to mask transmit | |
665 | * interrupts so that they do not interfere, enable the transmitter | |
666 | * for the line requested and then wait till the transmit scanner | |
667 | * requests data for this line. But it may request data for another | |
668 | * line first, in which case we have to disable its transmitter and | |
669 | * repeat waiting till our line pops up. Only then the character may | |
670 | * be transmitted. Finally, the state of the transmitter mask is | |
671 | * restored. Welcome to the world of PDP-11! | |
672 | * ------------------------------------------------------------------- | |
673 | */ | |
d608ab99 | 674 | static void dz_console_putchar(struct uart_port *uport, int ch) |
1da177e4 | 675 | { |
d358788f | 676 | struct dz_port *dport = (struct dz_port *)uport; |
1da177e4 | 677 | unsigned long flags; |
9399575d MR |
678 | unsigned short csr, tcr, trdy, mask; |
679 | int loops = 10000; | |
1da177e4 LT |
680 | |
681 | spin_lock_irqsave(&dport->port.lock, flags); | |
9399575d MR |
682 | csr = dz_in(dport, DZ_CSR); |
683 | dz_out(dport, DZ_CSR, csr & ~DZ_TIE); | |
684 | tcr = dz_in(dport, DZ_TCR); | |
685 | tcr |= 1 << dport->port.line; | |
686 | mask = tcr; | |
687 | dz_out(dport, DZ_TCR, mask); | |
688 | iob(); | |
689 | spin_unlock_irqrestore(&dport->port.lock, flags); | |
1da177e4 | 690 | |
dbab8128 | 691 | do { |
9399575d MR |
692 | trdy = dz_in(dport, DZ_CSR); |
693 | if (!(trdy & DZ_TRDY)) | |
694 | continue; | |
695 | trdy = (trdy & DZ_TLINE) >> 8; | |
696 | if (trdy == dport->port.line) | |
697 | break; | |
698 | mask &= ~(1 << trdy); | |
699 | dz_out(dport, DZ_TCR, mask); | |
700 | iob(); | |
701 | udelay(2); | |
dbab8128 | 702 | } while (loops--); |
1da177e4 | 703 | |
9399575d MR |
704 | if (loops) /* Cannot send otherwise. */ |
705 | dz_out(dport, DZ_TDR, ch); | |
1da177e4 | 706 | |
9399575d MR |
707 | dz_out(dport, DZ_TCR, tcr); |
708 | dz_out(dport, DZ_CSR, csr); | |
1da177e4 | 709 | } |
d358788f | 710 | |
fd8c5972 | 711 | /* |
1da177e4 LT |
712 | * ------------------------------------------------------------------- |
713 | * dz_console_print () | |
714 | * | |
715 | * dz_console_print is registered for printk. | |
716 | * The console must be locked when we get here. | |
fd8c5972 | 717 | * ------------------------------------------------------------------- |
1da177e4 | 718 | */ |
9399575d | 719 | static void dz_console_print(struct console *co, |
1da177e4 LT |
720 | const char *str, |
721 | unsigned int count) | |
722 | { | |
9399575d | 723 | struct dz_port *dport = &dz_ports[co->index]; |
1da177e4 LT |
724 | #ifdef DEBUG_DZ |
725 | prom_printf((char *) str); | |
726 | #endif | |
d358788f | 727 | uart_console_write(&dport->port, str, count, dz_console_putchar); |
1da177e4 LT |
728 | } |
729 | ||
730 | static int __init dz_console_setup(struct console *co, char *options) | |
731 | { | |
9399575d | 732 | struct dz_port *dport = &dz_ports[co->index]; |
1da177e4 LT |
733 | int baud = 9600; |
734 | int bits = 8; | |
735 | int parity = 'n'; | |
736 | int flow = 'n'; | |
1da177e4 LT |
737 | |
738 | if (options) | |
739 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
740 | ||
741 | dz_reset(dport); | |
742 | ||
9399575d | 743 | return uart_set_options(&dport->port, co, baud, parity, bits, flow); |
1da177e4 LT |
744 | } |
745 | ||
9399575d MR |
746 | static struct uart_driver dz_reg; |
747 | static struct console dz_sercons = { | |
1da177e4 LT |
748 | .name = "ttyS", |
749 | .write = dz_console_print, | |
750 | .device = uart_console_device, | |
751 | .setup = dz_console_setup, | |
9399575d MR |
752 | .flags = CON_PRINTBUFFER, |
753 | .index = -1, | |
754 | .data = &dz_reg, | |
1da177e4 LT |
755 | }; |
756 | ||
9399575d | 757 | static int __init dz_serial_console_init(void) |
1da177e4 | 758 | { |
9399575d MR |
759 | if (!IOASIC) { |
760 | dz_init_ports(); | |
761 | register_console(&dz_sercons); | |
762 | return 0; | |
763 | } else | |
764 | return -ENXIO; | |
1da177e4 LT |
765 | } |
766 | ||
9399575d MR |
767 | console_initcall(dz_serial_console_init); |
768 | ||
1da177e4 LT |
769 | #define SERIAL_DZ_CONSOLE &dz_sercons |
770 | #else | |
771 | #define SERIAL_DZ_CONSOLE NULL | |
772 | #endif /* CONFIG_SERIAL_DZ_CONSOLE */ | |
773 | ||
774 | static struct uart_driver dz_reg = { | |
775 | .owner = THIS_MODULE, | |
776 | .driver_name = "serial", | |
9399575d | 777 | .dev_name = "ttyS", |
1da177e4 LT |
778 | .major = TTY_MAJOR, |
779 | .minor = 64, | |
780 | .nr = DZ_NB_PORT, | |
781 | .cons = SERIAL_DZ_CONSOLE, | |
782 | }; | |
783 | ||
9399575d | 784 | static int __init dz_init(void) |
1da177e4 | 785 | { |
1da177e4 LT |
786 | int ret, i; |
787 | ||
9399575d MR |
788 | if (IOASIC) |
789 | return -ENXIO; | |
790 | ||
1da177e4 LT |
791 | printk("%s%s\n", dz_name, dz_version); |
792 | ||
793 | dz_init_ports(); | |
794 | ||
1da177e4 LT |
795 | #ifndef CONFIG_SERIAL_DZ_CONSOLE |
796 | /* reset the chip */ | |
797 | dz_reset(&dz_ports[0]); | |
798 | #endif | |
799 | ||
1da177e4 LT |
800 | ret = uart_register_driver(&dz_reg); |
801 | if (ret != 0) | |
0ba137e2 MR |
802 | goto out; |
803 | ||
804 | ret = request_irq(dz_ports[0].port.irq, dz_interrupt, IRQF_DISABLED, | |
805 | "DZ", &dz_ports[0]); | |
806 | if (ret != 0) { | |
807 | printk(KERN_ERR "dz: Cannot get IRQ %d!\n", | |
808 | dz_ports[0].port.irq); | |
809 | goto out_unregister; | |
810 | } | |
1da177e4 LT |
811 | |
812 | for (i = 0; i < DZ_NB_PORT; i++) | |
813 | uart_add_one_port(&dz_reg, &dz_ports[i].port); | |
814 | ||
815 | return ret; | |
0ba137e2 MR |
816 | |
817 | out_unregister: | |
818 | uart_unregister_driver(&dz_reg); | |
819 | ||
820 | out: | |
821 | return ret; | |
1da177e4 LT |
822 | } |
823 | ||
9399575d MR |
824 | module_init(dz_init); |
825 | ||
1da177e4 LT |
826 | MODULE_DESCRIPTION("DECstation DZ serial driver"); |
827 | MODULE_LICENSE("GPL"); |