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[ARM] 4995/1: <IMX UART>: Do not use URXD_CHARRDY for polling
[deliverable/linux.git] / drivers / serial / imx.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
27 */
1da177e4
LT		 28
29#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/ioport.h>
35#include <linux/init.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
d052d1be 38#include <linux/platform_device.h>
1da177e4
LT		 39#include <linux/tty.h>
40#include <linux/tty_flip.h>
41#include <linux/serial_core.h>
42#include <linux/serial.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46#include <asm/hardware.h>
5b802344 47#include <asm/arch/imx-uart.h>
1da177e4 48
ff4bfb21
SH		 49/* Register definitions */
50#define URXD0 0x0 /* Receiver Register */
51#define URTX0 0x40 /* Transmitter Register */
52#define UCR1 0x80 /* Control Register 1 */
53#define UCR2 0x84 /* Control Register 2 */
54#define UCR3 0x88 /* Control Register 3 */
55#define UCR4 0x8c /* Control Register 4 */
56#define UFCR 0x90 /* FIFO Control Register */
57#define USR1 0x94 /* Status Register 1 */
58#define USR2 0x98 /* Status Register 2 */
59#define UESC 0x9c /* Escape Character Register */
60#define UTIM 0xa0 /* Escape Timer Register */
61#define UBIR 0xa4 /* BRM Incremental Register */
62#define UBMR 0xa8 /* BRM Modulator Register */
63#define UBRC 0xac /* Baud Rate Count Register */
64#define BIPR1 0xb0 /* Incremental Preset Register 1 */
65#define BIPR2 0xb4 /* Incremental Preset Register 2 */
66#define BIPR3 0xb8 /* Incremental Preset Register 3 */
67#define BIPR4 0xbc /* Incremental Preset Register 4 */
68#define BMPR1 0xc0 /* BRM Modulator Register 1 */
69#define BMPR2 0xc4 /* BRM Modulator Register 2 */
70#define BMPR3 0xc8 /* BRM Modulator Register 3 */
71#define BMPR4 0xcc /* BRM Modulator Register 4 */
72#define UTS 0xd0 /* UART Test Register */
73
74/* UART Control Register Bit Fields.*/
75#define URXD_CHARRDY (1<<15)
76#define URXD_ERR (1<<14)
77#define URXD_OVRRUN (1<<13)
78#define URXD_FRMERR (1<<12)
79#define URXD_BRK (1<<11)
80#define URXD_PRERR (1<<10)
81#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87#define UCR1_IREN (1<<7) /* Infrared interface enable */
88#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90#define UCR1_SNDBRK (1<<4) /* Send break */
91#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93#define UCR1_DOZE (1<<1) /* Doze */
94#define UCR1_UARTEN (1<<0) /* UART enabled */
95#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97#define UCR2_CTSC (1<<13) /* CTS pin control */
98#define UCR2_CTS (1<<12) /* Clear to send */
99#define UCR2_ESCEN (1<<11) /* Escape enable */
100#define UCR2_PREN (1<<8) /* Parity enable */
101#define UCR2_PROE (1<<7) /* Parity odd/even */
102#define UCR2_STPB (1<<6) /* Stop */
103#define UCR2_WS (1<<5) /* Word size */
104#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105#define UCR2_TXEN (1<<2) /* Transmitter enabled */
106#define UCR2_RXEN (1<<1) /* Receiver enabled */
107#define UCR2_SRST (1<<0) /* SW reset */
108#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109#define UCR3_PARERREN (1<<12) /* Parity enable */
110#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111#define UCR3_DSR (1<<10) /* Data set ready */
112#define UCR3_DCD (1<<9) /* Data carrier detect */
113#define UCR3_RI (1<<8) /* Ring indicator */
114#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121#define UCR3_BPEN (1<<0) /* Preset registers enable */
122#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
123#define UCR4_INVR (1<<9) /* Inverted infrared reception */
124#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127#define UCR4_IRSC (1<<5) /* IR special case */
128#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136#define USR1_RTSS (1<<14) /* RTS pin status */
137#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138#define USR1_RTSD (1<<12) /* RTS delta */
139#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149#define USR2_IDLE (1<<12) /* Idle condition */
150#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151#define USR2_WAKE (1<<7) /* Wake */
152#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153#define USR2_TXDC (1<<3) /* Transmitter complete */
154#define USR2_BRCD (1<<2) /* Break condition */
155#define USR2_ORE (1<<1) /* Overrun error */
156#define USR2_RDR (1<<0) /* Recv data ready */
157#define UTS_FRCPERR (1<<13) /* Force parity error */
158#define UTS_LOOP (1<<12) /* Loop tx and rx */
159#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161#define UTS_TXFULL (1<<4) /* TxFIFO full */
162#define UTS_RXFULL (1<<3) /* RxFIFO full */
163#define UTS_SOFTRST (1<<0) /* Software reset */
164
1da177e4
LT		 165/* We've been assigned a range on the "Low-density serial ports" major */
166#define SERIAL_IMX_MAJOR 204
167#define MINOR_START 41
168
1da177e4
LT		 169/*
170 * This is the size of our serial port register set.
171 */
172#define UART_PORT_SIZE 0x100
173
174/*
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
179 */
180#define MCTRL_TIMEOUT (250*HZ/1000)
181
182#define DRIVER_NAME "IMX-uart"
183
184struct imx_port {
185 struct uart_port port;
186 struct timer_list timer;
187 unsigned int old_status;
5b802344
SH		 188 int txirq,rxirq,rtsirq;
189 int have_rtscts:1;
1da177e4
LT		 190};
191
192/*
193 * Handle any change of modem status signal since we were last called.
194 */
195static void imx_mctrl_check(struct imx_port *sport)
196{
197 unsigned int status, changed;
198
199 status = sport->port.ops->get_mctrl(&sport->port);
200 changed = status ^ sport->old_status;
201
202 if (changed == 0)
203 return;
204
205 sport->old_status = status;
206
207 if (changed & TIOCM_RI)
208 sport->port.icount.rng++;
209 if (changed & TIOCM_DSR)
210 sport->port.icount.dsr++;
211 if (changed & TIOCM_CAR)
212 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
213 if (changed & TIOCM_CTS)
214 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
215
216 wake_up_interruptible(&sport->port.info->delta_msr_wait);
217}
218
219/*
220 * This is our per-port timeout handler, for checking the
221 * modem status signals.
222 */
223static void imx_timeout(unsigned long data)
224{
225 struct imx_port *sport = (struct imx_port *)data;
226 unsigned long flags;
227
228 if (sport->port.info) {
229 spin_lock_irqsave(&sport->port.lock, flags);
230 imx_mctrl_check(sport);
231 spin_unlock_irqrestore(&sport->port.lock, flags);
232
233 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
234 }
235}
236
237/*
238 * interrupts disabled on entry
239 */
b129a8cc 240static void imx_stop_tx(struct uart_port *port)
1da177e4
LT		 241{
242 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 243 unsigned long temp;
244
245 temp = readl(sport->port.membase + UCR1);
246 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4
LT		 247}
248
249/*
250 * interrupts disabled on entry
251 */
252static void imx_stop_rx(struct uart_port *port)
253{
254 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 255 unsigned long temp;
256
257 temp = readl(sport->port.membase + UCR2);
258 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
1da177e4
LT		 259}
260
261/*
262 * Set the modem control timer to fire immediately.
263 */
264static void imx_enable_ms(struct uart_port *port)
265{
266 struct imx_port *sport = (struct imx_port *)port;
267
268 mod_timer(&sport->timer, jiffies);
269}
270
271static inline void imx_transmit_buffer(struct imx_port *sport)
272{
273 struct circ_buf *xmit = &sport->port.info->xmit;
274
ff4bfb21 275 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
1da177e4
LT		 276 /* send xmit->buf[xmit->tail]
277 * out the port here */
ff4bfb21 278 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
1da177e4
LT		 279 xmit->tail = (xmit->tail + 1) &
280 (UART_XMIT_SIZE - 1);
281 sport->port.icount.tx++;
282 if (uart_circ_empty(xmit))
283 break;
8c0b254b 284 }
1da177e4
LT		 285
286 if (uart_circ_empty(xmit))
b129a8cc 287 imx_stop_tx(&sport->port);
1da177e4
LT		 288}
289
290/*
291 * interrupts disabled on entry
292 */
b129a8cc 293static void imx_start_tx(struct uart_port *port)
1da177e4
LT		 294{
295 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 296 unsigned long temp;
1da177e4 297
ff4bfb21
SH		 298 temp = readl(sport->port.membase + UCR1);
299 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4 300
ff4bfb21
SH		 301 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
302 imx_transmit_buffer(sport);
1da177e4
LT		 303}
304
7d12e780 305static irqreturn_t imx_rtsint(int irq, void *dev_id)
ceca629e 306{
15aafa2f 307 struct imx_port *sport = dev_id;
ff4bfb21 308 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
ceca629e
SH		 309 unsigned long flags;
310
311 spin_lock_irqsave(&sport->port.lock, flags);
312
ff4bfb21 313 writel(USR1_RTSD, sport->port.membase + USR1);
ceca629e
SH		 314 uart_handle_cts_change(&sport->port, !!val);
315 wake_up_interruptible(&sport->port.info->delta_msr_wait);
316
317 spin_unlock_irqrestore(&sport->port.lock, flags);
318 return IRQ_HANDLED;
319}
320
7d12e780 321static irqreturn_t imx_txint(int irq, void *dev_id)
1da177e4 322{
15aafa2f 323 struct imx_port *sport = dev_id;
1da177e4
LT		 324 struct circ_buf *xmit = &sport->port.info->xmit;
325 unsigned long flags;
326
327 spin_lock_irqsave(&sport->port.lock,flags);
328 if (sport->port.x_char)
329 {
330 /* Send next char */
ff4bfb21 331 writel(sport->port.x_char, sport->port.membase + URTX0);
1da177e4
LT		 332 goto out;
333 }
334
335 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
b129a8cc 336 imx_stop_tx(&sport->port);
1da177e4
LT		 337 goto out;
338 }
339
340 imx_transmit_buffer(sport);
341
342 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(&sport->port);
344
345out:
346 spin_unlock_irqrestore(&sport->port.lock,flags);
347 return IRQ_HANDLED;
348}
349
7d12e780 350static irqreturn_t imx_rxint(int irq, void *dev_id)
1da177e4
LT		 351{
352 struct imx_port *sport = dev_id;
353 unsigned int rx,flg,ignored = 0;
354 struct tty_struct *tty = sport->port.info->tty;
ff4bfb21 355 unsigned long flags, temp;
1da177e4 356
1da177e4
LT		 357 spin_lock_irqsave(&sport->port.lock,flags);
358
0d3c3938 359 while (readl(sport->port.membase + USR2) & USR2_RDR) {
1da177e4
LT		 360 flg = TTY_NORMAL;
361 sport->port.icount.rx++;
362
0d3c3938
SH		 363 rx = readl(sport->port.membase + URXD0);
364
ff4bfb21 365 temp = readl(sport->port.membase + USR2);
864eeed0 366 if (temp & USR2_BRCD) {
ff4bfb21 367 writel(temp | USR2_BRCD, sport->port.membase + USR2);
864eeed0
SH		 368 if (uart_handle_break(&sport->port))
369 continue;
1da177e4
LT		 370 }
371
372 if (uart_handle_sysrq_char
7d12e780 373 (&sport->port, (unsigned char)rx))
864eeed0
SH		 374 continue;
375
376 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
377 if (rx & URXD_PRERR)
378 sport->port.icount.parity++;
379 else if (rx & URXD_FRMERR)
380 sport->port.icount.frame++;
381 if (rx & URXD_OVRRUN)
382 sport->port.icount.overrun++;
383
384 if (rx & sport->port.ignore_status_mask) {
385 if (++ignored > 100)
386 goto out;
387 continue;
388 }
389
390 rx &= sport->port.read_status_mask;
391
392 if (rx & URXD_PRERR)
393 flg = TTY_PARITY;
394 else if (rx & URXD_FRMERR)
395 flg = TTY_FRAME;
396 if (rx & URXD_OVRRUN)
397 flg = TTY_OVERRUN;
1da177e4 398
864eeed0
SH		 399#ifdef SUPPORT_SYSRQ
400 sport->port.sysrq = 0;
401#endif
402 }
1da177e4 403
1da177e4 404 tty_insert_flip_char(tty, rx, flg);
864eeed0 405 }
1da177e4
LT		 406
407out:
408 spin_unlock_irqrestore(&sport->port.lock,flags);
409 tty_flip_buffer_push(tty);
410 return IRQ_HANDLED;
1da177e4
LT		 411}
412
413/*
414 * Return TIOCSER_TEMT when transmitter is not busy.
415 */
416static unsigned int imx_tx_empty(struct uart_port *port)
417{
418 struct imx_port *sport = (struct imx_port *)port;
419
ff4bfb21 420 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1da177e4
LT		 421}
422
0f302dc3
SH		 423/*
424 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
425 */
1da177e4
LT		 426static unsigned int imx_get_mctrl(struct uart_port *port)
427{
0f302dc3
SH		 428 struct imx_port *sport = (struct imx_port *)port;
429 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
430
ff4bfb21 431 if (readl(sport->port.membase + USR1) & USR1_RTSS)
0f302dc3
SH		 432 tmp |= TIOCM_CTS;
433
ff4bfb21 434 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
0f302dc3
SH		 435 tmp |= TIOCM_RTS;
436
437 return tmp;
1da177e4
LT		 438}
439
440static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
441{
0f302dc3 442 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 443 unsigned long temp;
444
445 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
0f302dc3
SH		 446
447 if (mctrl & TIOCM_RTS)
ff4bfb21
SH		 448 temp |= UCR2_CTS;
449
450 writel(temp, sport->port.membase + UCR2);
1da177e4
LT		 451}
452
453/*
454 * Interrupts always disabled.
455 */
456static void imx_break_ctl(struct uart_port *port, int break_state)
457{
458 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 459 unsigned long flags, temp;
1da177e4
LT		 460
461 spin_lock_irqsave(&sport->port.lock, flags);
462
ff4bfb21
SH		 463 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
464
1da177e4 465 if ( break_state != 0 )
ff4bfb21
SH		 466 temp |= UCR1_SNDBRK;
467
468 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 469
470 spin_unlock_irqrestore(&sport->port.lock, flags);
471}
472
473#define TXTL 2 /* reset default */
474#define RXTL 1 /* reset default */
475
587897f5
SH		 476static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
477{
478 unsigned int val;
479 unsigned int ufcr_rfdiv;
480
481 /* set receiver / transmitter trigger level.
482 * RFDIV is set such way to satisfy requested uartclk value
483 */
ff4bfb21 484 val = TXTL << 10 | RXTL;
587897f5
SH		 485 ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
486
487 if(!ufcr_rfdiv)
488 ufcr_rfdiv = 1;
489
490 if(ufcr_rfdiv >= 7)
491 ufcr_rfdiv = 6;
492 else
493 ufcr_rfdiv = 6 - ufcr_rfdiv;
494
495 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
496
ff4bfb21 497 writel(val, sport->port.membase + UFCR);
587897f5
SH		 498
499 return 0;
500}
501
1da177e4
LT		 502static int imx_startup(struct uart_port *port)
503{
504 struct imx_port *sport = (struct imx_port *)port;
505 int retval;
ff4bfb21 506 unsigned long flags, temp;
1da177e4 507
587897f5 508 imx_setup_ufcr(sport, 0);
1da177e4
LT		 509
510 /* disable the DREN bit (Data Ready interrupt enable) before
511 * requesting IRQs
512 */
ff4bfb21
SH		 513 temp = readl(sport->port.membase + UCR4);
514 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1da177e4
LT		 515
516 /*
517 * Allocate the IRQ
518 */
519 retval = request_irq(sport->rxirq, imx_rxint, 0,
520 DRIVER_NAME, sport);
86371d07 521 if (retval) goto error_out1;
1da177e4
LT		 522
523 retval = request_irq(sport->txirq, imx_txint, 0,
ceca629e 524 DRIVER_NAME, sport);
86371d07 525 if (retval) goto error_out2;
1da177e4 526
f43aaba1 527 retval = request_irq(sport->rtsirq, imx_rtsint,
d7ea10d9
PP		 528 (sport->rtsirq < IMX_IRQS) ? 0 :
529 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
ceca629e
SH		 530 DRIVER_NAME, sport);
531 if (retval) goto error_out3;
ceca629e 532
1da177e4
LT		 533 /*
534 * Finally, clear and enable interrupts
535 */
ff4bfb21
SH		 536 writel(USR1_RTSD, sport->port.membase + USR1);
537
538 temp = readl(sport->port.membase + UCR1);
539 temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
540 writel(temp, sport->port.membase + UCR1);
1da177e4 541
ff4bfb21
SH		 542 temp = readl(sport->port.membase + UCR2);
543 temp |= (UCR2_RXEN | UCR2_TXEN);
544 writel(temp, sport->port.membase + UCR2);
1da177e4 545
1da177e4
LT		 546 /*
547 * Enable modem status interrupts
548 */
549 spin_lock_irqsave(&sport->port.lock,flags);
550 imx_enable_ms(&sport->port);
551 spin_unlock_irqrestore(&sport->port.lock,flags);
552
553 return 0;
554
ceca629e
SH		 555error_out3:
556 free_irq(sport->txirq, sport);
1da177e4 557error_out2:
86371d07
SH		 558 free_irq(sport->rxirq, sport);
559error_out1:
1da177e4
LT		 560 return retval;
561}
562
563static void imx_shutdown(struct uart_port *port)
564{
565 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 566 unsigned long temp;
1da177e4
LT		 567
568 /*
569 * Stop our timer.
570 */
571 del_timer_sync(&sport->timer);
572
573 /*
574 * Free the interrupts
575 */
ceca629e 576 free_irq(sport->rtsirq, sport);
1da177e4
LT		 577 free_irq(sport->txirq, sport);
578 free_irq(sport->rxirq, sport);
579
580 /*
581 * Disable all interrupts, port and break condition.
582 */
583
ff4bfb21
SH		 584 temp = readl(sport->port.membase + UCR1);
585 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
586 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 587}
588
589static void
606d099c
AC		 590imx_set_termios(struct uart_port *port, struct ktermios *termios,
591 struct ktermios *old)
1da177e4
LT		 592{
593 struct imx_port *sport = (struct imx_port *)port;
594 unsigned long flags;
595 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
596 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
597
598 /*
599 * If we don't support modem control lines, don't allow
600 * these to be set.
601 */
602 if (0) {
603 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
604 termios->c_cflag |= CLOCAL;
605 }
606
607 /*
608 * We only support CS7 and CS8.
609 */
610 while ((termios->c_cflag & CSIZE) != CS7 &&
611 (termios->c_cflag & CSIZE) != CS8) {
612 termios->c_cflag &= ~CSIZE;
613 termios->c_cflag |= old_csize;
614 old_csize = CS8;
615 }
616
617 if ((termios->c_cflag & CSIZE) == CS8)
618 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
619 else
620 ucr2 = UCR2_SRST | UCR2_IRTS;
621
622 if (termios->c_cflag & CRTSCTS) {
5b802344
SH		 623 if( sport->have_rtscts ) {
624 ucr2 &= ~UCR2_IRTS;
625 ucr2 |= UCR2_CTSC;
626 } else {
627 termios->c_cflag &= ~CRTSCTS;
628 }
1da177e4
LT		 629 }
630
631 if (termios->c_cflag & CSTOPB)
632 ucr2 |= UCR2_STPB;
633 if (termios->c_cflag & PARENB) {
634 ucr2 |= UCR2_PREN;
3261e362 635 if (termios->c_cflag & PARODD)
1da177e4
LT		 636 ucr2 |= UCR2_PROE;
637 }
638
639 /*
640 * Ask the core to calculate the divisor for us.
641 */
642 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
643 quot = uart_get_divisor(port, baud);
644
645 spin_lock_irqsave(&sport->port.lock, flags);
646
647 sport->port.read_status_mask = 0;
648 if (termios->c_iflag & INPCK)
649 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
650 if (termios->c_iflag & (BRKINT | PARMRK))
651 sport->port.read_status_mask |= URXD_BRK;
652
653 /*
654 * Characters to ignore
655 */
656 sport->port.ignore_status_mask = 0;
657 if (termios->c_iflag & IGNPAR)
658 sport->port.ignore_status_mask |= URXD_PRERR;
659 if (termios->c_iflag & IGNBRK) {
660 sport->port.ignore_status_mask |= URXD_BRK;
661 /*
662 * If we're ignoring parity and break indicators,
663 * ignore overruns too (for real raw support).
664 */
665 if (termios->c_iflag & IGNPAR)
666 sport->port.ignore_status_mask |= URXD_OVRRUN;
667 }
668
669 del_timer_sync(&sport->timer);
670
671 /*
672 * Update the per-port timeout.
673 */
674 uart_update_timeout(port, termios->c_cflag, baud);
675
676 /*
677 * disable interrupts and drain transmitter
678 */
ff4bfb21
SH		 679 old_ucr1 = readl(sport->port.membase + UCR1);
680 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
681 sport->port.membase + UCR1);
1da177e4 682
ff4bfb21 683 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
1da177e4
LT		 684 barrier();
685
686 /* then, disable everything */
ff4bfb21
SH		 687 old_txrxen = readl(sport->port.membase + UCR2);
688 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
689 sport->port.membase + UCR2);
690 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1da177e4
LT		 691
692 /* set the baud rate. We assume uartclk = 16 MHz
693 *
694 * baud * 16 UBIR - 1
695 * --------- = --------
696 * uartclk UBMR - 1
697 */
ff4bfb21
SH		 698 writel((baud / 100) - 1, sport->port.membase + UBIR);
699 writel(10000 - 1, sport->port.membase + UBMR);
700
701 writel(old_ucr1, sport->port.membase + UCR1);
1da177e4 702
ff4bfb21
SH		 703 /* set the parity, stop bits and data size */
704 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1da177e4
LT		 705
706 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
707 imx_enable_ms(&sport->port);
708
709 spin_unlock_irqrestore(&sport->port.lock, flags);
710}
711
712static const char *imx_type(struct uart_port *port)
713{
714 struct imx_port *sport = (struct imx_port *)port;
715
716 return sport->port.type == PORT_IMX ? "IMX" : NULL;
717}
718
719/*
720 * Release the memory region(s) being used by 'port'.
721 */
722static void imx_release_port(struct uart_port *port)
723{
724 struct imx_port *sport = (struct imx_port *)port;
725
726 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
727}
728
729/*
730 * Request the memory region(s) being used by 'port'.
731 */
732static int imx_request_port(struct uart_port *port)
733{
734 struct imx_port *sport = (struct imx_port *)port;
735
736 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
737 "imx-uart") != NULL ? 0 : -EBUSY;
738}
739
740/*
741 * Configure/autoconfigure the port.
742 */
743static void imx_config_port(struct uart_port *port, int flags)
744{
745 struct imx_port *sport = (struct imx_port *)port;
746
747 if (flags & UART_CONFIG_TYPE &&
748 imx_request_port(&sport->port) == 0)
749 sport->port.type = PORT_IMX;
750}
751
752/*
753 * Verify the new serial_struct (for TIOCSSERIAL).
754 * The only change we allow are to the flags and type, and
755 * even then only between PORT_IMX and PORT_UNKNOWN
756 */
757static int
758imx_verify_port(struct uart_port *port, struct serial_struct *ser)
759{
760 struct imx_port *sport = (struct imx_port *)port;
761 int ret = 0;
762
763 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
764 ret = -EINVAL;
765 if (sport->port.irq != ser->irq)
766 ret = -EINVAL;
767 if (ser->io_type != UPIO_MEM)
768 ret = -EINVAL;
769 if (sport->port.uartclk / 16 != ser->baud_base)
770 ret = -EINVAL;
771 if ((void *)sport->port.mapbase != ser->iomem_base)
772 ret = -EINVAL;
773 if (sport->port.iobase != ser->port)
774 ret = -EINVAL;
775 if (ser->hub6 != 0)
776 ret = -EINVAL;
777 return ret;
778}
779
780static struct uart_ops imx_pops = {
781 .tx_empty = imx_tx_empty,
782 .set_mctrl = imx_set_mctrl,
783 .get_mctrl = imx_get_mctrl,
784 .stop_tx = imx_stop_tx,
785 .start_tx = imx_start_tx,
786 .stop_rx = imx_stop_rx,
787 .enable_ms = imx_enable_ms,
788 .break_ctl = imx_break_ctl,
789 .startup = imx_startup,
790 .shutdown = imx_shutdown,
791 .set_termios = imx_set_termios,
792 .type = imx_type,
793 .release_port = imx_release_port,
794 .request_port = imx_request_port,
795 .config_port = imx_config_port,
796 .verify_port = imx_verify_port,
797};
798
799static struct imx_port imx_ports[] = {
800 {
801 .txirq = UART1_MINT_TX,
802 .rxirq = UART1_MINT_RX,
ceca629e 803 .rtsirq = UART1_MINT_RTS,
1da177e4
LT		 804 .port = {
805 .type = PORT_IMX,
9b4a1617 806 .iotype = UPIO_MEM,
1da177e4
LT		 807 .membase = (void *)IMX_UART1_BASE,
808 .mapbase = IMX_UART1_BASE, /* FIXME */
809 .irq = UART1_MINT_RX,
810 .uartclk = 16000000,
8c0b254b 811 .fifosize = 32,
ce8337cb 812 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 813 .ops = &imx_pops,
814 .line = 0,
815 },
816 }, {
817 .txirq = UART2_MINT_TX,
818 .rxirq = UART2_MINT_RX,
ceca629e 819 .rtsirq = UART2_MINT_RTS,
1da177e4
LT		 820 .port = {
821 .type = PORT_IMX,
9b4a1617 822 .iotype = UPIO_MEM,
1da177e4
LT		 823 .membase = (void *)IMX_UART2_BASE,
824 .mapbase = IMX_UART2_BASE, /* FIXME */
825 .irq = UART2_MINT_RX,
826 .uartclk = 16000000,
8c0b254b 827 .fifosize = 32,
ce8337cb 828 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 829 .ops = &imx_pops,
830 .line = 1,
831 },
832 }
833};
834
835/*
836 * Setup the IMX serial ports.
837 * Note also that we support "console=ttySMXx" where "x" is either 0 or 1.
838 * Which serial port this ends up being depends on the machine you're
839 * running this kernel on. I'm not convinced that this is a good idea,
840 * but that's the way it traditionally works.
841 *
842 */
843static void __init imx_init_ports(void)
844{
845 static int first = 1;
846 int i;
847
848 if (!first)
849 return;
850 first = 0;
851
852 for (i = 0; i < ARRAY_SIZE(imx_ports); i++) {
853 init_timer(&imx_ports[i].timer);
854 imx_ports[i].timer.function = imx_timeout;
855 imx_ports[i].timer.data = (unsigned long)&imx_ports[i];
856 }
1da177e4
LT		 857}
858
859#ifdef CONFIG_SERIAL_IMX_CONSOLE
d358788f
RK		 860static void imx_console_putchar(struct uart_port *port, int ch)
861{
862 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 863
864 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
d358788f 865 barrier();
ff4bfb21
SH		 866
867 writel(ch, sport->port.membase + URTX0);
d358788f 868}
1da177e4
LT		 869
870/*
871 * Interrupts are disabled on entering
872 */
873static void
874imx_console_write(struct console *co, const char *s, unsigned int count)
875{
876 struct imx_port *sport = &imx_ports[co->index];
d358788f 877 unsigned int old_ucr1, old_ucr2;
1da177e4
LT		 878
879 /*
880 * First, save UCR1/2 and then disable interrupts
881 */
ff4bfb21
SH		 882 old_ucr1 = readl(sport->port.membase + UCR1);
883 old_ucr2 = readl(sport->port.membase + UCR2);
1da177e4 884
ff4bfb21
SH		 885 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
886 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
887 sport->port.membase + UCR1);
888
889 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1da177e4 890
d358788f 891 uart_console_write(&sport->port, s, count, imx_console_putchar);
1da177e4
LT		 892
893 /*
894 * Finally, wait for transmitter to become empty
895 * and restore UCR1/2
896 */
ff4bfb21 897 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1da177e4 898
ff4bfb21
SH		 899 writel(old_ucr1, sport->port.membase + UCR1);
900 writel(old_ucr2, sport->port.membase + UCR2);
1da177e4
LT		 901}
902
903/*
904 * If the port was already initialised (eg, by a boot loader),
905 * try to determine the current setup.
906 */
907static void __init
908imx_console_get_options(struct imx_port *sport, int *baud,
909 int *parity, int *bits)
910{
587897f5 911
ff4bfb21 912 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
1da177e4
LT		 913 /* ok, the port was enabled */
914 unsigned int ucr2, ubir,ubmr, uartclk;
587897f5
SH		 915 unsigned int baud_raw;
916 unsigned int ucfr_rfdiv;
1da177e4 917
ff4bfb21 918 ucr2 = readl(sport->port.membase + UCR2);
1da177e4
LT		 919
920 *parity = 'n';
921 if (ucr2 & UCR2_PREN) {
922 if (ucr2 & UCR2_PROE)
923 *parity = 'o';
924 else
925 *parity = 'e';
926 }
927
928 if (ucr2 & UCR2_WS)
929 *bits = 8;
930 else
931 *bits = 7;
932
ff4bfb21
SH		 933 ubir = readl(sport->port.membase + UBIR) & 0xffff;
934 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
587897f5 935
ff4bfb21 936 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
587897f5
SH		 937 if (ucfr_rfdiv == 6)
938 ucfr_rfdiv = 7;
939 else
940 ucfr_rfdiv = 6 - ucfr_rfdiv;
941
942 uartclk = imx_get_perclk1();
943 uartclk /= ucfr_rfdiv;
944
945 { /*
946 * The next code provides exact computation of
947 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
948 * without need of float support or long long division,
949 * which would be required to prevent 32bit arithmetic overflow
950 */
951 unsigned int mul = ubir + 1;
952 unsigned int div = 16 * (ubmr + 1);
953 unsigned int rem = uartclk % div;
954
955 baud_raw = (uartclk / div) * mul;
956 baud_raw += (rem * mul + div / 2) / div;
957 *baud = (baud_raw + 50) / 100 * 100;
958 }
959
960 if(*baud != baud_raw)
961 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
962 baud_raw, *baud);
1da177e4
LT		 963 }
964}
965
966static int __init
967imx_console_setup(struct console *co, char *options)
968{
969 struct imx_port *sport;
970 int baud = 9600;
971 int bits = 8;
972 int parity = 'n';
973 int flow = 'n';
974
975 /*
976 * Check whether an invalid uart number has been specified, and
977 * if so, search for the first available port that does have
978 * console support.
979 */
980 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
981 co->index = 0;
982 sport = &imx_ports[co->index];
983
984 if (options)
985 uart_parse_options(options, &baud, &parity, &bits, &flow);
986 else
987 imx_console_get_options(sport, &baud, &parity, &bits);
988
587897f5
SH		 989 imx_setup_ufcr(sport, 0);
990
1da177e4
LT		 991 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
992}
993
9f4426dd 994static struct uart_driver imx_reg;
1da177e4
LT		 995static struct console imx_console = {
996 .name = "ttySMX",
997 .write = imx_console_write,
998 .device = uart_console_device,
999 .setup = imx_console_setup,
1000 .flags = CON_PRINTBUFFER,
1001 .index = -1,
1002 .data = &imx_reg,
1003};
1004
1005static int __init imx_rs_console_init(void)
1006{
1007 imx_init_ports();
1008 register_console(&imx_console);
1009 return 0;
1010}
1011console_initcall(imx_rs_console_init);
1012
1013#define IMX_CONSOLE &imx_console
1014#else
1015#define IMX_CONSOLE NULL
1016#endif
1017
1018static struct uart_driver imx_reg = {
1019 .owner = THIS_MODULE,
1020 .driver_name = DRIVER_NAME,
1021 .dev_name = "ttySMX",
1da177e4
LT		 1022 .major = SERIAL_IMX_MAJOR,
1023 .minor = MINOR_START,
1024 .nr = ARRAY_SIZE(imx_ports),
1025 .cons = IMX_CONSOLE,
1026};
1027
3ae5eaec 1028static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1029{
3ae5eaec 1030 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1031
9480e307 1032 if (sport)
1da177e4
LT		 1033 uart_suspend_port(&imx_reg, &sport->port);
1034
1035 return 0;
1036}
1037
3ae5eaec 1038static int serial_imx_resume(struct platform_device *dev)
1da177e4 1039{
3ae5eaec 1040 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1041
9480e307 1042 if (sport)
1da177e4
LT		 1043 uart_resume_port(&imx_reg, &sport->port);
1044
1045 return 0;
1046}
1047
3ae5eaec 1048static int serial_imx_probe(struct platform_device *dev)
1da177e4 1049{
5b802344
SH		 1050 struct imxuart_platform_data *pdata;
1051
3ae5eaec 1052 imx_ports[dev->id].port.dev = &dev->dev;
5b802344
SH		 1053
1054 pdata = (struct imxuart_platform_data *)dev->dev.platform_data;
1055 if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1056 imx_ports[dev->id].have_rtscts = 1;
1057
1da177e4 1058 uart_add_one_port(&imx_reg, &imx_ports[dev->id].port);
3ae5eaec 1059 platform_set_drvdata(dev, &imx_ports[dev->id]);
1da177e4
LT		 1060 return 0;
1061}
1062
3ae5eaec 1063static int serial_imx_remove(struct platform_device *dev)
1da177e4 1064{
3ae5eaec 1065 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1066
3ae5eaec 1067 platform_set_drvdata(dev, NULL);
1da177e4
LT		 1068
1069 if (sport)
1070 uart_remove_one_port(&imx_reg, &sport->port);
1071
1072 return 0;
1073}
1074
3ae5eaec 1075static struct platform_driver serial_imx_driver = {
1da177e4
LT		 1076 .probe = serial_imx_probe,
1077 .remove = serial_imx_remove,
1078
1079 .suspend = serial_imx_suspend,
1080 .resume = serial_imx_resume,
3ae5eaec
RK		 1081 .driver = {
1082 .name = "imx-uart",
1083 },
1da177e4
LT		 1084};
1085
1086static int __init imx_serial_init(void)
1087{
1088 int ret;
1089
1090 printk(KERN_INFO "Serial: IMX driver\n");
1091
1092 imx_init_ports();
1093
1094 ret = uart_register_driver(&imx_reg);
1095 if (ret)
1096 return ret;
1097
3ae5eaec 1098 ret = platform_driver_register(&serial_imx_driver);
1da177e4
LT		 1099 if (ret != 0)
1100 uart_unregister_driver(&imx_reg);
1101
1102 return 0;
1103}
1104
1105static void __exit imx_serial_exit(void)
1106{
c889b896 1107 platform_driver_unregister(&serial_imx_driver);
4b300c36 1108 uart_unregister_driver(&imx_reg);
1da177e4
LT		 1109}
1110
1111module_init(imx_serial_init);
1112module_exit(imx_serial_exit);
1113
1114MODULE_AUTHOR("Sascha Hauer");
1115MODULE_DESCRIPTION("IMX generic serial port driver");
1116MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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