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[ARM] 4993/1: <IMX UART>: Trivial: Remove unused defines
[deliverable/linux.git] / drivers / serial / imx.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
27 */
1da177e4
LT		 28
29#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/ioport.h>
35#include <linux/init.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
d052d1be 38#include <linux/platform_device.h>
1da177e4
LT		 39#include <linux/tty.h>
40#include <linux/tty_flip.h>
41#include <linux/serial_core.h>
42#include <linux/serial.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46#include <asm/hardware.h>
5b802344 47#include <asm/arch/imx-uart.h>
1da177e4 48
ff4bfb21
SH		 49/* Register definitions */
50#define URXD0 0x0 /* Receiver Register */
51#define URTX0 0x40 /* Transmitter Register */
52#define UCR1 0x80 /* Control Register 1 */
53#define UCR2 0x84 /* Control Register 2 */
54#define UCR3 0x88 /* Control Register 3 */
55#define UCR4 0x8c /* Control Register 4 */
56#define UFCR 0x90 /* FIFO Control Register */
57#define USR1 0x94 /* Status Register 1 */
58#define USR2 0x98 /* Status Register 2 */
59#define UESC 0x9c /* Escape Character Register */
60#define UTIM 0xa0 /* Escape Timer Register */
61#define UBIR 0xa4 /* BRM Incremental Register */
62#define UBMR 0xa8 /* BRM Modulator Register */
63#define UBRC 0xac /* Baud Rate Count Register */
64#define BIPR1 0xb0 /* Incremental Preset Register 1 */
65#define BIPR2 0xb4 /* Incremental Preset Register 2 */
66#define BIPR3 0xb8 /* Incremental Preset Register 3 */
67#define BIPR4 0xbc /* Incremental Preset Register 4 */
68#define BMPR1 0xc0 /* BRM Modulator Register 1 */
69#define BMPR2 0xc4 /* BRM Modulator Register 2 */
70#define BMPR3 0xc8 /* BRM Modulator Register 3 */
71#define BMPR4 0xcc /* BRM Modulator Register 4 */
72#define UTS 0xd0 /* UART Test Register */
73
74/* UART Control Register Bit Fields.*/
75#define URXD_CHARRDY (1<<15)
76#define URXD_ERR (1<<14)
77#define URXD_OVRRUN (1<<13)
78#define URXD_FRMERR (1<<12)
79#define URXD_BRK (1<<11)
80#define URXD_PRERR (1<<10)
81#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87#define UCR1_IREN (1<<7) /* Infrared interface enable */
88#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90#define UCR1_SNDBRK (1<<4) /* Send break */
91#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93#define UCR1_DOZE (1<<1) /* Doze */
94#define UCR1_UARTEN (1<<0) /* UART enabled */
95#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97#define UCR2_CTSC (1<<13) /* CTS pin control */
98#define UCR2_CTS (1<<12) /* Clear to send */
99#define UCR2_ESCEN (1<<11) /* Escape enable */
100#define UCR2_PREN (1<<8) /* Parity enable */
101#define UCR2_PROE (1<<7) /* Parity odd/even */
102#define UCR2_STPB (1<<6) /* Stop */
103#define UCR2_WS (1<<5) /* Word size */
104#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105#define UCR2_TXEN (1<<2) /* Transmitter enabled */
106#define UCR2_RXEN (1<<1) /* Receiver enabled */
107#define UCR2_SRST (1<<0) /* SW reset */
108#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109#define UCR3_PARERREN (1<<12) /* Parity enable */
110#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111#define UCR3_DSR (1<<10) /* Data set ready */
112#define UCR3_DCD (1<<9) /* Data carrier detect */
113#define UCR3_RI (1<<8) /* Ring indicator */
114#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121#define UCR3_BPEN (1<<0) /* Preset registers enable */
122#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
123#define UCR4_INVR (1<<9) /* Inverted infrared reception */
124#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127#define UCR4_IRSC (1<<5) /* IR special case */
128#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136#define USR1_RTSS (1<<14) /* RTS pin status */
137#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138#define USR1_RTSD (1<<12) /* RTS delta */
139#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149#define USR2_IDLE (1<<12) /* Idle condition */
150#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151#define USR2_WAKE (1<<7) /* Wake */
152#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153#define USR2_TXDC (1<<3) /* Transmitter complete */
154#define USR2_BRCD (1<<2) /* Break condition */
155#define USR2_ORE (1<<1) /* Overrun error */
156#define USR2_RDR (1<<0) /* Recv data ready */
157#define UTS_FRCPERR (1<<13) /* Force parity error */
158#define UTS_LOOP (1<<12) /* Loop tx and rx */
159#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161#define UTS_TXFULL (1<<4) /* TxFIFO full */
162#define UTS_RXFULL (1<<3) /* RxFIFO full */
163#define UTS_SOFTRST (1<<0) /* Software reset */
164
1da177e4
LT		 165/* We've been assigned a range on the "Low-density serial ports" major */
166#define SERIAL_IMX_MAJOR 204
167#define MINOR_START 41
168
1da177e4
LT		 169/*
170 * This is the size of our serial port register set.
171 */
172#define UART_PORT_SIZE 0x100
173
174/*
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
179 */
180#define MCTRL_TIMEOUT (250*HZ/1000)
181
182#define DRIVER_NAME "IMX-uart"
183
184struct imx_port {
185 struct uart_port port;
186 struct timer_list timer;
187 unsigned int old_status;
5b802344
SH		 188 int txirq,rxirq,rtsirq;
189 int have_rtscts:1;
1da177e4
LT		 190};
191
192/*
193 * Handle any change of modem status signal since we were last called.
194 */
195static void imx_mctrl_check(struct imx_port *sport)
196{
197 unsigned int status, changed;
198
199 status = sport->port.ops->get_mctrl(&sport->port);
200 changed = status ^ sport->old_status;
201
202 if (changed == 0)
203 return;
204
205 sport->old_status = status;
206
207 if (changed & TIOCM_RI)
208 sport->port.icount.rng++;
209 if (changed & TIOCM_DSR)
210 sport->port.icount.dsr++;
211 if (changed & TIOCM_CAR)
212 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
213 if (changed & TIOCM_CTS)
214 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
215
216 wake_up_interruptible(&sport->port.info->delta_msr_wait);
217}
218
219/*
220 * This is our per-port timeout handler, for checking the
221 * modem status signals.
222 */
223static void imx_timeout(unsigned long data)
224{
225 struct imx_port *sport = (struct imx_port *)data;
226 unsigned long flags;
227
228 if (sport->port.info) {
229 spin_lock_irqsave(&sport->port.lock, flags);
230 imx_mctrl_check(sport);
231 spin_unlock_irqrestore(&sport->port.lock, flags);
232
233 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
234 }
235}
236
237/*
238 * interrupts disabled on entry
239 */
b129a8cc 240static void imx_stop_tx(struct uart_port *port)
1da177e4
LT		 241{
242 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 243 unsigned long temp;
244
245 temp = readl(sport->port.membase + UCR1);
246 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4
LT		 247}
248
249/*
250 * interrupts disabled on entry
251 */
252static void imx_stop_rx(struct uart_port *port)
253{
254 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 255 unsigned long temp;
256
257 temp = readl(sport->port.membase + UCR2);
258 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
1da177e4
LT		 259}
260
261/*
262 * Set the modem control timer to fire immediately.
263 */
264static void imx_enable_ms(struct uart_port *port)
265{
266 struct imx_port *sport = (struct imx_port *)port;
267
268 mod_timer(&sport->timer, jiffies);
269}
270
271static inline void imx_transmit_buffer(struct imx_port *sport)
272{
273 struct circ_buf *xmit = &sport->port.info->xmit;
274
ff4bfb21 275 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
1da177e4
LT		 276 /* send xmit->buf[xmit->tail]
277 * out the port here */
ff4bfb21 278 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
1da177e4
LT		 279 xmit->tail = (xmit->tail + 1) &
280 (UART_XMIT_SIZE - 1);
281 sport->port.icount.tx++;
282 if (uart_circ_empty(xmit))
283 break;
8c0b254b 284 }
1da177e4
LT		 285
286 if (uart_circ_empty(xmit))
b129a8cc 287 imx_stop_tx(&sport->port);
1da177e4
LT		 288}
289
290/*
291 * interrupts disabled on entry
292 */
b129a8cc 293static void imx_start_tx(struct uart_port *port)
1da177e4
LT		 294{
295 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 296 unsigned long temp;
1da177e4 297
ff4bfb21
SH		 298 temp = readl(sport->port.membase + UCR1);
299 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4 300
ff4bfb21
SH		 301 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
302 imx_transmit_buffer(sport);
1da177e4
LT		 303}
304
7d12e780 305static irqreturn_t imx_rtsint(int irq, void *dev_id)
ceca629e 306{
15aafa2f 307 struct imx_port *sport = dev_id;
ff4bfb21 308 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
ceca629e
SH		 309 unsigned long flags;
310
311 spin_lock_irqsave(&sport->port.lock, flags);
312
ff4bfb21 313 writel(USR1_RTSD, sport->port.membase + USR1);
ceca629e
SH		 314 uart_handle_cts_change(&sport->port, !!val);
315 wake_up_interruptible(&sport->port.info->delta_msr_wait);
316
317 spin_unlock_irqrestore(&sport->port.lock, flags);
318 return IRQ_HANDLED;
319}
320
7d12e780 321static irqreturn_t imx_txint(int irq, void *dev_id)
1da177e4 322{
15aafa2f 323 struct imx_port *sport = dev_id;
1da177e4
LT		 324 struct circ_buf *xmit = &sport->port.info->xmit;
325 unsigned long flags;
326
327 spin_lock_irqsave(&sport->port.lock,flags);
328 if (sport->port.x_char)
329 {
330 /* Send next char */
ff4bfb21 331 writel(sport->port.x_char, sport->port.membase + URTX0);
1da177e4
LT		 332 goto out;
333 }
334
335 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
b129a8cc 336 imx_stop_tx(&sport->port);
1da177e4
LT		 337 goto out;
338 }
339
340 imx_transmit_buffer(sport);
341
342 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(&sport->port);
344
345out:
346 spin_unlock_irqrestore(&sport->port.lock,flags);
347 return IRQ_HANDLED;
348}
349
7d12e780 350static irqreturn_t imx_rxint(int irq, void *dev_id)
1da177e4
LT		 351{
352 struct imx_port *sport = dev_id;
353 unsigned int rx,flg,ignored = 0;
354 struct tty_struct *tty = sport->port.info->tty;
ff4bfb21 355 unsigned long flags, temp;
1da177e4 356
ff4bfb21 357 rx = readl(sport->port.membase + URXD0);
1da177e4
LT		 358 spin_lock_irqsave(&sport->port.lock,flags);
359
360 do {
361 flg = TTY_NORMAL;
362 sport->port.icount.rx++;
363
ff4bfb21
SH		 364 temp = readl(sport->port.membase + USR2);
365 if( temp & USR2_BRCD ) {
366 writel(temp | USR2_BRCD, sport->port.membase + USR2);
1da177e4
LT		 367 if(uart_handle_break(&sport->port))
368 goto ignore_char;
369 }
370
371 if (uart_handle_sysrq_char
7d12e780 372 (&sport->port, (unsigned char)rx))
1da177e4
LT		 373 goto ignore_char;
374
375 if( rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) )
376 goto handle_error;
377
378 error_return:
379 tty_insert_flip_char(tty, rx, flg);
380
1da177e4 381 ignore_char:
ff4bfb21 382 rx = readl(sport->port.membase + URXD0);
1da177e4
LT		 383 } while(rx & URXD_CHARRDY);
384
385out:
386 spin_unlock_irqrestore(&sport->port.lock,flags);
387 tty_flip_buffer_push(tty);
388 return IRQ_HANDLED;
389
390handle_error:
391 if (rx & URXD_PRERR)
392 sport->port.icount.parity++;
393 else if (rx & URXD_FRMERR)
394 sport->port.icount.frame++;
395 if (rx & URXD_OVRRUN)
396 sport->port.icount.overrun++;
397
398 if (rx & sport->port.ignore_status_mask) {
399 if (++ignored > 100)
400 goto out;
401 goto ignore_char;
402 }
403
404 rx &= sport->port.read_status_mask;
405
406 if (rx & URXD_PRERR)
407 flg = TTY_PARITY;
408 else if (rx & URXD_FRMERR)
409 flg = TTY_FRAME;
410 if (rx & URXD_OVRRUN)
411 flg = TTY_OVERRUN;
412
413#ifdef SUPPORT_SYSRQ
414 sport->port.sysrq = 0;
415#endif
416 goto error_return;
417}
418
419/*
420 * Return TIOCSER_TEMT when transmitter is not busy.
421 */
422static unsigned int imx_tx_empty(struct uart_port *port)
423{
424 struct imx_port *sport = (struct imx_port *)port;
425
ff4bfb21 426 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1da177e4
LT		 427}
428
0f302dc3
SH		 429/*
430 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
431 */
1da177e4
LT		 432static unsigned int imx_get_mctrl(struct uart_port *port)
433{
0f302dc3
SH		 434 struct imx_port *sport = (struct imx_port *)port;
435 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
436
ff4bfb21 437 if (readl(sport->port.membase + USR1) & USR1_RTSS)
0f302dc3
SH		 438 tmp |= TIOCM_CTS;
439
ff4bfb21 440 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
0f302dc3
SH		 441 tmp |= TIOCM_RTS;
442
443 return tmp;
1da177e4
LT		 444}
445
446static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
447{
0f302dc3 448 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 449 unsigned long temp;
450
451 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
0f302dc3
SH		 452
453 if (mctrl & TIOCM_RTS)
ff4bfb21
SH		 454 temp |= UCR2_CTS;
455
456 writel(temp, sport->port.membase + UCR2);
1da177e4
LT		 457}
458
459/*
460 * Interrupts always disabled.
461 */
462static void imx_break_ctl(struct uart_port *port, int break_state)
463{
464 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 465 unsigned long flags, temp;
1da177e4
LT		 466
467 spin_lock_irqsave(&sport->port.lock, flags);
468
ff4bfb21
SH		 469 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
470
1da177e4 471 if ( break_state != 0 )
ff4bfb21
SH		 472 temp |= UCR1_SNDBRK;
473
474 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 475
476 spin_unlock_irqrestore(&sport->port.lock, flags);
477}
478
479#define TXTL 2 /* reset default */
480#define RXTL 1 /* reset default */
481
587897f5
SH		 482static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
483{
484 unsigned int val;
485 unsigned int ufcr_rfdiv;
486
487 /* set receiver / transmitter trigger level.
488 * RFDIV is set such way to satisfy requested uartclk value
489 */
ff4bfb21 490 val = TXTL << 10 | RXTL;
587897f5
SH		 491 ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
492
493 if(!ufcr_rfdiv)
494 ufcr_rfdiv = 1;
495
496 if(ufcr_rfdiv >= 7)
497 ufcr_rfdiv = 6;
498 else
499 ufcr_rfdiv = 6 - ufcr_rfdiv;
500
501 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
502
ff4bfb21 503 writel(val, sport->port.membase + UFCR);
587897f5
SH		 504
505 return 0;
506}
507
1da177e4
LT		 508static int imx_startup(struct uart_port *port)
509{
510 struct imx_port *sport = (struct imx_port *)port;
511 int retval;
ff4bfb21 512 unsigned long flags, temp;
1da177e4 513
587897f5 514 imx_setup_ufcr(sport, 0);
1da177e4
LT		 515
516 /* disable the DREN bit (Data Ready interrupt enable) before
517 * requesting IRQs
518 */
ff4bfb21
SH		 519 temp = readl(sport->port.membase + UCR4);
520 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1da177e4
LT		 521
522 /*
523 * Allocate the IRQ
524 */
525 retval = request_irq(sport->rxirq, imx_rxint, 0,
526 DRIVER_NAME, sport);
86371d07 527 if (retval) goto error_out1;
1da177e4
LT		 528
529 retval = request_irq(sport->txirq, imx_txint, 0,
ceca629e 530 DRIVER_NAME, sport);
86371d07 531 if (retval) goto error_out2;
1da177e4 532
f43aaba1 533 retval = request_irq(sport->rtsirq, imx_rtsint,
d7ea10d9
PP		 534 (sport->rtsirq < IMX_IRQS) ? 0 :
535 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
ceca629e
SH		 536 DRIVER_NAME, sport);
537 if (retval) goto error_out3;
ceca629e 538
1da177e4
LT		 539 /*
540 * Finally, clear and enable interrupts
541 */
ff4bfb21
SH		 542 writel(USR1_RTSD, sport->port.membase + USR1);
543
544 temp = readl(sport->port.membase + UCR1);
545 temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
546 writel(temp, sport->port.membase + UCR1);
1da177e4 547
ff4bfb21
SH		 548 temp = readl(sport->port.membase + UCR2);
549 temp |= (UCR2_RXEN | UCR2_TXEN);
550 writel(temp, sport->port.membase + UCR2);
1da177e4 551
1da177e4
LT		 552 /*
553 * Enable modem status interrupts
554 */
555 spin_lock_irqsave(&sport->port.lock,flags);
556 imx_enable_ms(&sport->port);
557 spin_unlock_irqrestore(&sport->port.lock,flags);
558
559 return 0;
560
ceca629e
SH		 561error_out3:
562 free_irq(sport->txirq, sport);
1da177e4 563error_out2:
86371d07
SH		 564 free_irq(sport->rxirq, sport);
565error_out1:
1da177e4
LT		 566 return retval;
567}
568
569static void imx_shutdown(struct uart_port *port)
570{
571 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 572 unsigned long temp;
1da177e4
LT		 573
574 /*
575 * Stop our timer.
576 */
577 del_timer_sync(&sport->timer);
578
579 /*
580 * Free the interrupts
581 */
ceca629e 582 free_irq(sport->rtsirq, sport);
1da177e4
LT		 583 free_irq(sport->txirq, sport);
584 free_irq(sport->rxirq, sport);
585
586 /*
587 * Disable all interrupts, port and break condition.
588 */
589
ff4bfb21
SH		 590 temp = readl(sport->port.membase + UCR1);
591 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
592 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 593}
594
595static void
606d099c
AC		 596imx_set_termios(struct uart_port *port, struct ktermios *termios,
597 struct ktermios *old)
1da177e4
LT		 598{
599 struct imx_port *sport = (struct imx_port *)port;
600 unsigned long flags;
601 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
602 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
603
604 /*
605 * If we don't support modem control lines, don't allow
606 * these to be set.
607 */
608 if (0) {
609 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
610 termios->c_cflag |= CLOCAL;
611 }
612
613 /*
614 * We only support CS7 and CS8.
615 */
616 while ((termios->c_cflag & CSIZE) != CS7 &&
617 (termios->c_cflag & CSIZE) != CS8) {
618 termios->c_cflag &= ~CSIZE;
619 termios->c_cflag |= old_csize;
620 old_csize = CS8;
621 }
622
623 if ((termios->c_cflag & CSIZE) == CS8)
624 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
625 else
626 ucr2 = UCR2_SRST | UCR2_IRTS;
627
628 if (termios->c_cflag & CRTSCTS) {
5b802344
SH		 629 if( sport->have_rtscts ) {
630 ucr2 &= ~UCR2_IRTS;
631 ucr2 |= UCR2_CTSC;
632 } else {
633 termios->c_cflag &= ~CRTSCTS;
634 }
1da177e4
LT		 635 }
636
637 if (termios->c_cflag & CSTOPB)
638 ucr2 |= UCR2_STPB;
639 if (termios->c_cflag & PARENB) {
640 ucr2 |= UCR2_PREN;
3261e362 641 if (termios->c_cflag & PARODD)
1da177e4
LT		 642 ucr2 |= UCR2_PROE;
643 }
644
645 /*
646 * Ask the core to calculate the divisor for us.
647 */
648 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
649 quot = uart_get_divisor(port, baud);
650
651 spin_lock_irqsave(&sport->port.lock, flags);
652
653 sport->port.read_status_mask = 0;
654 if (termios->c_iflag & INPCK)
655 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
656 if (termios->c_iflag & (BRKINT | PARMRK))
657 sport->port.read_status_mask |= URXD_BRK;
658
659 /*
660 * Characters to ignore
661 */
662 sport->port.ignore_status_mask = 0;
663 if (termios->c_iflag & IGNPAR)
664 sport->port.ignore_status_mask |= URXD_PRERR;
665 if (termios->c_iflag & IGNBRK) {
666 sport->port.ignore_status_mask |= URXD_BRK;
667 /*
668 * If we're ignoring parity and break indicators,
669 * ignore overruns too (for real raw support).
670 */
671 if (termios->c_iflag & IGNPAR)
672 sport->port.ignore_status_mask |= URXD_OVRRUN;
673 }
674
675 del_timer_sync(&sport->timer);
676
677 /*
678 * Update the per-port timeout.
679 */
680 uart_update_timeout(port, termios->c_cflag, baud);
681
682 /*
683 * disable interrupts and drain transmitter
684 */
ff4bfb21
SH		 685 old_ucr1 = readl(sport->port.membase + UCR1);
686 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
687 sport->port.membase + UCR1);
1da177e4 688
ff4bfb21 689 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
1da177e4
LT		 690 barrier();
691
692 /* then, disable everything */
ff4bfb21
SH		 693 old_txrxen = readl(sport->port.membase + UCR2);
694 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
695 sport->port.membase + UCR2);
696 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1da177e4
LT		 697
698 /* set the baud rate. We assume uartclk = 16 MHz
699 *
700 * baud * 16 UBIR - 1
701 * --------- = --------
702 * uartclk UBMR - 1
703 */
ff4bfb21
SH		 704 writel((baud / 100) - 1, sport->port.membase + UBIR);
705 writel(10000 - 1, sport->port.membase + UBMR);
706
707 writel(old_ucr1, sport->port.membase + UCR1);
1da177e4 708
ff4bfb21
SH		 709 /* set the parity, stop bits and data size */
710 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1da177e4
LT		 711
712 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
713 imx_enable_ms(&sport->port);
714
715 spin_unlock_irqrestore(&sport->port.lock, flags);
716}
717
718static const char *imx_type(struct uart_port *port)
719{
720 struct imx_port *sport = (struct imx_port *)port;
721
722 return sport->port.type == PORT_IMX ? "IMX" : NULL;
723}
724
725/*
726 * Release the memory region(s) being used by 'port'.
727 */
728static void imx_release_port(struct uart_port *port)
729{
730 struct imx_port *sport = (struct imx_port *)port;
731
732 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
733}
734
735/*
736 * Request the memory region(s) being used by 'port'.
737 */
738static int imx_request_port(struct uart_port *port)
739{
740 struct imx_port *sport = (struct imx_port *)port;
741
742 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
743 "imx-uart") != NULL ? 0 : -EBUSY;
744}
745
746/*
747 * Configure/autoconfigure the port.
748 */
749static void imx_config_port(struct uart_port *port, int flags)
750{
751 struct imx_port *sport = (struct imx_port *)port;
752
753 if (flags & UART_CONFIG_TYPE &&
754 imx_request_port(&sport->port) == 0)
755 sport->port.type = PORT_IMX;
756}
757
758/*
759 * Verify the new serial_struct (for TIOCSSERIAL).
760 * The only change we allow are to the flags and type, and
761 * even then only between PORT_IMX and PORT_UNKNOWN
762 */
763static int
764imx_verify_port(struct uart_port *port, struct serial_struct *ser)
765{
766 struct imx_port *sport = (struct imx_port *)port;
767 int ret = 0;
768
769 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
770 ret = -EINVAL;
771 if (sport->port.irq != ser->irq)
772 ret = -EINVAL;
773 if (ser->io_type != UPIO_MEM)
774 ret = -EINVAL;
775 if (sport->port.uartclk / 16 != ser->baud_base)
776 ret = -EINVAL;
777 if ((void *)sport->port.mapbase != ser->iomem_base)
778 ret = -EINVAL;
779 if (sport->port.iobase != ser->port)
780 ret = -EINVAL;
781 if (ser->hub6 != 0)
782 ret = -EINVAL;
783 return ret;
784}
785
786static struct uart_ops imx_pops = {
787 .tx_empty = imx_tx_empty,
788 .set_mctrl = imx_set_mctrl,
789 .get_mctrl = imx_get_mctrl,
790 .stop_tx = imx_stop_tx,
791 .start_tx = imx_start_tx,
792 .stop_rx = imx_stop_rx,
793 .enable_ms = imx_enable_ms,
794 .break_ctl = imx_break_ctl,
795 .startup = imx_startup,
796 .shutdown = imx_shutdown,
797 .set_termios = imx_set_termios,
798 .type = imx_type,
799 .release_port = imx_release_port,
800 .request_port = imx_request_port,
801 .config_port = imx_config_port,
802 .verify_port = imx_verify_port,
803};
804
805static struct imx_port imx_ports[] = {
806 {
807 .txirq = UART1_MINT_TX,
808 .rxirq = UART1_MINT_RX,
ceca629e 809 .rtsirq = UART1_MINT_RTS,
1da177e4
LT		 810 .port = {
811 .type = PORT_IMX,
9b4a1617 812 .iotype = UPIO_MEM,
1da177e4
LT		 813 .membase = (void *)IMX_UART1_BASE,
814 .mapbase = IMX_UART1_BASE, /* FIXME */
815 .irq = UART1_MINT_RX,
816 .uartclk = 16000000,
8c0b254b 817 .fifosize = 32,
ce8337cb 818 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 819 .ops = &imx_pops,
820 .line = 0,
821 },
822 }, {
823 .txirq = UART2_MINT_TX,
824 .rxirq = UART2_MINT_RX,
ceca629e 825 .rtsirq = UART2_MINT_RTS,
1da177e4
LT		 826 .port = {
827 .type = PORT_IMX,
9b4a1617 828 .iotype = UPIO_MEM,
1da177e4
LT		 829 .membase = (void *)IMX_UART2_BASE,
830 .mapbase = IMX_UART2_BASE, /* FIXME */
831 .irq = UART2_MINT_RX,
832 .uartclk = 16000000,
8c0b254b 833 .fifosize = 32,
ce8337cb 834 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 835 .ops = &imx_pops,
836 .line = 1,
837 },
838 }
839};
840
841/*
842 * Setup the IMX serial ports.
843 * Note also that we support "console=ttySMXx" where "x" is either 0 or 1.
844 * Which serial port this ends up being depends on the machine you're
845 * running this kernel on. I'm not convinced that this is a good idea,
846 * but that's the way it traditionally works.
847 *
848 */
849static void __init imx_init_ports(void)
850{
851 static int first = 1;
852 int i;
853
854 if (!first)
855 return;
856 first = 0;
857
858 for (i = 0; i < ARRAY_SIZE(imx_ports); i++) {
859 init_timer(&imx_ports[i].timer);
860 imx_ports[i].timer.function = imx_timeout;
861 imx_ports[i].timer.data = (unsigned long)&imx_ports[i];
862 }
1da177e4
LT		 863}
864
865#ifdef CONFIG_SERIAL_IMX_CONSOLE
d358788f
RK		 866static void imx_console_putchar(struct uart_port *port, int ch)
867{
868 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 869
870 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
d358788f 871 barrier();
ff4bfb21
SH		 872
873 writel(ch, sport->port.membase + URTX0);
d358788f 874}
1da177e4
LT		 875
876/*
877 * Interrupts are disabled on entering
878 */
879static void
880imx_console_write(struct console *co, const char *s, unsigned int count)
881{
882 struct imx_port *sport = &imx_ports[co->index];
d358788f 883 unsigned int old_ucr1, old_ucr2;
1da177e4
LT		 884
885 /*
886 * First, save UCR1/2 and then disable interrupts
887 */
ff4bfb21
SH		 888 old_ucr1 = readl(sport->port.membase + UCR1);
889 old_ucr2 = readl(sport->port.membase + UCR2);
1da177e4 890
ff4bfb21
SH		 891 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
892 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
893 sport->port.membase + UCR1);
894
895 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1da177e4 896
d358788f 897 uart_console_write(&sport->port, s, count, imx_console_putchar);
1da177e4
LT		 898
899 /*
900 * Finally, wait for transmitter to become empty
901 * and restore UCR1/2
902 */
ff4bfb21 903 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1da177e4 904
ff4bfb21
SH		 905 writel(old_ucr1, sport->port.membase + UCR1);
906 writel(old_ucr2, sport->port.membase + UCR2);
1da177e4
LT		 907}
908
909/*
910 * If the port was already initialised (eg, by a boot loader),
911 * try to determine the current setup.
912 */
913static void __init
914imx_console_get_options(struct imx_port *sport, int *baud,
915 int *parity, int *bits)
916{
587897f5 917
ff4bfb21 918 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
1da177e4
LT		 919 /* ok, the port was enabled */
920 unsigned int ucr2, ubir,ubmr, uartclk;
587897f5
SH		 921 unsigned int baud_raw;
922 unsigned int ucfr_rfdiv;
1da177e4 923
ff4bfb21 924 ucr2 = readl(sport->port.membase + UCR2);
1da177e4
LT		 925
926 *parity = 'n';
927 if (ucr2 & UCR2_PREN) {
928 if (ucr2 & UCR2_PROE)
929 *parity = 'o';
930 else
931 *parity = 'e';
932 }
933
934 if (ucr2 & UCR2_WS)
935 *bits = 8;
936 else
937 *bits = 7;
938
ff4bfb21
SH		 939 ubir = readl(sport->port.membase + UBIR) & 0xffff;
940 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
587897f5 941
ff4bfb21 942 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
587897f5
SH		 943 if (ucfr_rfdiv == 6)
944 ucfr_rfdiv = 7;
945 else
946 ucfr_rfdiv = 6 - ucfr_rfdiv;
947
948 uartclk = imx_get_perclk1();
949 uartclk /= ucfr_rfdiv;
950
951 { /*
952 * The next code provides exact computation of
953 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
954 * without need of float support or long long division,
955 * which would be required to prevent 32bit arithmetic overflow
956 */
957 unsigned int mul = ubir + 1;
958 unsigned int div = 16 * (ubmr + 1);
959 unsigned int rem = uartclk % div;
960
961 baud_raw = (uartclk / div) * mul;
962 baud_raw += (rem * mul + div / 2) / div;
963 *baud = (baud_raw + 50) / 100 * 100;
964 }
965
966 if(*baud != baud_raw)
967 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
968 baud_raw, *baud);
1da177e4
LT		 969 }
970}
971
972static int __init
973imx_console_setup(struct console *co, char *options)
974{
975 struct imx_port *sport;
976 int baud = 9600;
977 int bits = 8;
978 int parity = 'n';
979 int flow = 'n';
980
981 /*
982 * Check whether an invalid uart number has been specified, and
983 * if so, search for the first available port that does have
984 * console support.
985 */
986 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
987 co->index = 0;
988 sport = &imx_ports[co->index];
989
990 if (options)
991 uart_parse_options(options, &baud, &parity, &bits, &flow);
992 else
993 imx_console_get_options(sport, &baud, &parity, &bits);
994
587897f5
SH		 995 imx_setup_ufcr(sport, 0);
996
1da177e4
LT		 997 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
998}
999
9f4426dd 1000static struct uart_driver imx_reg;
1da177e4
LT		 1001static struct console imx_console = {
1002 .name = "ttySMX",
1003 .write = imx_console_write,
1004 .device = uart_console_device,
1005 .setup = imx_console_setup,
1006 .flags = CON_PRINTBUFFER,
1007 .index = -1,
1008 .data = &imx_reg,
1009};
1010
1011static int __init imx_rs_console_init(void)
1012{
1013 imx_init_ports();
1014 register_console(&imx_console);
1015 return 0;
1016}
1017console_initcall(imx_rs_console_init);
1018
1019#define IMX_CONSOLE &imx_console
1020#else
1021#define IMX_CONSOLE NULL
1022#endif
1023
1024static struct uart_driver imx_reg = {
1025 .owner = THIS_MODULE,
1026 .driver_name = DRIVER_NAME,
1027 .dev_name = "ttySMX",
1da177e4
LT		 1028 .major = SERIAL_IMX_MAJOR,
1029 .minor = MINOR_START,
1030 .nr = ARRAY_SIZE(imx_ports),
1031 .cons = IMX_CONSOLE,
1032};
1033
3ae5eaec 1034static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1035{
3ae5eaec 1036 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1037
9480e307 1038 if (sport)
1da177e4
LT		 1039 uart_suspend_port(&imx_reg, &sport->port);
1040
1041 return 0;
1042}
1043
3ae5eaec 1044static int serial_imx_resume(struct platform_device *dev)
1da177e4 1045{
3ae5eaec 1046 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1047
9480e307 1048 if (sport)
1da177e4
LT		 1049 uart_resume_port(&imx_reg, &sport->port);
1050
1051 return 0;
1052}
1053
3ae5eaec 1054static int serial_imx_probe(struct platform_device *dev)
1da177e4 1055{
5b802344
SH		 1056 struct imxuart_platform_data *pdata;
1057
3ae5eaec 1058 imx_ports[dev->id].port.dev = &dev->dev;
5b802344
SH		 1059
1060 pdata = (struct imxuart_platform_data *)dev->dev.platform_data;
1061 if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1062 imx_ports[dev->id].have_rtscts = 1;
1063
1da177e4 1064 uart_add_one_port(&imx_reg, &imx_ports[dev->id].port);
3ae5eaec 1065 platform_set_drvdata(dev, &imx_ports[dev->id]);
1da177e4
LT		 1066 return 0;
1067}
1068
3ae5eaec 1069static int serial_imx_remove(struct platform_device *dev)
1da177e4 1070{
3ae5eaec 1071 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1072
3ae5eaec 1073 platform_set_drvdata(dev, NULL);
1da177e4
LT		 1074
1075 if (sport)
1076 uart_remove_one_port(&imx_reg, &sport->port);
1077
1078 return 0;
1079}
1080
3ae5eaec 1081static struct platform_driver serial_imx_driver = {
1da177e4
LT		 1082 .probe = serial_imx_probe,
1083 .remove = serial_imx_remove,
1084
1085 .suspend = serial_imx_suspend,
1086 .resume = serial_imx_resume,
3ae5eaec
RK		 1087 .driver = {
1088 .name = "imx-uart",
1089 },
1da177e4
LT		 1090};
1091
1092static int __init imx_serial_init(void)
1093{
1094 int ret;
1095
1096 printk(KERN_INFO "Serial: IMX driver\n");
1097
1098 imx_init_ports();
1099
1100 ret = uart_register_driver(&imx_reg);
1101 if (ret)
1102 return ret;
1103
3ae5eaec 1104 ret = platform_driver_register(&serial_imx_driver);
1da177e4
LT		 1105 if (ret != 0)
1106 uart_unregister_driver(&imx_reg);
1107
1108 return 0;
1109}
1110
1111static void __exit imx_serial_exit(void)
1112{
c889b896 1113 platform_driver_unregister(&serial_imx_driver);
4b300c36 1114 uart_unregister_driver(&imx_reg);
1da177e4
LT		 1115}
1116
1117module_init(imx_serial_init);
1118module_exit(imx_serial_exit);
1119
1120MODULE_AUTHOR("Sascha Hauer");
1121MODULE_DESCRIPTION("IMX generic serial port driver");
1122MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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