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IMX UART: remove statically initialized tables
[deliverable/linux.git] / drivers / serial / imx.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * [29-Mar-2005] Mike Lee
26 * Added hardware handshake
27 */
1da177e4
LT		 28
29#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/ioport.h>
35#include <linux/init.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
d052d1be 38#include <linux/platform_device.h>
1da177e4
LT		 39#include <linux/tty.h>
40#include <linux/tty_flip.h>
41#include <linux/serial_core.h>
42#include <linux/serial.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46#include <asm/hardware.h>
5b802344 47#include <asm/arch/imx-uart.h>
1da177e4 48
ff4bfb21
SH		 49/* Register definitions */
50#define URXD0 0x0 /* Receiver Register */
51#define URTX0 0x40 /* Transmitter Register */
52#define UCR1 0x80 /* Control Register 1 */
53#define UCR2 0x84 /* Control Register 2 */
54#define UCR3 0x88 /* Control Register 3 */
55#define UCR4 0x8c /* Control Register 4 */
56#define UFCR 0x90 /* FIFO Control Register */
57#define USR1 0x94 /* Status Register 1 */
58#define USR2 0x98 /* Status Register 2 */
59#define UESC 0x9c /* Escape Character Register */
60#define UTIM 0xa0 /* Escape Timer Register */
61#define UBIR 0xa4 /* BRM Incremental Register */
62#define UBMR 0xa8 /* BRM Modulator Register */
63#define UBRC 0xac /* Baud Rate Count Register */
64#define BIPR1 0xb0 /* Incremental Preset Register 1 */
65#define BIPR2 0xb4 /* Incremental Preset Register 2 */
66#define BIPR3 0xb8 /* Incremental Preset Register 3 */
67#define BIPR4 0xbc /* Incremental Preset Register 4 */
68#define BMPR1 0xc0 /* BRM Modulator Register 1 */
69#define BMPR2 0xc4 /* BRM Modulator Register 2 */
70#define BMPR3 0xc8 /* BRM Modulator Register 3 */
71#define BMPR4 0xcc /* BRM Modulator Register 4 */
72#define UTS 0xd0 /* UART Test Register */
73
74/* UART Control Register Bit Fields.*/
75#define URXD_CHARRDY (1<<15)
76#define URXD_ERR (1<<14)
77#define URXD_OVRRUN (1<<13)
78#define URXD_FRMERR (1<<12)
79#define URXD_BRK (1<<11)
80#define URXD_PRERR (1<<10)
81#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
82#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87#define UCR1_IREN (1<<7) /* Infrared interface enable */
88#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90#define UCR1_SNDBRK (1<<4) /* Send break */
91#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
93#define UCR1_DOZE (1<<1) /* Doze */
94#define UCR1_UARTEN (1<<0) /* UART enabled */
95#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97#define UCR2_CTSC (1<<13) /* CTS pin control */
98#define UCR2_CTS (1<<12) /* Clear to send */
99#define UCR2_ESCEN (1<<11) /* Escape enable */
100#define UCR2_PREN (1<<8) /* Parity enable */
101#define UCR2_PROE (1<<7) /* Parity odd/even */
102#define UCR2_STPB (1<<6) /* Stop */
103#define UCR2_WS (1<<5) /* Word size */
104#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105#define UCR2_TXEN (1<<2) /* Transmitter enabled */
106#define UCR2_RXEN (1<<1) /* Receiver enabled */
107#define UCR2_SRST (1<<0) /* SW reset */
108#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109#define UCR3_PARERREN (1<<12) /* Parity enable */
110#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111#define UCR3_DSR (1<<10) /* Data set ready */
112#define UCR3_DCD (1<<9) /* Data carrier detect */
113#define UCR3_RI (1<<8) /* Ring indicator */
114#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
119#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
120#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121#define UCR3_BPEN (1<<0) /* Preset registers enable */
122#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
123#define UCR4_INVR (1<<9) /* Inverted infrared reception */
124#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127#define UCR4_IRSC (1<<5) /* IR special case */
128#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136#define USR1_RTSS (1<<14) /* RTS pin status */
137#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138#define USR1_RTSD (1<<12) /* RTS delta */
139#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
143#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
144#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
145#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
146#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
147#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
148#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
149#define USR2_IDLE (1<<12) /* Idle condition */
150#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
151#define USR2_WAKE (1<<7) /* Wake */
152#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
153#define USR2_TXDC (1<<3) /* Transmitter complete */
154#define USR2_BRCD (1<<2) /* Break condition */
155#define USR2_ORE (1<<1) /* Overrun error */
156#define USR2_RDR (1<<0) /* Recv data ready */
157#define UTS_FRCPERR (1<<13) /* Force parity error */
158#define UTS_LOOP (1<<12) /* Loop tx and rx */
159#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
160#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
161#define UTS_TXFULL (1<<4) /* TxFIFO full */
162#define UTS_RXFULL (1<<3) /* RxFIFO full */
163#define UTS_SOFTRST (1<<0) /* Software reset */
164
1da177e4
LT		 165/* We've been assigned a range on the "Low-density serial ports" major */
166#define SERIAL_IMX_MAJOR 204
167#define MINOR_START 41
168
1da177e4
LT		 169/*
170 * This determines how often we check the modem status signals
171 * for any change. They generally aren't connected to an IRQ
172 * so we have to poll them. We also check immediately before
173 * filling the TX fifo incase CTS has been dropped.
174 */
175#define MCTRL_TIMEOUT (250*HZ/1000)
176
177#define DRIVER_NAME "IMX-uart"
178
dbff4e9e
SH		 179#define UART_NR 8
180
1da177e4
LT		 181struct imx_port {
182 struct uart_port port;
183 struct timer_list timer;
184 unsigned int old_status;
5b802344
SH		 185 int txirq,rxirq,rtsirq;
186 int have_rtscts:1;
1da177e4
LT		 187};
188
189/*
190 * Handle any change of modem status signal since we were last called.
191 */
192static void imx_mctrl_check(struct imx_port *sport)
193{
194 unsigned int status, changed;
195
196 status = sport->port.ops->get_mctrl(&sport->port);
197 changed = status ^ sport->old_status;
198
199 if (changed == 0)
200 return;
201
202 sport->old_status = status;
203
204 if (changed & TIOCM_RI)
205 sport->port.icount.rng++;
206 if (changed & TIOCM_DSR)
207 sport->port.icount.dsr++;
208 if (changed & TIOCM_CAR)
209 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
210 if (changed & TIOCM_CTS)
211 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
212
213 wake_up_interruptible(&sport->port.info->delta_msr_wait);
214}
215
216/*
217 * This is our per-port timeout handler, for checking the
218 * modem status signals.
219 */
220static void imx_timeout(unsigned long data)
221{
222 struct imx_port *sport = (struct imx_port *)data;
223 unsigned long flags;
224
225 if (sport->port.info) {
226 spin_lock_irqsave(&sport->port.lock, flags);
227 imx_mctrl_check(sport);
228 spin_unlock_irqrestore(&sport->port.lock, flags);
229
230 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
231 }
232}
233
234/*
235 * interrupts disabled on entry
236 */
b129a8cc 237static void imx_stop_tx(struct uart_port *port)
1da177e4
LT		 238{
239 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 240 unsigned long temp;
241
242 temp = readl(sport->port.membase + UCR1);
243 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4
LT		 244}
245
246/*
247 * interrupts disabled on entry
248 */
249static void imx_stop_rx(struct uart_port *port)
250{
251 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 252 unsigned long temp;
253
254 temp = readl(sport->port.membase + UCR2);
255 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
1da177e4
LT		 256}
257
258/*
259 * Set the modem control timer to fire immediately.
260 */
261static void imx_enable_ms(struct uart_port *port)
262{
263 struct imx_port *sport = (struct imx_port *)port;
264
265 mod_timer(&sport->timer, jiffies);
266}
267
268static inline void imx_transmit_buffer(struct imx_port *sport)
269{
270 struct circ_buf *xmit = &sport->port.info->xmit;
271
ff4bfb21 272 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
1da177e4
LT		 273 /* send xmit->buf[xmit->tail]
274 * out the port here */
ff4bfb21 275 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
1da177e4
LT		 276 xmit->tail = (xmit->tail + 1) &
277 (UART_XMIT_SIZE - 1);
278 sport->port.icount.tx++;
279 if (uart_circ_empty(xmit))
280 break;
8c0b254b 281 }
1da177e4
LT		 282
283 if (uart_circ_empty(xmit))
b129a8cc 284 imx_stop_tx(&sport->port);
1da177e4
LT		 285}
286
287/*
288 * interrupts disabled on entry
289 */
b129a8cc 290static void imx_start_tx(struct uart_port *port)
1da177e4
LT		 291{
292 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 293 unsigned long temp;
1da177e4 294
ff4bfb21
SH		 295 temp = readl(sport->port.membase + UCR1);
296 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4 297
ff4bfb21
SH		 298 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
299 imx_transmit_buffer(sport);
1da177e4
LT		 300}
301
7d12e780 302static irqreturn_t imx_rtsint(int irq, void *dev_id)
ceca629e 303{
15aafa2f 304 struct imx_port *sport = dev_id;
ff4bfb21 305 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
ceca629e
SH		 306 unsigned long flags;
307
308 spin_lock_irqsave(&sport->port.lock, flags);
309
ff4bfb21 310 writel(USR1_RTSD, sport->port.membase + USR1);
ceca629e
SH		 311 uart_handle_cts_change(&sport->port, !!val);
312 wake_up_interruptible(&sport->port.info->delta_msr_wait);
313
314 spin_unlock_irqrestore(&sport->port.lock, flags);
315 return IRQ_HANDLED;
316}
317
7d12e780 318static irqreturn_t imx_txint(int irq, void *dev_id)
1da177e4 319{
15aafa2f 320 struct imx_port *sport = dev_id;
1da177e4
LT		 321 struct circ_buf *xmit = &sport->port.info->xmit;
322 unsigned long flags;
323
324 spin_lock_irqsave(&sport->port.lock,flags);
325 if (sport->port.x_char)
326 {
327 /* Send next char */
ff4bfb21 328 writel(sport->port.x_char, sport->port.membase + URTX0);
1da177e4
LT		 329 goto out;
330 }
331
332 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
b129a8cc 333 imx_stop_tx(&sport->port);
1da177e4
LT		 334 goto out;
335 }
336
337 imx_transmit_buffer(sport);
338
339 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
340 uart_write_wakeup(&sport->port);
341
342out:
343 spin_unlock_irqrestore(&sport->port.lock,flags);
344 return IRQ_HANDLED;
345}
346
7d12e780 347static irqreturn_t imx_rxint(int irq, void *dev_id)
1da177e4
LT		 348{
349 struct imx_port *sport = dev_id;
350 unsigned int rx,flg,ignored = 0;
351 struct tty_struct *tty = sport->port.info->tty;
ff4bfb21 352 unsigned long flags, temp;
1da177e4 353
1da177e4
LT		 354 spin_lock_irqsave(&sport->port.lock,flags);
355
0d3c3938 356 while (readl(sport->port.membase + USR2) & USR2_RDR) {
1da177e4
LT		 357 flg = TTY_NORMAL;
358 sport->port.icount.rx++;
359
0d3c3938
SH		 360 rx = readl(sport->port.membase + URXD0);
361
ff4bfb21 362 temp = readl(sport->port.membase + USR2);
864eeed0 363 if (temp & USR2_BRCD) {
ff4bfb21 364 writel(temp | USR2_BRCD, sport->port.membase + USR2);
864eeed0
SH		 365 if (uart_handle_break(&sport->port))
366 continue;
1da177e4
LT		 367 }
368
369 if (uart_handle_sysrq_char
7d12e780 370 (&sport->port, (unsigned char)rx))
864eeed0
SH		 371 continue;
372
373 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
374 if (rx & URXD_PRERR)
375 sport->port.icount.parity++;
376 else if (rx & URXD_FRMERR)
377 sport->port.icount.frame++;
378 if (rx & URXD_OVRRUN)
379 sport->port.icount.overrun++;
380
381 if (rx & sport->port.ignore_status_mask) {
382 if (++ignored > 100)
383 goto out;
384 continue;
385 }
386
387 rx &= sport->port.read_status_mask;
388
389 if (rx & URXD_PRERR)
390 flg = TTY_PARITY;
391 else if (rx & URXD_FRMERR)
392 flg = TTY_FRAME;
393 if (rx & URXD_OVRRUN)
394 flg = TTY_OVERRUN;
1da177e4 395
864eeed0
SH		 396#ifdef SUPPORT_SYSRQ
397 sport->port.sysrq = 0;
398#endif
399 }
1da177e4 400
1da177e4 401 tty_insert_flip_char(tty, rx, flg);
864eeed0 402 }
1da177e4
LT		 403
404out:
405 spin_unlock_irqrestore(&sport->port.lock,flags);
406 tty_flip_buffer_push(tty);
407 return IRQ_HANDLED;
1da177e4
LT		 408}
409
410/*
411 * Return TIOCSER_TEMT when transmitter is not busy.
412 */
413static unsigned int imx_tx_empty(struct uart_port *port)
414{
415 struct imx_port *sport = (struct imx_port *)port;
416
ff4bfb21 417 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1da177e4
LT		 418}
419
0f302dc3
SH		 420/*
421 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
422 */
1da177e4
LT		 423static unsigned int imx_get_mctrl(struct uart_port *port)
424{
0f302dc3
SH		 425 struct imx_port *sport = (struct imx_port *)port;
426 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
427
ff4bfb21 428 if (readl(sport->port.membase + USR1) & USR1_RTSS)
0f302dc3
SH		 429 tmp |= TIOCM_CTS;
430
ff4bfb21 431 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
0f302dc3
SH		 432 tmp |= TIOCM_RTS;
433
434 return tmp;
1da177e4
LT		 435}
436
437static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
438{
0f302dc3 439 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 440 unsigned long temp;
441
442 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
0f302dc3
SH		 443
444 if (mctrl & TIOCM_RTS)
ff4bfb21
SH		 445 temp |= UCR2_CTS;
446
447 writel(temp, sport->port.membase + UCR2);
1da177e4
LT		 448}
449
450/*
451 * Interrupts always disabled.
452 */
453static void imx_break_ctl(struct uart_port *port, int break_state)
454{
455 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 456 unsigned long flags, temp;
1da177e4
LT		 457
458 spin_lock_irqsave(&sport->port.lock, flags);
459
ff4bfb21
SH		 460 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
461
1da177e4 462 if ( break_state != 0 )
ff4bfb21
SH		 463 temp |= UCR1_SNDBRK;
464
465 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 466
467 spin_unlock_irqrestore(&sport->port.lock, flags);
468}
469
470#define TXTL 2 /* reset default */
471#define RXTL 1 /* reset default */
472
587897f5
SH		 473static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
474{
475 unsigned int val;
476 unsigned int ufcr_rfdiv;
477
478 /* set receiver / transmitter trigger level.
479 * RFDIV is set such way to satisfy requested uartclk value
480 */
ff4bfb21 481 val = TXTL << 10 | RXTL;
587897f5
SH		 482 ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
483
484 if(!ufcr_rfdiv)
485 ufcr_rfdiv = 1;
486
487 if(ufcr_rfdiv >= 7)
488 ufcr_rfdiv = 6;
489 else
490 ufcr_rfdiv = 6 - ufcr_rfdiv;
491
492 val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
493
ff4bfb21 494 writel(val, sport->port.membase + UFCR);
587897f5
SH		 495
496 return 0;
497}
498
1da177e4
LT		 499static int imx_startup(struct uart_port *port)
500{
501 struct imx_port *sport = (struct imx_port *)port;
502 int retval;
ff4bfb21 503 unsigned long flags, temp;
1da177e4 504
587897f5 505 imx_setup_ufcr(sport, 0);
1da177e4
LT		 506
507 /* disable the DREN bit (Data Ready interrupt enable) before
508 * requesting IRQs
509 */
ff4bfb21
SH		 510 temp = readl(sport->port.membase + UCR4);
511 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1da177e4
LT		 512
513 /*
514 * Allocate the IRQ
515 */
516 retval = request_irq(sport->rxirq, imx_rxint, 0,
517 DRIVER_NAME, sport);
86371d07 518 if (retval) goto error_out1;
1da177e4
LT		 519
520 retval = request_irq(sport->txirq, imx_txint, 0,
ceca629e 521 DRIVER_NAME, sport);
86371d07 522 if (retval) goto error_out2;
1da177e4 523
f43aaba1 524 retval = request_irq(sport->rtsirq, imx_rtsint,
d7ea10d9
PP		 525 (sport->rtsirq < IMX_IRQS) ? 0 :
526 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
ceca629e
SH		 527 DRIVER_NAME, sport);
528 if (retval) goto error_out3;
ceca629e 529
1da177e4
LT		 530 /*
531 * Finally, clear and enable interrupts
532 */
ff4bfb21
SH		 533 writel(USR1_RTSD, sport->port.membase + USR1);
534
535 temp = readl(sport->port.membase + UCR1);
789d5258 536 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
ff4bfb21 537 writel(temp, sport->port.membase + UCR1);
1da177e4 538
ff4bfb21
SH		 539 temp = readl(sport->port.membase + UCR2);
540 temp |= (UCR2_RXEN | UCR2_TXEN);
541 writel(temp, sport->port.membase + UCR2);
1da177e4 542
1da177e4
LT		 543 /*
544 * Enable modem status interrupts
545 */
546 spin_lock_irqsave(&sport->port.lock,flags);
547 imx_enable_ms(&sport->port);
548 spin_unlock_irqrestore(&sport->port.lock,flags);
549
550 return 0;
551
ceca629e
SH		 552error_out3:
553 free_irq(sport->txirq, sport);
1da177e4 554error_out2:
86371d07
SH		 555 free_irq(sport->rxirq, sport);
556error_out1:
1da177e4
LT		 557 return retval;
558}
559
560static void imx_shutdown(struct uart_port *port)
561{
562 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 563 unsigned long temp;
1da177e4
LT		 564
565 /*
566 * Stop our timer.
567 */
568 del_timer_sync(&sport->timer);
569
570 /*
571 * Free the interrupts
572 */
ceca629e 573 free_irq(sport->rtsirq, sport);
1da177e4
LT		 574 free_irq(sport->txirq, sport);
575 free_irq(sport->rxirq, sport);
576
577 /*
578 * Disable all interrupts, port and break condition.
579 */
580
ff4bfb21
SH		 581 temp = readl(sport->port.membase + UCR1);
582 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
583 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 584}
585
586static void
606d099c
AC		 587imx_set_termios(struct uart_port *port, struct ktermios *termios,
588 struct ktermios *old)
1da177e4
LT		 589{
590 struct imx_port *sport = (struct imx_port *)port;
591 unsigned long flags;
592 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
593 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
036bb15e 594 unsigned int div, num, denom, ufcr;
1da177e4
LT		 595
596 /*
597 * If we don't support modem control lines, don't allow
598 * these to be set.
599 */
600 if (0) {
601 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
602 termios->c_cflag |= CLOCAL;
603 }
604
605 /*
606 * We only support CS7 and CS8.
607 */
608 while ((termios->c_cflag & CSIZE) != CS7 &&
609 (termios->c_cflag & CSIZE) != CS8) {
610 termios->c_cflag &= ~CSIZE;
611 termios->c_cflag |= old_csize;
612 old_csize = CS8;
613 }
614
615 if ((termios->c_cflag & CSIZE) == CS8)
616 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
617 else
618 ucr2 = UCR2_SRST | UCR2_IRTS;
619
620 if (termios->c_cflag & CRTSCTS) {
5b802344
SH		 621 if( sport->have_rtscts ) {
622 ucr2 &= ~UCR2_IRTS;
623 ucr2 |= UCR2_CTSC;
624 } else {
625 termios->c_cflag &= ~CRTSCTS;
626 }
1da177e4
LT		 627 }
628
629 if (termios->c_cflag & CSTOPB)
630 ucr2 |= UCR2_STPB;
631 if (termios->c_cflag & PARENB) {
632 ucr2 |= UCR2_PREN;
3261e362 633 if (termios->c_cflag & PARODD)
1da177e4
LT		 634 ucr2 |= UCR2_PROE;
635 }
636
637 /*
638 * Ask the core to calculate the divisor for us.
639 */
036bb15e 640 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1da177e4
LT		 641 quot = uart_get_divisor(port, baud);
642
643 spin_lock_irqsave(&sport->port.lock, flags);
644
645 sport->port.read_status_mask = 0;
646 if (termios->c_iflag & INPCK)
647 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
648 if (termios->c_iflag & (BRKINT | PARMRK))
649 sport->port.read_status_mask |= URXD_BRK;
650
651 /*
652 * Characters to ignore
653 */
654 sport->port.ignore_status_mask = 0;
655 if (termios->c_iflag & IGNPAR)
656 sport->port.ignore_status_mask |= URXD_PRERR;
657 if (termios->c_iflag & IGNBRK) {
658 sport->port.ignore_status_mask |= URXD_BRK;
659 /*
660 * If we're ignoring parity and break indicators,
661 * ignore overruns too (for real raw support).
662 */
663 if (termios->c_iflag & IGNPAR)
664 sport->port.ignore_status_mask |= URXD_OVRRUN;
665 }
666
667 del_timer_sync(&sport->timer);
668
669 /*
670 * Update the per-port timeout.
671 */
672 uart_update_timeout(port, termios->c_cflag, baud);
673
674 /*
675 * disable interrupts and drain transmitter
676 */
ff4bfb21
SH		 677 old_ucr1 = readl(sport->port.membase + UCR1);
678 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
679 sport->port.membase + UCR1);
1da177e4 680
ff4bfb21 681 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
1da177e4
LT		 682 barrier();
683
684 /* then, disable everything */
ff4bfb21
SH		 685 old_txrxen = readl(sport->port.membase + UCR2);
686 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
687 sport->port.membase + UCR2);
688 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1da177e4 689
036bb15e
SH		 690 div = sport->port.uartclk / (baud * 16);
691 if (div > 7)
692 div = 7;
693 if (!div)
694 div = 1;
695
696 num = baud;
697 denom = port->uartclk / div / 16;
698
699 /* shift num and denom right until they fit into 16 bits */
700 while (num > 0x10000 || denom > 0x10000) {
701 num >>= 1;
702 denom >>= 1;
703 }
704 if (num > 0)
705 num -= 1;
706 if (denom > 0)
707 denom -= 1;
708
709 writel(num, sport->port.membase + UBIR);
710 writel(denom, sport->port.membase + UBMR);
711
712 if (div == 7)
713 div = 6; /* 6 in RFDIV means divide by 7 */
714 else
715 div = 6 - div;
716
717 ufcr = readl(sport->port.membase + UFCR);
718 ufcr = (ufcr & (~UFCR_RFDIV)) |
719 (div << 7);
720 writel(ufcr, sport->port.membase + UFCR);
721
722#ifdef ONEMS
723 writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
724#endif
ff4bfb21
SH		 725
726 writel(old_ucr1, sport->port.membase + UCR1);
1da177e4 727
ff4bfb21
SH		 728 /* set the parity, stop bits and data size */
729 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1da177e4
LT		 730
731 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
732 imx_enable_ms(&sport->port);
733
734 spin_unlock_irqrestore(&sport->port.lock, flags);
735}
736
737static const char *imx_type(struct uart_port *port)
738{
739 struct imx_port *sport = (struct imx_port *)port;
740
741 return sport->port.type == PORT_IMX ? "IMX" : NULL;
742}
743
744/*
745 * Release the memory region(s) being used by 'port'.
746 */
747static void imx_release_port(struct uart_port *port)
748{
3d454446
SH		 749 struct platform_device *pdev = to_platform_device(port->dev);
750 struct resource *mmres;
1da177e4 751
3d454446
SH		 752 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
753 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
1da177e4
LT		 754}
755
756/*
757 * Request the memory region(s) being used by 'port'.
758 */
759static int imx_request_port(struct uart_port *port)
760{
3d454446
SH		 761 struct platform_device *pdev = to_platform_device(port->dev);
762 struct resource *mmres;
763 void *ret;
764
765 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
766 if (!mmres)
767 return -ENODEV;
768
769 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
770 "imx-uart");
1da177e4 771
3d454446 772 return ret ? 0 : -EBUSY;
1da177e4
LT		 773}
774
775/*
776 * Configure/autoconfigure the port.
777 */
778static void imx_config_port(struct uart_port *port, int flags)
779{
780 struct imx_port *sport = (struct imx_port *)port;
781
782 if (flags & UART_CONFIG_TYPE &&
783 imx_request_port(&sport->port) == 0)
784 sport->port.type = PORT_IMX;
785}
786
787/*
788 * Verify the new serial_struct (for TIOCSSERIAL).
789 * The only change we allow are to the flags and type, and
790 * even then only between PORT_IMX and PORT_UNKNOWN
791 */
792static int
793imx_verify_port(struct uart_port *port, struct serial_struct *ser)
794{
795 struct imx_port *sport = (struct imx_port *)port;
796 int ret = 0;
797
798 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
799 ret = -EINVAL;
800 if (sport->port.irq != ser->irq)
801 ret = -EINVAL;
802 if (ser->io_type != UPIO_MEM)
803 ret = -EINVAL;
804 if (sport->port.uartclk / 16 != ser->baud_base)
805 ret = -EINVAL;
806 if ((void *)sport->port.mapbase != ser->iomem_base)
807 ret = -EINVAL;
808 if (sport->port.iobase != ser->port)
809 ret = -EINVAL;
810 if (ser->hub6 != 0)
811 ret = -EINVAL;
812 return ret;
813}
814
815static struct uart_ops imx_pops = {
816 .tx_empty = imx_tx_empty,
817 .set_mctrl = imx_set_mctrl,
818 .get_mctrl = imx_get_mctrl,
819 .stop_tx = imx_stop_tx,
820 .start_tx = imx_start_tx,
821 .stop_rx = imx_stop_rx,
822 .enable_ms = imx_enable_ms,
823 .break_ctl = imx_break_ctl,
824 .startup = imx_startup,
825 .shutdown = imx_shutdown,
826 .set_termios = imx_set_termios,
827 .type = imx_type,
828 .release_port = imx_release_port,
829 .request_port = imx_request_port,
830 .config_port = imx_config_port,
831 .verify_port = imx_verify_port,
832};
833
dbff4e9e 834static struct imx_port *imx_ports[UART_NR];
1da177e4
LT		 835
836#ifdef CONFIG_SERIAL_IMX_CONSOLE
d358788f
RK		 837static void imx_console_putchar(struct uart_port *port, int ch)
838{
839 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 840
841 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
d358788f 842 barrier();
ff4bfb21
SH		 843
844 writel(ch, sport->port.membase + URTX0);
d358788f 845}
1da177e4
LT		 846
847/*
848 * Interrupts are disabled on entering
849 */
850static void
851imx_console_write(struct console *co, const char *s, unsigned int count)
852{
dbff4e9e 853 struct imx_port *sport = imx_ports[co->index];
d358788f 854 unsigned int old_ucr1, old_ucr2;
1da177e4
LT		 855
856 /*
857 * First, save UCR1/2 and then disable interrupts
858 */
ff4bfb21
SH		 859 old_ucr1 = readl(sport->port.membase + UCR1);
860 old_ucr2 = readl(sport->port.membase + UCR2);
1da177e4 861
ff4bfb21
SH		 862 writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
863 ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
864 sport->port.membase + UCR1);
865
866 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1da177e4 867
d358788f 868 uart_console_write(&sport->port, s, count, imx_console_putchar);
1da177e4
LT		 869
870 /*
871 * Finally, wait for transmitter to become empty
872 * and restore UCR1/2
873 */
ff4bfb21 874 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1da177e4 875
ff4bfb21
SH		 876 writel(old_ucr1, sport->port.membase + UCR1);
877 writel(old_ucr2, sport->port.membase + UCR2);
1da177e4
LT		 878}
879
880/*
881 * If the port was already initialised (eg, by a boot loader),
882 * try to determine the current setup.
883 */
884static void __init
885imx_console_get_options(struct imx_port *sport, int *baud,
886 int *parity, int *bits)
887{
587897f5 888
ff4bfb21 889 if ( readl(sport->port.membase + UCR1) | UCR1_UARTEN ) {
1da177e4
LT		 890 /* ok, the port was enabled */
891 unsigned int ucr2, ubir,ubmr, uartclk;
587897f5
SH		 892 unsigned int baud_raw;
893 unsigned int ucfr_rfdiv;
1da177e4 894
ff4bfb21 895 ucr2 = readl(sport->port.membase + UCR2);
1da177e4
LT		 896
897 *parity = 'n';
898 if (ucr2 & UCR2_PREN) {
899 if (ucr2 & UCR2_PROE)
900 *parity = 'o';
901 else
902 *parity = 'e';
903 }
904
905 if (ucr2 & UCR2_WS)
906 *bits = 8;
907 else
908 *bits = 7;
909
ff4bfb21
SH		 910 ubir = readl(sport->port.membase + UBIR) & 0xffff;
911 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
587897f5 912
ff4bfb21 913 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
587897f5
SH		 914 if (ucfr_rfdiv == 6)
915 ucfr_rfdiv = 7;
916 else
917 ucfr_rfdiv = 6 - ucfr_rfdiv;
918
919 uartclk = imx_get_perclk1();
920 uartclk /= ucfr_rfdiv;
921
922 { /*
923 * The next code provides exact computation of
924 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
925 * without need of float support or long long division,
926 * which would be required to prevent 32bit arithmetic overflow
927 */
928 unsigned int mul = ubir + 1;
929 unsigned int div = 16 * (ubmr + 1);
930 unsigned int rem = uartclk % div;
931
932 baud_raw = (uartclk / div) * mul;
933 baud_raw += (rem * mul + div / 2) / div;
934 *baud = (baud_raw + 50) / 100 * 100;
935 }
936
937 if(*baud != baud_raw)
938 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
939 baud_raw, *baud);
1da177e4
LT		 940 }
941}
942
943static int __init
944imx_console_setup(struct console *co, char *options)
945{
946 struct imx_port *sport;
947 int baud = 9600;
948 int bits = 8;
949 int parity = 'n';
950 int flow = 'n';
951
952 /*
953 * Check whether an invalid uart number has been specified, and
954 * if so, search for the first available port that does have
955 * console support.
956 */
957 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
958 co->index = 0;
dbff4e9e 959 sport = imx_ports[co->index];
1da177e4
LT		 960
961 if (options)
962 uart_parse_options(options, &baud, &parity, &bits, &flow);
963 else
964 imx_console_get_options(sport, &baud, &parity, &bits);
965
587897f5
SH		 966 imx_setup_ufcr(sport, 0);
967
1da177e4
LT		 968 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
969}
970
9f4426dd 971static struct uart_driver imx_reg;
1da177e4
LT		 972static struct console imx_console = {
973 .name = "ttySMX",
974 .write = imx_console_write,
975 .device = uart_console_device,
976 .setup = imx_console_setup,
977 .flags = CON_PRINTBUFFER,
978 .index = -1,
979 .data = &imx_reg,
980};
981
1da177e4
LT		 982#define IMX_CONSOLE &imx_console
983#else
984#define IMX_CONSOLE NULL
985#endif
986
987static struct uart_driver imx_reg = {
988 .owner = THIS_MODULE,
989 .driver_name = DRIVER_NAME,
990 .dev_name = "ttySMX",
1da177e4
LT		 991 .major = SERIAL_IMX_MAJOR,
992 .minor = MINOR_START,
993 .nr = ARRAY_SIZE(imx_ports),
994 .cons = IMX_CONSOLE,
995};
996
3ae5eaec 997static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 998{
3ae5eaec 999 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1000
9480e307 1001 if (sport)
1da177e4
LT		 1002 uart_suspend_port(&imx_reg, &sport->port);
1003
1004 return 0;
1005}
1006
3ae5eaec 1007static int serial_imx_resume(struct platform_device *dev)
1da177e4 1008{
3ae5eaec 1009 struct imx_port *sport = platform_get_drvdata(dev);
1da177e4 1010
9480e307 1011 if (sport)
1da177e4
LT		 1012 uart_resume_port(&imx_reg, &sport->port);
1013
1014 return 0;
1015}
1016
2582d8c1 1017static int serial_imx_probe(struct platform_device *pdev)
1da177e4 1018{
dbff4e9e 1019 struct imx_port *sport;
5b802344 1020 struct imxuart_platform_data *pdata;
dbff4e9e
SH		 1021 void __iomem *base;
1022 int ret = 0;
1023 struct resource *res;
1024
1025 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1026 if (!sport)
1027 return -ENOMEM;
5b802344 1028
dbff4e9e
SH		 1029 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1030 if (!res) {
1031 ret = -ENODEV;
1032 goto free;
1033 }
1034
1035 base = ioremap(res->start, PAGE_SIZE);
1036 if (!base) {
1037 ret = -ENOMEM;
1038 goto free;
1039 }
1040
1041 sport->port.dev = &pdev->dev;
1042 sport->port.mapbase = res->start;
1043 sport->port.membase = base;
1044 sport->port.type = PORT_IMX,
1045 sport->port.iotype = UPIO_MEM;
1046 sport->port.irq = platform_get_irq(pdev, 0);
1047 sport->rxirq = platform_get_irq(pdev, 0);
1048 sport->txirq = platform_get_irq(pdev, 1);
1049 sport->rtsirq = platform_get_irq(pdev, 2);
1050 sport->port.fifosize = 32;
1051 sport->port.ops = &imx_pops;
1052 sport->port.flags = UPF_BOOT_AUTOCONF;
1053 sport->port.line = pdev->id;
1054 init_timer(&sport->timer);
1055 sport->timer.function = imx_timeout;
1056 sport->timer.data = (unsigned long)sport;
1057 sport->port.uartclk = imx_get_perclk1();
1058
1059 imx_ports[pdev->id] = sport;
5b802344 1060
2582d8c1 1061 pdata = pdev->dev.platform_data;
5b802344 1062 if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
dbff4e9e 1063 sport->have_rtscts = 1;
2582d8c1
SH		 1064
1065 if (pdata->init)
1066 pdata->init(pdev);
1067
dbff4e9e
SH		 1068 uart_add_one_port(&imx_reg, &sport->port);
1069 platform_set_drvdata(pdev, &sport->port);
5b802344 1070
1da177e4 1071 return 0;
dbff4e9e
SH		 1072free:
1073 kfree(sport);
1074
1075 return ret;
1da177e4
LT		 1076}
1077
2582d8c1 1078static int serial_imx_remove(struct platform_device *pdev)
1da177e4 1079{
2582d8c1
SH		 1080 struct imxuart_platform_data *pdata;
1081 struct imx_port *sport = platform_get_drvdata(pdev);
1da177e4 1082
2582d8c1
SH		 1083 pdata = pdev->dev.platform_data;
1084
1085 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1086
1087 if (sport)
1088 uart_remove_one_port(&imx_reg, &sport->port);
1089
2582d8c1
SH		 1090 if (pdata->exit)
1091 pdata->exit(pdev);
1092
dbff4e9e
SH		 1093 iounmap(sport->port.membase);
1094 kfree(sport);
1095
1da177e4
LT		 1096 return 0;
1097}
1098
3ae5eaec 1099static struct platform_driver serial_imx_driver = {
1da177e4
LT		 1100 .probe = serial_imx_probe,
1101 .remove = serial_imx_remove,
1102
1103 .suspend = serial_imx_suspend,
1104 .resume = serial_imx_resume,
3ae5eaec
RK		 1105 .driver = {
1106 .name = "imx-uart",
e169c139 1107 .owner = THIS_MODULE,
3ae5eaec 1108 },
1da177e4
LT		 1109};
1110
1111static int __init imx_serial_init(void)
1112{
1113 int ret;
1114
1115 printk(KERN_INFO "Serial: IMX driver\n");
1116
1da177e4
LT		 1117 ret = uart_register_driver(&imx_reg);
1118 if (ret)
1119 return ret;
1120
3ae5eaec 1121 ret = platform_driver_register(&serial_imx_driver);
1da177e4
LT		 1122 if (ret != 0)
1123 uart_unregister_driver(&imx_reg);
1124
1125 return 0;
1126}
1127
1128static void __exit imx_serial_exit(void)
1129{
c889b896 1130 platform_driver_unregister(&serial_imx_driver);
4b300c36 1131 uart_unregister_driver(&imx_reg);
1da177e4
LT		 1132}
1133
1134module_init(imx_serial_init);
1135module_exit(imx_serial_exit);
1136
1137MODULE_AUTHOR("Sascha Hauer");
1138MODULE_DESCRIPTION("IMX generic serial port driver");
1139MODULE_LICENSE("GPL");
e169c139 1140MODULE_ALIAS("platform:imx-uart");
Linux kernel - Deliverables
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