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[PATCH] Locking problems while EXT3FS_DEBUG on
[deliverable/linux.git] / drivers / serial / ioc4_serial.c
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1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9
10/*
11 * This file contains a module version of the ioc4 serial driver. This
12 * includes all the support functions needed (support functions, etc.)
13 * and the serial driver itself.
14 */
15#include <linux/errno.h>
16#include <linux/tty.h>
17#include <linux/serial.h>
18#include <linux/serialP.h>
19#include <linux/circ_buf.h>
20#include <linux/serial_reg.h>
21#include <linux/module.h>
22#include <linux/pci.h>
22329b51 23#include <linux/ioc4.h>
1da177e4
LT		 24#include <linux/serial_core.h>
25
26/*
27 * interesting things about the ioc4
28 */
29
30#define IOC4_NUM_SERIAL_PORTS 4 /* max ports per card */
31#define IOC4_NUM_CARDS 8 /* max cards per partition */
32
33#define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
34 (_n == 1) ? (IOC4_SIO_IR_S1) : \
35 (_n == 2) ? (IOC4_SIO_IR_S2) : \
36 (IOC4_SIO_IR_S3)
37
38#define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
39 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
40 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
41 (IOC4_OTHER_IR_S3_MEMERR)
42
43
44/*
45 * All IOC4 registers are 32 bits wide.
46 */
47
48/*
49 * PCI Memory Space Map
50 */
51#define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */
52#define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
53#define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
54#define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
55#define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
56#define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
57#define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
58
59/* Interrupt types */
60#define IOC4_SIO_INTR_TYPE 0
61#define IOC4_OTHER_INTR_TYPE 1
62#define IOC4_NUM_INTR_TYPES 2
63
64/* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */
65#define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */
66#define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */
67#define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */
68#define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */
69#define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */
70#define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */
71#define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */
72#define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */
73#define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */
74#define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */
75#define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */
76#define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */
77#define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */
78#define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */
79#define IOC4_SIO_IR_S1_INT 0x00004000 /* */
80#define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */
81#define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */
82#define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */
83#define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */
84#define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */
85#define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */
86#define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */
87#define IOC4_SIO_IR_S2_INT 0x00400000 /* */
88#define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */
89#define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */
90#define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */
91#define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */
92#define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */
93#define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */
94#define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */
95#define IOC4_SIO_IR_S3_INT 0x40000000 /* */
96#define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */
97
98/* Per device interrupt masks */
99#define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
100 IOC4_SIO_IR_S0_RX_FULL | \
101 IOC4_SIO_IR_S0_RX_HIGH | \
102 IOC4_SIO_IR_S0_RX_TIMER | \
103 IOC4_SIO_IR_S0_DELTA_DCD | \
104 IOC4_SIO_IR_S0_DELTA_CTS | \
105 IOC4_SIO_IR_S0_INT | \
106 IOC4_SIO_IR_S0_TX_EXPLICIT)
107#define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
108 IOC4_SIO_IR_S1_RX_FULL | \
109 IOC4_SIO_IR_S1_RX_HIGH | \
110 IOC4_SIO_IR_S1_RX_TIMER | \
111 IOC4_SIO_IR_S1_DELTA_DCD | \
112 IOC4_SIO_IR_S1_DELTA_CTS | \
113 IOC4_SIO_IR_S1_INT | \
114 IOC4_SIO_IR_S1_TX_EXPLICIT)
115#define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
116 IOC4_SIO_IR_S2_RX_FULL | \
117 IOC4_SIO_IR_S2_RX_HIGH | \
118 IOC4_SIO_IR_S2_RX_TIMER | \
119 IOC4_SIO_IR_S2_DELTA_DCD | \
120 IOC4_SIO_IR_S2_DELTA_CTS | \
121 IOC4_SIO_IR_S2_INT | \
122 IOC4_SIO_IR_S2_TX_EXPLICIT)
123#define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
124 IOC4_SIO_IR_S3_RX_FULL | \
125 IOC4_SIO_IR_S3_RX_HIGH | \
126 IOC4_SIO_IR_S3_RX_TIMER | \
127 IOC4_SIO_IR_S3_DELTA_DCD | \
128 IOC4_SIO_IR_S3_DELTA_CTS | \
129 IOC4_SIO_IR_S3_INT | \
130 IOC4_SIO_IR_S3_TX_EXPLICIT)
131
132/* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */
22329b51
BC		 133#define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */
134#define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */
135#define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */
136#define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */
137#define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */
138#define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */
139#define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Keyboard/mouse */
140#define IOC4_OTHER_IR_RESERVED 0x007fff80 /* Reserved */
141#define IOC4_OTHER_IR_RT_INT 0x00800000 /* INT_OUT section output */
142#define IOC4_OTHER_IR_GEN_INT 0xff000000 /* Generic pins */
143
144#define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
145 IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
1da177e4
LT		 146
147/* Bitmasks for IOC4_SIO_CR */
148#define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 /* byte bus strobe shift */
149#define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
150#define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
151#define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
152#define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
153#define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
154#define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
155#define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
156#define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
157#define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among
158 serial ports (ro) */
159/* Defs for some of the generic I/O pins */
160#define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0
161 mode sel */
162#define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1
163 mode sel */
164#define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2
165 mode sel */
166#define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3
167 mode sel */
168
169#define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling
170 uart 0 mode select */
171#define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling
172 uart 1 mode select */
173#define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling
174 uart 2 mode select */
175#define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling
176 uart 3 mode select */
177
178/* Bitmasks for serial RX status byte */
179#define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */
180#define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */
181#define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */
182#define IOC4_RXSB_BREAK 0x08 /* Break character */
183#define IOC4_RXSB_CTS 0x10 /* State of CTS */
184#define IOC4_RXSB_DCD 0x20 /* State of DCD */
185#define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */
186#define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR
187 * & BREAK valid */
188
189/* Bitmasks for serial TX control byte */
190#define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */
191#define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */
192#define IOC4_TXCB_VALID 0x40 /* Byte is valid */
193#define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */
194#define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */
195
196/* Bitmasks for IOC4_SBBR_L */
197#define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
198
199/* Bitmasks for IOC4_SSCR_<3:0> */
200#define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */
201#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
202#define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
203#define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */
204#define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */
205#define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */
206#define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */
207#define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */
208#define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */
209#define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */
210#define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */
211
212/* All producer/comsumer pointers are the same bitfield */
213#define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */
214#define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */
215#define IOC4_PROD_CONS_PTR_OFF 3
216
217/* Bitmasks for IOC4_SRCIR_<3:0> */
218#define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */
219
220/* Bitmasks for IOC4_SHADOW_<3:0> */
221#define IOC4_SHADOW_DR 0x00000001 /* Data ready */
222#define IOC4_SHADOW_OE 0x00000002 /* Overrun error */
223#define IOC4_SHADOW_PE 0x00000004 /* Parity error */
224#define IOC4_SHADOW_FE 0x00000008 /* Framing error */
225#define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */
226#define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */
227#define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */
228#define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */
229#define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */
230#define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */
231#define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */
232#define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */
233#define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */
234#define IOC4_SHADOW_RTS 0x02000000 /* Request to send */
235#define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
236#define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
237#define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */
238
239/* Bitmasks for IOC4_SRTR_<3:0> */
240#define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */
241#define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */
242#define IOC4_SRTR_CNT_VAL_SHIFT 16
243#define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */
244
245/* Serial port register map used for DMA and PIO serial I/O */
246struct ioc4_serialregs {
247 uint32_t sscr;
248 uint32_t stpir;
249 uint32_t stcir;
250 uint32_t srpir;
251 uint32_t srcir;
252 uint32_t srtr;
253 uint32_t shadow;
254};
255
256/* IOC4 UART register map */
257struct ioc4_uartregs {
258 char i4u_lcr;
259 union {
260 char iir; /* read only */
261 char fcr; /* write only */
262 } u3;
263 union {
264 char ier; /* DLAB == 0 */
265 char dlm; /* DLAB == 1 */
266 } u2;
267 union {
268 char rbr; /* read only, DLAB == 0 */
269 char thr; /* write only, DLAB == 0 */
270 char dll; /* DLAB == 1 */
271 } u1;
272 char i4u_scr;
273 char i4u_msr;
274 char i4u_lsr;
275 char i4u_mcr;
276};
277
278/* short names */
279#define i4u_dll u1.dll
280#define i4u_ier u2.ier
281#define i4u_dlm u2.dlm
282#define i4u_fcr u3.fcr
283
22329b51
BC		 284/* Serial port registers used for DMA serial I/O */
285struct ioc4_serial {
286 uint32_t sbbr01_l;
287 uint32_t sbbr01_h;
288 uint32_t sbbr23_l;
289 uint32_t sbbr23_h;
290
291 struct ioc4_serialregs port_0;
292 struct ioc4_serialregs port_1;
293 struct ioc4_serialregs port_2;
294 struct ioc4_serialregs port_3;
295 struct ioc4_uartregs uart_0;
296 struct ioc4_uartregs uart_1;
297 struct ioc4_uartregs uart_2;
298 struct ioc4_uartregs uart_3;
299} ioc4_serial;
1da177e4
LT		 300
301/* UART clock speed */
1da177e4
LT		 302#define IOC4_SER_XIN_CLK_66 66666667
303#define IOC4_SER_XIN_CLK_33 33333333
304
305#define IOC4_W_IES 0
306#define IOC4_W_IEC 1
307
308typedef void ioc4_intr_func_f(void *, uint32_t);
309typedef ioc4_intr_func_f *ioc4_intr_func_t;
310
311/* defining this will get you LOTS of great debug info */
312//#define DEBUG_INTERRUPTS
313#define DPRINT_CONFIG(_x...) ;
314//#define DPRINT_CONFIG(_x...) printk _x
315
316/* number of characters left in xmit buffer before we ask for more */
317#define WAKEUP_CHARS 256
318
319/* number of characters we want to transmit to the lower level at a time */
320#define IOC4_MAX_CHARS 128
321
322/* Device name we're using */
323#define DEVICE_NAME "ttyIOC"
324#define DEVICE_MAJOR 204
325#define DEVICE_MINOR 50
326
327/* register offsets */
328#define IOC4_SERIAL_OFFSET 0x300
329
330/* flags for next_char_state */
331#define NCS_BREAK 0x1
332#define NCS_PARITY 0x2
333#define NCS_FRAMING 0x4
334#define NCS_OVERRUN 0x8
335
336/* cause we need SOME parameters ... */
337#define MIN_BAUD_SUPPORTED 1200
338#define MAX_BAUD_SUPPORTED 115200
339
340/* protocol types supported */
341enum sio_proto {
342 PROTO_RS232,
343 PROTO_RS422
344};
345
346/* Notification types */
347#define N_DATA_READY 0x01
348#define N_OUTPUT_LOWAT 0x02
349#define N_BREAK 0x04
350#define N_PARITY_ERROR 0x08
351#define N_FRAMING_ERROR 0x10
352#define N_OVERRUN_ERROR 0x20
353#define N_DDCD 0x40
354#define N_DCTS 0x80
355
356#define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
357 N_PARITY_ERROR | N_FRAMING_ERROR | \
358 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
359
360#define N_ALL_OUTPUT N_OUTPUT_LOWAT
361
362#define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
363
364#define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
365 N_PARITY_ERROR | N_FRAMING_ERROR | \
366 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
367
368#define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
369#define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
370
371/* Some masks */
372#define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
373 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
374#define LCR_MASK_STOP_BITS (UART_LCR_STOP)
375
22329b51
BC		 376#define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
377#define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
1da177e4
LT		 378
379/* Default to 4k buffers */
380#ifdef IOC4_1K_BUFFERS
381#define RING_BUF_SIZE 1024
382#define IOC4_BUF_SIZE_BIT 0
383#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
384#else
385#define RING_BUF_SIZE 4096
386#define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
387#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
388#endif
389
390#define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
391
392/*
393 * This is the entry saved by the driver - one per card
394 */
395struct ioc4_control {
396 int ic_irq;
397 struct {
398 /* uart ports are allocated here */
399 struct uart_port icp_uart_port;
400 /* Handy reference material */
401 struct ioc4_port *icp_port;
402 } ic_port[IOC4_NUM_SERIAL_PORTS];
403 struct ioc4_soft *ic_soft;
404};
405
406/*
407 * per-IOC4 data structure
408 */
409#define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
410struct ioc4_soft {
22329b51 411 struct ioc4_misc_regs __iomem *is_ioc4_misc_addr;
1da177e4
LT		 412 struct ioc4_serial __iomem *is_ioc4_serial_addr;
413
414 /* Each interrupt type has an entry in the array */
415 struct ioc4_intr_type {
416
417 /*
418 * Each in-use entry in this array contains at least
419 * one nonzero bit in sd_bits; no two entries in this
420 * array have overlapping sd_bits values.
421 */
422 struct ioc4_intr_info {
423 uint32_t sd_bits;
424 ioc4_intr_func_f *sd_intr;
425 void *sd_info;
426 } is_intr_info[MAX_IOC4_INTR_ENTS];
427
428 /* Number of entries active in the above array */
429 atomic_t is_num_intrs;
430 } is_intr_type[IOC4_NUM_INTR_TYPES];
431
432 /* is_ir_lock must be held while
433 * modifying sio_ie values, so
434 * we can be sure that sio_ie is
435 * not changing when we read it
436 * along with sio_ir.
437 */
438 spinlock_t is_ir_lock; /* SIO_IE[SC] mod lock */
439};
440
441/* Local port info for each IOC4 serial ports */
442struct ioc4_port {
443 struct uart_port *ip_port;
444 /* Back ptrs for this port */
445 struct ioc4_control *ip_control;
446 struct pci_dev *ip_pdev;
447 struct ioc4_soft *ip_ioc4_soft;
448
449 /* pci mem addresses */
22329b51 450 struct ioc4_misc_regs __iomem *ip_mem;
1da177e4
LT		 451 struct ioc4_serial __iomem *ip_serial;
452 struct ioc4_serialregs __iomem *ip_serial_regs;
453 struct ioc4_uartregs __iomem *ip_uart_regs;
454
455 /* Ring buffer page for this port */
456 dma_addr_t ip_dma_ringbuf;
457 /* vaddr of ring buffer */
458 struct ring_buffer *ip_cpu_ringbuf;
459
460 /* Rings for this port */
461 struct ring *ip_inring;
462 struct ring *ip_outring;
463
464 /* Hook to port specific values */
465 struct hooks *ip_hooks;
466
467 spinlock_t ip_lock;
468
469 /* Various rx/tx parameters */
470 int ip_baud;
471 int ip_tx_lowat;
472 int ip_rx_timeout;
473
474 /* Copy of notification bits */
475 int ip_notify;
476
477 /* Shadow copies of various registers so we don't need to PIO
478 * read them constantly
479 */
480 uint32_t ip_ienb; /* Enabled interrupts */
481 uint32_t ip_sscr;
482 uint32_t ip_tx_prod;
483 uint32_t ip_rx_cons;
484 int ip_pci_bus_speed;
485 unsigned char ip_flags;
486};
487
488/* tx low water mark. We need to notify the driver whenever tx is getting
489 * close to empty so it can refill the tx buffer and keep things going.
490 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
491 * have no trouble getting in more chars in time (I certainly hope so).
492 */
493#define TX_LOWAT_LATENCY 1000
494#define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
495#define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
496
497/* Flags per port */
498#define INPUT_HIGH 0x01
499#define DCD_ON 0x02
500#define LOWAT_WRITTEN 0x04
501#define READ_ABORTED 0x08
502
503/* Since each port has different register offsets and bitmasks
504 * for everything, we'll store those that we need in tables so we
505 * don't have to be constantly checking the port we are dealing with.
506 */
507struct hooks {
508 uint32_t intr_delta_dcd;
509 uint32_t intr_delta_cts;
510 uint32_t intr_tx_mt;
511 uint32_t intr_rx_timer;
512 uint32_t intr_rx_high;
513 uint32_t intr_tx_explicit;
514 uint32_t intr_dma_error;
515 uint32_t intr_clear;
516 uint32_t intr_all;
22329b51 517 int rs422_select_pin;
1da177e4
LT		 518};
519
520static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
521 /* Values for port 0 */
522 {
523 IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
524 IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
525 IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
526 IOC4_OTHER_IR_S0_MEMERR,
527 (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
528 IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
529 IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
530 IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
531 IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
532 },
533
534 /* Values for port 1 */
535 {
536 IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
537 IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
538 IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
539 IOC4_OTHER_IR_S1_MEMERR,
540 (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
541 IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
542 IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
543 IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
544 IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
545 },
546
547 /* Values for port 2 */
548 {
549 IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
550 IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
551 IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
552 IOC4_OTHER_IR_S2_MEMERR,
553 (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
554 IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
555 IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
556 IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
557 IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
558 },
559
560 /* Values for port 3 */
561 {
562 IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
563 IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
564 IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
565 IOC4_OTHER_IR_S3_MEMERR,
566 (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
567 IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
568 IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
569 IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
570 IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
571 }
572};
573
574/* A ring buffer entry */
575struct ring_entry {
576 union {
577 struct {
578 uint32_t alldata;
579 uint32_t allsc;
580 } all;
581 struct {
582 char data[4]; /* data bytes */
583 char sc[4]; /* status/control */
584 } s;
585 } u;
586};
587
588/* Test the valid bits in any of the 4 sc chars using "allsc" member */
589#define RING_ANY_VALID \
590 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
591
592#define ring_sc u.s.sc
593#define ring_data u.s.data
594#define ring_allsc u.all.allsc
595
596/* Number of entries per ring buffer. */
597#define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
598
599/* An individual ring */
600struct ring {
601 struct ring_entry entries[ENTRIES_PER_RING];
602};
603
604/* The whole enchilada */
605struct ring_buffer {
606 struct ring TX_0_OR_2;
607 struct ring RX_0_OR_2;
608 struct ring TX_1_OR_3;
609 struct ring RX_1_OR_3;
610};
611
612/* Get a ring from a port struct */
613#define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
614
615/* Infinite loop detection.
616 */
617#define MAXITER 10000000
618
619/* Prototypes */
620static void receive_chars(struct uart_port *);
621static void handle_intr(void *arg, uint32_t sio_ir);
622
623/**
624 * write_ireg - write the interrupt regs
625 * @ioc4_soft: ptr to soft struct for this port
626 * @val: value to write
627 * @which: which register
628 * @type: which ireg set
629 */
630static inline void
631write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
632{
22329b51 633 struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr;
1da177e4
LT		 634 unsigned long flags;
635
636 spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
637
638 switch (type) {
639 case IOC4_SIO_INTR_TYPE:
640 switch (which) {
641 case IOC4_W_IES:
22329b51 642 writel(val, &mem->sio_ies.raw);
1da177e4
LT		 643 break;
644
645 case IOC4_W_IEC:
22329b51 646 writel(val, &mem->sio_iec.raw);
1da177e4
LT		 647 break;
648 }
649 break;
650
651 case IOC4_OTHER_INTR_TYPE:
652 switch (which) {
653 case IOC4_W_IES:
22329b51 654 writel(val, &mem->other_ies.raw);
1da177e4
LT		 655 break;
656
657 case IOC4_W_IEC:
22329b51 658 writel(val, &mem->other_iec.raw);
1da177e4
LT		 659 break;
660 }
661 break;
662
663 default:
664 break;
665 }
666 spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
667}
668
669/**
670 * set_baud - Baud rate setting code
671 * @port: port to set
672 * @baud: baud rate to use
673 */
674static int set_baud(struct ioc4_port *port, int baud)
675{
676 int actual_baud;
677 int diff;
678 int lcr;
679 unsigned short divisor;
680 struct ioc4_uartregs __iomem *uart;
681
682 divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
683 if (!divisor)
684 return 1;
685 actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
686
687 diff = actual_baud - baud;
688 if (diff < 0)
689 diff = -diff;
690
691 /* If we're within 1%, we've found a match */
692 if (diff * 100 > actual_baud)
693 return 1;
694
695 uart = port->ip_uart_regs;
696 lcr = readb(&uart->i4u_lcr);
697 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
698 writeb((unsigned char)divisor, &uart->i4u_dll);
699 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
700 writeb(lcr, &uart->i4u_lcr);
701 return 0;
702}
703
704
705/**
706 * get_ioc4_port - given a uart port, return the control structure
707 * @port: uart port
708 */
709static struct ioc4_port *get_ioc4_port(struct uart_port *the_port)
710{
22329b51
BC		 711 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
712 struct ioc4_control *control = idd->idd_serial_data;
1da177e4
LT		 713 int ii;
714
715 if (control) {
716 for ( ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++ ) {
717 if (!control->ic_port[ii].icp_port)
718 continue;
719 if (the_port == control->ic_port[ii].icp_port->ip_port)
720 return control->ic_port[ii].icp_port;
721 }
722 }
723 return NULL;
724}
725
726/* The IOC4 hardware provides no atomic way to determine if interrupts
727 * are pending since two reads are required to do so. The handler must
728 * read the SIO_IR and the SIO_IES, and take the logical and of the
729 * two. When this value is zero, all interrupts have been serviced and
730 * the handler may return.
731 *
732 * This has the unfortunate "hole" that, if some other CPU or
733 * some other thread or some higher level interrupt manages to
734 * modify SIO_IE between our reads of SIO_IR and SIO_IE, we may
735 * think we have observed SIO_IR&SIO_IE==0 when in fact this
736 * condition never really occurred.
737 *
738 * To solve this, we use a simple spinlock that must be held
739 * whenever modifying SIO_IE; holding this lock while observing
740 * both SIO_IR and SIO_IE guarantees that we do not falsely
741 * conclude that no enabled interrupts are pending.
742 */
743
744static inline uint32_t
745pending_intrs(struct ioc4_soft *soft, int type)
746{
22329b51 747 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
1da177e4
LT		 748 unsigned long flag;
749 uint32_t intrs = 0;
750
751 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
752 || (type == IOC4_OTHER_INTR_TYPE)));
753
754 spin_lock_irqsave(&soft->is_ir_lock, flag);
755
756 switch (type) {
757 case IOC4_SIO_INTR_TYPE:
22329b51 758 intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw);
1da177e4
LT		 759 break;
760
761 case IOC4_OTHER_INTR_TYPE:
22329b51 762 intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw);
1da177e4
LT		 763
764 /* Don't process any ATA interrupte */
765 intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
766 break;
767
768 default:
769 break;
770 }
771 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
772 return intrs;
773}
774
775/**
776 * port_init - Initialize the sio and ioc4 hardware for a given port
777 * called per port from attach...
778 * @port: port to initialize
779 */
780static int inline port_init(struct ioc4_port *port)
781{
782 uint32_t sio_cr;
783 struct hooks *hooks = port->ip_hooks;
784 struct ioc4_uartregs __iomem *uart;
785
786 /* Idle the IOC4 serial interface */
787 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
788
789 /* Wait until any pending bus activity for this port has ceased */
790 do
22329b51 791 sio_cr = readl(&port->ip_mem->sio_cr.raw);
1da177e4
LT		 792 while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
793
794 /* Finish reset sequence */
795 writel(0, &port->ip_serial_regs->sscr);
796
797 /* Once RESET is done, reload cached tx_prod and rx_cons values
798 * and set rings to empty by making prod == cons
799 */
800 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
801 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
802 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
5b052d8b 803 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
1da177e4
LT		 804
805 /* Disable interrupts for this 16550 */
806 uart = port->ip_uart_regs;
807 writeb(0, &uart->i4u_lcr);
808 writeb(0, &uart->i4u_ier);
809
810 /* Set the default baud */
811 set_baud(port, port->ip_baud);
812
813 /* Set line control to 8 bits no parity */
814 writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
815 /* UART_LCR_STOP == 1 stop */
816
817 /* Enable the FIFOs */
818 writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
819 /* then reset 16550 FIFOs */
820 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
821 &uart->i4u_fcr);
822
823 /* Clear modem control register */
824 writeb(0, &uart->i4u_mcr);
825
826 /* Clear deltas in modem status register */
827 readb(&uart->i4u_msr);
828
829 /* Only do this once per port pair */
830 if (port->ip_hooks == &hooks_array[0]
831 || port->ip_hooks == &hooks_array[2]) {
832 unsigned long ring_pci_addr;
833 uint32_t __iomem *sbbr_l;
834 uint32_t __iomem *sbbr_h;
835
836 if (port->ip_hooks == &hooks_array[0]) {
837 sbbr_l = &port->ip_serial->sbbr01_l;
838 sbbr_h = &port->ip_serial->sbbr01_h;
839 } else {
840 sbbr_l = &port->ip_serial->sbbr23_l;
841 sbbr_h = &port->ip_serial->sbbr23_h;
842 }
843
844 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
845 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
846 __FUNCTION__, ring_pci_addr));
847
848 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
849 writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
850 }
851
852 /* Set the receive timeout value to 10 msec */
853 writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
854
855 /* Set rx threshold, enable DMA */
856 /* Set high water mark at 3/4 of full ring */
857 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
858 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
859
860 /* Disable and clear all serial related interrupt bits */
861 write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
862 IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
863 port->ip_ienb &= ~hooks->intr_clear;
22329b51 864 writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw);
1da177e4
LT		 865 return 0;
866}
867
868/**
869 * handle_dma_error_intr - service any pending DMA error interrupts for the
870 * given port - 2nd level called via sd_intr
871 * @arg: handler arg
872 * @other_ir: ioc4regs
873 */
874static void handle_dma_error_intr(void *arg, uint32_t other_ir)
875{
876 struct ioc4_port *port = (struct ioc4_port *)arg;
877 struct hooks *hooks = port->ip_hooks;
878 unsigned int flags;
879
880 spin_lock_irqsave(&port->ip_lock, flags);
881
882 /* ACK the interrupt */
22329b51 883 writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw);
1da177e4 884
22329b51 885 if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) {
1da177e4
LT		 886 printk(KERN_ERR
887 "PCI error address is 0x%lx, "
888 "master is serial port %c %s\n",
889 (((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
890 << 32)
22329b51 891 | readl(&port->ip_mem->pci_err_addr_l.raw))
1da177e4 892 & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
22329b51 893 ((char)(readl(&port->ip_mem->pci_err_addr_l.raw) &
1da177e4 894 IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
22329b51 895 (readl(&port->ip_mem->pci_err_addr_l.raw)
1da177e4
LT		 896 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
897 ? "RX" : "TX");
898
22329b51 899 if (readl(&port->ip_mem->pci_err_addr_l.raw)
1da177e4
LT		 900 & IOC4_PCI_ERR_ADDR_MUL_ERR) {
901 printk(KERN_ERR
902 "Multiple errors occurred\n");
903 }
904 }
905 spin_unlock_irqrestore(&port->ip_lock, flags);
906
907 /* Re-enable DMA error interrupts */
908 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
909 IOC4_OTHER_INTR_TYPE);
910}
911
912/**
913 * intr_connect - interrupt connect function
914 * @soft: soft struct for this card
915 * @type: interrupt type
916 * @intrbits: bit pattern to set
917 * @intr: handler function
918 * @info: handler arg
919 */
920static void
921intr_connect(struct ioc4_soft *soft, int type,
922 uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
923{
924 int i;
925 struct ioc4_intr_info *intr_ptr;
926
927 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
928 || (type == IOC4_OTHER_INTR_TYPE)));
929
930 i = atomic_inc(&soft-> is_intr_type[type].is_num_intrs) - 1;
931 BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
932
933 /* Save off the lower level interrupt handler */
934 intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
935 intr_ptr->sd_bits = intrbits;
936 intr_ptr->sd_intr = intr;
937 intr_ptr->sd_info = info;
938}
939
940/**
941 * ioc4_intr - Top level IOC4 interrupt handler.
942 * @irq: irq value
943 * @arg: handler arg
944 * @regs: registers
945 */
946static irqreturn_t ioc4_intr(int irq, void *arg, struct pt_regs *regs)
947{
948 struct ioc4_soft *soft;
949 uint32_t this_ir, this_mir;
950 int xx, num_intrs = 0;
951 int intr_type;
952 int handled = 0;
953 struct ioc4_intr_info *ii;
954
955 soft = arg;
956 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
957 num_intrs = (int)atomic_read(
958 &soft->is_intr_type[intr_type].is_num_intrs);
959
960 this_mir = this_ir = pending_intrs(soft, intr_type);
961
962 /* Farm out the interrupt to the various drivers depending on
963 * which interrupt bits are set.
964 */
965 for (xx = 0; xx < num_intrs; xx++) {
966 ii = &soft->is_intr_type[intr_type].is_intr_info[xx];
967 if ((this_mir = this_ir & ii->sd_bits)) {
968 /* Disable owned interrupts, call handler */
969 handled++;
970 write_ireg(soft, ii->sd_bits, IOC4_W_IEC,
971 intr_type);
972 ii->sd_intr(ii->sd_info, this_mir);
973 this_ir &= ~this_mir;
974 }
975 }
1da177e4
LT		 976 }
977#ifdef DEBUG_INTERRUPTS
978 {
22329b51 979 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
1da177e4
LT		 980 spinlock_t *lp = &soft->is_ir_lock;
981 unsigned long flag;
982
983 spin_lock_irqsave(&soft->is_ir_lock, flag);
22329b51
BC		 984 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
985 "other_ir 0x%x other_ies 0x%x mask 0x%x\n",
1da177e4 986 __FUNCTION__, __LINE__,
22329b51
BC		 987 (void *)mem, readl(&mem->sio_ir.raw),
988 readl(&mem->sio_ies.raw),
989 readl(&mem->other_ir.raw),
990 readl(&mem->other_ies.raw),
1da177e4
LT		 991 IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
992 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
993 }
994#endif
995 return handled ? IRQ_HANDLED : IRQ_NONE;
996}
997
998/**
999 * ioc4_attach_local - Device initialization.
1000 * Called at *_attach() time for each
1001 * IOC4 with serial ports in the system.
d4c477ca 1002 * @idd: Master module data for this IOC4
1da177e4 1003 */
d4c477ca 1004static int inline ioc4_attach_local(struct ioc4_driver_data *idd)
1da177e4
LT		 1005{
1006 struct ioc4_port *port;
1007 struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1008 int port_number;
1009 uint16_t ioc4_revid_min = 62;
1010 uint16_t ioc4_revid;
d4c477ca
BC		 1011 struct pci_dev *pdev = idd->idd_pdev;
1012 struct ioc4_control* control = idd->idd_serial_data;
1013 struct ioc4_soft *soft = control->ic_soft;
1014 void __iomem *ioc4_misc = idd->idd_misc_regs;
1015 void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
1da177e4
LT		 1016
1017 /* IOC4 firmware must be at least rev 62 */
1018 pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1019
1020 printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1021 if (ioc4_revid < ioc4_revid_min) {
1022 printk(KERN_WARNING
1023 "IOC4 serial not supported on firmware rev %d, "
1024 "please upgrade to rev %d or higher\n",
1025 ioc4_revid, ioc4_revid_min);
1026 return -EPERM;
1027 }
22329b51 1028 BUG_ON(ioc4_misc == NULL);
1da177e4
LT		 1029 BUG_ON(ioc4_serial == NULL);
1030
1031 /* Create port structures for each port */
1032 for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1033 port_number++) {
1034 port = kmalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1035 if (!port) {
1036 printk(KERN_WARNING
1037 "IOC4 serial memory not available for port\n");
1038 return -ENOMEM;
1039 }
1040 memset(port, 0, sizeof(struct ioc4_port));
1041
1042 /* we need to remember the previous ones, to point back to
1043 * them farther down - setting up the ring buffers.
1044 */
1045 ports[port_number] = port;
1046
1047 /* Allocate buffers and jumpstart the hardware. */
1048 control->ic_port[port_number].icp_port = port;
1049 port->ip_ioc4_soft = soft;
1050 port->ip_pdev = pdev;
1051 port->ip_ienb = 0;
d4c477ca
BC		 1052 /* Use baud rate calculations based on detected PCI
1053 * bus speed. Simply test whether the PCI clock is
1054 * running closer to 66MHz or 33MHz.
1055 */
1056 if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
1057 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
1058 } else {
1059 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
1060 }
1da177e4
LT		 1061 port->ip_baud = 9600;
1062 port->ip_control = control;
22329b51 1063 port->ip_mem = ioc4_misc;
1da177e4
LT		 1064 port->ip_serial = ioc4_serial;
1065
1066 /* point to the right hook */
1067 port->ip_hooks = &hooks_array[port_number];
1068
1069 /* Get direct hooks to the serial regs and uart regs
1070 * for this port
1071 */
1072 switch (port_number) {
1073 case 0:
1074 port->ip_serial_regs = &(port->ip_serial->port_0);
1075 port->ip_uart_regs = &(port->ip_serial->uart_0);
1076 break;
1077 case 1:
1078 port->ip_serial_regs = &(port->ip_serial->port_1);
1079 port->ip_uart_regs = &(port->ip_serial->uart_1);
1080 break;
1081 case 2:
1082 port->ip_serial_regs = &(port->ip_serial->port_2);
1083 port->ip_uart_regs = &(port->ip_serial->uart_2);
1084 break;
1085 default:
1086 case 3:
1087 port->ip_serial_regs = &(port->ip_serial->port_3);
1088 port->ip_uart_regs = &(port->ip_serial->uart_3);
1089 break;
1090 }
1091
1092 /* ring buffers are 1 to a pair of ports */
1093 if (port_number && (port_number & 1)) {
1094 /* odd use the evens buffer */
1095 port->ip_dma_ringbuf =
1096 ports[port_number - 1]->ip_dma_ringbuf;
1097 port->ip_cpu_ringbuf =
1098 ports[port_number - 1]->ip_cpu_ringbuf;
1099 port->ip_inring = RING(port, RX_1_OR_3);
1100 port->ip_outring = RING(port, TX_1_OR_3);
1101
1102 } else {
1103 if (port->ip_dma_ringbuf == 0) {
1104 port->ip_cpu_ringbuf = pci_alloc_consistent
1105 (pdev, TOTAL_RING_BUF_SIZE,
1106 &port->ip_dma_ringbuf);
1107
1108 }
1109 BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1110 (TOTAL_RING_BUF_SIZE - 1)) == 0));
1111 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1112 "ip_dma_ringbuf 0x%p\n",
1113 __FUNCTION__,
1114 (void *)port->ip_cpu_ringbuf,
1115 (void *)port->ip_dma_ringbuf));
1116 port->ip_inring = RING(port, RX_0_OR_2);
1117 port->ip_outring = RING(port, TX_0_OR_2);
1118 }
1119 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1120 __FUNCTION__,
1121 port_number, (void *)port, (void *)control));
1122 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1123 (void *)port->ip_serial_regs,
1124 (void *)port->ip_uart_regs));
1125
1126 /* Initialize the hardware for IOC4 */
1127 port_init(port);
1128
1129 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1130 "outring 0x%p\n",
1131 __FUNCTION__,
1132 port_number, (void *)port,
1133 (void *)port->ip_inring,
1134 (void *)port->ip_outring));
1135
1136 /* Attach interrupt handlers */
1137 intr_connect(soft, IOC4_SIO_INTR_TYPE,
1138 GET_SIO_IR(port_number),
1139 handle_intr, port);
1140
1141 intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1142 GET_OTHER_IR(port_number),
1143 handle_dma_error_intr, port);
1144 }
1145 return 0;
1146}
1147
1148/**
1149 * enable_intrs - enable interrupts
1150 * @port: port to enable
1151 * @mask: mask to use
1152 */
1153static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1154{
1155 struct hooks *hooks = port->ip_hooks;
1156
1157 if ((port->ip_ienb & mask) != mask) {
1158 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1159 IOC4_SIO_INTR_TYPE);
1160 port->ip_ienb |= mask;
1161 }
1162
1163 if (port->ip_ienb)
1164 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1165 IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1166}
1167
1168/**
1169 * local_open - local open a port
1170 * @port: port to open
1171 */
1172static inline int local_open(struct ioc4_port *port)
1173{
1174 int spiniter = 0;
1175
1176 port->ip_flags = 0;
1177
1178 /* Pause the DMA interface if necessary */
1179 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1180 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1181 &port->ip_serial_regs->sscr);
1182 while((readl(&port->ip_serial_regs-> sscr)
1183 & IOC4_SSCR_PAUSE_STATE) == 0) {
1184 spiniter++;
1185 if (spiniter > MAXITER) {
1186 return -1;
1187 }
1188 }
1189 }
1190
1191 /* Reset the input fifo. If the uart received chars while the port
1192 * was closed and DMA is not enabled, the uart may have a bunch of
1193 * chars hanging around in its rx fifo which will not be discarded
1194 * by rclr in the upper layer. We must get rid of them here.
1195 */
1196 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1197 &port->ip_uart_regs->i4u_fcr);
1198
1199 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1200 /* UART_LCR_STOP == 1 stop */
1201
1202 /* Re-enable DMA, set default threshold to intr whenever there is
1203 * data available.
1204 */
1205 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1206 port->ip_sscr |= 1; /* default threshold */
1207
1208 /* Plug in the new sscr. This implicitly clears the DMA_PAUSE
1209 * flag if it was set above
1210 */
1211 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1212 port->ip_tx_lowat = 1;
1213 return 0;
1214}
1215
1216/**
1217 * set_rx_timeout - Set rx timeout and threshold values.
1218 * @port: port to use
1219 * @timeout: timeout value in ticks
1220 */
1221static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1222{
1223 int threshold;
1224
1225 port->ip_rx_timeout = timeout;
1226
1227 /* Timeout is in ticks. Let's figure out how many chars we
1228 * can receive at the current baud rate in that interval
1229 * and set the rx threshold to that amount. There are 4 chars
1230 * per ring entry, so we'll divide the number of chars that will
1231 * arrive in timeout by 4.
6cb2875f 1232 * So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
1da177e4 1233 */
6cb2875f 1234 threshold = timeout * port->ip_baud / 4000;
1da177e4
LT		 1235 if (threshold == 0)
1236 threshold = 1; /* otherwise we'll intr all the time! */
1237
1238 if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1239 return 1;
1240
1241 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1242 port->ip_sscr |= threshold;
1243
1244 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1245
6cb2875f
PG		 1246 /* Now set the rx timeout to the given value
1247 * again timeout * IOC4_SRTR_HZ / HZ
1248 */
1249 timeout = timeout * IOC4_SRTR_HZ / 100;
1da177e4
LT		 1250 if (timeout > IOC4_SRTR_CNT)
1251 timeout = IOC4_SRTR_CNT;
1252
1253 writel(timeout, &port->ip_serial_regs->srtr);
1254 return 0;
1255}
1256
1257/**
1258 * config_port - config the hardware
1259 * @port: port to config
1260 * @baud: baud rate for the port
1261 * @byte_size: data size
1262 * @stop_bits: number of stop bits
1263 * @parenb: parity enable ?
1264 * @parodd: odd parity ?
1265 */
1266static inline int
1267config_port(struct ioc4_port *port,
1268 int baud, int byte_size, int stop_bits, int parenb, int parodd)
1269{
1270 char lcr, sizebits;
1271 int spiniter = 0;
1272
1273 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1274 __FUNCTION__, baud, byte_size, stop_bits, parenb, parodd));
1275
1276 if (set_baud(port, baud))
1277 return 1;
1278
1279 switch (byte_size) {
1280 case 5:
1281 sizebits = UART_LCR_WLEN5;
1282 break;
1283 case 6:
1284 sizebits = UART_LCR_WLEN6;
1285 break;
1286 case 7:
1287 sizebits = UART_LCR_WLEN7;
1288 break;
1289 case 8:
1290 sizebits = UART_LCR_WLEN8;
1291 break;
1292 default:
1293 return 1;
1294 }
1295
1296 /* Pause the DMA interface if necessary */
1297 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1298 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1299 &port->ip_serial_regs->sscr);
1300 while((readl(&port->ip_serial_regs->sscr)
1301 & IOC4_SSCR_PAUSE_STATE) == 0) {
1302 spiniter++;
1303 if (spiniter > MAXITER)
1304 return -1;
1305 }
1306 }
1307
1308 /* Clear relevant fields in lcr */
1309 lcr = readb(&port->ip_uart_regs->i4u_lcr);
1310 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1311 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1312
1313 /* Set byte size in lcr */
1314 lcr |= sizebits;
1315
1316 /* Set parity */
1317 if (parenb) {
1318 lcr |= UART_LCR_PARITY;
1319 if (!parodd)
1320 lcr |= UART_LCR_EPAR;
1321 }
1322
1323 /* Set stop bits */
1324 if (stop_bits)
1325 lcr |= UART_LCR_STOP /* 2 stop bits */ ;
1326
1327 writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1328
1329 /* Re-enable the DMA interface if necessary */
1330 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1331 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1332 }
1333 port->ip_baud = baud;
1334
1335 /* When we get within this number of ring entries of filling the
1336 * entire ring on tx, place an EXPLICIT intr to generate a lowat
1337 * notification when output has drained.
1338 */
1339 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1340 if (port->ip_tx_lowat == 0)
1341 port->ip_tx_lowat = 1;
1342
6cb2875f 1343 set_rx_timeout(port, 2);
1da177e4
LT		 1344
1345 return 0;
1346}
1347
1348/**
1349 * do_write - Write bytes to the port. Returns the number of bytes
1350 * actually written. Called from transmit_chars
1351 * @port: port to use
1352 * @buf: the stuff to write
1353 * @len: how many bytes in 'buf'
1354 */
1355static inline int do_write(struct ioc4_port *port, char *buf, int len)
1356{
1357 int prod_ptr, cons_ptr, total = 0;
1358 struct ring *outring;
1359 struct ring_entry *entry;
1360 struct hooks *hooks = port->ip_hooks;
1361
1362 BUG_ON(!(len >= 0));
1363
1364 prod_ptr = port->ip_tx_prod;
1365 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1366 outring = port->ip_outring;
1367
1368 /* Maintain a 1-entry red-zone. The ring buffer is full when
1369 * (cons - prod) % ring_size is 1. Rather than do this subtraction
1370 * in the body of the loop, I'll do it now.
1371 */
1372 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1373
1374 /* Stuff the bytes into the output */
1375 while ((prod_ptr != cons_ptr) && (len > 0)) {
1376 int xx;
1377
1378 /* Get 4 bytes (one ring entry) at a time */
1379 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1380
1381 /* Invalidate all entries */
1382 entry->ring_allsc = 0;
1383
1384 /* Copy in some bytes */
1385 for (xx = 0; (xx < 4) && (len > 0); xx++) {
1386 entry->ring_data[xx] = *buf++;
1387 entry->ring_sc[xx] = IOC4_TXCB_VALID;
1388 len--;
1389 total++;
1390 }
1391
1392 /* If we are within some small threshold of filling up the
1393 * entire ring buffer, we must place an EXPLICIT intr here
1394 * to generate a lowat interrupt in case we subsequently
1395 * really do fill up the ring and the caller goes to sleep.
1396 * No need to place more than one though.
1397 */
1398 if (!(port->ip_flags & LOWAT_WRITTEN) &&
1399 ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1400 <= port->ip_tx_lowat
1401 * (int)sizeof(struct ring_entry)) {
1402 port->ip_flags |= LOWAT_WRITTEN;
1403 entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1404 }
1405
1406 /* Go on to next entry */
1407 prod_ptr += sizeof(struct ring_entry);
1408 prod_ptr &= PROD_CONS_MASK;
1409 }
1410
1411 /* If we sent something, start DMA if necessary */
1412 if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1413 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1414 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1415 }
1416
1417 /* Store the new producer pointer. If tx is disabled, we stuff the
1418 * data into the ring buffer, but we don't actually start tx.
1419 */
1420 if (!uart_tx_stopped(port->ip_port)) {
1421 writel(prod_ptr, &port->ip_serial_regs->stpir);
1422
1423 /* If we are now transmitting, enable tx_mt interrupt so we
1424 * can disable DMA if necessary when the tx finishes.
1425 */
1426 if (total > 0)
1427 enable_intrs(port, hooks->intr_tx_mt);
1428 }
1429 port->ip_tx_prod = prod_ptr;
1430 return total;
1431}
1432
1433/**
1434 * disable_intrs - disable interrupts
1435 * @port: port to enable
1436 * @mask: mask to use
1437 */
1438static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1439{
1440 struct hooks *hooks = port->ip_hooks;
1441
1442 if (port->ip_ienb & mask) {
1443 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1444 IOC4_SIO_INTR_TYPE);
1445 port->ip_ienb &= ~mask;
1446 }
1447
1448 if (!port->ip_ienb)
1449 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1450 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1451}
1452
1453/**
1454 * set_notification - Modify event notification
1455 * @port: port to use
1456 * @mask: events mask
1457 * @set_on: set ?
1458 */
1459static int set_notification(struct ioc4_port *port, int mask, int set_on)
1460{
1461 struct hooks *hooks = port->ip_hooks;
1462 uint32_t intrbits, sscrbits;
1463
1464 BUG_ON(!mask);
1465
1466 intrbits = sscrbits = 0;
1467
1468 if (mask & N_DATA_READY)
1469 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1470 if (mask & N_OUTPUT_LOWAT)
1471 intrbits |= hooks->intr_tx_explicit;
1472 if (mask & N_DDCD) {
1473 intrbits |= hooks->intr_delta_dcd;
1474 sscrbits |= IOC4_SSCR_RX_RING_DCD;
1475 }
1476 if (mask & N_DCTS)
1477 intrbits |= hooks->intr_delta_cts;
1478
1479 if (set_on) {
1480 enable_intrs(port, intrbits);
1481 port->ip_notify |= mask;
1482 port->ip_sscr |= sscrbits;
1483 } else {
1484 disable_intrs(port, intrbits);
1485 port->ip_notify &= ~mask;
1486 port->ip_sscr &= ~sscrbits;
1487 }
1488
1489 /* We require DMA if either DATA_READY or DDCD notification is
1490 * currently requested. If neither of these is requested and
1491 * there is currently no tx in progress, DMA may be disabled.
1492 */
1493 if (port->ip_notify & (N_DATA_READY | N_DDCD))
1494 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1495 else if (!(port->ip_ienb & hooks->intr_tx_mt))
1496 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1497
1498 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1499 return 0;
1500}
1501
1502/**
1503 * set_mcr - set the master control reg
1504 * @the_port: port to use
1505 * @set: set ?
1506 * @mask1: mcr mask
1507 * @mask2: shadow mask
1508 */
1509static inline int set_mcr(struct uart_port *the_port, int set,
1510 int mask1, int mask2)
1511{
1512 struct ioc4_port *port = get_ioc4_port(the_port);
1513 uint32_t shadow;
1514 int spiniter = 0;
1515 char mcr;
1516
1517 if (!port)
1518 return -1;
1519
1520 /* Pause the DMA interface if necessary */
1521 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1522 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1523 &port->ip_serial_regs->sscr);
1524 while ((readl(&port->ip_serial_regs->sscr)
1525 & IOC4_SSCR_PAUSE_STATE) == 0) {
1526 spiniter++;
1527 if (spiniter > MAXITER)
1528 return -1;
1529 }
1530 }
1531 shadow = readl(&port->ip_serial_regs->shadow);
1532 mcr = (shadow & 0xff000000) >> 24;
1533
1534 /* Set new value */
1535 if (set) {
1536 mcr |= mask1;
1537 shadow |= mask2;
1538 } else {
1539 mcr &= ~mask1;
1540 shadow &= ~mask2;
1541 }
1542 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1543 writel(shadow, &port->ip_serial_regs->shadow);
1544
1545 /* Re-enable the DMA interface if necessary */
1546 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1547 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1548 }
1549 return 0;
1550}
1551
1552/**
1553 * ioc4_set_proto - set the protocol for the port
1554 * @port: port to use
1555 * @proto: protocol to use
1556 */
1557static int ioc4_set_proto(struct ioc4_port *port, enum sio_proto proto)
1558{
1559 struct hooks *hooks = port->ip_hooks;
1560
1561 switch (proto) {
1562 case PROTO_RS232:
1563 /* Clear the appropriate GIO pin */
22329b51 1564 writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1da177e4
LT		 1565 break;
1566
1567 case PROTO_RS422:
1568 /* Set the appropriate GIO pin */
22329b51 1569 writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1da177e4
LT		 1570 break;
1571
1572 default:
1573 return 1;
1574 }
1575 return 0;
1576}
1577
1578/**
1579 * transmit_chars - upper level write, called with ip_lock
1580 * @the_port: port to write
1581 */
1582static void transmit_chars(struct uart_port *the_port)
1583{
1584 int xmit_count, tail, head;
1585 int result;
1586 char *start;
1587 struct tty_struct *tty;
1588 struct ioc4_port *port = get_ioc4_port(the_port);
1589 struct uart_info *info;
1590
1591 if (!the_port)
1592 return;
1593 if (!port)
1594 return;
1595
1596 info = the_port->info;
1597 tty = info->tty;
1598
1599 if (uart_circ_empty(&info->xmit) || uart_tx_stopped(the_port)) {
1600 /* Nothing to do or hw stopped */
1601 set_notification(port, N_ALL_OUTPUT, 0);
1602 return;
1603 }
1604
1605 head = info->xmit.head;
1606 tail = info->xmit.tail;
1607 start = (char *)&info->xmit.buf[tail];
1608
1609 /* write out all the data or until the end of the buffer */
1610 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1611 if (xmit_count > 0) {
1612 result = do_write(port, start, xmit_count);
1613 if (result > 0) {
1614 /* booking */
1615 xmit_count -= result;
1616 the_port->icount.tx += result;
1617 /* advance the pointers */
1618 tail += result;
1619 tail &= UART_XMIT_SIZE - 1;
1620 info->xmit.tail = tail;
1621 start = (char *)&info->xmit.buf[tail];
1622 }
1623 }
1624 if (uart_circ_chars_pending(&info->xmit) < WAKEUP_CHARS)
1625 uart_write_wakeup(the_port);
1626
1627 if (uart_circ_empty(&info->xmit)) {
1628 set_notification(port, N_OUTPUT_LOWAT, 0);
1629 } else {
1630 set_notification(port, N_OUTPUT_LOWAT, 1);
1631 }
1632}
1633
1634/**
1635 * ioc4_change_speed - change the speed of the port
1636 * @the_port: port to change
1637 * @new_termios: new termios settings
1638 * @old_termios: old termios settings
1639 */
1640static void
1641ioc4_change_speed(struct uart_port *the_port,
1642 struct termios *new_termios, struct termios *old_termios)
1643{
1644 struct ioc4_port *port = get_ioc4_port(the_port);
1645 int baud, bits;
68985e48
PG		 1646 unsigned cflag;
1647 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1da177e4
LT		 1648 struct uart_info *info = the_port->info;
1649
1650 cflag = new_termios->c_cflag;
1651
1652 switch (cflag & CSIZE) {
1653 case CS5:
1654 new_data = 5;
1da177e4
LT		 1655 bits = 7;
1656 break;
1657 case CS6:
1658 new_data = 6;
1da177e4
LT		 1659 bits = 8;
1660 break;
1661 case CS7:
1662 new_data = 7;
1da177e4
LT		 1663 bits = 9;
1664 break;
1665 case CS8:
1666 new_data = 8;
1da177e4
LT		 1667 bits = 10;
1668 break;
1669 default:
1670 /* cuz we always need a default ... */
1671 new_data = 5;
1da177e4
LT		 1672 bits = 7;
1673 break;
1674 }
1675 if (cflag & CSTOPB) {
1da177e4
LT		 1676 bits++;
1677 new_stop = 1;
1678 }
1679 if (cflag & PARENB) {
1da177e4
LT		 1680 bits++;
1681 new_parity_enable = 1;
68985e48
PG		 1682 if (cflag & PARODD)
1683 new_parity = 1;
1da177e4
LT		 1684 }
1685 baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1686 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1687 DPRINT_CONFIG(("%s: returned baud %d\n", __FUNCTION__, baud));
1688
1689 /* default is 9600 */
1690 if (!baud)
1691 baud = 9600;
1692
1693 if (!the_port->fifosize)
1694 the_port->fifosize = IOC4_MAX_CHARS;
1695 the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1696 the_port->timeout += HZ / 50; /* Add .02 seconds of slop */
1697
1698 the_port->ignore_status_mask = N_ALL_INPUT;
1699
1700 if (I_IGNPAR(info->tty))
1701 the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1702 | N_FRAMING_ERROR);
1703 if (I_IGNBRK(info->tty)) {
1704 the_port->ignore_status_mask &= ~N_BREAK;
1705 if (I_IGNPAR(info->tty))
1706 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1707 }
1708 if (!(cflag & CREAD)) {
1709 /* ignore everything */
1710 the_port->ignore_status_mask &= ~N_DATA_READY;
1711 }
1712
149733d4 1713 if (cflag & CRTSCTS) {
1da177e4 1714 info->flags |= ASYNC_CTS_FLOW;
149733d4 1715 port->ip_sscr |= IOC4_SSCR_HFC_EN;
149733d4 1716 }
68985e48 1717 else {
1da177e4 1718 info->flags &= ~ASYNC_CTS_FLOW;
68985e48
PG		 1719 port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1720 }
1721 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1da177e4
LT		 1722
1723 /* Set the configuration and proper notification call */
1724 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1725 "config_port(baud %d data %d stop %d p enable %d parity %d),"
1726 " notification 0x%x\n",
1727 __FUNCTION__, (void *)port, cflag, baud, new_data, new_stop,
1728 new_parity_enable, new_parity, the_port->ignore_status_mask));
1729
1730 if ((config_port(port, baud, /* baud */
1731 new_data, /* byte size */
1732 new_stop, /* stop bits */
1733 new_parity_enable, /* set parity */
1734 new_parity)) >= 0) { /* parity 1==odd */
1735 set_notification(port, the_port->ignore_status_mask, 1);
1736 }
1737}
1738
1739/**
1740 * ic4_startup_local - Start up the serial port - returns >= 0 if no errors
1741 * @the_port: Port to operate on
1742 */
1743static inline int ic4_startup_local(struct uart_port *the_port)
1744{
1745 int retval = 0;
1746 struct ioc4_port *port;
1747 struct uart_info *info;
1748
1749 if (!the_port)
1750 return -1;
1751
1752 port = get_ioc4_port(the_port);
1753 if (!port)
1754 return -1;
1755
1756 info = the_port->info;
1757 if (info->flags & UIF_INITIALIZED) {
1758 return retval;
1759 }
1760
1761 if (info->tty) {
1762 set_bit(TTY_IO_ERROR, &info->tty->flags);
1763 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1764 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
1765 info->tty->alt_speed = 57600;
1766 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
1767 info->tty->alt_speed = 115200;
1768 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI)
1769 info->tty->alt_speed = 230400;
1770 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP)
1771 info->tty->alt_speed = 460800;
1772 }
1773 local_open(port);
1774
1775 /* set the speed of the serial port */
1776 ioc4_change_speed(the_port, info->tty->termios, (struct termios *)0);
1777
1da177e4
LT		 1778 info->flags |= UIF_INITIALIZED;
1779 return 0;
1780}
1781
1782/*
1783 * ioc4_cb_output_lowat - called when the output low water mark is hit
1784 * @port: port to output
1785 */
1786static void ioc4_cb_output_lowat(struct ioc4_port *port)
1787{
1788 /* ip_lock is set on the call here */
1789 if (port->ip_port) {
1790 transmit_chars(port->ip_port);
1791 }
1792}
1793
1da177e4
LT		 1794/**
1795 * handle_intr - service any interrupts for the given port - 2nd level
1796 * called via sd_intr
1797 * @arg: handler arg
1798 * @sio_ir: ioc4regs
1799 */
1800static void handle_intr(void *arg, uint32_t sio_ir)
1801{
1802 struct ioc4_port *port = (struct ioc4_port *)arg;
1803 struct hooks *hooks = port->ip_hooks;
1804 unsigned int rx_high_rd_aborted = 0;
1805 unsigned int flags;
1806 struct uart_port *the_port;
1807 int loop_counter;
1808
1809 /* Possible race condition here: The tx_mt interrupt bit may be
1810 * cleared without the intervention of the interrupt handler,
1811 * e.g. by a write. If the top level interrupt handler reads a
1812 * tx_mt, then some other processor does a write, starting up
1813 * output, then we come in here, see the tx_mt and stop DMA, the
1814 * output started by the other processor will hang. Thus we can
1815 * only rely on tx_mt being legitimate if it is read while the
1816 * port lock is held. Therefore this bit must be ignored in the
1817 * passed in interrupt mask which was read by the top level
1818 * interrupt handler since the port lock was not held at the time
1819 * it was read. We can only rely on this bit being accurate if it
1820 * is read while the port lock is held. So we'll clear it for now,
1821 * and reload it later once we have the port lock.
1822 */
1823 sio_ir &= ~(hooks->intr_tx_mt);
1824
1825 spin_lock_irqsave(&port->ip_lock, flags);
1826
1827 loop_counter = MAXITER; /* to avoid hangs */
1828
1829 do {
1830 uint32_t shadow;
1831
1832 if ( loop_counter-- <= 0 ) {
1833 printk(KERN_WARNING "IOC4 serial: "
1834 "possible hang condition/"
1835 "port stuck on interrupt.\n");
1836 break;
1837 }
1838
1839 /* Handle a DCD change */
1840 if (sio_ir & hooks->intr_delta_dcd) {
1841 /* ACK the interrupt */
1842 writel(hooks->intr_delta_dcd,
22329b51 1843 &port->ip_mem->sio_ir.raw);
1da177e4
LT		 1844
1845 shadow = readl(&port->ip_serial_regs->shadow);
1846
1847 if ((port->ip_notify & N_DDCD)
1848 && (shadow & IOC4_SHADOW_DCD)
1849 && (port->ip_port)) {
1850 the_port = port->ip_port;
1851 the_port->icount.dcd = 1;
1852 wake_up_interruptible
1853 (&the_port-> info->delta_msr_wait);
1854 } else if ((port->ip_notify & N_DDCD)
1855 && !(shadow & IOC4_SHADOW_DCD)) {
1856 /* Flag delta DCD/no DCD */
1857 port->ip_flags |= DCD_ON;
1858 }
1859 }
1860
1861 /* Handle a CTS change */
1862 if (sio_ir & hooks->intr_delta_cts) {
1863 /* ACK the interrupt */
1864 writel(hooks->intr_delta_cts,
22329b51 1865 &port->ip_mem->sio_ir.raw);
1da177e4
LT		 1866
1867 shadow = readl(&port->ip_serial_regs->shadow);
1868
1869 if ((port->ip_notify & N_DCTS)
1870 && (port->ip_port)) {
1871 the_port = port->ip_port;
1872 the_port->icount.cts =
1873 (shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1874 wake_up_interruptible
1875 (&the_port->info->delta_msr_wait);
1876 }
1877 }
1878
1879 /* rx timeout interrupt. Must be some data available. Put this
1880 * before the check for rx_high since servicing this condition
1881 * may cause that condition to clear.
1882 */
1883 if (sio_ir & hooks->intr_rx_timer) {
1884 /* ACK the interrupt */
1885 writel(hooks->intr_rx_timer,
22329b51 1886 &port->ip_mem->sio_ir.raw);
1da177e4
LT		 1887
1888 if ((port->ip_notify & N_DATA_READY)
1889 && (port->ip_port)) {
1890 /* ip_lock is set on call here */
1891 receive_chars(port->ip_port);
1892 }
1893 }
1894
1895 /* rx high interrupt. Must be after rx_timer. */
1896 else if (sio_ir & hooks->intr_rx_high) {
1897 /* Data available, notify upper layer */
1898 if ((port->ip_notify & N_DATA_READY)
1899 && port->ip_port) {
1900 /* ip_lock is set on call here */
1901 receive_chars(port->ip_port);
1902 }
1903
1904 /* We can't ACK this interrupt. If receive_chars didn't
1905 * cause the condition to clear, we'll have to disable
1906 * the interrupt until the data is drained.
1907 * If the read was aborted, don't disable the interrupt
1908 * as this may cause us to hang indefinitely. An
1909 * aborted read generally means that this interrupt
1910 * hasn't been delivered to the cpu yet anyway, even
1911 * though we see it as asserted when we read the sio_ir.
1912 */
1913 if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1914 if ((port->ip_flags & READ_ABORTED) == 0) {
1915 port->ip_ienb &= ~hooks->intr_rx_high;
1916 port->ip_flags |= INPUT_HIGH;
1917 } else {
1918 rx_high_rd_aborted++;
1919 }
1920 }
1921 }
1922
1923 /* We got a low water interrupt: notify upper layer to
1924 * send more data. Must come before tx_mt since servicing
1925 * this condition may cause that condition to clear.
1926 */
1927 if (sio_ir & hooks->intr_tx_explicit) {
1928 port->ip_flags &= ~LOWAT_WRITTEN;
1929
1930 /* ACK the interrupt */
1931 writel(hooks->intr_tx_explicit,
22329b51 1932 &port->ip_mem->sio_ir.raw);
1da177e4
LT		 1933
1934 if (port->ip_notify & N_OUTPUT_LOWAT)
1935 ioc4_cb_output_lowat(port);
1936 }
1937
1938 /* Handle tx_mt. Must come after tx_explicit. */
1939 else if (sio_ir & hooks->intr_tx_mt) {
1940 /* If we are expecting a lowat notification
1941 * and we get to this point it probably means that for
1942 * some reason the tx_explicit didn't work as expected
1943 * (that can legitimately happen if the output buffer is
1944 * filled up in just the right way).
1945 * So send the notification now.
1946 */
1947 if (port->ip_notify & N_OUTPUT_LOWAT) {
1948 ioc4_cb_output_lowat(port);
1949
1950 /* We need to reload the sio_ir since the lowat
1951 * call may have caused another write to occur,
1952 * clearing the tx_mt condition.
1953 */
1954 sio_ir = PENDING(port);
1955 }
1956
1957 /* If the tx_mt condition still persists even after the
1958 * lowat call, we've got some work to do.
1959 */
1960 if (sio_ir & hooks->intr_tx_mt) {
1961
1962 /* If we are not currently expecting DMA input,
1963 * and the transmitter has just gone idle,
1964 * there is no longer any reason for DMA, so
1965 * disable it.
1966 */
1967 if (!(port->ip_notify
1968 & (N_DATA_READY | N_DDCD))) {
1969 BUG_ON(!(port->ip_sscr
1970 & IOC4_SSCR_DMA_EN));
1971 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1972 writel(port->ip_sscr,
1973 &port->ip_serial_regs->sscr);
1974 }
1975
1976 /* Prevent infinite tx_mt interrupt */
1977 port->ip_ienb &= ~hooks->intr_tx_mt;
1978 }
1979 }
1980 sio_ir = PENDING(port);
1981
1982 /* if the read was aborted and only hooks->intr_rx_high,
1983 * clear hooks->intr_rx_high, so we do not loop forever.
1984 */
1985
1986 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
1987 sio_ir &= ~hooks->intr_rx_high;
1988 }
1989 } while (sio_ir & hooks->intr_all);
1990
1991 spin_unlock_irqrestore(&port->ip_lock, flags);
1992
1993 /* Re-enable interrupts before returning from interrupt handler.
1994 * Getting interrupted here is okay. It'll just v() our semaphore, and
1995 * we'll come through the loop again.
1996 */
1997
1998 write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
1999 IOC4_SIO_INTR_TYPE);
2000}
2001
2002/*
2003 * ioc4_cb_post_ncs - called for some basic errors
2004 * @port: port to use
2005 * @ncs: event
2006 */
2007static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2008{
2009 struct uart_icount *icount;
2010
2011 icount = &the_port->icount;
2012
2013 if (ncs & NCS_BREAK)
2014 icount->brk++;
2015 if (ncs & NCS_FRAMING)
2016 icount->frame++;
2017 if (ncs & NCS_OVERRUN)
2018 icount->overrun++;
2019 if (ncs & NCS_PARITY)
2020 icount->parity++;
2021}
2022
2023/**
2024 * do_read - Read in bytes from the port. Return the number of bytes
2025 * actually read.
2026 * @the_port: port to use
2027 * @buf: place to put the stuff we read
2028 * @len: how big 'buf' is
2029 */
2030
2031static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2032 int len)
2033{
2034 int prod_ptr, cons_ptr, total;
2035 struct ioc4_port *port = get_ioc4_port(the_port);
2036 struct ring *inring;
2037 struct ring_entry *entry;
2038 struct hooks *hooks = port->ip_hooks;
2039 int byte_num;
2040 char *sc;
2041 int loop_counter;
2042
2043 BUG_ON(!(len >= 0));
2044 BUG_ON(!port);
2045
2046 /* There is a nasty timing issue in the IOC4. When the rx_timer
2047 * expires or the rx_high condition arises, we take an interrupt.
2048 * At some point while servicing the interrupt, we read bytes from
2049 * the ring buffer and re-arm the rx_timer. However the rx_timer is
2050 * not started until the first byte is received *after* it is armed,
2051 * and any bytes pending in the rx construction buffers are not drained
2052 * to memory until either there are 4 bytes available or the rx_timer
2053 * expires. This leads to a potential situation where data is left
2054 * in the construction buffers forever - 1 to 3 bytes were received
2055 * after the interrupt was generated but before the rx_timer was
2056 * re-armed. At that point as long as no subsequent bytes are received
2057 * the timer will never be started and the bytes will remain in the
2058 * construction buffer forever. The solution is to execute a DRAIN
2059 * command after rearming the timer. This way any bytes received before
2060 * the DRAIN will be drained to memory, and any bytes received after
2061 * the DRAIN will start the TIMER and be drained when it expires.
2062 * Luckily, this only needs to be done when the DMA buffer is empty
2063 * since there is no requirement that this function return all
2064 * available data as long as it returns some.
2065 */
2066 /* Re-arm the timer */
2067 writel(port->ip_rx_cons | IOC4_SRCIR_ARM,
2068 &port->ip_serial_regs->srcir);
2069
2070 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2071 cons_ptr = port->ip_rx_cons;
2072
2073 if (prod_ptr == cons_ptr) {
2074 int reset_dma = 0;
2075
2076 /* Input buffer appears empty, do a flush. */
2077
2078 /* DMA must be enabled for this to work. */
2079 if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2080 port->ip_sscr |= IOC4_SSCR_DMA_EN;
2081 reset_dma = 1;
2082 }
2083
2084 /* Potential race condition: we must reload the srpir after
2085 * issuing the drain command, otherwise we could think the rx
2086 * buffer is empty, then take a very long interrupt, and when
2087 * we come back it's full and we wait forever for the drain to
2088 * complete.
2089 */
2090 writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2091 &port->ip_serial_regs->sscr);
2092 prod_ptr = readl(&port->ip_serial_regs->srpir)
2093 & PROD_CONS_MASK;
2094
2095 /* We must not wait for the DRAIN to complete unless there are
2096 * at least 8 bytes (2 ring entries) available to receive the
2097 * data otherwise the DRAIN will never complete and we'll
2098 * deadlock here.
2099 * In fact, to make things easier, I'll just ignore the flush if
2100 * there is any data at all now available.
2101 */
2102 if (prod_ptr == cons_ptr) {
2103 loop_counter = 0;
2104 while (readl(&port->ip_serial_regs->sscr) &
2105 IOC4_SSCR_RX_DRAIN) {
2106 loop_counter++;
2107 if (loop_counter > MAXITER)
2108 return -1;
2109 }
2110
2111 /* SIGH. We have to reload the prod_ptr *again* since
2112 * the drain may have caused it to change
2113 */
2114 prod_ptr = readl(&port->ip_serial_regs->srpir)
2115 & PROD_CONS_MASK;
2116 }
2117 if (reset_dma) {
2118 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2119 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2120 }
2121 }
2122 inring = port->ip_inring;
2123 port->ip_flags &= ~READ_ABORTED;
2124
2125 total = 0;
2126 loop_counter = 0xfffff; /* to avoid hangs */
2127
2128 /* Grab bytes from the hardware */
2129 while ((prod_ptr != cons_ptr) && (len > 0)) {
2130 entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2131
2132 if ( loop_counter-- <= 0 ) {
2133 printk(KERN_WARNING "IOC4 serial: "
2134 "possible hang condition/"
2135 "port stuck on read.\n");
2136 break;
2137 }
2138
2139 /* According to the producer pointer, this ring entry
2140 * must contain some data. But if the PIO happened faster
2141 * than the DMA, the data may not be available yet, so let's
2142 * wait until it arrives.
2143 */
2144 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2145 /* Indicate the read is aborted so we don't disable
2146 * the interrupt thinking that the consumer is
2147 * congested.
2148 */
2149 port->ip_flags |= READ_ABORTED;
2150 len = 0;
2151 break;
2152 }
2153
2154 /* Load the bytes/status out of the ring entry */
2155 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2156 sc = &(entry->ring_sc[byte_num]);
2157
2158 /* Check for change in modem state or overrun */
2159 if ((*sc & IOC4_RXSB_MODEM_VALID)
2160 && (port->ip_notify & N_DDCD)) {
2161 /* Notify upper layer if DCD dropped */
2162
2163 if ((port->ip_flags & DCD_ON)
2164 && !(*sc & IOC4_RXSB_DCD)) {
2165
2166 /* If we have already copied some data,
2167 * return it. We'll pick up the carrier
2168 * drop on the next pass. That way we
2169 * don't throw away the data that has
2170 * already been copied back to
2171 * the caller's buffer.
2172 */
2173 if (total > 0) {
2174 len = 0;
2175 break;
2176 }
2177 port->ip_flags &= ~DCD_ON;
2178
2179 /* Turn off this notification so the
2180 * carrier drop protocol won't see it
2181 * again when it does a read.
2182 */
2183 *sc &= ~IOC4_RXSB_MODEM_VALID;
2184
2185 /* To keep things consistent, we need
2186 * to update the consumer pointer so
2187 * the next reader won't come in and
2188 * try to read the same ring entries
2189 * again. This must be done here before
2190 * the dcd change.
2191 */
2192
2193 if ((entry->ring_allsc & RING_ANY_VALID)
2194 == 0) {
2195 cons_ptr += (int)sizeof
2196 (struct ring_entry);
2197 cons_ptr &= PROD_CONS_MASK;
2198 }
2199 writel(cons_ptr,
2200 &port->ip_serial_regs->srcir);
2201 port->ip_rx_cons = cons_ptr;
2202
2203 /* Notify upper layer of carrier drop */
2204 if ((port->ip_notify & N_DDCD)
2205 && port->ip_port) {
2206 the_port->icount.dcd = 0;
2207 wake_up_interruptible
2208 (&the_port->info->
2209 delta_msr_wait);
2210 }
2211
2212 /* If we had any data to return, we
2213 * would have returned it above.
2214 */
2215 return 0;
2216 }
2217 }
2218 if (*sc & IOC4_RXSB_MODEM_VALID) {
2219 /* Notify that an input overrun occurred */
2220 if ((*sc & IOC4_RXSB_OVERRUN)
2221 && (port->ip_notify & N_OVERRUN_ERROR)) {
2222 ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2223 }
2224 /* Don't look at this byte again */
2225 *sc &= ~IOC4_RXSB_MODEM_VALID;
2226 }
2227
2228 /* Check for valid data or RX errors */
2229 if ((*sc & IOC4_RXSB_DATA_VALID) &&
2230 ((*sc & (IOC4_RXSB_PAR_ERR
2231 | IOC4_RXSB_FRAME_ERR
2232 | IOC4_RXSB_BREAK))
2233 && (port->ip_notify & (N_PARITY_ERROR
2234 | N_FRAMING_ERROR
2235 | N_BREAK)))) {
2236 /* There is an error condition on the next byte.
2237 * If we have already transferred some bytes,
2238 * we'll stop here. Otherwise if this is the
2239 * first byte to be read, we'll just transfer
2240 * it alone after notifying the
2241 * upper layer of its status.
2242 */
2243 if (total > 0) {
2244 len = 0;
2245 break;
2246 } else {
2247 if ((*sc & IOC4_RXSB_PAR_ERR) &&
2248 (port->ip_notify & N_PARITY_ERROR)) {
2249 ioc4_cb_post_ncs(the_port,
2250 NCS_PARITY);
2251 }
2252 if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2253 (port->ip_notify & N_FRAMING_ERROR)){
2254 ioc4_cb_post_ncs(the_port,
2255 NCS_FRAMING);
2256 }
2257 if ((*sc & IOC4_RXSB_BREAK)
2258 && (port->ip_notify & N_BREAK)) {
2259 ioc4_cb_post_ncs
2260 (the_port,
2261 NCS_BREAK);
2262 }
2263 len = 1;
2264 }
2265 }
2266 if (*sc & IOC4_RXSB_DATA_VALID) {
2267 *sc &= ~IOC4_RXSB_DATA_VALID;
2268 *buf = entry->ring_data[byte_num];
2269 buf++;
2270 len--;
2271 total++;
2272 }
2273 }
2274
2275 /* If we used up this entry entirely, go on to the next one,
2276 * otherwise we must have run out of buffer space, so
2277 * leave the consumer pointer here for the next read in case
2278 * there are still unread bytes in this entry.
2279 */
2280 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2281 cons_ptr += (int)sizeof(struct ring_entry);
2282 cons_ptr &= PROD_CONS_MASK;
2283 }
2284 }
2285
2286 /* Update consumer pointer and re-arm rx timer interrupt */
2287 writel(cons_ptr, &port->ip_serial_regs->srcir);
2288 port->ip_rx_cons = cons_ptr;
2289
2290 /* If we have now dipped below the rx high water mark and we have
2291 * rx_high interrupt turned off, we can now turn it back on again.
2292 */
2293 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2294 & PROD_CONS_MASK) < ((port->ip_sscr &
2295 IOC4_SSCR_RX_THRESHOLD)
2296 << IOC4_PROD_CONS_PTR_OFF))) {
2297 port->ip_flags &= ~INPUT_HIGH;
2298 enable_intrs(port, hooks->intr_rx_high);
2299 }
2300 return total;
2301}
2302/**
2303 * receive_chars - upper level read. Called with ip_lock.
2304 * @the_port: port to read from
2305 */
2306static void receive_chars(struct uart_port *the_port)
2307{
2308 struct tty_struct *tty;
2309 unsigned char ch[IOC4_MAX_CHARS];
2310 int read_count, request_count;
2311 struct uart_icount *icount;
2312 struct uart_info *info = the_port->info;
2313
2314 /* Make sure all the pointers are "good" ones */
2315 if (!info)
2316 return;
2317 if (!info->tty)
2318 return;
2319
2320 tty = info->tty;
2321
2322 request_count = TTY_FLIPBUF_SIZE - tty->flip.count - 1;
2323
2324 if (request_count > 0) {
2325 if (request_count > IOC4_MAX_CHARS - 2)
2326 request_count = IOC4_MAX_CHARS - 2;
2327 icount = &the_port->icount;
2328 read_count = do_read(the_port, ch, request_count);
2329 if (read_count > 0) {
2330 memcpy(tty->flip.char_buf_ptr, ch, read_count);
2331 memset(tty->flip.flag_buf_ptr, TTY_NORMAL, read_count);
2332 tty->flip.char_buf_ptr += read_count;
2333 tty->flip.flag_buf_ptr += read_count;
2334 tty->flip.count += read_count;
2335 icount->rx += read_count;
2336 }
2337 }
2338 tty_flip_buffer_push(tty);
2339}
2340
2341/**
2342 * ic4_type - What type of console are we?
2343 * @port: Port to operate with (we ignore since we only have one port)
2344 *
2345 */
2346static const char *ic4_type(struct uart_port *the_port)
2347{
2348 return "SGI IOC4 Serial";
2349}
2350
2351/**
2352 * ic4_tx_empty - Is the transmitter empty? We pretend we're always empty
2353 * @port: Port to operate on (we ignore since we always return 1)
2354 *
2355 */
2356static unsigned int ic4_tx_empty(struct uart_port *the_port)
2357{
2358 return 1;
2359}
2360
2361/**
2362 * ic4_stop_tx - stop the transmitter
2363 * @port: Port to operate on
1da177e4
LT		 2364 *
2365 */
b129a8cc 2366static void ic4_stop_tx(struct uart_port *the_port)
1da177e4
LT		 2367{
2368}
2369
2370/**
2371 * null_void_function -
2372 * @port: Port to operate on
2373 *
2374 */
2375static void null_void_function(struct uart_port *the_port)
2376{
2377}
2378
2379/**
2380 * ic4_shutdown - shut down the port - free irq and disable
2381 * @port: Port to shut down
2382 *
2383 */
2384static void ic4_shutdown(struct uart_port *the_port)
2385{
2386 unsigned long port_flags;
2387 struct ioc4_port *port;
2388 struct uart_info *info;
2389
2390 port = get_ioc4_port(the_port);
2391 if (!port)
2392 return;
2393
2394 info = the_port->info;
2395
2396 if (!(info->flags & UIF_INITIALIZED))
2397 return;
2398
2399 wake_up_interruptible(&info->delta_msr_wait);
2400
2401 if (info->tty)
2402 set_bit(TTY_IO_ERROR, &info->tty->flags);
2403
2404 spin_lock_irqsave(&port->ip_lock, port_flags);
2405 set_notification(port, N_ALL, 0);
2406 info->flags &= ~UIF_INITIALIZED;
2407 spin_unlock_irqrestore(&port->ip_lock, port_flags);
2408}
2409
2410/**
2411 * ic4_set_mctrl - set control lines (dtr, rts, etc)
2412 * @port: Port to operate on
2413 * @mctrl: Lines to set/unset
2414 *
2415 */
2416static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2417{
2418 unsigned char mcr = 0;
2419
2420 if (mctrl & TIOCM_RTS)
2421 mcr |= UART_MCR_RTS;
2422 if (mctrl & TIOCM_DTR)
2423 mcr |= UART_MCR_DTR;
2424 if (mctrl & TIOCM_OUT1)
2425 mcr |= UART_MCR_OUT1;
2426 if (mctrl & TIOCM_OUT2)
2427 mcr |= UART_MCR_OUT2;
2428 if (mctrl & TIOCM_LOOP)
2429 mcr |= UART_MCR_LOOP;
2430
2431 set_mcr(the_port, 1, mcr, IOC4_SHADOW_DTR);
2432}
2433
2434/**
2435 * ic4_get_mctrl - get control line info
2436 * @port: port to operate on
2437 *
2438 */
2439static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2440{
2441 struct ioc4_port *port = get_ioc4_port(the_port);
2442 uint32_t shadow;
2443 unsigned int ret = 0;
2444
2445 if (!port)
2446 return 0;
2447
2448 shadow = readl(&port->ip_serial_regs->shadow);
2449 if (shadow & IOC4_SHADOW_DCD)
2450 ret |= TIOCM_CAR;
2451 if (shadow & IOC4_SHADOW_DR)
2452 ret |= TIOCM_DSR;
2453 if (shadow & IOC4_SHADOW_CTS)
2454 ret |= TIOCM_CTS;
2455 return ret;
2456}
2457
2458/**
2459 * ic4_start_tx - Start transmitter, flush any output
2460 * @port: Port to operate on
1da177e4
LT		 2461 *
2462 */
b129a8cc 2463static void ic4_start_tx(struct uart_port *the_port)
1da177e4
LT		 2464{
2465 struct ioc4_port *port = get_ioc4_port(the_port);
2466 unsigned long flags;
2467
2468 if (port) {
2469 spin_lock_irqsave(&port->ip_lock, flags);
2470 transmit_chars(the_port);
2471 spin_unlock_irqrestore(&port->ip_lock, flags);
2472 }
2473}
2474
2475/**
2476 * ic4_break_ctl - handle breaks
2477 * @port: Port to operate on
2478 * @break_state: Break state
2479 *
2480 */
2481static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2482{
2483}
2484
2485/**
2486 * ic4_startup - Start up the serial port - always return 0 (We're always on)
2487 * @port: Port to operate on
2488 *
2489 */
2490static int ic4_startup(struct uart_port *the_port)
2491{
2492 int retval;
2493 struct ioc4_port *port;
2494 struct ioc4_control *control;
2495 struct uart_info *info;
2496 unsigned long port_flags;
2497
2498 if (!the_port) {
2499 return -ENODEV;
2500 }
2501 port = get_ioc4_port(the_port);
2502 if (!port) {
2503 return -ENODEV;
2504 }
2505 info = the_port->info;
2506
2507 control = port->ip_control;
2508 if (!control) {
2509 return -ENODEV;
2510 }
2511
2512 /* Start up the serial port */
2513 spin_lock_irqsave(&port->ip_lock, port_flags);
2514 retval = ic4_startup_local(the_port);
2515 spin_unlock_irqrestore(&port->ip_lock, port_flags);
2516 return retval;
2517}
2518
2519/**
2520 * ic4_set_termios - set termios stuff
2521 * @port: port to operate on
2522 * @termios: New settings
2523 * @termios: Old
2524 *
2525 */
2526static void
2527ic4_set_termios(struct uart_port *the_port,
2528 struct termios *termios, struct termios *old_termios)
2529{
2530 struct ioc4_port *port = get_ioc4_port(the_port);
2531 unsigned long port_flags;
2532
2533 spin_lock_irqsave(&port->ip_lock, port_flags);
2534 ioc4_change_speed(the_port, termios, old_termios);
2535 spin_unlock_irqrestore(&port->ip_lock, port_flags);
2536}
2537
2538/**
2539 * ic4_request_port - allocate resources for port - no op....
2540 * @port: port to operate on
2541 *
2542 */
2543static int ic4_request_port(struct uart_port *port)
2544{
2545 return 0;
2546}
2547
2548/* Associate the uart functions above - given to serial core */
2549
2550static struct uart_ops ioc4_ops = {
2551 .tx_empty = ic4_tx_empty,
2552 .set_mctrl = ic4_set_mctrl,
2553 .get_mctrl = ic4_get_mctrl,
2554 .stop_tx = ic4_stop_tx,
2555 .start_tx = ic4_start_tx,
2556 .stop_rx = null_void_function,
2557 .enable_ms = null_void_function,
2558 .break_ctl = ic4_break_ctl,
2559 .startup = ic4_startup,
2560 .shutdown = ic4_shutdown,
2561 .set_termios = ic4_set_termios,
2562 .type = ic4_type,
2563 .release_port = null_void_function,
2564 .request_port = ic4_request_port,
2565};
2566
2567/*
2568 * Boot-time initialization code
2569 */
2570
2571static struct uart_driver ioc4_uart = {
2572 .owner = THIS_MODULE,
2573 .driver_name = "ioc4_serial",
2574 .dev_name = DEVICE_NAME,
2575 .major = DEVICE_MAJOR,
2576 .minor = DEVICE_MINOR,
2577 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2578};
2579
2580/**
2581 * ioc4_serial_core_attach - register with serial core
2582 * This is done during pci probing
2583 * @pdev: handle for this card
2584 */
2585static inline int
2586ioc4_serial_core_attach(struct pci_dev *pdev)
2587{
2588 struct ioc4_port *port;
2589 struct uart_port *the_port;
22329b51
BC		 2590 struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2591 struct ioc4_control *control = idd->idd_serial_data;
1da177e4
LT		 2592 int ii;
2593
2594 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2595 __FUNCTION__, pdev, (void *)control));
2596
2597 if (!control)
2598 return -ENODEV;
2599
2600 /* once around for each port on this card */
2601 for (ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++) {
2602 the_port = &control->ic_port[ii].icp_uart_port;
2603 port = control->ic_port[ii].icp_port;
2604 port->ip_port = the_port;
2605
2606 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p\n",
2607 __FUNCTION__, (void *)the_port,
2608 (void *)port));
2609
2610 spin_lock_init(&the_port->lock);
2611 /* membase, iobase and mapbase just need to be non-0 */
2612 the_port->membase = (unsigned char __iomem *)1;
2613 the_port->line = the_port->iobase = ii;
2614 the_port->mapbase = 1;
2615 the_port->type = PORT_16550A;
2616 the_port->fifosize = IOC4_MAX_CHARS;
2617 the_port->ops = &ioc4_ops;
2618 the_port->irq = control->ic_irq;
2619 the_port->dev = &pdev->dev;
2620 if (uart_add_one_port(&ioc4_uart, the_port) < 0) {
2621 printk(KERN_WARNING
2622 "%s: unable to add port %d\n",
2623 __FUNCTION__, the_port->line);
2624 } else {
2625 DPRINT_CONFIG(
2626 ("IOC4 serial driver port %d irq = %d\n",
2627 the_port->line, the_port->irq));
2628 }
2629 /* all ports are rs232 for now */
2630 ioc4_set_proto(port, PROTO_RS232);
2631 }
2632 return 0;
2633}
2634
2635/**
2636 * ioc4_serial_attach_one - register attach function
22329b51
BC		 2637 * called per card found from IOC4 master module.
2638 * @idd: Master module data for this IOC4
1da177e4
LT		 2639 */
2640int
22329b51 2641ioc4_serial_attach_one(struct ioc4_driver_data *idd)
1da177e4 2642{
22329b51 2643 unsigned long tmp_addr1;
1da177e4
LT		 2644 struct ioc4_serial __iomem *serial;
2645 struct ioc4_soft *soft;
2646 struct ioc4_control *control;
22329b51 2647 int ret = 0;
1da177e4
LT		 2648
2649
22329b51 2650 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev, idd->idd_pci_id));
1da177e4
LT		 2651
2652 /* request serial registers */
22329b51 2653 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
1da177e4
LT		 2654
2655 if (!request_region(tmp_addr1, sizeof(struct ioc4_serial),
2656 "sioc4_uart")) {
2657 printk(KERN_WARNING
2658 "ioc4 (%p): unable to get request region for "
22329b51 2659 "uart space\n", (void *)idd->idd_pdev);
1da177e4
LT		 2660 ret = -ENODEV;
2661 goto out1;
2662 }
2663 serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2664 if (!serial) {
2665 printk(KERN_WARNING
2666 "ioc4 (%p) : unable to remap ioc4 serial register\n",
22329b51 2667 (void *)idd->idd_pdev);
1da177e4
LT		 2668 ret = -ENODEV;
2669 goto out2;
2670 }
2671 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
22329b51 2672 __FUNCTION__, (void *)idd->idd_misc_regs, (void *)serial));
1da177e4
LT		 2673
2674 /* Get memory for the new card */
2675 control = kmalloc(sizeof(struct ioc4_control) * IOC4_NUM_SERIAL_PORTS,
2676 GFP_KERNEL);
2677
2678 if (!control) {
2679 printk(KERN_WARNING "ioc4_attach_one"
2680 ": unable to get memory for the IOC4\n");
2681 ret = -ENOMEM;
2682 goto out2;
2683 }
2684 memset(control, 0, sizeof(struct ioc4_control));
22329b51 2685 idd->idd_serial_data = control;
1da177e4
LT		 2686
2687 /* Allocate the soft structure */
2688 soft = kmalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2689 if (!soft) {
2690 printk(KERN_WARNING
2691 "ioc4 (%p): unable to get memory for the soft struct\n",
22329b51 2692 (void *)idd->idd_pdev);
1da177e4
LT		 2693 ret = -ENOMEM;
2694 goto out3;
2695 }
2696 memset(soft, 0, sizeof(struct ioc4_soft));
2697
2698 spin_lock_init(&soft->is_ir_lock);
22329b51 2699 soft->is_ioc4_misc_addr = idd->idd_misc_regs;
1da177e4
LT		 2700 soft->is_ioc4_serial_addr = serial;
2701
2702 /* Init the IOC4 */
22329b51
BC		 2703 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT,
2704 &idd->idd_misc_regs->sio_cr.raw);
1da177e4
LT		 2705
2706 /* Enable serial port mode select generic PIO pins as outputs */
2707 writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2708 | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
22329b51 2709 &idd->idd_misc_regs->gpcr_s.raw);
1da177e4 2710
22329b51 2711 /* Clear and disable all serial interrupts */
1da177e4 2712 write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
22329b51
BC		 2713 writel(~0, &idd->idd_misc_regs->sio_ir.raw);
2714 write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC,
2715 IOC4_OTHER_INTR_TYPE);
2716 writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw);
1da177e4 2717 control->ic_soft = soft;
22329b51
BC		 2718
2719 /* Hook up interrupt handler */
2720 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, SA_SHIRQ,
1da177e4 2721 "sgi-ioc4serial", (void *)soft)) {
22329b51 2722 control->ic_irq = idd->idd_pdev->irq;
1da177e4
LT		 2723 } else {
2724 printk(KERN_WARNING
2725 "%s : request_irq fails for IRQ 0x%x\n ",
22329b51 2726 __FUNCTION__, idd->idd_pdev->irq);
1da177e4 2727 }
d4c477ca
BC		 2728 ret = ioc4_attach_local(idd);
2729 if (ret)
1da177e4
LT		 2730 goto out4;
2731
2732 /* register port with the serial core */
2733
22329b51 2734 if ((ret = ioc4_serial_core_attach(idd->idd_pdev)))
1da177e4
LT		 2735 goto out4;
2736
2737 return ret;
2738
2739 /* error exits that give back resources */
2740out4:
2741 kfree(soft);
2742out3:
2743 kfree(control);
2744out2:
2745 release_region(tmp_addr1, sizeof(struct ioc4_serial));
2746out1:
1da177e4
LT		 2747
2748 return ret;
2749}
2750
2751
2752/**
2753 * ioc4_serial_remove_one - detach function
2754 *
22329b51 2755 * @idd: IOC4 master module data for this IOC4
1da177e4
LT		 2756 */
2757
22329b51 2758int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
1da177e4
LT		 2759{
2760 int ii;
2761 struct ioc4_control *control;
2762 struct uart_port *the_port;
2763 struct ioc4_port *port;
2764 struct ioc4_soft *soft;
2765
22329b51 2766 control = idd->idd_serial_data;
1da177e4
LT		 2767
2768 for (ii = 0; ii < IOC4_NUM_SERIAL_PORTS; ii++) {
2769 the_port = &control->ic_port[ii].icp_uart_port;
2770 if (the_port) {
2771 uart_remove_one_port(&ioc4_uart, the_port);
2772 }
2773 port = control->ic_port[ii].icp_port;
2774 if (!(ii & 1) && port) {
2775 pci_free_consistent(port->ip_pdev,
2776 TOTAL_RING_BUF_SIZE,
2777 (void *)port->ip_cpu_ringbuf,
2778 port->ip_dma_ringbuf);
2779 kfree(port);
2780 }
2781 }
2782 soft = control->ic_soft;
2783 if (soft) {
2784 free_irq(control->ic_irq, (void *)soft);
2785 if (soft->is_ioc4_serial_addr) {
2786 release_region((unsigned long)
2787 soft->is_ioc4_serial_addr,
2788 sizeof(struct ioc4_serial));
2789 }
2790 kfree(soft);
2791 }
2792 kfree(control);
22329b51
BC		 2793 idd->idd_serial_data = NULL;
2794
2795 return 0;
1da177e4 2796}
22329b51
BC		 2797
2798static struct ioc4_submodule ioc4_serial_submodule = {
2799 .is_name = "IOC4_serial",
2800 .is_owner = THIS_MODULE,
2801 .is_probe = ioc4_serial_attach_one,
2802 .is_remove = ioc4_serial_remove_one,
2803};
1da177e4
LT		 2804
2805/**
2806 * ioc4_serial_init - module init
2807 */
2808int ioc4_serial_init(void)
2809{
2810 int ret;
2811
2812 /* register with serial core */
2813 if ((ret = uart_register_driver(&ioc4_uart)) < 0) {
2814 printk(KERN_WARNING
2815 "%s: Couldn't register IOC4 serial driver\n",
2816 __FUNCTION__);
2817 return ret;
2818 }
22329b51
BC		 2819
2820 /* register with IOC4 main module */
2821 return ioc4_register_submodule(&ioc4_serial_submodule);
1da177e4
LT		 2822}
2823
22329b51
BC		 2824static void __devexit ioc4_serial_exit(void)
2825{
2826 ioc4_unregister_submodule(&ioc4_serial_submodule);
2827 uart_unregister_driver(&ioc4_uart);
2828}
2829
2830module_init(ioc4_serial_init);
2831module_exit(ioc4_serial_exit);
2832
1da177e4
LT		 2833MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2834MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2835MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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