Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Driver for Zilog serial chips found on SGI workstations and | |
3 | * servers. This driver could actually be made more generic. | |
4 | * | |
5 | * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the | |
6 | * old drivers/sgi/char/sgiserial.c code which itself is based of the original | |
7 | * drivers/sbus/char/zs.c code. A lot of code has been simply moved over | |
8 | * directly from there but much has been rewritten. Credits therefore go out | |
9 | * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell | |
10 | * for their work there. | |
11 | * | |
12 | * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org) | |
13 | * Copyright (C) 2002 David S. Miller (davem@redhat.com) | |
14 | */ | |
15 | #include <linux/config.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/tty_flip.h> | |
23 | #include <linux/major.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/circ_buf.h> | |
29 | #include <linux/serial.h> | |
30 | #include <linux/sysrq.h> | |
31 | #include <linux/console.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <linux/init.h> | |
34 | ||
35 | #include <asm/io.h> | |
36 | #include <asm/irq.h> | |
37 | #include <asm/sgialib.h> | |
38 | #include <asm/sgi/ioc.h> | |
39 | #include <asm/sgi/hpc3.h> | |
40 | #include <asm/sgi/ip22.h> | |
41 | ||
42 | #if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
43 | #define SUPPORT_SYSRQ | |
44 | #endif | |
45 | ||
46 | #include <linux/serial_core.h> | |
47 | ||
48 | #include "ip22zilog.h" | |
49 | ||
50 | void ip22_do_break(void); | |
51 | ||
52 | /* | |
53 | * On IP22 we need to delay after register accesses but we do not need to | |
54 | * flush writes. | |
55 | */ | |
56 | #define ZSDELAY() udelay(5) | |
57 | #define ZSDELAY_LONG() udelay(20) | |
58 | #define ZS_WSYNC(channel) do { } while (0) | |
59 | ||
60 | #define NUM_IP22ZILOG 1 | |
61 | #define NUM_CHANNELS (NUM_IP22ZILOG * 2) | |
62 | ||
63 | #define ZS_CLOCK 3672000 /* Zilog input clock rate. */ | |
64 | #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */ | |
65 | ||
66 | /* | |
67 | * We wrap our port structure around the generic uart_port. | |
68 | */ | |
69 | struct uart_ip22zilog_port { | |
70 | struct uart_port port; | |
71 | ||
72 | /* IRQ servicing chain. */ | |
73 | struct uart_ip22zilog_port *next; | |
74 | ||
75 | /* Current values of Zilog write registers. */ | |
76 | unsigned char curregs[NUM_ZSREGS]; | |
77 | ||
78 | unsigned int flags; | |
79 | #define IP22ZILOG_FLAG_IS_CONS 0x00000004 | |
80 | #define IP22ZILOG_FLAG_IS_KGDB 0x00000008 | |
81 | #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010 | |
82 | #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020 | |
83 | #define IP22ZILOG_FLAG_REGS_HELD 0x00000040 | |
84 | #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080 | |
85 | #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100 | |
86 | ||
87 | unsigned int cflag; | |
88 | ||
89 | /* L1-A keyboard break state. */ | |
90 | int kbd_id; | |
91 | int l1_down; | |
92 | ||
93 | unsigned char parity_mask; | |
94 | unsigned char prev_status; | |
95 | }; | |
96 | ||
97 | #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase)) | |
98 | #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT)) | |
99 | #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \ | |
100 | (UART_ZILOG(PORT)->curregs[REGNUM]) | |
101 | #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \ | |
102 | ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL)) | |
103 | #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS) | |
104 | #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB) | |
105 | #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS) | |
106 | #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A) | |
107 | #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD) | |
108 | #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED) | |
109 | #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE) | |
110 | ||
111 | /* Reading and writing Zilog8530 registers. The delays are to make this | |
112 | * driver work on the IP22 which needs a settling delay after each chip | |
113 | * register access, other machines handle this in hardware via auxiliary | |
114 | * flip-flops which implement the settle time we do in software. | |
115 | * | |
116 | * The port lock must be held and local IRQs must be disabled | |
117 | * when {read,write}_zsreg is invoked. | |
118 | */ | |
119 | static unsigned char read_zsreg(struct zilog_channel *channel, | |
120 | unsigned char reg) | |
121 | { | |
122 | unsigned char retval; | |
123 | ||
124 | writeb(reg, &channel->control); | |
125 | ZSDELAY(); | |
126 | retval = readb(&channel->control); | |
127 | ZSDELAY(); | |
128 | ||
129 | return retval; | |
130 | } | |
131 | ||
132 | static void write_zsreg(struct zilog_channel *channel, | |
133 | unsigned char reg, unsigned char value) | |
134 | { | |
135 | writeb(reg, &channel->control); | |
136 | ZSDELAY(); | |
137 | writeb(value, &channel->control); | |
138 | ZSDELAY(); | |
139 | } | |
140 | ||
141 | static void ip22zilog_clear_fifo(struct zilog_channel *channel) | |
142 | { | |
143 | int i; | |
144 | ||
145 | for (i = 0; i < 32; i++) { | |
146 | unsigned char regval; | |
147 | ||
148 | regval = readb(&channel->control); | |
149 | ZSDELAY(); | |
150 | if (regval & Rx_CH_AV) | |
151 | break; | |
152 | ||
153 | regval = read_zsreg(channel, R1); | |
154 | readb(&channel->data); | |
155 | ZSDELAY(); | |
156 | ||
157 | if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { | |
158 | writeb(ERR_RES, &channel->control); | |
159 | ZSDELAY(); | |
160 | ZS_WSYNC(channel); | |
161 | } | |
162 | } | |
163 | } | |
164 | ||
165 | /* This function must only be called when the TX is not busy. The UART | |
166 | * port lock must be held and local interrupts disabled. | |
167 | */ | |
168 | static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs) | |
169 | { | |
170 | int i; | |
171 | ||
172 | /* Let pending transmits finish. */ | |
173 | for (i = 0; i < 1000; i++) { | |
174 | unsigned char stat = read_zsreg(channel, R1); | |
175 | if (stat & ALL_SNT) | |
176 | break; | |
177 | udelay(100); | |
178 | } | |
179 | ||
180 | writeb(ERR_RES, &channel->control); | |
181 | ZSDELAY(); | |
182 | ZS_WSYNC(channel); | |
183 | ||
184 | ip22zilog_clear_fifo(channel); | |
185 | ||
186 | /* Disable all interrupts. */ | |
187 | write_zsreg(channel, R1, | |
188 | regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); | |
189 | ||
190 | /* Set parity, sync config, stop bits, and clock divisor. */ | |
191 | write_zsreg(channel, R4, regs[R4]); | |
192 | ||
193 | /* Set misc. TX/RX control bits. */ | |
194 | write_zsreg(channel, R10, regs[R10]); | |
195 | ||
196 | /* Set TX/RX controls sans the enable bits. */ | |
197 | write_zsreg(channel, R3, regs[R3] & ~RxENAB); | |
198 | write_zsreg(channel, R5, regs[R5] & ~TxENAB); | |
199 | ||
200 | /* Synchronous mode config. */ | |
201 | write_zsreg(channel, R6, regs[R6]); | |
202 | write_zsreg(channel, R7, regs[R7]); | |
203 | ||
204 | /* Don't mess with the interrupt vector (R2, unused by us) and | |
205 | * master interrupt control (R9). We make sure this is setup | |
206 | * properly at probe time then never touch it again. | |
207 | */ | |
208 | ||
209 | /* Disable baud generator. */ | |
210 | write_zsreg(channel, R14, regs[R14] & ~BRENAB); | |
211 | ||
212 | /* Clock mode control. */ | |
213 | write_zsreg(channel, R11, regs[R11]); | |
214 | ||
215 | /* Lower and upper byte of baud rate generator divisor. */ | |
216 | write_zsreg(channel, R12, regs[R12]); | |
217 | write_zsreg(channel, R13, regs[R13]); | |
7369a8b3 | 218 | |
1da177e4 LT |
219 | /* Now rewrite R14, with BRENAB (if set). */ |
220 | write_zsreg(channel, R14, regs[R14]); | |
221 | ||
222 | /* External status interrupt control. */ | |
223 | write_zsreg(channel, R15, regs[R15]); | |
224 | ||
225 | /* Reset external status interrupts. */ | |
226 | write_zsreg(channel, R0, RES_EXT_INT); | |
227 | write_zsreg(channel, R0, RES_EXT_INT); | |
228 | ||
229 | /* Rewrite R3/R5, this time without enables masked. */ | |
230 | write_zsreg(channel, R3, regs[R3]); | |
231 | write_zsreg(channel, R5, regs[R5]); | |
232 | ||
233 | /* Rewrite R1, this time without IRQ enabled masked. */ | |
234 | write_zsreg(channel, R1, regs[R1]); | |
235 | } | |
236 | ||
237 | /* Reprogram the Zilog channel HW registers with the copies found in the | |
238 | * software state struct. If the transmitter is busy, we defer this update | |
239 | * until the next TX complete interrupt. Else, we do it right now. | |
240 | * | |
241 | * The UART port lock must be held and local interrupts disabled. | |
242 | */ | |
243 | static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up, | |
244 | struct zilog_channel *channel) | |
245 | { | |
246 | if (!ZS_REGS_HELD(up)) { | |
247 | if (ZS_TX_ACTIVE(up)) { | |
248 | up->flags |= IP22ZILOG_FLAG_REGS_HELD; | |
249 | } else { | |
250 | __load_zsregs(channel, up->curregs); | |
251 | } | |
252 | } | |
253 | } | |
254 | ||
255 | static void ip22zilog_receive_chars(struct uart_ip22zilog_port *up, | |
256 | struct zilog_channel *channel, | |
257 | struct pt_regs *regs) | |
258 | { | |
259 | struct tty_struct *tty = up->port.info->tty; /* XXX info==NULL? */ | |
260 | ||
261 | while (1) { | |
33f0f88f | 262 | unsigned char ch, r1, flag; |
1da177e4 LT |
263 | |
264 | r1 = read_zsreg(channel, R1); | |
265 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { | |
266 | writeb(ERR_RES, &channel->control); | |
267 | ZSDELAY(); | |
268 | ZS_WSYNC(channel); | |
269 | } | |
270 | ||
271 | ch = readb(&channel->control); | |
272 | ZSDELAY(); | |
273 | ||
274 | /* This funny hack depends upon BRK_ABRT not interfering | |
275 | * with the other bits we care about in R1. | |
276 | */ | |
277 | if (ch & BRK_ABRT) | |
278 | r1 |= BRK_ABRT; | |
279 | ||
280 | ch = readb(&channel->data); | |
281 | ZSDELAY(); | |
282 | ||
283 | ch &= up->parity_mask; | |
284 | ||
285 | if (ZS_IS_CONS(up) && (r1 & BRK_ABRT)) { | |
286 | /* Wait for BREAK to deassert to avoid potentially | |
287 | * confusing the PROM. | |
288 | */ | |
289 | while (1) { | |
290 | ch = readb(&channel->control); | |
291 | ZSDELAY(); | |
292 | if (!(ch & BRK_ABRT)) | |
293 | break; | |
294 | } | |
295 | ip22_do_break(); | |
296 | return; | |
297 | } | |
298 | ||
299 | /* A real serial line, record the character and status. */ | |
33f0f88f | 300 | flag = TTY_NORMAL; |
1da177e4 LT |
301 | up->port.icount.rx++; |
302 | if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) { | |
303 | if (r1 & BRK_ABRT) { | |
304 | r1 &= ~(PAR_ERR | CRC_ERR); | |
305 | up->port.icount.brk++; | |
306 | if (uart_handle_break(&up->port)) | |
307 | goto next_char; | |
308 | } | |
309 | else if (r1 & PAR_ERR) | |
310 | up->port.icount.parity++; | |
311 | else if (r1 & CRC_ERR) | |
312 | up->port.icount.frame++; | |
313 | if (r1 & Rx_OVR) | |
314 | up->port.icount.overrun++; | |
315 | r1 &= up->port.read_status_mask; | |
316 | if (r1 & BRK_ABRT) | |
33f0f88f | 317 | flag = TTY_BREAK; |
1da177e4 | 318 | else if (r1 & PAR_ERR) |
33f0f88f | 319 | flag = TTY_PARITY; |
1da177e4 | 320 | else if (r1 & CRC_ERR) |
33f0f88f | 321 | flag = TTY_FRAME; |
1da177e4 LT |
322 | } |
323 | if (uart_handle_sysrq_char(&up->port, ch, regs)) | |
324 | goto next_char; | |
325 | ||
326 | if (up->port.ignore_status_mask == 0xff || | |
33f0f88f AC |
327 | (r1 & up->port.ignore_status_mask) == 0) |
328 | tty_insert_flip_char(tty, ch, flag); | |
329 | ||
330 | if (r1 & Rx_OVR) | |
331 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
1da177e4 LT |
332 | next_char: |
333 | ch = readb(&channel->control); | |
334 | ZSDELAY(); | |
335 | if (!(ch & Rx_CH_AV)) | |
336 | break; | |
337 | } | |
338 | ||
339 | tty_flip_buffer_push(tty); | |
340 | } | |
341 | ||
342 | static void ip22zilog_status_handle(struct uart_ip22zilog_port *up, | |
343 | struct zilog_channel *channel, | |
344 | struct pt_regs *regs) | |
345 | { | |
346 | unsigned char status; | |
347 | ||
348 | status = readb(&channel->control); | |
349 | ZSDELAY(); | |
350 | ||
351 | writeb(RES_EXT_INT, &channel->control); | |
352 | ZSDELAY(); | |
353 | ZS_WSYNC(channel); | |
354 | ||
355 | if (ZS_WANTS_MODEM_STATUS(up)) { | |
356 | if (status & SYNC) | |
357 | up->port.icount.dsr++; | |
358 | ||
359 | /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. | |
360 | * But it does not tell us which bit has changed, we have to keep | |
361 | * track of this ourselves. | |
362 | */ | |
363 | if ((status & DCD) ^ up->prev_status) | |
364 | uart_handle_dcd_change(&up->port, | |
365 | (status & DCD)); | |
366 | if ((status & CTS) ^ up->prev_status) | |
367 | uart_handle_cts_change(&up->port, | |
368 | (status & CTS)); | |
369 | ||
370 | wake_up_interruptible(&up->port.info->delta_msr_wait); | |
371 | } | |
372 | ||
373 | up->prev_status = status; | |
374 | } | |
375 | ||
376 | static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up, | |
377 | struct zilog_channel *channel) | |
378 | { | |
379 | struct circ_buf *xmit; | |
380 | ||
381 | if (ZS_IS_CONS(up)) { | |
382 | unsigned char status = readb(&channel->control); | |
383 | ZSDELAY(); | |
384 | ||
385 | /* TX still busy? Just wait for the next TX done interrupt. | |
386 | * | |
387 | * It can occur because of how we do serial console writes. It would | |
388 | * be nice to transmit console writes just like we normally would for | |
389 | * a TTY line. (ie. buffered and TX interrupt driven). That is not | |
390 | * easy because console writes cannot sleep. One solution might be | |
391 | * to poll on enough port->xmit space becomming free. -DaveM | |
392 | */ | |
393 | if (!(status & Tx_BUF_EMP)) | |
394 | return; | |
395 | } | |
396 | ||
397 | up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE; | |
398 | ||
399 | if (ZS_REGS_HELD(up)) { | |
400 | __load_zsregs(channel, up->curregs); | |
401 | up->flags &= ~IP22ZILOG_FLAG_REGS_HELD; | |
402 | } | |
403 | ||
404 | if (ZS_TX_STOPPED(up)) { | |
405 | up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; | |
406 | goto ack_tx_int; | |
407 | } | |
408 | ||
409 | if (up->port.x_char) { | |
410 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; | |
411 | writeb(up->port.x_char, &channel->data); | |
412 | ZSDELAY(); | |
413 | ZS_WSYNC(channel); | |
414 | ||
415 | up->port.icount.tx++; | |
416 | up->port.x_char = 0; | |
417 | return; | |
418 | } | |
419 | ||
420 | if (up->port.info == NULL) | |
421 | goto ack_tx_int; | |
422 | xmit = &up->port.info->xmit; | |
c4432c41 | 423 | if (uart_circ_empty(xmit)) |
1da177e4 | 424 | goto ack_tx_int; |
1da177e4 LT |
425 | if (uart_tx_stopped(&up->port)) |
426 | goto ack_tx_int; | |
427 | ||
428 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; | |
429 | writeb(xmit->buf[xmit->tail], &channel->data); | |
430 | ZSDELAY(); | |
431 | ZS_WSYNC(channel); | |
432 | ||
433 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
434 | up->port.icount.tx++; | |
435 | ||
436 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
437 | uart_write_wakeup(&up->port); | |
438 | ||
439 | return; | |
440 | ||
441 | ack_tx_int: | |
442 | writeb(RES_Tx_P, &channel->control); | |
443 | ZSDELAY(); | |
444 | ZS_WSYNC(channel); | |
445 | } | |
446 | ||
447 | static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
448 | { | |
449 | struct uart_ip22zilog_port *up = dev_id; | |
450 | ||
451 | while (up) { | |
452 | struct zilog_channel *channel | |
453 | = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
454 | unsigned char r3; | |
455 | ||
456 | spin_lock(&up->port.lock); | |
457 | r3 = read_zsreg(channel, R3); | |
458 | ||
459 | /* Channel A */ | |
460 | if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { | |
461 | writeb(RES_H_IUS, &channel->control); | |
462 | ZSDELAY(); | |
463 | ZS_WSYNC(channel); | |
464 | ||
465 | if (r3 & CHARxIP) | |
466 | ip22zilog_receive_chars(up, channel, regs); | |
467 | if (r3 & CHAEXT) | |
468 | ip22zilog_status_handle(up, channel, regs); | |
469 | if (r3 & CHATxIP) | |
470 | ip22zilog_transmit_chars(up, channel); | |
471 | } | |
472 | spin_unlock(&up->port.lock); | |
473 | ||
474 | /* Channel B */ | |
475 | up = up->next; | |
476 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
477 | ||
478 | spin_lock(&up->port.lock); | |
479 | if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { | |
480 | writeb(RES_H_IUS, &channel->control); | |
481 | ZSDELAY(); | |
482 | ZS_WSYNC(channel); | |
483 | ||
484 | if (r3 & CHBRxIP) | |
485 | ip22zilog_receive_chars(up, channel, regs); | |
486 | if (r3 & CHBEXT) | |
487 | ip22zilog_status_handle(up, channel, regs); | |
488 | if (r3 & CHBTxIP) | |
489 | ip22zilog_transmit_chars(up, channel); | |
490 | } | |
491 | spin_unlock(&up->port.lock); | |
492 | ||
493 | up = up->next; | |
494 | } | |
495 | ||
496 | return IRQ_HANDLED; | |
497 | } | |
498 | ||
499 | /* A convenient way to quickly get R0 status. The caller must _not_ hold the | |
500 | * port lock, it is acquired here. | |
501 | */ | |
502 | static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port) | |
503 | { | |
504 | struct zilog_channel *channel; | |
1da177e4 LT |
505 | unsigned char status; |
506 | ||
1da177e4 LT |
507 | channel = ZILOG_CHANNEL_FROM_PORT(port); |
508 | status = readb(&channel->control); | |
509 | ZSDELAY(); | |
510 | ||
1da177e4 LT |
511 | return status; |
512 | } | |
513 | ||
514 | /* The port lock is not held. */ | |
515 | static unsigned int ip22zilog_tx_empty(struct uart_port *port) | |
516 | { | |
c5f4644e | 517 | unsigned long flags; |
1da177e4 LT |
518 | unsigned char status; |
519 | unsigned int ret; | |
520 | ||
c5f4644e RK |
521 | spin_lock_irqsave(&port->lock, flags); |
522 | ||
1da177e4 | 523 | status = ip22zilog_read_channel_status(port); |
c5f4644e RK |
524 | |
525 | spin_unlock_irqrestore(&port->lock, flags); | |
526 | ||
1da177e4 LT |
527 | if (status & Tx_BUF_EMP) |
528 | ret = TIOCSER_TEMT; | |
529 | else | |
530 | ret = 0; | |
531 | ||
532 | return ret; | |
533 | } | |
534 | ||
c5f4644e | 535 | /* The port lock is held and interrupts are disabled. */ |
1da177e4 LT |
536 | static unsigned int ip22zilog_get_mctrl(struct uart_port *port) |
537 | { | |
538 | unsigned char status; | |
539 | unsigned int ret; | |
540 | ||
541 | status = ip22zilog_read_channel_status(port); | |
542 | ||
543 | ret = 0; | |
544 | if (status & DCD) | |
545 | ret |= TIOCM_CAR; | |
546 | if (status & SYNC) | |
547 | ret |= TIOCM_DSR; | |
548 | if (status & CTS) | |
549 | ret |= TIOCM_CTS; | |
550 | ||
551 | return ret; | |
552 | } | |
553 | ||
554 | /* The port lock is held and interrupts are disabled. */ | |
555 | static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
556 | { | |
557 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
558 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
559 | unsigned char set_bits, clear_bits; | |
560 | ||
561 | set_bits = clear_bits = 0; | |
562 | ||
563 | if (mctrl & TIOCM_RTS) | |
564 | set_bits |= RTS; | |
565 | else | |
566 | clear_bits |= RTS; | |
567 | if (mctrl & TIOCM_DTR) | |
568 | set_bits |= DTR; | |
569 | else | |
570 | clear_bits |= DTR; | |
571 | ||
7369a8b3 | 572 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
573 | up->curregs[R5] |= set_bits; |
574 | up->curregs[R5] &= ~clear_bits; | |
575 | write_zsreg(channel, R5, up->curregs[R5]); | |
576 | } | |
577 | ||
578 | /* The port lock is held and interrupts are disabled. */ | |
b129a8cc | 579 | static void ip22zilog_stop_tx(struct uart_port *port) |
1da177e4 LT |
580 | { |
581 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
582 | ||
583 | up->flags |= IP22ZILOG_FLAG_TX_STOPPED; | |
584 | } | |
585 | ||
586 | /* The port lock is held and interrupts are disabled. */ | |
b129a8cc | 587 | static void ip22zilog_start_tx(struct uart_port *port) |
1da177e4 LT |
588 | { |
589 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
590 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
591 | unsigned char status; | |
592 | ||
593 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; | |
594 | up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; | |
595 | ||
596 | status = readb(&channel->control); | |
597 | ZSDELAY(); | |
598 | ||
599 | /* TX busy? Just wait for the TX done interrupt. */ | |
600 | if (!(status & Tx_BUF_EMP)) | |
601 | return; | |
602 | ||
603 | /* Send the first character to jump-start the TX done | |
604 | * IRQ sending engine. | |
605 | */ | |
606 | if (port->x_char) { | |
607 | writeb(port->x_char, &channel->data); | |
608 | ZSDELAY(); | |
609 | ZS_WSYNC(channel); | |
610 | ||
611 | port->icount.tx++; | |
612 | port->x_char = 0; | |
613 | } else { | |
614 | struct circ_buf *xmit = &port->info->xmit; | |
615 | ||
616 | writeb(xmit->buf[xmit->tail], &channel->data); | |
617 | ZSDELAY(); | |
618 | ZS_WSYNC(channel); | |
619 | ||
620 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
621 | port->icount.tx++; | |
622 | ||
623 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
624 | uart_write_wakeup(&up->port); | |
625 | } | |
626 | } | |
627 | ||
628 | /* The port lock is held and interrupts are disabled. */ | |
629 | static void ip22zilog_stop_rx(struct uart_port *port) | |
630 | { | |
631 | struct uart_ip22zilog_port *up = UART_ZILOG(port); | |
632 | struct zilog_channel *channel; | |
633 | ||
634 | if (ZS_IS_CONS(up)) | |
635 | return; | |
636 | ||
637 | channel = ZILOG_CHANNEL_FROM_PORT(port); | |
638 | ||
639 | /* Disable all RX interrupts. */ | |
640 | up->curregs[R1] &= ~RxINT_MASK; | |
641 | ip22zilog_maybe_update_regs(up, channel); | |
642 | } | |
643 | ||
644 | /* The port lock is held. */ | |
645 | static void ip22zilog_enable_ms(struct uart_port *port) | |
646 | { | |
647 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
648 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
649 | unsigned char new_reg; | |
650 | ||
651 | new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE); | |
652 | if (new_reg != up->curregs[R15]) { | |
653 | up->curregs[R15] = new_reg; | |
654 | ||
7369a8b3 | 655 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
656 | write_zsreg(channel, R15, up->curregs[R15]); |
657 | } | |
658 | } | |
659 | ||
660 | /* The port lock is not held. */ | |
661 | static void ip22zilog_break_ctl(struct uart_port *port, int break_state) | |
662 | { | |
663 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
664 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
665 | unsigned char set_bits, clear_bits, new_reg; | |
666 | unsigned long flags; | |
667 | ||
668 | set_bits = clear_bits = 0; | |
669 | ||
670 | if (break_state) | |
671 | set_bits |= SND_BRK; | |
672 | else | |
673 | clear_bits |= SND_BRK; | |
674 | ||
675 | spin_lock_irqsave(&port->lock, flags); | |
676 | ||
677 | new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; | |
678 | if (new_reg != up->curregs[R5]) { | |
679 | up->curregs[R5] = new_reg; | |
680 | ||
7369a8b3 | 681 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
682 | write_zsreg(channel, R5, up->curregs[R5]); |
683 | } | |
684 | ||
685 | spin_unlock_irqrestore(&port->lock, flags); | |
686 | } | |
687 | ||
688 | static void __ip22zilog_startup(struct uart_ip22zilog_port *up) | |
689 | { | |
690 | struct zilog_channel *channel; | |
691 | ||
692 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
693 | up->prev_status = readb(&channel->control); | |
694 | ||
695 | /* Enable receiver and transmitter. */ | |
696 | up->curregs[R3] |= RxENAB; | |
697 | up->curregs[R5] |= TxENAB; | |
698 | ||
699 | up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; | |
700 | ip22zilog_maybe_update_regs(up, channel); | |
701 | } | |
702 | ||
703 | static int ip22zilog_startup(struct uart_port *port) | |
704 | { | |
705 | struct uart_ip22zilog_port *up = UART_ZILOG(port); | |
706 | unsigned long flags; | |
707 | ||
708 | if (ZS_IS_CONS(up)) | |
709 | return 0; | |
710 | ||
711 | spin_lock_irqsave(&port->lock, flags); | |
712 | __ip22zilog_startup(up); | |
713 | spin_unlock_irqrestore(&port->lock, flags); | |
714 | return 0; | |
715 | } | |
716 | ||
717 | /* | |
718 | * The test for ZS_IS_CONS is explained by the following e-mail: | |
719 | ***** | |
720 | * From: Russell King <rmk@arm.linux.org.uk> | |
721 | * Date: Sun, 8 Dec 2002 10:18:38 +0000 | |
722 | * | |
723 | * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote: | |
724 | * > I boot my 2.5 boxes using "console=ttyS0,9600" argument, | |
725 | * > and I noticed that something is not right with reference | |
726 | * > counting in this case. It seems that when the console | |
727 | * > is open by kernel initially, this is not accounted | |
728 | * > as an open, and uart_startup is not called. | |
729 | * | |
730 | * That is correct. We are unable to call uart_startup when the serial | |
731 | * console is initialised because it may need to allocate memory (as | |
732 | * request_irq does) and the memory allocators may not have been | |
733 | * initialised. | |
734 | * | |
735 | * 1. initialise the port into a state where it can send characters in the | |
736 | * console write method. | |
737 | * | |
738 | * 2. don't do the actual hardware shutdown in your shutdown() method (but | |
739 | * do the normal software shutdown - ie, free irqs etc) | |
740 | ***** | |
741 | */ | |
742 | static void ip22zilog_shutdown(struct uart_port *port) | |
743 | { | |
744 | struct uart_ip22zilog_port *up = UART_ZILOG(port); | |
745 | struct zilog_channel *channel; | |
746 | unsigned long flags; | |
747 | ||
748 | if (ZS_IS_CONS(up)) | |
749 | return; | |
750 | ||
751 | spin_lock_irqsave(&port->lock, flags); | |
752 | ||
753 | channel = ZILOG_CHANNEL_FROM_PORT(port); | |
754 | ||
755 | /* Disable receiver and transmitter. */ | |
756 | up->curregs[R3] &= ~RxENAB; | |
757 | up->curregs[R5] &= ~TxENAB; | |
758 | ||
759 | /* Disable all interrupts and BRK assertion. */ | |
760 | up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); | |
761 | up->curregs[R5] &= ~SND_BRK; | |
762 | ip22zilog_maybe_update_regs(up, channel); | |
763 | ||
764 | spin_unlock_irqrestore(&port->lock, flags); | |
765 | } | |
766 | ||
767 | /* Shared by TTY driver and serial console setup. The port lock is held | |
768 | * and local interrupts are disabled. | |
769 | */ | |
770 | static void | |
771 | ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag, | |
772 | unsigned int iflag, int brg) | |
773 | { | |
774 | ||
775 | up->curregs[R10] = NRZ; | |
776 | up->curregs[R11] = TCBR | RCBR; | |
777 | ||
778 | /* Program BAUD and clock source. */ | |
779 | up->curregs[R4] &= ~XCLK_MASK; | |
780 | up->curregs[R4] |= X16CLK; | |
781 | up->curregs[R12] = brg & 0xff; | |
782 | up->curregs[R13] = (brg >> 8) & 0xff; | |
783 | up->curregs[R14] = BRENAB; | |
784 | ||
785 | /* Character size, stop bits, and parity. */ | |
786 | up->curregs[3] &= ~RxN_MASK; | |
787 | up->curregs[5] &= ~TxN_MASK; | |
788 | switch (cflag & CSIZE) { | |
789 | case CS5: | |
790 | up->curregs[3] |= Rx5; | |
791 | up->curregs[5] |= Tx5; | |
792 | up->parity_mask = 0x1f; | |
793 | break; | |
794 | case CS6: | |
795 | up->curregs[3] |= Rx6; | |
796 | up->curregs[5] |= Tx6; | |
797 | up->parity_mask = 0x3f; | |
798 | break; | |
799 | case CS7: | |
800 | up->curregs[3] |= Rx7; | |
801 | up->curregs[5] |= Tx7; | |
802 | up->parity_mask = 0x7f; | |
803 | break; | |
804 | case CS8: | |
805 | default: | |
806 | up->curregs[3] |= Rx8; | |
807 | up->curregs[5] |= Tx8; | |
808 | up->parity_mask = 0xff; | |
809 | break; | |
810 | }; | |
811 | up->curregs[4] &= ~0x0c; | |
812 | if (cflag & CSTOPB) | |
813 | up->curregs[4] |= SB2; | |
814 | else | |
815 | up->curregs[4] |= SB1; | |
816 | if (cflag & PARENB) | |
817 | up->curregs[4] |= PAR_ENAB; | |
818 | else | |
819 | up->curregs[4] &= ~PAR_ENAB; | |
820 | if (!(cflag & PARODD)) | |
821 | up->curregs[4] |= PAR_EVEN; | |
822 | else | |
823 | up->curregs[4] &= ~PAR_EVEN; | |
824 | ||
825 | up->port.read_status_mask = Rx_OVR; | |
826 | if (iflag & INPCK) | |
827 | up->port.read_status_mask |= CRC_ERR | PAR_ERR; | |
828 | if (iflag & (BRKINT | PARMRK)) | |
829 | up->port.read_status_mask |= BRK_ABRT; | |
830 | ||
831 | up->port.ignore_status_mask = 0; | |
832 | if (iflag & IGNPAR) | |
833 | up->port.ignore_status_mask |= CRC_ERR | PAR_ERR; | |
834 | if (iflag & IGNBRK) { | |
835 | up->port.ignore_status_mask |= BRK_ABRT; | |
836 | if (iflag & IGNPAR) | |
837 | up->port.ignore_status_mask |= Rx_OVR; | |
838 | } | |
839 | ||
840 | if ((cflag & CREAD) == 0) | |
841 | up->port.ignore_status_mask = 0xff; | |
842 | } | |
843 | ||
844 | /* The port lock is not held. */ | |
845 | static void | |
846 | ip22zilog_set_termios(struct uart_port *port, struct termios *termios, | |
847 | struct termios *old) | |
848 | { | |
849 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
850 | unsigned long flags; | |
851 | int baud, brg; | |
852 | ||
853 | baud = uart_get_baud_rate(port, termios, old, 1200, 76800); | |
854 | ||
855 | spin_lock_irqsave(&up->port.lock, flags); | |
856 | ||
857 | brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); | |
858 | ||
859 | ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg); | |
860 | ||
861 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
862 | up->flags |= IP22ZILOG_FLAG_MODEM_STATUS; | |
863 | else | |
864 | up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS; | |
865 | ||
866 | up->cflag = termios->c_cflag; | |
867 | ||
868 | ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); | |
869 | ||
870 | spin_unlock_irqrestore(&up->port.lock, flags); | |
871 | } | |
872 | ||
873 | static const char *ip22zilog_type(struct uart_port *port) | |
874 | { | |
875 | return "IP22-Zilog"; | |
876 | } | |
877 | ||
878 | /* We do not request/release mappings of the registers here, this | |
879 | * happens at early serial probe time. | |
880 | */ | |
881 | static void ip22zilog_release_port(struct uart_port *port) | |
882 | { | |
883 | } | |
884 | ||
885 | static int ip22zilog_request_port(struct uart_port *port) | |
886 | { | |
887 | return 0; | |
888 | } | |
889 | ||
890 | /* These do not need to do anything interesting either. */ | |
891 | static void ip22zilog_config_port(struct uart_port *port, int flags) | |
892 | { | |
893 | } | |
894 | ||
895 | /* We do not support letting the user mess with the divisor, IRQ, etc. */ | |
896 | static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser) | |
897 | { | |
898 | return -EINVAL; | |
899 | } | |
900 | ||
901 | static struct uart_ops ip22zilog_pops = { | |
902 | .tx_empty = ip22zilog_tx_empty, | |
903 | .set_mctrl = ip22zilog_set_mctrl, | |
904 | .get_mctrl = ip22zilog_get_mctrl, | |
905 | .stop_tx = ip22zilog_stop_tx, | |
906 | .start_tx = ip22zilog_start_tx, | |
907 | .stop_rx = ip22zilog_stop_rx, | |
908 | .enable_ms = ip22zilog_enable_ms, | |
909 | .break_ctl = ip22zilog_break_ctl, | |
910 | .startup = ip22zilog_startup, | |
911 | .shutdown = ip22zilog_shutdown, | |
912 | .set_termios = ip22zilog_set_termios, | |
913 | .type = ip22zilog_type, | |
914 | .release_port = ip22zilog_release_port, | |
915 | .request_port = ip22zilog_request_port, | |
916 | .config_port = ip22zilog_config_port, | |
917 | .verify_port = ip22zilog_verify_port, | |
918 | }; | |
919 | ||
920 | static struct uart_ip22zilog_port *ip22zilog_port_table; | |
921 | static struct zilog_layout **ip22zilog_chip_regs; | |
922 | ||
923 | static struct uart_ip22zilog_port *ip22zilog_irq_chain; | |
924 | static int zilog_irq = -1; | |
925 | ||
926 | static void * __init alloc_one_table(unsigned long size) | |
927 | { | |
928 | void *ret; | |
929 | ||
930 | ret = kmalloc(size, GFP_KERNEL); | |
931 | if (ret != NULL) | |
932 | memset(ret, 0, size); | |
933 | ||
934 | return ret; | |
935 | } | |
936 | ||
937 | static void __init ip22zilog_alloc_tables(void) | |
938 | { | |
939 | ip22zilog_port_table = (struct uart_ip22zilog_port *) | |
940 | alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port)); | |
941 | ip22zilog_chip_regs = (struct zilog_layout **) | |
942 | alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *)); | |
943 | ||
944 | if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) { | |
945 | panic("IP22-Zilog: Cannot allocate IP22-Zilog tables."); | |
946 | } | |
947 | } | |
948 | ||
949 | /* Get the address of the registers for IP22-Zilog instance CHIP. */ | |
950 | static struct zilog_layout * __init get_zs(int chip) | |
951 | { | |
952 | unsigned long base; | |
953 | ||
954 | if (chip < 0 || chip >= NUM_IP22ZILOG) { | |
955 | panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip); | |
956 | } | |
957 | ||
958 | /* Not probe-able, hard code it. */ | |
959 | base = (unsigned long) &sgioc->uart; | |
960 | ||
961 | zilog_irq = SGI_SERIAL_IRQ; | |
962 | request_mem_region(base, 8, "IP22-Zilog"); | |
963 | ||
964 | return (struct zilog_layout *) base; | |
965 | } | |
966 | ||
967 | #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */ | |
968 | ||
969 | #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE | |
d358788f | 970 | static void ip22zilog_put_char(struct uart_port *port, int ch) |
1da177e4 | 971 | { |
d358788f | 972 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
1da177e4 LT |
973 | int loops = ZS_PUT_CHAR_MAX_DELAY; |
974 | ||
975 | /* This is a timed polling loop so do not switch the explicit | |
976 | * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM | |
977 | */ | |
978 | do { | |
979 | unsigned char val = readb(&channel->control); | |
980 | if (val & Tx_BUF_EMP) { | |
981 | ZSDELAY(); | |
982 | break; | |
983 | } | |
984 | udelay(5); | |
985 | } while (--loops); | |
986 | ||
987 | writeb(ch, &channel->data); | |
988 | ZSDELAY(); | |
989 | ZS_WSYNC(channel); | |
990 | } | |
991 | ||
992 | static void | |
993 | ip22zilog_console_write(struct console *con, const char *s, unsigned int count) | |
994 | { | |
995 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; | |
1da177e4 | 996 | unsigned long flags; |
1da177e4 LT |
997 | |
998 | spin_lock_irqsave(&up->port.lock, flags); | |
d358788f | 999 | uart_console_write(&up->port, s, count, ip22zilog_put_char); |
1da177e4 LT |
1000 | udelay(2); |
1001 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1002 | } | |
1003 | ||
1004 | void | |
1005 | ip22serial_console_termios(struct console *con, char *options) | |
1006 | { | |
1007 | int baud = 9600, bits = 8, cflag; | |
1008 | int parity = 'n'; | |
1009 | int flow = 'n'; | |
1010 | ||
1011 | if (options) | |
1012 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1013 | ||
1014 | cflag = CREAD | HUPCL | CLOCAL; | |
1015 | ||
1016 | switch (baud) { | |
1017 | case 150: cflag |= B150; break; | |
1018 | case 300: cflag |= B300; break; | |
1019 | case 600: cflag |= B600; break; | |
1020 | case 1200: cflag |= B1200; break; | |
1021 | case 2400: cflag |= B2400; break; | |
1022 | case 4800: cflag |= B4800; break; | |
1023 | case 9600: cflag |= B9600; break; | |
1024 | case 19200: cflag |= B19200; break; | |
1025 | case 38400: cflag |= B38400; break; | |
1026 | default: baud = 9600; cflag |= B9600; break; | |
1027 | } | |
1028 | ||
1029 | con->cflag = cflag | CS8; /* 8N1 */ | |
1030 | } | |
1031 | ||
1032 | static int __init ip22zilog_console_setup(struct console *con, char *options) | |
1033 | { | |
1034 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; | |
1035 | unsigned long flags; | |
1036 | int baud, brg; | |
1037 | ||
1038 | printk("Console: ttyS%d (IP22-Zilog)\n", con->index); | |
1039 | ||
1040 | /* Get firmware console settings. */ | |
1041 | ip22serial_console_termios(con, options); | |
1042 | ||
1043 | /* Firmware console speed is limited to 150-->38400 baud so | |
1044 | * this hackish cflag thing is OK. | |
1045 | */ | |
1046 | switch (con->cflag & CBAUD) { | |
1047 | case B150: baud = 150; break; | |
1048 | case B300: baud = 300; break; | |
1049 | case B600: baud = 600; break; | |
1050 | case B1200: baud = 1200; break; | |
1051 | case B2400: baud = 2400; break; | |
1052 | case B4800: baud = 4800; break; | |
1053 | default: case B9600: baud = 9600; break; | |
1054 | case B19200: baud = 19200; break; | |
1055 | case B38400: baud = 38400; break; | |
1056 | }; | |
1057 | ||
1058 | brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); | |
1059 | ||
1060 | spin_lock_irqsave(&up->port.lock, flags); | |
1061 | ||
1062 | up->curregs[R15] = BRKIE; | |
1063 | ip22zilog_convert_to_zs(up, con->cflag, 0, brg); | |
1064 | ||
1065 | __ip22zilog_startup(up); | |
1066 | ||
1067 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
1072 | static struct uart_driver ip22zilog_reg; | |
1073 | ||
1074 | static struct console ip22zilog_console = { | |
1075 | .name = "ttyS", | |
1076 | .write = ip22zilog_console_write, | |
1077 | .device = uart_console_device, | |
1078 | .setup = ip22zilog_console_setup, | |
1079 | .flags = CON_PRINTBUFFER, | |
1080 | .index = -1, | |
1081 | .data = &ip22zilog_reg, | |
1082 | }; | |
1083 | #endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */ | |
1084 | ||
1085 | static struct uart_driver ip22zilog_reg = { | |
1086 | .owner = THIS_MODULE, | |
1087 | .driver_name = "serial", | |
1088 | .devfs_name = "tts/", | |
1089 | .dev_name = "ttyS", | |
1090 | .major = TTY_MAJOR, | |
1091 | .minor = 64, | |
1092 | .nr = NUM_CHANNELS, | |
1093 | #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE | |
1094 | .cons = &ip22zilog_console, | |
1095 | #endif | |
1096 | }; | |
1097 | ||
1098 | static void __init ip22zilog_prepare(void) | |
1099 | { | |
1100 | struct uart_ip22zilog_port *up; | |
1101 | struct zilog_layout *rp; | |
1102 | int channel, chip; | |
1103 | ||
1104 | /* | |
1105 | * Temporary fix. | |
1106 | */ | |
1107 | for (channel = 0; channel < NUM_CHANNELS; channel++) | |
1108 | spin_lock_init(&ip22zilog_port_table[channel].port.lock); | |
1109 | ||
1110 | ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; | |
1111 | up = &ip22zilog_port_table[0]; | |
1112 | for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) | |
1113 | up[channel].next = &up[channel - 1]; | |
1114 | up[channel].next = NULL; | |
1115 | ||
1116 | for (chip = 0; chip < NUM_IP22ZILOG; chip++) { | |
1117 | if (!ip22zilog_chip_regs[chip]) { | |
1118 | ip22zilog_chip_regs[chip] = rp = get_zs(chip); | |
1119 | ||
1120 | up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; | |
1121 | up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; | |
1122 | ||
1123 | /* In theory mapbase is the physical address ... */ | |
1124 | up[(chip * 2) + 0].port.mapbase = | |
1125 | (unsigned long) ioremap((unsigned long) &rp->channelB, 8); | |
1126 | up[(chip * 2) + 1].port.mapbase = | |
1127 | (unsigned long) ioremap((unsigned long) &rp->channelA, 8); | |
1128 | } | |
1129 | ||
1130 | /* Channel A */ | |
1131 | up[(chip * 2) + 0].port.iotype = UPIO_MEM; | |
1132 | up[(chip * 2) + 0].port.irq = zilog_irq; | |
1133 | up[(chip * 2) + 0].port.uartclk = ZS_CLOCK; | |
1134 | up[(chip * 2) + 0].port.fifosize = 1; | |
1135 | up[(chip * 2) + 0].port.ops = &ip22zilog_pops; | |
1136 | up[(chip * 2) + 0].port.type = PORT_IP22ZILOG; | |
1137 | up[(chip * 2) + 0].port.flags = 0; | |
1138 | up[(chip * 2) + 0].port.line = (chip * 2) + 0; | |
1139 | up[(chip * 2) + 0].flags = 0; | |
1140 | ||
1141 | /* Channel B */ | |
1142 | up[(chip * 2) + 1].port.iotype = UPIO_MEM; | |
1143 | up[(chip * 2) + 1].port.irq = zilog_irq; | |
1144 | up[(chip * 2) + 1].port.uartclk = ZS_CLOCK; | |
1145 | up[(chip * 2) + 1].port.fifosize = 1; | |
1146 | up[(chip * 2) + 1].port.ops = &ip22zilog_pops; | |
1147 | up[(chip * 2) + 1].port.type = PORT_IP22ZILOG; | |
1148 | up[(chip * 2) + 1].port.flags |= IP22ZILOG_FLAG_IS_CHANNEL_A; | |
1149 | up[(chip * 2) + 1].port.line = (chip * 2) + 1; | |
1150 | up[(chip * 2) + 1].flags = 0; | |
1151 | } | |
1152 | } | |
1153 | ||
1154 | static void __init ip22zilog_init_hw(void) | |
1155 | { | |
1156 | int i; | |
1157 | ||
1158 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1159 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; | |
1160 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
1161 | unsigned long flags; | |
1162 | int baud, brg; | |
1163 | ||
1164 | spin_lock_irqsave(&up->port.lock, flags); | |
1165 | ||
1166 | if (ZS_IS_CHANNEL_A(up)) { | |
1167 | write_zsreg(channel, R9, FHWRES); | |
1168 | ZSDELAY_LONG(); | |
1169 | (void) read_zsreg(channel, R0); | |
1170 | } | |
1171 | ||
1172 | /* Normal serial TTY. */ | |
1173 | up->parity_mask = 0xff; | |
1174 | up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; | |
1175 | up->curregs[R4] = PAR_EVEN | X16CLK | SB1; | |
1176 | up->curregs[R3] = RxENAB | Rx8; | |
1177 | up->curregs[R5] = TxENAB | Tx8; | |
1178 | up->curregs[R9] = NV | MIE; | |
1179 | up->curregs[R10] = NRZ; | |
1180 | up->curregs[R11] = TCBR | RCBR; | |
1181 | baud = 9600; | |
1182 | brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); | |
1183 | up->curregs[R12] = (brg & 0xff); | |
1184 | up->curregs[R13] = (brg >> 8) & 0xff; | |
1185 | up->curregs[R14] = BRENAB; | |
1186 | __load_zsregs(channel, up->curregs); | |
1187 | /* set master interrupt enable */ | |
1188 | write_zsreg(channel, R9, up->curregs[R9]); | |
1189 | ||
1190 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | static int __init ip22zilog_ports_init(void) | |
1195 | { | |
1196 | int ret; | |
1197 | ||
1198 | printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG); | |
1199 | ||
1200 | ip22zilog_prepare(); | |
1201 | ||
1202 | if (request_irq(zilog_irq, ip22zilog_interrupt, 0, | |
1203 | "IP22-Zilog", ip22zilog_irq_chain)) { | |
1204 | panic("IP22-Zilog: Unable to register zs interrupt handler.\n"); | |
1205 | } | |
1206 | ||
1207 | ip22zilog_init_hw(); | |
1208 | ||
1209 | ret = uart_register_driver(&ip22zilog_reg); | |
1210 | if (ret == 0) { | |
1211 | int i; | |
1212 | ||
1213 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1214 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; | |
1215 | ||
1216 | uart_add_one_port(&ip22zilog_reg, &up->port); | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | return ret; | |
1221 | } | |
1222 | ||
1223 | static int __init ip22zilog_init(void) | |
1224 | { | |
1225 | /* IP22 Zilog setup is hard coded, no probing to do. */ | |
1226 | ip22zilog_alloc_tables(); | |
1227 | ip22zilog_ports_init(); | |
1228 | ||
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | static void __exit ip22zilog_exit(void) | |
1233 | { | |
1234 | int i; | |
1235 | ||
1236 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1237 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; | |
1238 | ||
1239 | uart_remove_one_port(&ip22zilog_reg, &up->port); | |
1240 | } | |
1241 | ||
1242 | uart_unregister_driver(&ip22zilog_reg); | |
1243 | } | |
1244 | ||
1245 | module_init(ip22zilog_init); | |
1246 | module_exit(ip22zilog_exit); | |
1247 | ||
1248 | /* David wrote it but I'm to blame for the bugs ... */ | |
1249 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); | |
1250 | MODULE_DESCRIPTION("SGI Zilog serial port driver"); | |
1251 | MODULE_LICENSE("GPL"); |