Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. |
3 | * | |
4 | * FIXME According to the usermanual the status bits in the status register | |
5 | * are only updated when the peripherals access the FIFO and not when the | |
6 | * CPU access them. So since we use this bits to know when we stop writing | |
7 | * and reading, they may not be updated in-time and a race condition may | |
8 | * exists. But I haven't be able to prove this and I don't care. But if | |
9 | * any problem arises, it might worth checking. The TX/RX FIFO Stats | |
10 | * registers should be used in addition. | |
11 | * Update: Actually, they seem updated ... At least the bits we use. | |
12 | * | |
13 | * | |
14 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | |
9b9129e7 | 15 | * |
1da177e4 LT |
16 | * Some of the code has been inspired/copied from the 2.4 code written |
17 | * by Dale Farnsworth <dfarnsworth@mvista.com>. | |
9b9129e7 | 18 | * |
25ae3a07 JR |
19 | * Copyright (C) 2008 Freescale Semiconductor Inc. |
20 | * John Rigby <jrigby@gmail.com> | |
21 | * Added support for MPC5121 | |
b9272dfd GL |
22 | * Copyright (C) 2006 Secret Lab Technologies Ltd. |
23 | * Grant Likely <grant.likely@secretlab.ca> | |
24 | * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> | |
1da177e4 | 25 | * Copyright (C) 2003 MontaVista, Software, Inc. |
9b9129e7 | 26 | * |
1da177e4 LT |
27 | * This file is licensed under the terms of the GNU General Public License |
28 | * version 2. This program is licensed "as is" without any warranty of any | |
29 | * kind, whether express or implied. | |
30 | */ | |
9b9129e7 | 31 | |
1da177e4 LT |
32 | /* Platform device Usage : |
33 | * | |
34 | * Since PSCs can have multiple function, the correct driver for each one | |
35 | * is selected by calling mpc52xx_match_psc_function(...). The function | |
36 | * handled by this driver is "uart". | |
37 | * | |
38 | * The driver init all necessary registers to place the PSC in uart mode without | |
39 | * DCD. However, the pin multiplexing aren't changed and should be set either | |
40 | * by the bootloader or in the platform init code. | |
41 | * | |
406b7d4f | 42 | * The idx field must be equal to the PSC index (e.g. 0 for PSC1, 1 for PSC2, |
d62de3aa SM |
43 | * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and |
44 | * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly | |
45 | * fpr the console code : without this 1:1 mapping, at early boot time, when we | |
c30fe7f7 | 46 | * are parsing the kernel args console=ttyPSC?, we wouldn't know which PSC it |
d62de3aa | 47 | * will be mapped to. |
1da177e4 LT |
48 | */ |
49 | ||
b9272dfd GL |
50 | /* OF Platform device Usage : |
51 | * | |
52 | * This driver is only used for PSCs configured in uart mode. The device | |
3b5ebf8e GL |
53 | * tree will have a node for each PSC with "mpc52xx-psc-uart" in the compatible |
54 | * list. | |
b9272dfd GL |
55 | * |
56 | * By default, PSC devices are enumerated in the order they are found. However | |
57 | * a particular PSC number can be forces by adding 'device_no = <port#>' | |
58 | * to the device node. | |
59 | * | |
60 | * The driver init all necessary registers to place the PSC in uart mode without | |
61 | * DCD. However, the pin multiplexing aren't changed and should be set either | |
62 | * by the bootloader or in the platform init code. | |
63 | */ | |
64 | ||
65 | #undef DEBUG | |
66 | ||
67 | #include <linux/device.h> | |
1da177e4 LT |
68 | #include <linux/module.h> |
69 | #include <linux/tty.h> | |
70 | #include <linux/serial.h> | |
71 | #include <linux/sysrq.h> | |
72 | #include <linux/console.h> | |
406b7d4f JR |
73 | #include <linux/delay.h> |
74 | #include <linux/io.h> | |
283029d1 GL |
75 | #include <linux/of.h> |
76 | #include <linux/of_platform.h> | |
b9272dfd | 77 | |
1da177e4 | 78 | #include <asm/mpc52xx.h> |
25ae3a07 | 79 | #include <asm/mpc512x.h> |
1da177e4 LT |
80 | #include <asm/mpc52xx_psc.h> |
81 | ||
82 | #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
83 | #define SUPPORT_SYSRQ | |
84 | #endif | |
85 | ||
86 | #include <linux/serial_core.h> | |
87 | ||
88 | ||
d62de3aa SM |
89 | /* We've been assigned a range on the "Low-density serial ports" major */ |
90 | #define SERIAL_PSC_MAJOR 204 | |
91 | #define SERIAL_PSC_MINOR 148 | |
92 | ||
1da177e4 LT |
93 | |
94 | #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ | |
95 | ||
96 | ||
97 | static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; | |
98 | /* Rem: - We use the read_status_mask as a shadow of | |
99 | * psc->mpc52xx_psc_imr | |
100 | * - It's important that is array is all zero on start as we | |
101 | * use it to know if it's initialized or not ! If it's not sure | |
102 | * it's cleared, then a memset(...,0,...) should be added to | |
103 | * the console_init | |
104 | */ | |
8d1fb8cb | 105 | |
b9272dfd GL |
106 | /* lookup table for matching device nodes to index numbers */ |
107 | static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; | |
108 | ||
109 | static void mpc52xx_uart_of_enumerate(void); | |
1da177e4 | 110 | |
599f030c | 111 | |
1da177e4 LT |
112 | #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) |
113 | ||
114 | ||
115 | /* Forward declaration of the interruption handling routine */ | |
406b7d4f | 116 | static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); |
1da177e4 LT |
117 | |
118 | ||
119 | /* Simple macro to test if a port is console or not. This one is taken | |
120 | * for serial_core.c and maybe should be moved to serial_core.h ? */ | |
121 | #ifdef CONFIG_SERIAL_CORE_CONSOLE | |
406b7d4f JR |
122 | #define uart_console(port) \ |
123 | ((port)->cons && (port)->cons->index == (port)->line) | |
1da177e4 LT |
124 | #else |
125 | #define uart_console(port) (0) | |
126 | #endif | |
127 | ||
599f030c JR |
128 | /* ======================================================================== */ |
129 | /* PSC fifo operations for isolating differences between 52xx and 512x */ | |
130 | /* ======================================================================== */ | |
131 | ||
132 | struct psc_ops { | |
133 | void (*fifo_init)(struct uart_port *port); | |
134 | int (*raw_rx_rdy)(struct uart_port *port); | |
135 | int (*raw_tx_rdy)(struct uart_port *port); | |
136 | int (*rx_rdy)(struct uart_port *port); | |
137 | int (*tx_rdy)(struct uart_port *port); | |
138 | int (*tx_empty)(struct uart_port *port); | |
139 | void (*stop_rx)(struct uart_port *port); | |
140 | void (*start_tx)(struct uart_port *port); | |
141 | void (*stop_tx)(struct uart_port *port); | |
142 | void (*rx_clr_irq)(struct uart_port *port); | |
143 | void (*tx_clr_irq)(struct uart_port *port); | |
144 | void (*write_char)(struct uart_port *port, unsigned char c); | |
145 | unsigned char (*read_char)(struct uart_port *port); | |
146 | void (*cw_disable_ints)(struct uart_port *port); | |
147 | void (*cw_restore_ints)(struct uart_port *port); | |
148 | unsigned long (*getuartclk)(void *p); | |
149 | }; | |
150 | ||
25ae3a07 | 151 | #ifdef CONFIG_PPC_MPC52xx |
599f030c JR |
152 | #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) |
153 | static void mpc52xx_psc_fifo_init(struct uart_port *port) | |
154 | { | |
155 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
156 | struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); | |
157 | ||
158 | /* /32 prescaler */ | |
159 | out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00); | |
160 | ||
161 | out_8(&fifo->rfcntl, 0x00); | |
162 | out_be16(&fifo->rfalarm, 0x1ff); | |
163 | out_8(&fifo->tfcntl, 0x07); | |
164 | out_be16(&fifo->tfalarm, 0x80); | |
165 | ||
166 | port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; | |
167 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
168 | } | |
169 | ||
170 | static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) | |
171 | { | |
172 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
173 | & MPC52xx_PSC_SR_RXRDY; | |
174 | } | |
175 | ||
176 | static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) | |
177 | { | |
178 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
179 | & MPC52xx_PSC_SR_TXRDY; | |
180 | } | |
181 | ||
182 | ||
183 | static int mpc52xx_psc_rx_rdy(struct uart_port *port) | |
184 | { | |
185 | return in_be16(&PSC(port)->mpc52xx_psc_isr) | |
186 | & port->read_status_mask | |
187 | & MPC52xx_PSC_IMR_RXRDY; | |
188 | } | |
189 | ||
190 | static int mpc52xx_psc_tx_rdy(struct uart_port *port) | |
191 | { | |
192 | return in_be16(&PSC(port)->mpc52xx_psc_isr) | |
193 | & port->read_status_mask | |
194 | & MPC52xx_PSC_IMR_TXRDY; | |
195 | } | |
196 | ||
197 | static int mpc52xx_psc_tx_empty(struct uart_port *port) | |
198 | { | |
199 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
200 | & MPC52xx_PSC_SR_TXEMP; | |
201 | } | |
202 | ||
203 | static void mpc52xx_psc_start_tx(struct uart_port *port) | |
204 | { | |
205 | port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; | |
206 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
207 | } | |
208 | ||
209 | static void mpc52xx_psc_stop_tx(struct uart_port *port) | |
210 | { | |
211 | port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; | |
212 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
213 | } | |
214 | ||
215 | static void mpc52xx_psc_stop_rx(struct uart_port *port) | |
216 | { | |
217 | port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; | |
218 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
219 | } | |
220 | ||
221 | static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) | |
222 | { | |
223 | } | |
224 | ||
225 | static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) | |
226 | { | |
227 | } | |
228 | ||
229 | static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) | |
230 | { | |
231 | out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); | |
232 | } | |
233 | ||
234 | static unsigned char mpc52xx_psc_read_char(struct uart_port *port) | |
235 | { | |
236 | return in_8(&PSC(port)->mpc52xx_psc_buffer_8); | |
237 | } | |
238 | ||
239 | static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) | |
240 | { | |
241 | out_be16(&PSC(port)->mpc52xx_psc_imr, 0); | |
242 | } | |
243 | ||
244 | static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) | |
245 | { | |
246 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
247 | } | |
248 | ||
249 | /* Search for bus-frequency property in this node or a parent */ | |
250 | static unsigned long mpc52xx_getuartclk(void *p) | |
251 | { | |
599f030c JR |
252 | /* |
253 | * 5200 UARTs have a / 32 prescaler | |
254 | * but the generic serial code assumes 16 | |
255 | * so return ipb freq / 2 | |
256 | */ | |
257 | return mpc52xx_find_ipb_freq(p) / 2; | |
599f030c JR |
258 | } |
259 | ||
260 | static struct psc_ops mpc52xx_psc_ops = { | |
261 | .fifo_init = mpc52xx_psc_fifo_init, | |
262 | .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, | |
263 | .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, | |
264 | .rx_rdy = mpc52xx_psc_rx_rdy, | |
265 | .tx_rdy = mpc52xx_psc_tx_rdy, | |
266 | .tx_empty = mpc52xx_psc_tx_empty, | |
267 | .stop_rx = mpc52xx_psc_stop_rx, | |
268 | .start_tx = mpc52xx_psc_start_tx, | |
269 | .stop_tx = mpc52xx_psc_stop_tx, | |
270 | .rx_clr_irq = mpc52xx_psc_rx_clr_irq, | |
271 | .tx_clr_irq = mpc52xx_psc_tx_clr_irq, | |
272 | .write_char = mpc52xx_psc_write_char, | |
273 | .read_char = mpc52xx_psc_read_char, | |
274 | .cw_disable_ints = mpc52xx_psc_cw_disable_ints, | |
275 | .cw_restore_ints = mpc52xx_psc_cw_restore_ints, | |
276 | .getuartclk = mpc52xx_getuartclk, | |
277 | }; | |
278 | ||
25ae3a07 JR |
279 | #endif /* CONFIG_MPC52xx */ |
280 | ||
281 | #ifdef CONFIG_PPC_MPC512x | |
282 | #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) | |
283 | static void mpc512x_psc_fifo_init(struct uart_port *port) | |
284 | { | |
285 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); | |
286 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
287 | out_be32(&FIFO_512x(port)->txalarm, 1); | |
288 | out_be32(&FIFO_512x(port)->tximr, 0); | |
289 | ||
290 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); | |
291 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
292 | out_be32(&FIFO_512x(port)->rxalarm, 1); | |
293 | out_be32(&FIFO_512x(port)->rximr, 0); | |
294 | ||
295 | out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); | |
296 | out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); | |
297 | } | |
298 | ||
299 | static int mpc512x_psc_raw_rx_rdy(struct uart_port *port) | |
300 | { | |
301 | return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); | |
302 | } | |
303 | ||
304 | static int mpc512x_psc_raw_tx_rdy(struct uart_port *port) | |
305 | { | |
306 | return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); | |
307 | } | |
308 | ||
309 | static int mpc512x_psc_rx_rdy(struct uart_port *port) | |
310 | { | |
311 | return in_be32(&FIFO_512x(port)->rxsr) | |
312 | & in_be32(&FIFO_512x(port)->rximr) | |
313 | & MPC512x_PSC_FIFO_ALARM; | |
314 | } | |
315 | ||
316 | static int mpc512x_psc_tx_rdy(struct uart_port *port) | |
317 | { | |
318 | return in_be32(&FIFO_512x(port)->txsr) | |
319 | & in_be32(&FIFO_512x(port)->tximr) | |
320 | & MPC512x_PSC_FIFO_ALARM; | |
321 | } | |
322 | ||
323 | static int mpc512x_psc_tx_empty(struct uart_port *port) | |
324 | { | |
325 | return in_be32(&FIFO_512x(port)->txsr) | |
326 | & MPC512x_PSC_FIFO_EMPTY; | |
327 | } | |
328 | ||
329 | static void mpc512x_psc_stop_rx(struct uart_port *port) | |
330 | { | |
331 | unsigned long rx_fifo_imr; | |
332 | ||
333 | rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); | |
334 | rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
335 | out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); | |
336 | } | |
337 | ||
338 | static void mpc512x_psc_start_tx(struct uart_port *port) | |
339 | { | |
340 | unsigned long tx_fifo_imr; | |
341 | ||
342 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); | |
343 | tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; | |
344 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); | |
345 | } | |
346 | ||
347 | static void mpc512x_psc_stop_tx(struct uart_port *port) | |
348 | { | |
349 | unsigned long tx_fifo_imr; | |
350 | ||
351 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); | |
352 | tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
353 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); | |
354 | } | |
355 | ||
356 | static void mpc512x_psc_rx_clr_irq(struct uart_port *port) | |
357 | { | |
358 | out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); | |
359 | } | |
360 | ||
361 | static void mpc512x_psc_tx_clr_irq(struct uart_port *port) | |
362 | { | |
363 | out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); | |
364 | } | |
365 | ||
366 | static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) | |
367 | { | |
368 | out_8(&FIFO_512x(port)->txdata_8, c); | |
369 | } | |
370 | ||
371 | static unsigned char mpc512x_psc_read_char(struct uart_port *port) | |
372 | { | |
373 | return in_8(&FIFO_512x(port)->rxdata_8); | |
374 | } | |
375 | ||
376 | static void mpc512x_psc_cw_disable_ints(struct uart_port *port) | |
377 | { | |
378 | port->read_status_mask = | |
379 | in_be32(&FIFO_512x(port)->tximr) << 16 | | |
380 | in_be32(&FIFO_512x(port)->rximr); | |
381 | out_be32(&FIFO_512x(port)->tximr, 0); | |
382 | out_be32(&FIFO_512x(port)->rximr, 0); | |
383 | } | |
384 | ||
385 | static void mpc512x_psc_cw_restore_ints(struct uart_port *port) | |
386 | { | |
387 | out_be32(&FIFO_512x(port)->tximr, | |
388 | (port->read_status_mask >> 16) & 0x7f); | |
389 | out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); | |
390 | } | |
391 | ||
392 | static unsigned long mpc512x_getuartclk(void *p) | |
393 | { | |
394 | return mpc512x_find_ips_freq(p); | |
395 | } | |
396 | ||
397 | static struct psc_ops mpc512x_psc_ops = { | |
398 | .fifo_init = mpc512x_psc_fifo_init, | |
399 | .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, | |
400 | .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, | |
401 | .rx_rdy = mpc512x_psc_rx_rdy, | |
402 | .tx_rdy = mpc512x_psc_tx_rdy, | |
403 | .tx_empty = mpc512x_psc_tx_empty, | |
404 | .stop_rx = mpc512x_psc_stop_rx, | |
405 | .start_tx = mpc512x_psc_start_tx, | |
406 | .stop_tx = mpc512x_psc_stop_tx, | |
407 | .rx_clr_irq = mpc512x_psc_rx_clr_irq, | |
408 | .tx_clr_irq = mpc512x_psc_tx_clr_irq, | |
409 | .write_char = mpc512x_psc_write_char, | |
410 | .read_char = mpc512x_psc_read_char, | |
411 | .cw_disable_ints = mpc512x_psc_cw_disable_ints, | |
412 | .cw_restore_ints = mpc512x_psc_cw_restore_ints, | |
413 | .getuartclk = mpc512x_getuartclk, | |
414 | }; | |
415 | #endif | |
416 | ||
417 | static struct psc_ops *psc_ops; | |
1da177e4 LT |
418 | |
419 | /* ======================================================================== */ | |
420 | /* UART operations */ | |
421 | /* ======================================================================== */ | |
422 | ||
9b9129e7 | 423 | static unsigned int |
1da177e4 LT |
424 | mpc52xx_uart_tx_empty(struct uart_port *port) |
425 | { | |
599f030c | 426 | return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; |
1da177e4 LT |
427 | } |
428 | ||
9b9129e7 | 429 | static void |
1da177e4 LT |
430 | mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
431 | { | |
aec739e0 WS |
432 | if (mctrl & TIOCM_RTS) |
433 | out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); | |
434 | else | |
435 | out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); | |
1da177e4 LT |
436 | } |
437 | ||
9b9129e7 | 438 | static unsigned int |
1da177e4 LT |
439 | mpc52xx_uart_get_mctrl(struct uart_port *port) |
440 | { | |
aec739e0 WS |
441 | unsigned int ret = TIOCM_DSR; |
442 | u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr); | |
443 | ||
444 | if (!(status & MPC52xx_PSC_CTS)) | |
445 | ret |= TIOCM_CTS; | |
446 | if (!(status & MPC52xx_PSC_DCD)) | |
447 | ret |= TIOCM_CAR; | |
448 | ||
449 | return ret; | |
1da177e4 LT |
450 | } |
451 | ||
9b9129e7 | 452 | static void |
b129a8cc | 453 | mpc52xx_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
454 | { |
455 | /* port->lock taken by caller */ | |
599f030c | 456 | psc_ops->stop_tx(port); |
1da177e4 LT |
457 | } |
458 | ||
9b9129e7 | 459 | static void |
b129a8cc | 460 | mpc52xx_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
461 | { |
462 | /* port->lock taken by caller */ | |
599f030c | 463 | psc_ops->start_tx(port); |
1da177e4 LT |
464 | } |
465 | ||
9b9129e7 | 466 | static void |
1da177e4 LT |
467 | mpc52xx_uart_send_xchar(struct uart_port *port, char ch) |
468 | { | |
469 | unsigned long flags; | |
470 | spin_lock_irqsave(&port->lock, flags); | |
9b9129e7 | 471 | |
1da177e4 LT |
472 | port->x_char = ch; |
473 | if (ch) { | |
474 | /* Make sure tx interrupts are on */ | |
475 | /* Truly necessary ??? They should be anyway */ | |
599f030c | 476 | psc_ops->start_tx(port); |
1da177e4 | 477 | } |
9b9129e7 | 478 | |
1da177e4 LT |
479 | spin_unlock_irqrestore(&port->lock, flags); |
480 | } | |
481 | ||
482 | static void | |
483 | mpc52xx_uart_stop_rx(struct uart_port *port) | |
484 | { | |
485 | /* port->lock taken by caller */ | |
599f030c | 486 | psc_ops->stop_rx(port); |
1da177e4 LT |
487 | } |
488 | ||
489 | static void | |
490 | mpc52xx_uart_enable_ms(struct uart_port *port) | |
491 | { | |
aec739e0 WS |
492 | struct mpc52xx_psc __iomem *psc = PSC(port); |
493 | ||
494 | /* clear D_*-bits by reading them */ | |
495 | in_8(&psc->mpc52xx_psc_ipcr); | |
496 | /* enable CTS and DCD as IPC interrupts */ | |
497 | out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); | |
498 | ||
499 | port->read_status_mask |= MPC52xx_PSC_IMR_IPC; | |
500 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
1da177e4 LT |
501 | } |
502 | ||
503 | static void | |
504 | mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) | |
505 | { | |
506 | unsigned long flags; | |
507 | spin_lock_irqsave(&port->lock, flags); | |
508 | ||
406b7d4f JR |
509 | if (ctl == -1) |
510 | out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK); | |
1da177e4 | 511 | else |
406b7d4f | 512 | out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK); |
9b9129e7 | 513 | |
1da177e4 LT |
514 | spin_unlock_irqrestore(&port->lock, flags); |
515 | } | |
516 | ||
517 | static int | |
518 | mpc52xx_uart_startup(struct uart_port *port) | |
519 | { | |
520 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
521 | int ret; | |
522 | ||
523 | /* Request IRQ */ | |
524 | ret = request_irq(port->irq, mpc52xx_uart_int, | |
d9f0c5f9 | 525 | IRQF_DISABLED | IRQF_SAMPLE_RANDOM, |
25ae3a07 | 526 | "mpc52xx_psc_uart", port); |
1da177e4 LT |
527 | if (ret) |
528 | return ret; | |
529 | ||
530 | /* Reset/activate the port, clear and enable interrupts */ | |
406b7d4f JR |
531 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
532 | out_8(&psc->command, MPC52xx_PSC_RST_TX); | |
9b9129e7 | 533 | |
406b7d4f | 534 | out_be32(&psc->sicr, 0); /* UART mode DCD ignored */ |
1da177e4 | 535 | |
599f030c | 536 | psc_ops->fifo_init(port); |
9b9129e7 | 537 | |
406b7d4f JR |
538 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE); |
539 | out_8(&psc->command, MPC52xx_PSC_RX_ENABLE); | |
9b9129e7 | 540 | |
1da177e4 LT |
541 | return 0; |
542 | } | |
543 | ||
544 | static void | |
545 | mpc52xx_uart_shutdown(struct uart_port *port) | |
546 | { | |
547 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
9b9129e7 | 548 | |
a3481197 | 549 | /* Shut down the port. Leave TX active if on a console port */ |
406b7d4f | 550 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
a3481197 | 551 | if (!uart_console(port)) |
406b7d4f | 552 | out_8(&psc->command, MPC52xx_PSC_RST_TX); |
9b9129e7 GL |
553 | |
554 | port->read_status_mask = 0; | |
406b7d4f | 555 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); |
1da177e4 LT |
556 | |
557 | /* Release interrupt */ | |
558 | free_irq(port->irq, port); | |
559 | } | |
560 | ||
9b9129e7 | 561 | static void |
606d099c | 562 | mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, |
406b7d4f | 563 | struct ktermios *old) |
1da177e4 LT |
564 | { |
565 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
566 | unsigned long flags; | |
567 | unsigned char mr1, mr2; | |
568 | unsigned short ctr; | |
569 | unsigned int j, baud, quot; | |
9b9129e7 | 570 | |
1da177e4 LT |
571 | /* Prepare what we're gonna write */ |
572 | mr1 = 0; | |
9b9129e7 | 573 | |
1da177e4 | 574 | switch (new->c_cflag & CSIZE) { |
406b7d4f JR |
575 | case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; |
576 | break; | |
577 | case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; | |
578 | break; | |
579 | case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; | |
580 | break; | |
581 | case CS8: | |
582 | default: mr1 |= MPC52xx_PSC_MODE_8_BITS; | |
1da177e4 LT |
583 | } |
584 | ||
585 | if (new->c_cflag & PARENB) { | |
586 | mr1 |= (new->c_cflag & PARODD) ? | |
587 | MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; | |
588 | } else | |
589 | mr1 |= MPC52xx_PSC_MODE_PARNONE; | |
9b9129e7 GL |
590 | |
591 | ||
1da177e4 LT |
592 | mr2 = 0; |
593 | ||
594 | if (new->c_cflag & CSTOPB) | |
595 | mr2 |= MPC52xx_PSC_MODE_TWO_STOP; | |
596 | else | |
597 | mr2 |= ((new->c_cflag & CSIZE) == CS5) ? | |
598 | MPC52xx_PSC_MODE_ONE_STOP_5_BITS : | |
599 | MPC52xx_PSC_MODE_ONE_STOP; | |
600 | ||
aec739e0 WS |
601 | if (new->c_cflag & CRTSCTS) { |
602 | mr1 |= MPC52xx_PSC_MODE_RXRTS; | |
603 | mr2 |= MPC52xx_PSC_MODE_TXCTS; | |
604 | } | |
1da177e4 LT |
605 | |
606 | baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16); | |
607 | quot = uart_get_divisor(port, baud); | |
608 | ctr = quot & 0xffff; | |
9b9129e7 | 609 | |
1da177e4 LT |
610 | /* Get the lock */ |
611 | spin_lock_irqsave(&port->lock, flags); | |
612 | ||
613 | /* Update the per-port timeout */ | |
614 | uart_update_timeout(port, new->c_cflag, baud); | |
615 | ||
c4f01240 NA |
616 | /* Do our best to flush TX & RX, so we don't lose anything */ |
617 | /* But we don't wait indefinitely ! */ | |
1da177e4 LT |
618 | j = 5000000; /* Maximum wait */ |
619 | /* FIXME Can't receive chars since set_termios might be called at early | |
620 | * boot for the console, all stuff is not yet ready to receive at that | |
621 | * time and that just makes the kernel oops */ | |
622 | /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ | |
599f030c | 623 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
624 | udelay(1); |
625 | ||
626 | if (!j) | |
406b7d4f | 627 | printk(KERN_ERR "mpc52xx_uart.c: " |
1da177e4 | 628 | "Unable to flush RX & TX fifos in-time in set_termios." |
406b7d4f | 629 | "Some chars may have been lost.\n"); |
1da177e4 LT |
630 | |
631 | /* Reset the TX & RX */ | |
406b7d4f JR |
632 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
633 | out_8(&psc->command, MPC52xx_PSC_RST_TX); | |
1da177e4 LT |
634 | |
635 | /* Send new mode settings */ | |
406b7d4f JR |
636 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); |
637 | out_8(&psc->mode, mr1); | |
638 | out_8(&psc->mode, mr2); | |
639 | out_8(&psc->ctur, ctr >> 8); | |
640 | out_8(&psc->ctlr, ctr & 0xff); | |
9b9129e7 | 641 | |
aec739e0 WS |
642 | if (UART_ENABLE_MS(port, new->c_cflag)) |
643 | mpc52xx_uart_enable_ms(port); | |
644 | ||
1da177e4 | 645 | /* Reenable TX & RX */ |
406b7d4f JR |
646 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE); |
647 | out_8(&psc->command, MPC52xx_PSC_RX_ENABLE); | |
1da177e4 LT |
648 | |
649 | /* We're all set, release the lock */ | |
650 | spin_unlock_irqrestore(&port->lock, flags); | |
651 | } | |
652 | ||
653 | static const char * | |
654 | mpc52xx_uart_type(struct uart_port *port) | |
655 | { | |
656 | return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL; | |
657 | } | |
658 | ||
659 | static void | |
660 | mpc52xx_uart_release_port(struct uart_port *port) | |
661 | { | |
406b7d4f JR |
662 | /* remapped by us ? */ |
663 | if (port->flags & UPF_IOREMAP) { | |
1da177e4 LT |
664 | iounmap(port->membase); |
665 | port->membase = NULL; | |
666 | } | |
667 | ||
b9272dfd | 668 | release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); |
1da177e4 LT |
669 | } |
670 | ||
671 | static int | |
672 | mpc52xx_uart_request_port(struct uart_port *port) | |
673 | { | |
be618f55 AL |
674 | int err; |
675 | ||
1da177e4 | 676 | if (port->flags & UPF_IOREMAP) /* Need to remap ? */ |
b9272dfd | 677 | port->membase = ioremap(port->mapbase, |
406b7d4f | 678 | sizeof(struct mpc52xx_psc)); |
1da177e4 LT |
679 | |
680 | if (!port->membase) | |
681 | return -EINVAL; | |
682 | ||
b9272dfd | 683 | err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc), |
1da177e4 | 684 | "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; |
be618f55 AL |
685 | |
686 | if (err && (port->flags & UPF_IOREMAP)) { | |
687 | iounmap(port->membase); | |
688 | port->membase = NULL; | |
689 | } | |
690 | ||
691 | return err; | |
1da177e4 LT |
692 | } |
693 | ||
694 | static void | |
695 | mpc52xx_uart_config_port(struct uart_port *port, int flags) | |
696 | { | |
406b7d4f JR |
697 | if ((flags & UART_CONFIG_TYPE) |
698 | && (mpc52xx_uart_request_port(port) == 0)) | |
699 | port->type = PORT_MPC52xx; | |
1da177e4 LT |
700 | } |
701 | ||
702 | static int | |
703 | mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) | |
704 | { | |
406b7d4f | 705 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx) |
1da177e4 LT |
706 | return -EINVAL; |
707 | ||
406b7d4f JR |
708 | if ((ser->irq != port->irq) || |
709 | (ser->io_type != SERIAL_IO_MEM) || | |
710 | (ser->baud_base != port->uartclk) || | |
711 | (ser->iomem_base != (void *)port->mapbase) || | |
712 | (ser->hub6 != 0)) | |
1da177e4 LT |
713 | return -EINVAL; |
714 | ||
715 | return 0; | |
716 | } | |
717 | ||
718 | ||
719 | static struct uart_ops mpc52xx_uart_ops = { | |
720 | .tx_empty = mpc52xx_uart_tx_empty, | |
721 | .set_mctrl = mpc52xx_uart_set_mctrl, | |
722 | .get_mctrl = mpc52xx_uart_get_mctrl, | |
723 | .stop_tx = mpc52xx_uart_stop_tx, | |
724 | .start_tx = mpc52xx_uart_start_tx, | |
725 | .send_xchar = mpc52xx_uart_send_xchar, | |
726 | .stop_rx = mpc52xx_uart_stop_rx, | |
727 | .enable_ms = mpc52xx_uart_enable_ms, | |
728 | .break_ctl = mpc52xx_uart_break_ctl, | |
729 | .startup = mpc52xx_uart_startup, | |
730 | .shutdown = mpc52xx_uart_shutdown, | |
731 | .set_termios = mpc52xx_uart_set_termios, | |
732 | /* .pm = mpc52xx_uart_pm, Not supported yet */ | |
733 | /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */ | |
734 | .type = mpc52xx_uart_type, | |
735 | .release_port = mpc52xx_uart_release_port, | |
736 | .request_port = mpc52xx_uart_request_port, | |
737 | .config_port = mpc52xx_uart_config_port, | |
738 | .verify_port = mpc52xx_uart_verify_port | |
739 | }; | |
740 | ||
9b9129e7 | 741 | |
1da177e4 LT |
742 | /* ======================================================================== */ |
743 | /* Interrupt handling */ | |
744 | /* ======================================================================== */ | |
9b9129e7 | 745 | |
1da177e4 | 746 | static inline int |
7d12e780 | 747 | mpc52xx_uart_int_rx_chars(struct uart_port *port) |
1da177e4 | 748 | { |
a88487c7 | 749 | struct tty_struct *tty = port->info->port.tty; |
33f0f88f | 750 | unsigned char ch, flag; |
1da177e4 LT |
751 | unsigned short status; |
752 | ||
753 | /* While we can read, do so ! */ | |
599f030c | 754 | while (psc_ops->raw_rx_rdy(port)) { |
1da177e4 | 755 | /* Get the char */ |
599f030c | 756 | ch = psc_ops->read_char(port); |
1da177e4 LT |
757 | |
758 | /* Handle sysreq char */ | |
759 | #ifdef SUPPORT_SYSRQ | |
7d12e780 | 760 | if (uart_handle_sysrq_char(port, ch)) { |
1da177e4 LT |
761 | port->sysrq = 0; |
762 | continue; | |
763 | } | |
764 | #endif | |
765 | ||
766 | /* Store it */ | |
33f0f88f AC |
767 | |
768 | flag = TTY_NORMAL; | |
1da177e4 | 769 | port->icount.rx++; |
9b9129e7 | 770 | |
599f030c JR |
771 | status = in_be16(&PSC(port)->mpc52xx_psc_status); |
772 | ||
406b7d4f JR |
773 | if (status & (MPC52xx_PSC_SR_PE | |
774 | MPC52xx_PSC_SR_FE | | |
775 | MPC52xx_PSC_SR_RB)) { | |
9b9129e7 | 776 | |
1da177e4 | 777 | if (status & MPC52xx_PSC_SR_RB) { |
33f0f88f | 778 | flag = TTY_BREAK; |
1da177e4 | 779 | uart_handle_break(port); |
b6514988 RB |
780 | port->icount.brk++; |
781 | } else if (status & MPC52xx_PSC_SR_PE) { | |
33f0f88f | 782 | flag = TTY_PARITY; |
b6514988 RB |
783 | port->icount.parity++; |
784 | } | |
785 | else if (status & MPC52xx_PSC_SR_FE) { | |
33f0f88f | 786 | flag = TTY_FRAME; |
b6514988 RB |
787 | port->icount.frame++; |
788 | } | |
1da177e4 LT |
789 | |
790 | /* Clear error condition */ | |
406b7d4f | 791 | out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT); |
1da177e4 LT |
792 | |
793 | } | |
33f0f88f AC |
794 | tty_insert_flip_char(tty, ch, flag); |
795 | if (status & MPC52xx_PSC_SR_OE) { | |
796 | /* | |
797 | * Overrun is special, since it's | |
798 | * reported immediately, and doesn't | |
799 | * affect the current character | |
800 | */ | |
801 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
b6514988 | 802 | port->icount.overrun++; |
33f0f88f | 803 | } |
1da177e4 LT |
804 | } |
805 | ||
fbe543b4 | 806 | spin_unlock(&port->lock); |
1da177e4 | 807 | tty_flip_buffer_push(tty); |
fbe543b4 | 808 | spin_lock(&port->lock); |
9b9129e7 | 809 | |
599f030c | 810 | return psc_ops->raw_rx_rdy(port); |
1da177e4 LT |
811 | } |
812 | ||
813 | static inline int | |
814 | mpc52xx_uart_int_tx_chars(struct uart_port *port) | |
815 | { | |
816 | struct circ_buf *xmit = &port->info->xmit; | |
817 | ||
818 | /* Process out of band chars */ | |
819 | if (port->x_char) { | |
599f030c | 820 | psc_ops->write_char(port, port->x_char); |
1da177e4 LT |
821 | port->icount.tx++; |
822 | port->x_char = 0; | |
823 | return 1; | |
824 | } | |
825 | ||
826 | /* Nothing to do ? */ | |
827 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 828 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
829 | return 0; |
830 | } | |
831 | ||
832 | /* Send chars */ | |
599f030c JR |
833 | while (psc_ops->raw_tx_rdy(port)) { |
834 | psc_ops->write_char(port, xmit->buf[xmit->tail]); | |
1da177e4 LT |
835 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
836 | port->icount.tx++; | |
837 | if (uart_circ_empty(xmit)) | |
838 | break; | |
839 | } | |
840 | ||
841 | /* Wake up */ | |
842 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
843 | uart_write_wakeup(port); | |
844 | ||
845 | /* Maybe we're done after all */ | |
846 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 847 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
848 | return 0; |
849 | } | |
850 | ||
851 | return 1; | |
852 | } | |
853 | ||
9b9129e7 | 854 | static irqreturn_t |
7d12e780 | 855 | mpc52xx_uart_int(int irq, void *dev_id) |
1da177e4 | 856 | { |
c7bec5ab | 857 | struct uart_port *port = dev_id; |
1da177e4 LT |
858 | unsigned long pass = ISR_PASS_LIMIT; |
859 | unsigned int keepgoing; | |
aec739e0 | 860 | u8 status; |
9b9129e7 | 861 | |
1da177e4 | 862 | spin_lock(&port->lock); |
9b9129e7 | 863 | |
1da177e4 LT |
864 | /* While we have stuff to do, we continue */ |
865 | do { | |
866 | /* If we don't find anything to do, we stop */ | |
9b9129e7 GL |
867 | keepgoing = 0; |
868 | ||
599f030c JR |
869 | psc_ops->rx_clr_irq(port); |
870 | if (psc_ops->rx_rdy(port)) | |
7d12e780 | 871 | keepgoing |= mpc52xx_uart_int_rx_chars(port); |
1da177e4 | 872 | |
599f030c JR |
873 | psc_ops->tx_clr_irq(port); |
874 | if (psc_ops->tx_rdy(port)) | |
1da177e4 | 875 | keepgoing |= mpc52xx_uart_int_tx_chars(port); |
9b9129e7 | 876 | |
aec739e0 WS |
877 | status = in_8(&PSC(port)->mpc52xx_psc_ipcr); |
878 | if (status & MPC52xx_PSC_D_DCD) | |
879 | uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD)); | |
880 | ||
881 | if (status & MPC52xx_PSC_D_CTS) | |
882 | uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS)); | |
883 | ||
1da177e4 | 884 | /* Limit number of iteration */ |
406b7d4f | 885 | if (!(--pass)) |
1da177e4 LT |
886 | keepgoing = 0; |
887 | ||
888 | } while (keepgoing); | |
9b9129e7 | 889 | |
1da177e4 | 890 | spin_unlock(&port->lock); |
9b9129e7 | 891 | |
1da177e4 LT |
892 | return IRQ_HANDLED; |
893 | } | |
894 | ||
895 | ||
896 | /* ======================================================================== */ | |
897 | /* Console ( if applicable ) */ | |
898 | /* ======================================================================== */ | |
899 | ||
900 | #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE | |
901 | ||
902 | static void __init | |
903 | mpc52xx_console_get_options(struct uart_port *port, | |
406b7d4f | 904 | int *baud, int *parity, int *bits, int *flow) |
1da177e4 LT |
905 | { |
906 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
907 | unsigned char mr1; | |
908 | ||
b9272dfd GL |
909 | pr_debug("mpc52xx_console_get_options(port=%p)\n", port); |
910 | ||
1da177e4 | 911 | /* Read the mode registers */ |
406b7d4f | 912 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); |
1da177e4 | 913 | mr1 = in_8(&psc->mode); |
9b9129e7 | 914 | |
1da177e4 | 915 | /* CT{U,L}R are write-only ! */ |
b9272dfd | 916 | *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; |
1da177e4 LT |
917 | |
918 | /* Parse them */ | |
919 | switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { | |
406b7d4f JR |
920 | case MPC52xx_PSC_MODE_5_BITS: |
921 | *bits = 5; | |
922 | break; | |
923 | case MPC52xx_PSC_MODE_6_BITS: | |
924 | *bits = 6; | |
925 | break; | |
926 | case MPC52xx_PSC_MODE_7_BITS: | |
927 | *bits = 7; | |
928 | break; | |
929 | case MPC52xx_PSC_MODE_8_BITS: | |
930 | default: | |
931 | *bits = 8; | |
1da177e4 | 932 | } |
9b9129e7 | 933 | |
1da177e4 LT |
934 | if (mr1 & MPC52xx_PSC_MODE_PARNONE) |
935 | *parity = 'n'; | |
936 | else | |
937 | *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; | |
938 | } | |
939 | ||
9b9129e7 | 940 | static void |
1da177e4 LT |
941 | mpc52xx_console_write(struct console *co, const char *s, unsigned int count) |
942 | { | |
943 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
1da177e4 | 944 | unsigned int i, j; |
9b9129e7 | 945 | |
1da177e4 | 946 | /* Disable interrupts */ |
599f030c | 947 | psc_ops->cw_disable_ints(port); |
1da177e4 LT |
948 | |
949 | /* Wait the TX buffer to be empty */ | |
9b9129e7 | 950 | j = 5000000; /* Maximum wait */ |
599f030c | 951 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
952 | udelay(1); |
953 | ||
954 | /* Write all the chars */ | |
d358788f | 955 | for (i = 0; i < count; i++, s++) { |
1da177e4 | 956 | /* Line return handling */ |
d358788f | 957 | if (*s == '\n') |
599f030c | 958 | psc_ops->write_char(port, '\r'); |
9b9129e7 | 959 | |
d358788f | 960 | /* Send the char */ |
599f030c | 961 | psc_ops->write_char(port, *s); |
d358788f | 962 | |
1da177e4 | 963 | /* Wait the TX buffer to be empty */ |
9b9129e7 | 964 | j = 20000; /* Maximum wait */ |
599f030c | 965 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
966 | udelay(1); |
967 | } | |
968 | ||
969 | /* Restore interrupt state */ | |
599f030c | 970 | psc_ops->cw_restore_ints(port); |
1da177e4 LT |
971 | } |
972 | ||
b9272dfd GL |
973 | |
974 | static int __init | |
975 | mpc52xx_console_setup(struct console *co, char *options) | |
976 | { | |
977 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
978 | struct device_node *np = mpc52xx_uart_nodes[co->index]; | |
599f030c | 979 | unsigned int uartclk; |
b9272dfd GL |
980 | struct resource res; |
981 | int ret; | |
982 | ||
983 | int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; | |
984 | int bits = 8; | |
985 | int parity = 'n'; | |
986 | int flow = 'n'; | |
987 | ||
988 | pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n", | |
989 | co, co->index, options); | |
990 | ||
991 | if ((co->index < 0) || (co->index > MPC52xx_PSC_MAXNUM)) { | |
992 | pr_debug("PSC%x out of range\n", co->index); | |
993 | return -EINVAL; | |
994 | } | |
995 | ||
996 | if (!np) { | |
997 | pr_debug("PSC%x not found in device tree\n", co->index); | |
998 | return -EINVAL; | |
999 | } | |
1000 | ||
1001 | pr_debug("Console on ttyPSC%x is %s\n", | |
406b7d4f | 1002 | co->index, mpc52xx_uart_nodes[co->index]->full_name); |
b9272dfd GL |
1003 | |
1004 | /* Fetch register locations */ | |
406b7d4f JR |
1005 | ret = of_address_to_resource(np, 0, &res); |
1006 | if (ret) { | |
b9272dfd GL |
1007 | pr_debug("Could not get resources for PSC%x\n", co->index); |
1008 | return ret; | |
1009 | } | |
1010 | ||
599f030c JR |
1011 | uartclk = psc_ops->getuartclk(np); |
1012 | if (uartclk == 0) { | |
1013 | pr_debug("Could not find uart clock frequency!\n"); | |
b9272dfd GL |
1014 | return -EINVAL; |
1015 | } | |
1016 | ||
1017 | /* Basic port init. Needed since we use some uart_??? func before | |
1018 | * real init for early access */ | |
1019 | spin_lock_init(&port->lock); | |
599f030c | 1020 | port->uartclk = uartclk; |
b9272dfd GL |
1021 | port->ops = &mpc52xx_uart_ops; |
1022 | port->mapbase = res.start; | |
1023 | port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); | |
1024 | port->irq = irq_of_parse_and_map(np, 0); | |
1025 | ||
1026 | if (port->membase == NULL) | |
1027 | return -EINVAL; | |
1028 | ||
5dd80d5d | 1029 | pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n", |
406b7d4f JR |
1030 | (void *)port->mapbase, port->membase, |
1031 | port->irq, port->uartclk); | |
b9272dfd GL |
1032 | |
1033 | /* Setup the port parameters accoding to options */ | |
1034 | if (options) | |
1035 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1036 | else | |
1037 | mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); | |
1038 | ||
1039 | pr_debug("Setting console parameters: %i %i%c1 flow=%c\n", | |
406b7d4f | 1040 | baud, bits, parity, flow); |
b9272dfd GL |
1041 | |
1042 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1043 | } | |
b9272dfd | 1044 | |
1da177e4 | 1045 | |
2d8179c0 | 1046 | static struct uart_driver mpc52xx_uart_driver; |
1da177e4 LT |
1047 | |
1048 | static struct console mpc52xx_console = { | |
d62de3aa | 1049 | .name = "ttyPSC", |
1da177e4 LT |
1050 | .write = mpc52xx_console_write, |
1051 | .device = uart_console_device, | |
1052 | .setup = mpc52xx_console_setup, | |
1053 | .flags = CON_PRINTBUFFER, | |
406b7d4f | 1054 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */ |
1da177e4 LT |
1055 | .data = &mpc52xx_uart_driver, |
1056 | }; | |
1057 | ||
9b9129e7 GL |
1058 | |
1059 | static int __init | |
1da177e4 LT |
1060 | mpc52xx_console_init(void) |
1061 | { | |
b9272dfd | 1062 | mpc52xx_uart_of_enumerate(); |
1da177e4 LT |
1063 | register_console(&mpc52xx_console); |
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | console_initcall(mpc52xx_console_init); | |
1068 | ||
1069 | #define MPC52xx_PSC_CONSOLE &mpc52xx_console | |
1070 | #else | |
1071 | #define MPC52xx_PSC_CONSOLE NULL | |
1072 | #endif | |
1073 | ||
1074 | ||
1075 | /* ======================================================================== */ | |
1076 | /* UART Driver */ | |
1077 | /* ======================================================================== */ | |
1078 | ||
1079 | static struct uart_driver mpc52xx_uart_driver = { | |
1da177e4 | 1080 | .driver_name = "mpc52xx_psc_uart", |
d62de3aa | 1081 | .dev_name = "ttyPSC", |
d62de3aa SM |
1082 | .major = SERIAL_PSC_MAJOR, |
1083 | .minor = SERIAL_PSC_MINOR, | |
1da177e4 LT |
1084 | .nr = MPC52xx_PSC_MAXNUM, |
1085 | .cons = MPC52xx_PSC_CONSOLE, | |
1086 | }; | |
1087 | ||
b9272dfd GL |
1088 | /* ======================================================================== */ |
1089 | /* OF Platform Driver */ | |
1090 | /* ======================================================================== */ | |
1091 | ||
52b80482 GL |
1092 | static struct of_device_id mpc52xx_uart_of_match[] = { |
1093 | #ifdef CONFIG_PPC_MPC52xx | |
1094 | { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, | |
1095 | /* binding used by old lite5200 device trees: */ | |
1096 | { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, | |
1097 | /* binding used by efika: */ | |
1098 | { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, }, | |
1099 | #endif | |
1100 | #ifdef CONFIG_PPC_MPC512x | |
1101 | { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, }, | |
52b80482 | 1102 | #endif |
bc775eac | 1103 | {}, |
52b80482 GL |
1104 | }; |
1105 | ||
b9272dfd GL |
1106 | static int __devinit |
1107 | mpc52xx_uart_of_probe(struct of_device *op, const struct of_device_id *match) | |
1108 | { | |
1109 | int idx = -1; | |
599f030c | 1110 | unsigned int uartclk; |
b9272dfd GL |
1111 | struct uart_port *port = NULL; |
1112 | struct resource res; | |
1113 | int ret; | |
1114 | ||
1115 | dev_dbg(&op->dev, "mpc52xx_uart_probe(op=%p, match=%p)\n", op, match); | |
1116 | ||
1117 | /* Check validity & presence */ | |
1118 | for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++) | |
1119 | if (mpc52xx_uart_nodes[idx] == op->node) | |
1120 | break; | |
1121 | if (idx >= MPC52xx_PSC_MAXNUM) | |
1122 | return -EINVAL; | |
1123 | pr_debug("Found %s assigned to ttyPSC%x\n", | |
406b7d4f | 1124 | mpc52xx_uart_nodes[idx]->full_name, idx); |
b9272dfd | 1125 | |
599f030c JR |
1126 | uartclk = psc_ops->getuartclk(op->node); |
1127 | if (uartclk == 0) { | |
1128 | dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); | |
b9272dfd GL |
1129 | return -EINVAL; |
1130 | } | |
1131 | ||
1132 | /* Init the port structure */ | |
1133 | port = &mpc52xx_uart_ports[idx]; | |
1134 | ||
1135 | spin_lock_init(&port->lock); | |
599f030c | 1136 | port->uartclk = uartclk; |
b9272dfd GL |
1137 | port->fifosize = 512; |
1138 | port->iotype = UPIO_MEM; | |
1139 | port->flags = UPF_BOOT_AUTOCONF | | |
406b7d4f | 1140 | (uart_console(port) ? 0 : UPF_IOREMAP); |
b9272dfd GL |
1141 | port->line = idx; |
1142 | port->ops = &mpc52xx_uart_ops; | |
1143 | port->dev = &op->dev; | |
1144 | ||
1145 | /* Search for IRQ and mapbase */ | |
406b7d4f JR |
1146 | ret = of_address_to_resource(op->node, 0, &res); |
1147 | if (ret) | |
b9272dfd GL |
1148 | return ret; |
1149 | ||
1150 | port->mapbase = res.start; | |
418441d9 WS |
1151 | if (!port->mapbase) { |
1152 | dev_dbg(&op->dev, "Could not allocate resources for PSC\n"); | |
1153 | return -EINVAL; | |
1154 | } | |
1155 | ||
b9272dfd | 1156 | port->irq = irq_of_parse_and_map(op->node, 0); |
418441d9 WS |
1157 | if (port->irq == NO_IRQ) { |
1158 | dev_dbg(&op->dev, "Could not get irq\n"); | |
1159 | return -EINVAL; | |
1160 | } | |
b9272dfd | 1161 | |
5dd80d5d | 1162 | dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n", |
406b7d4f | 1163 | (void *)port->mapbase, port->irq, port->uartclk); |
b9272dfd | 1164 | |
b9272dfd GL |
1165 | /* Add the port to the uart sub-system */ |
1166 | ret = uart_add_one_port(&mpc52xx_uart_driver, port); | |
418441d9 WS |
1167 | if (ret) { |
1168 | irq_dispose_mapping(port->irq); | |
1169 | return ret; | |
1170 | } | |
b9272dfd | 1171 | |
418441d9 WS |
1172 | dev_set_drvdata(&op->dev, (void *)port); |
1173 | return 0; | |
b9272dfd GL |
1174 | } |
1175 | ||
1176 | static int | |
1177 | mpc52xx_uart_of_remove(struct of_device *op) | |
1178 | { | |
1179 | struct uart_port *port = dev_get_drvdata(&op->dev); | |
1180 | dev_set_drvdata(&op->dev, NULL); | |
1181 | ||
fc7900bb | 1182 | if (port) { |
b9272dfd | 1183 | uart_remove_one_port(&mpc52xx_uart_driver, port); |
fc7900bb SM |
1184 | irq_dispose_mapping(port->irq); |
1185 | } | |
b9272dfd GL |
1186 | |
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | #ifdef CONFIG_PM | |
1191 | static int | |
1192 | mpc52xx_uart_of_suspend(struct of_device *op, pm_message_t state) | |
1193 | { | |
1194 | struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev); | |
1195 | ||
1196 | if (port) | |
1197 | uart_suspend_port(&mpc52xx_uart_driver, port); | |
1198 | ||
1199 | return 0; | |
1200 | } | |
1201 | ||
1202 | static int | |
1203 | mpc52xx_uart_of_resume(struct of_device *op) | |
1204 | { | |
1205 | struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev); | |
1206 | ||
1207 | if (port) | |
1208 | uart_resume_port(&mpc52xx_uart_driver, port); | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | #endif | |
1213 | ||
1214 | static void | |
3b5ebf8e | 1215 | mpc52xx_uart_of_assign(struct device_node *np) |
b9272dfd | 1216 | { |
b9272dfd GL |
1217 | int i; |
1218 | ||
3b5ebf8e | 1219 | /* Find the first free PSC number */ |
b9272dfd GL |
1220 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { |
1221 | if (mpc52xx_uart_nodes[i] == NULL) { | |
3b5ebf8e GL |
1222 | of_node_get(np); |
1223 | mpc52xx_uart_nodes[i] = np; | |
1224 | return; | |
b9272dfd GL |
1225 | } |
1226 | } | |
b9272dfd GL |
1227 | } |
1228 | ||
1229 | static void | |
1230 | mpc52xx_uart_of_enumerate(void) | |
1231 | { | |
406b7d4f | 1232 | static int enum_done; |
b9272dfd | 1233 | struct device_node *np; |
25ae3a07 | 1234 | const struct of_device_id *match; |
b9272dfd GL |
1235 | int i; |
1236 | ||
1237 | if (enum_done) | |
1238 | return; | |
1239 | ||
3b5ebf8e GL |
1240 | /* Assign index to each PSC in device tree */ |
1241 | for_each_matching_node(np, mpc52xx_uart_of_match) { | |
25ae3a07 | 1242 | match = of_match_node(mpc52xx_uart_of_match, np); |
25ae3a07 | 1243 | psc_ops = match->data; |
3b5ebf8e | 1244 | mpc52xx_uart_of_assign(np); |
b9272dfd GL |
1245 | } |
1246 | ||
1247 | enum_done = 1; | |
1248 | ||
1249 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { | |
1250 | if (mpc52xx_uart_nodes[i]) | |
1251 | pr_debug("%s assigned to ttyPSC%x\n", | |
406b7d4f | 1252 | mpc52xx_uart_nodes[i]->full_name, i); |
b9272dfd GL |
1253 | } |
1254 | } | |
1255 | ||
1256 | MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match); | |
1257 | ||
1258 | static struct of_platform_driver mpc52xx_uart_of_driver = { | |
b9272dfd GL |
1259 | .match_table = mpc52xx_uart_of_match, |
1260 | .probe = mpc52xx_uart_of_probe, | |
1261 | .remove = mpc52xx_uart_of_remove, | |
1262 | #ifdef CONFIG_PM | |
1263 | .suspend = mpc52xx_uart_of_suspend, | |
1264 | .resume = mpc52xx_uart_of_resume, | |
1265 | #endif | |
1266 | .driver = { | |
1267 | .name = "mpc52xx-psc-uart", | |
1268 | }, | |
1269 | }; | |
1da177e4 LT |
1270 | |
1271 | ||
1272 | /* ======================================================================== */ | |
1273 | /* Module */ | |
1274 | /* ======================================================================== */ | |
1275 | ||
1276 | static int __init | |
1277 | mpc52xx_uart_init(void) | |
1278 | { | |
1279 | int ret; | |
1280 | ||
b9272dfd | 1281 | printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n"); |
1da177e4 | 1282 | |
406b7d4f JR |
1283 | ret = uart_register_driver(&mpc52xx_uart_driver); |
1284 | if (ret) { | |
b9272dfd GL |
1285 | printk(KERN_ERR "%s: uart_register_driver failed (%i)\n", |
1286 | __FILE__, ret); | |
1287 | return ret; | |
1da177e4 LT |
1288 | } |
1289 | ||
b9272dfd GL |
1290 | mpc52xx_uart_of_enumerate(); |
1291 | ||
1292 | ret = of_register_platform_driver(&mpc52xx_uart_of_driver); | |
1293 | if (ret) { | |
1294 | printk(KERN_ERR "%s: of_register_platform_driver failed (%i)\n", | |
1295 | __FILE__, ret); | |
1296 | uart_unregister_driver(&mpc52xx_uart_driver); | |
1297 | return ret; | |
1298 | } | |
b9272dfd GL |
1299 | |
1300 | return 0; | |
1da177e4 LT |
1301 | } |
1302 | ||
1303 | static void __exit | |
1304 | mpc52xx_uart_exit(void) | |
1305 | { | |
b9272dfd | 1306 | of_unregister_platform_driver(&mpc52xx_uart_of_driver); |
1da177e4 LT |
1307 | uart_unregister_driver(&mpc52xx_uart_driver); |
1308 | } | |
1309 | ||
1310 | ||
1311 | module_init(mpc52xx_uart_init); | |
1312 | module_exit(mpc52xx_uart_exit); | |
1313 | ||
1314 | MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); | |
1315 | MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); | |
1316 | MODULE_LICENSE("GPL"); |