Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. |
3 | * | |
4 | * FIXME According to the usermanual the status bits in the status register | |
5 | * are only updated when the peripherals access the FIFO and not when the | |
6 | * CPU access them. So since we use this bits to know when we stop writing | |
7 | * and reading, they may not be updated in-time and a race condition may | |
8 | * exists. But I haven't be able to prove this and I don't care. But if | |
9 | * any problem arises, it might worth checking. The TX/RX FIFO Stats | |
10 | * registers should be used in addition. | |
11 | * Update: Actually, they seem updated ... At least the bits we use. | |
12 | * | |
13 | * | |
14 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | |
9b9129e7 | 15 | * |
1da177e4 LT |
16 | * Some of the code has been inspired/copied from the 2.4 code written |
17 | * by Dale Farnsworth <dfarnsworth@mvista.com>. | |
9b9129e7 | 18 | * |
25ae3a07 JR |
19 | * Copyright (C) 2008 Freescale Semiconductor Inc. |
20 | * John Rigby <jrigby@gmail.com> | |
21 | * Added support for MPC5121 | |
b9272dfd GL |
22 | * Copyright (C) 2006 Secret Lab Technologies Ltd. |
23 | * Grant Likely <grant.likely@secretlab.ca> | |
24 | * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> | |
1da177e4 | 25 | * Copyright (C) 2003 MontaVista, Software, Inc. |
9b9129e7 | 26 | * |
1da177e4 LT |
27 | * This file is licensed under the terms of the GNU General Public License |
28 | * version 2. This program is licensed "as is" without any warranty of any | |
29 | * kind, whether express or implied. | |
30 | */ | |
9b9129e7 | 31 | |
1da177e4 LT |
32 | /* Platform device Usage : |
33 | * | |
34 | * Since PSCs can have multiple function, the correct driver for each one | |
35 | * is selected by calling mpc52xx_match_psc_function(...). The function | |
36 | * handled by this driver is "uart". | |
37 | * | |
38 | * The driver init all necessary registers to place the PSC in uart mode without | |
39 | * DCD. However, the pin multiplexing aren't changed and should be set either | |
40 | * by the bootloader or in the platform init code. | |
41 | * | |
406b7d4f | 42 | * The idx field must be equal to the PSC index (e.g. 0 for PSC1, 1 for PSC2, |
d62de3aa SM |
43 | * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and |
44 | * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly | |
45 | * fpr the console code : without this 1:1 mapping, at early boot time, when we | |
c30fe7f7 | 46 | * are parsing the kernel args console=ttyPSC?, we wouldn't know which PSC it |
d62de3aa | 47 | * will be mapped to. |
1da177e4 LT |
48 | */ |
49 | ||
b9272dfd GL |
50 | /* OF Platform device Usage : |
51 | * | |
52 | * This driver is only used for PSCs configured in uart mode. The device | |
3b5ebf8e GL |
53 | * tree will have a node for each PSC with "mpc52xx-psc-uart" in the compatible |
54 | * list. | |
b9272dfd GL |
55 | * |
56 | * By default, PSC devices are enumerated in the order they are found. However | |
57 | * a particular PSC number can be forces by adding 'device_no = <port#>' | |
58 | * to the device node. | |
59 | * | |
60 | * The driver init all necessary registers to place the PSC in uart mode without | |
61 | * DCD. However, the pin multiplexing aren't changed and should be set either | |
62 | * by the bootloader or in the platform init code. | |
63 | */ | |
64 | ||
65 | #undef DEBUG | |
66 | ||
67 | #include <linux/device.h> | |
1da177e4 LT |
68 | #include <linux/module.h> |
69 | #include <linux/tty.h> | |
70 | #include <linux/serial.h> | |
71 | #include <linux/sysrq.h> | |
72 | #include <linux/console.h> | |
406b7d4f JR |
73 | #include <linux/delay.h> |
74 | #include <linux/io.h> | |
283029d1 GL |
75 | #include <linux/of.h> |
76 | #include <linux/of_platform.h> | |
6acc6833 | 77 | #include <linux/clk.h> |
b9272dfd | 78 | |
1da177e4 LT |
79 | #include <asm/mpc52xx.h> |
80 | #include <asm/mpc52xx_psc.h> | |
81 | ||
82 | #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
83 | #define SUPPORT_SYSRQ | |
84 | #endif | |
85 | ||
86 | #include <linux/serial_core.h> | |
87 | ||
88 | ||
d62de3aa SM |
89 | /* We've been assigned a range on the "Low-density serial ports" major */ |
90 | #define SERIAL_PSC_MAJOR 204 | |
91 | #define SERIAL_PSC_MINOR 148 | |
92 | ||
1da177e4 LT |
93 | |
94 | #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ | |
95 | ||
96 | ||
97 | static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; | |
98 | /* Rem: - We use the read_status_mask as a shadow of | |
99 | * psc->mpc52xx_psc_imr | |
100 | * - It's important that is array is all zero on start as we | |
101 | * use it to know if it's initialized or not ! If it's not sure | |
102 | * it's cleared, then a memset(...,0,...) should be added to | |
103 | * the console_init | |
104 | */ | |
8d1fb8cb | 105 | |
b9272dfd GL |
106 | /* lookup table for matching device nodes to index numbers */ |
107 | static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; | |
108 | ||
109 | static void mpc52xx_uart_of_enumerate(void); | |
1da177e4 | 110 | |
599f030c | 111 | |
1da177e4 LT |
112 | #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) |
113 | ||
114 | ||
115 | /* Forward declaration of the interruption handling routine */ | |
406b7d4f | 116 | static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); |
6acc6833 | 117 | static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port); |
1da177e4 LT |
118 | |
119 | ||
120 | /* Simple macro to test if a port is console or not. This one is taken | |
121 | * for serial_core.c and maybe should be moved to serial_core.h ? */ | |
122 | #ifdef CONFIG_SERIAL_CORE_CONSOLE | |
406b7d4f JR |
123 | #define uart_console(port) \ |
124 | ((port)->cons && (port)->cons->index == (port)->line) | |
1da177e4 LT |
125 | #else |
126 | #define uart_console(port) (0) | |
127 | #endif | |
128 | ||
599f030c JR |
129 | /* ======================================================================== */ |
130 | /* PSC fifo operations for isolating differences between 52xx and 512x */ | |
131 | /* ======================================================================== */ | |
132 | ||
133 | struct psc_ops { | |
134 | void (*fifo_init)(struct uart_port *port); | |
135 | int (*raw_rx_rdy)(struct uart_port *port); | |
136 | int (*raw_tx_rdy)(struct uart_port *port); | |
137 | int (*rx_rdy)(struct uart_port *port); | |
138 | int (*tx_rdy)(struct uart_port *port); | |
139 | int (*tx_empty)(struct uart_port *port); | |
140 | void (*stop_rx)(struct uart_port *port); | |
141 | void (*start_tx)(struct uart_port *port); | |
142 | void (*stop_tx)(struct uart_port *port); | |
143 | void (*rx_clr_irq)(struct uart_port *port); | |
144 | void (*tx_clr_irq)(struct uart_port *port); | |
145 | void (*write_char)(struct uart_port *port, unsigned char c); | |
146 | unsigned char (*read_char)(struct uart_port *port); | |
147 | void (*cw_disable_ints)(struct uart_port *port); | |
148 | void (*cw_restore_ints)(struct uart_port *port); | |
149 | unsigned long (*getuartclk)(void *p); | |
6acc6833 AG |
150 | int (*clock)(struct uart_port *port, int enable); |
151 | int (*fifoc_init)(void); | |
152 | void (*fifoc_uninit)(void); | |
153 | void (*get_irq)(struct uart_port *, struct device_node *); | |
154 | irqreturn_t (*handle_irq)(struct uart_port *port); | |
599f030c JR |
155 | }; |
156 | ||
25ae3a07 | 157 | #ifdef CONFIG_PPC_MPC52xx |
599f030c JR |
158 | #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) |
159 | static void mpc52xx_psc_fifo_init(struct uart_port *port) | |
160 | { | |
161 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
162 | struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); | |
163 | ||
164 | /* /32 prescaler */ | |
165 | out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00); | |
166 | ||
167 | out_8(&fifo->rfcntl, 0x00); | |
168 | out_be16(&fifo->rfalarm, 0x1ff); | |
169 | out_8(&fifo->tfcntl, 0x07); | |
170 | out_be16(&fifo->tfalarm, 0x80); | |
171 | ||
172 | port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; | |
173 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
174 | } | |
175 | ||
176 | static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) | |
177 | { | |
178 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
179 | & MPC52xx_PSC_SR_RXRDY; | |
180 | } | |
181 | ||
182 | static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) | |
183 | { | |
184 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
185 | & MPC52xx_PSC_SR_TXRDY; | |
186 | } | |
187 | ||
188 | ||
189 | static int mpc52xx_psc_rx_rdy(struct uart_port *port) | |
190 | { | |
191 | return in_be16(&PSC(port)->mpc52xx_psc_isr) | |
192 | & port->read_status_mask | |
193 | & MPC52xx_PSC_IMR_RXRDY; | |
194 | } | |
195 | ||
196 | static int mpc52xx_psc_tx_rdy(struct uart_port *port) | |
197 | { | |
198 | return in_be16(&PSC(port)->mpc52xx_psc_isr) | |
199 | & port->read_status_mask | |
200 | & MPC52xx_PSC_IMR_TXRDY; | |
201 | } | |
202 | ||
203 | static int mpc52xx_psc_tx_empty(struct uart_port *port) | |
204 | { | |
205 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
206 | & MPC52xx_PSC_SR_TXEMP; | |
207 | } | |
208 | ||
209 | static void mpc52xx_psc_start_tx(struct uart_port *port) | |
210 | { | |
211 | port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; | |
212 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
213 | } | |
214 | ||
215 | static void mpc52xx_psc_stop_tx(struct uart_port *port) | |
216 | { | |
217 | port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; | |
218 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
219 | } | |
220 | ||
221 | static void mpc52xx_psc_stop_rx(struct uart_port *port) | |
222 | { | |
223 | port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; | |
224 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
225 | } | |
226 | ||
227 | static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) | |
228 | { | |
229 | } | |
230 | ||
231 | static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) | |
232 | { | |
233 | } | |
234 | ||
235 | static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) | |
236 | { | |
237 | out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); | |
238 | } | |
239 | ||
240 | static unsigned char mpc52xx_psc_read_char(struct uart_port *port) | |
241 | { | |
242 | return in_8(&PSC(port)->mpc52xx_psc_buffer_8); | |
243 | } | |
244 | ||
245 | static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) | |
246 | { | |
247 | out_be16(&PSC(port)->mpc52xx_psc_imr, 0); | |
248 | } | |
249 | ||
250 | static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) | |
251 | { | |
252 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
253 | } | |
254 | ||
255 | /* Search for bus-frequency property in this node or a parent */ | |
256 | static unsigned long mpc52xx_getuartclk(void *p) | |
257 | { | |
599f030c JR |
258 | /* |
259 | * 5200 UARTs have a / 32 prescaler | |
260 | * but the generic serial code assumes 16 | |
261 | * so return ipb freq / 2 | |
262 | */ | |
87c441e5 | 263 | return mpc5xxx_get_bus_frequency(p) / 2; |
599f030c JR |
264 | } |
265 | ||
6acc6833 AG |
266 | static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np) |
267 | { | |
268 | port->irqflags = IRQF_DISABLED; | |
269 | port->irq = irq_of_parse_and_map(np, 0); | |
270 | } | |
271 | ||
272 | /* 52xx specific interrupt handler. The caller holds the port lock */ | |
273 | static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port) | |
274 | { | |
275 | return mpc5xxx_uart_process_int(port); | |
276 | } | |
277 | ||
599f030c JR |
278 | static struct psc_ops mpc52xx_psc_ops = { |
279 | .fifo_init = mpc52xx_psc_fifo_init, | |
280 | .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, | |
281 | .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, | |
282 | .rx_rdy = mpc52xx_psc_rx_rdy, | |
283 | .tx_rdy = mpc52xx_psc_tx_rdy, | |
284 | .tx_empty = mpc52xx_psc_tx_empty, | |
285 | .stop_rx = mpc52xx_psc_stop_rx, | |
286 | .start_tx = mpc52xx_psc_start_tx, | |
287 | .stop_tx = mpc52xx_psc_stop_tx, | |
288 | .rx_clr_irq = mpc52xx_psc_rx_clr_irq, | |
289 | .tx_clr_irq = mpc52xx_psc_tx_clr_irq, | |
290 | .write_char = mpc52xx_psc_write_char, | |
291 | .read_char = mpc52xx_psc_read_char, | |
292 | .cw_disable_ints = mpc52xx_psc_cw_disable_ints, | |
293 | .cw_restore_ints = mpc52xx_psc_cw_restore_ints, | |
294 | .getuartclk = mpc52xx_getuartclk, | |
6acc6833 AG |
295 | .get_irq = mpc52xx_psc_get_irq, |
296 | .handle_irq = mpc52xx_psc_handle_irq, | |
599f030c JR |
297 | }; |
298 | ||
25ae3a07 JR |
299 | #endif /* CONFIG_MPC52xx */ |
300 | ||
301 | #ifdef CONFIG_PPC_MPC512x | |
302 | #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) | |
6acc6833 AG |
303 | |
304 | /* PSC FIFO Controller for mpc512x */ | |
305 | struct psc_fifoc { | |
306 | u32 fifoc_cmd; | |
307 | u32 fifoc_int; | |
308 | u32 fifoc_dma; | |
309 | u32 fifoc_axe; | |
310 | u32 fifoc_debug; | |
311 | }; | |
312 | ||
313 | static struct psc_fifoc __iomem *psc_fifoc; | |
314 | static unsigned int psc_fifoc_irq; | |
315 | ||
25ae3a07 JR |
316 | static void mpc512x_psc_fifo_init(struct uart_port *port) |
317 | { | |
6acc6833 AG |
318 | /* /32 prescaler */ |
319 | out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00); | |
320 | ||
25ae3a07 JR |
321 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); |
322 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
323 | out_be32(&FIFO_512x(port)->txalarm, 1); | |
324 | out_be32(&FIFO_512x(port)->tximr, 0); | |
325 | ||
326 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); | |
327 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
328 | out_be32(&FIFO_512x(port)->rxalarm, 1); | |
329 | out_be32(&FIFO_512x(port)->rximr, 0); | |
330 | ||
331 | out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); | |
332 | out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); | |
333 | } | |
334 | ||
335 | static int mpc512x_psc_raw_rx_rdy(struct uart_port *port) | |
336 | { | |
337 | return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); | |
338 | } | |
339 | ||
340 | static int mpc512x_psc_raw_tx_rdy(struct uart_port *port) | |
341 | { | |
342 | return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); | |
343 | } | |
344 | ||
345 | static int mpc512x_psc_rx_rdy(struct uart_port *port) | |
346 | { | |
347 | return in_be32(&FIFO_512x(port)->rxsr) | |
348 | & in_be32(&FIFO_512x(port)->rximr) | |
349 | & MPC512x_PSC_FIFO_ALARM; | |
350 | } | |
351 | ||
352 | static int mpc512x_psc_tx_rdy(struct uart_port *port) | |
353 | { | |
354 | return in_be32(&FIFO_512x(port)->txsr) | |
355 | & in_be32(&FIFO_512x(port)->tximr) | |
356 | & MPC512x_PSC_FIFO_ALARM; | |
357 | } | |
358 | ||
359 | static int mpc512x_psc_tx_empty(struct uart_port *port) | |
360 | { | |
361 | return in_be32(&FIFO_512x(port)->txsr) | |
362 | & MPC512x_PSC_FIFO_EMPTY; | |
363 | } | |
364 | ||
365 | static void mpc512x_psc_stop_rx(struct uart_port *port) | |
366 | { | |
367 | unsigned long rx_fifo_imr; | |
368 | ||
369 | rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); | |
370 | rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
371 | out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); | |
372 | } | |
373 | ||
374 | static void mpc512x_psc_start_tx(struct uart_port *port) | |
375 | { | |
376 | unsigned long tx_fifo_imr; | |
377 | ||
378 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); | |
379 | tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; | |
380 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); | |
381 | } | |
382 | ||
383 | static void mpc512x_psc_stop_tx(struct uart_port *port) | |
384 | { | |
385 | unsigned long tx_fifo_imr; | |
386 | ||
387 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); | |
388 | tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
389 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); | |
390 | } | |
391 | ||
392 | static void mpc512x_psc_rx_clr_irq(struct uart_port *port) | |
393 | { | |
394 | out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); | |
395 | } | |
396 | ||
397 | static void mpc512x_psc_tx_clr_irq(struct uart_port *port) | |
398 | { | |
399 | out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); | |
400 | } | |
401 | ||
402 | static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) | |
403 | { | |
404 | out_8(&FIFO_512x(port)->txdata_8, c); | |
405 | } | |
406 | ||
407 | static unsigned char mpc512x_psc_read_char(struct uart_port *port) | |
408 | { | |
409 | return in_8(&FIFO_512x(port)->rxdata_8); | |
410 | } | |
411 | ||
412 | static void mpc512x_psc_cw_disable_ints(struct uart_port *port) | |
413 | { | |
414 | port->read_status_mask = | |
415 | in_be32(&FIFO_512x(port)->tximr) << 16 | | |
416 | in_be32(&FIFO_512x(port)->rximr); | |
417 | out_be32(&FIFO_512x(port)->tximr, 0); | |
418 | out_be32(&FIFO_512x(port)->rximr, 0); | |
419 | } | |
420 | ||
421 | static void mpc512x_psc_cw_restore_ints(struct uart_port *port) | |
422 | { | |
423 | out_be32(&FIFO_512x(port)->tximr, | |
424 | (port->read_status_mask >> 16) & 0x7f); | |
425 | out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); | |
426 | } | |
427 | ||
428 | static unsigned long mpc512x_getuartclk(void *p) | |
429 | { | |
87c441e5 | 430 | return mpc5xxx_get_bus_frequency(p); |
25ae3a07 JR |
431 | } |
432 | ||
6acc6833 AG |
433 | #define DEFAULT_FIFO_SIZE 16 |
434 | ||
435 | static unsigned int __init get_fifo_size(struct device_node *np, | |
436 | char *fifo_name) | |
437 | { | |
438 | const unsigned int *fp; | |
439 | ||
440 | fp = of_get_property(np, fifo_name, NULL); | |
441 | if (fp) | |
442 | return *fp; | |
443 | ||
444 | pr_warning("no %s property in %s node, defaulting to %d\n", | |
445 | fifo_name, np->full_name, DEFAULT_FIFO_SIZE); | |
446 | ||
447 | return DEFAULT_FIFO_SIZE; | |
448 | } | |
449 | ||
450 | #define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \ | |
451 | ((u32)(_base) + sizeof(struct mpc52xx_psc))) | |
452 | ||
453 | /* Init PSC FIFO Controller */ | |
454 | static int __init mpc512x_psc_fifoc_init(void) | |
455 | { | |
456 | struct device_node *np; | |
457 | void __iomem *psc; | |
458 | unsigned int tx_fifo_size; | |
459 | unsigned int rx_fifo_size; | |
460 | int fifobase = 0; /* current fifo address in 32 bit words */ | |
461 | ||
462 | np = of_find_compatible_node(NULL, NULL, | |
463 | "fsl,mpc5121-psc-fifo"); | |
464 | if (!np) { | |
465 | pr_err("%s: Can't find FIFOC node\n", __func__); | |
466 | return -ENODEV; | |
467 | } | |
468 | ||
469 | psc_fifoc = of_iomap(np, 0); | |
470 | if (!psc_fifoc) { | |
471 | pr_err("%s: Can't map FIFOC\n", __func__); | |
472 | return -ENODEV; | |
473 | } | |
474 | ||
475 | psc_fifoc_irq = irq_of_parse_and_map(np, 0); | |
476 | of_node_put(np); | |
477 | if (psc_fifoc_irq == NO_IRQ) { | |
478 | pr_err("%s: Can't get FIFOC irq\n", __func__); | |
479 | iounmap(psc_fifoc); | |
480 | return -ENODEV; | |
481 | } | |
482 | ||
483 | for_each_compatible_node(np, NULL, "fsl,mpc5121-psc-uart") { | |
484 | tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size"); | |
485 | rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size"); | |
486 | ||
487 | /* size in register is in 4 byte units */ | |
488 | tx_fifo_size /= 4; | |
489 | rx_fifo_size /= 4; | |
490 | if (!tx_fifo_size) | |
491 | tx_fifo_size = 1; | |
492 | if (!rx_fifo_size) | |
493 | rx_fifo_size = 1; | |
494 | ||
495 | psc = of_iomap(np, 0); | |
496 | if (!psc) { | |
497 | pr_err("%s: Can't map %s device\n", | |
498 | __func__, np->full_name); | |
499 | continue; | |
500 | } | |
501 | ||
502 | /* FIFO space is 4KiB, check if requested size is available */ | |
503 | if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) { | |
504 | pr_err("%s: no fifo space available for %s\n", | |
505 | __func__, np->full_name); | |
506 | iounmap(psc); | |
507 | /* | |
508 | * chances are that another device requests less | |
509 | * fifo space, so we continue. | |
510 | */ | |
511 | continue; | |
512 | } | |
513 | /* set tx and rx fifo size registers */ | |
514 | out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size); | |
515 | fifobase += tx_fifo_size; | |
516 | out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size); | |
517 | fifobase += rx_fifo_size; | |
518 | ||
519 | /* reset and enable the slices */ | |
520 | out_be32(&FIFOC(psc)->txcmd, 0x80); | |
521 | out_be32(&FIFOC(psc)->txcmd, 0x01); | |
522 | out_be32(&FIFOC(psc)->rxcmd, 0x80); | |
523 | out_be32(&FIFOC(psc)->rxcmd, 0x01); | |
524 | ||
525 | iounmap(psc); | |
526 | } | |
527 | ||
528 | return 0; | |
529 | } | |
530 | ||
531 | static void __exit mpc512x_psc_fifoc_uninit(void) | |
532 | { | |
533 | iounmap(psc_fifoc); | |
534 | } | |
535 | ||
536 | /* 512x specific interrupt handler. The caller holds the port lock */ | |
537 | static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port) | |
538 | { | |
539 | unsigned long fifoc_int; | |
540 | int psc_num; | |
541 | ||
542 | /* Read pending PSC FIFOC interrupts */ | |
543 | fifoc_int = in_be32(&psc_fifoc->fifoc_int); | |
544 | ||
545 | /* Check if it is an interrupt for this port */ | |
546 | psc_num = (port->mapbase & 0xf00) >> 8; | |
547 | if (test_bit(psc_num, &fifoc_int) || | |
548 | test_bit(psc_num + 16, &fifoc_int)) | |
549 | return mpc5xxx_uart_process_int(port); | |
550 | ||
551 | return IRQ_NONE; | |
552 | } | |
553 | ||
554 | static int mpc512x_psc_clock(struct uart_port *port, int enable) | |
555 | { | |
556 | struct clk *psc_clk; | |
557 | int psc_num; | |
558 | char clk_name[10]; | |
559 | ||
560 | if (uart_console(port)) | |
561 | return 0; | |
562 | ||
563 | psc_num = (port->mapbase & 0xf00) >> 8; | |
564 | snprintf(clk_name, sizeof(clk_name), "psc%d_clk", psc_num); | |
565 | psc_clk = clk_get(port->dev, clk_name); | |
566 | if (IS_ERR(psc_clk)) { | |
567 | dev_err(port->dev, "Failed to get PSC clock entry!\n"); | |
568 | return -ENODEV; | |
569 | } | |
570 | ||
571 | dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis"); | |
572 | ||
573 | if (enable) | |
574 | clk_enable(psc_clk); | |
575 | else | |
576 | clk_disable(psc_clk); | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
581 | static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np) | |
582 | { | |
583 | port->irqflags = IRQF_SHARED; | |
584 | port->irq = psc_fifoc_irq; | |
585 | } | |
586 | ||
25ae3a07 JR |
587 | static struct psc_ops mpc512x_psc_ops = { |
588 | .fifo_init = mpc512x_psc_fifo_init, | |
589 | .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, | |
590 | .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, | |
591 | .rx_rdy = mpc512x_psc_rx_rdy, | |
592 | .tx_rdy = mpc512x_psc_tx_rdy, | |
593 | .tx_empty = mpc512x_psc_tx_empty, | |
594 | .stop_rx = mpc512x_psc_stop_rx, | |
595 | .start_tx = mpc512x_psc_start_tx, | |
596 | .stop_tx = mpc512x_psc_stop_tx, | |
597 | .rx_clr_irq = mpc512x_psc_rx_clr_irq, | |
598 | .tx_clr_irq = mpc512x_psc_tx_clr_irq, | |
599 | .write_char = mpc512x_psc_write_char, | |
600 | .read_char = mpc512x_psc_read_char, | |
601 | .cw_disable_ints = mpc512x_psc_cw_disable_ints, | |
602 | .cw_restore_ints = mpc512x_psc_cw_restore_ints, | |
603 | .getuartclk = mpc512x_getuartclk, | |
6acc6833 AG |
604 | .clock = mpc512x_psc_clock, |
605 | .fifoc_init = mpc512x_psc_fifoc_init, | |
606 | .fifoc_uninit = mpc512x_psc_fifoc_uninit, | |
607 | .get_irq = mpc512x_psc_get_irq, | |
608 | .handle_irq = mpc512x_psc_handle_irq, | |
25ae3a07 JR |
609 | }; |
610 | #endif | |
611 | ||
612 | static struct psc_ops *psc_ops; | |
1da177e4 LT |
613 | |
614 | /* ======================================================================== */ | |
615 | /* UART operations */ | |
616 | /* ======================================================================== */ | |
617 | ||
9b9129e7 | 618 | static unsigned int |
1da177e4 LT |
619 | mpc52xx_uart_tx_empty(struct uart_port *port) |
620 | { | |
599f030c | 621 | return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; |
1da177e4 LT |
622 | } |
623 | ||
9b9129e7 | 624 | static void |
1da177e4 LT |
625 | mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
626 | { | |
aec739e0 WS |
627 | if (mctrl & TIOCM_RTS) |
628 | out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); | |
629 | else | |
630 | out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); | |
1da177e4 LT |
631 | } |
632 | ||
9b9129e7 | 633 | static unsigned int |
1da177e4 LT |
634 | mpc52xx_uart_get_mctrl(struct uart_port *port) |
635 | { | |
aec739e0 WS |
636 | unsigned int ret = TIOCM_DSR; |
637 | u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr); | |
638 | ||
639 | if (!(status & MPC52xx_PSC_CTS)) | |
640 | ret |= TIOCM_CTS; | |
641 | if (!(status & MPC52xx_PSC_DCD)) | |
642 | ret |= TIOCM_CAR; | |
643 | ||
644 | return ret; | |
1da177e4 LT |
645 | } |
646 | ||
9b9129e7 | 647 | static void |
b129a8cc | 648 | mpc52xx_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
649 | { |
650 | /* port->lock taken by caller */ | |
599f030c | 651 | psc_ops->stop_tx(port); |
1da177e4 LT |
652 | } |
653 | ||
9b9129e7 | 654 | static void |
b129a8cc | 655 | mpc52xx_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
656 | { |
657 | /* port->lock taken by caller */ | |
599f030c | 658 | psc_ops->start_tx(port); |
1da177e4 LT |
659 | } |
660 | ||
9b9129e7 | 661 | static void |
1da177e4 LT |
662 | mpc52xx_uart_send_xchar(struct uart_port *port, char ch) |
663 | { | |
664 | unsigned long flags; | |
665 | spin_lock_irqsave(&port->lock, flags); | |
9b9129e7 | 666 | |
1da177e4 LT |
667 | port->x_char = ch; |
668 | if (ch) { | |
669 | /* Make sure tx interrupts are on */ | |
670 | /* Truly necessary ??? They should be anyway */ | |
599f030c | 671 | psc_ops->start_tx(port); |
1da177e4 | 672 | } |
9b9129e7 | 673 | |
1da177e4 LT |
674 | spin_unlock_irqrestore(&port->lock, flags); |
675 | } | |
676 | ||
677 | static void | |
678 | mpc52xx_uart_stop_rx(struct uart_port *port) | |
679 | { | |
680 | /* port->lock taken by caller */ | |
599f030c | 681 | psc_ops->stop_rx(port); |
1da177e4 LT |
682 | } |
683 | ||
684 | static void | |
685 | mpc52xx_uart_enable_ms(struct uart_port *port) | |
686 | { | |
aec739e0 WS |
687 | struct mpc52xx_psc __iomem *psc = PSC(port); |
688 | ||
689 | /* clear D_*-bits by reading them */ | |
690 | in_8(&psc->mpc52xx_psc_ipcr); | |
691 | /* enable CTS and DCD as IPC interrupts */ | |
692 | out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); | |
693 | ||
694 | port->read_status_mask |= MPC52xx_PSC_IMR_IPC; | |
695 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
1da177e4 LT |
696 | } |
697 | ||
698 | static void | |
699 | mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) | |
700 | { | |
701 | unsigned long flags; | |
702 | spin_lock_irqsave(&port->lock, flags); | |
703 | ||
406b7d4f JR |
704 | if (ctl == -1) |
705 | out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK); | |
1da177e4 | 706 | else |
406b7d4f | 707 | out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK); |
9b9129e7 | 708 | |
1da177e4 LT |
709 | spin_unlock_irqrestore(&port->lock, flags); |
710 | } | |
711 | ||
712 | static int | |
713 | mpc52xx_uart_startup(struct uart_port *port) | |
714 | { | |
715 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
716 | int ret; | |
717 | ||
6acc6833 AG |
718 | if (psc_ops->clock) { |
719 | ret = psc_ops->clock(port, 1); | |
720 | if (ret) | |
721 | return ret; | |
722 | } | |
723 | ||
1da177e4 LT |
724 | /* Request IRQ */ |
725 | ret = request_irq(port->irq, mpc52xx_uart_int, | |
6acc6833 | 726 | port->irqflags, "mpc52xx_psc_uart", port); |
1da177e4 LT |
727 | if (ret) |
728 | return ret; | |
729 | ||
730 | /* Reset/activate the port, clear and enable interrupts */ | |
406b7d4f JR |
731 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
732 | out_8(&psc->command, MPC52xx_PSC_RST_TX); | |
9b9129e7 | 733 | |
406b7d4f | 734 | out_be32(&psc->sicr, 0); /* UART mode DCD ignored */ |
1da177e4 | 735 | |
599f030c | 736 | psc_ops->fifo_init(port); |
9b9129e7 | 737 | |
406b7d4f JR |
738 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE); |
739 | out_8(&psc->command, MPC52xx_PSC_RX_ENABLE); | |
9b9129e7 | 740 | |
1da177e4 LT |
741 | return 0; |
742 | } | |
743 | ||
744 | static void | |
745 | mpc52xx_uart_shutdown(struct uart_port *port) | |
746 | { | |
747 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
9b9129e7 | 748 | |
a3481197 | 749 | /* Shut down the port. Leave TX active if on a console port */ |
406b7d4f | 750 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
a3481197 | 751 | if (!uart_console(port)) |
406b7d4f | 752 | out_8(&psc->command, MPC52xx_PSC_RST_TX); |
9b9129e7 GL |
753 | |
754 | port->read_status_mask = 0; | |
406b7d4f | 755 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); |
1da177e4 | 756 | |
6acc6833 AG |
757 | if (psc_ops->clock) |
758 | psc_ops->clock(port, 0); | |
759 | ||
1da177e4 LT |
760 | /* Release interrupt */ |
761 | free_irq(port->irq, port); | |
762 | } | |
763 | ||
9b9129e7 | 764 | static void |
606d099c | 765 | mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, |
406b7d4f | 766 | struct ktermios *old) |
1da177e4 LT |
767 | { |
768 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
769 | unsigned long flags; | |
770 | unsigned char mr1, mr2; | |
771 | unsigned short ctr; | |
772 | unsigned int j, baud, quot; | |
9b9129e7 | 773 | |
1da177e4 LT |
774 | /* Prepare what we're gonna write */ |
775 | mr1 = 0; | |
9b9129e7 | 776 | |
1da177e4 | 777 | switch (new->c_cflag & CSIZE) { |
406b7d4f JR |
778 | case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; |
779 | break; | |
780 | case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; | |
781 | break; | |
782 | case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; | |
783 | break; | |
784 | case CS8: | |
785 | default: mr1 |= MPC52xx_PSC_MODE_8_BITS; | |
1da177e4 LT |
786 | } |
787 | ||
788 | if (new->c_cflag & PARENB) { | |
789 | mr1 |= (new->c_cflag & PARODD) ? | |
790 | MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; | |
791 | } else | |
792 | mr1 |= MPC52xx_PSC_MODE_PARNONE; | |
9b9129e7 GL |
793 | |
794 | ||
1da177e4 LT |
795 | mr2 = 0; |
796 | ||
797 | if (new->c_cflag & CSTOPB) | |
798 | mr2 |= MPC52xx_PSC_MODE_TWO_STOP; | |
799 | else | |
800 | mr2 |= ((new->c_cflag & CSIZE) == CS5) ? | |
801 | MPC52xx_PSC_MODE_ONE_STOP_5_BITS : | |
802 | MPC52xx_PSC_MODE_ONE_STOP; | |
803 | ||
aec739e0 WS |
804 | if (new->c_cflag & CRTSCTS) { |
805 | mr1 |= MPC52xx_PSC_MODE_RXRTS; | |
806 | mr2 |= MPC52xx_PSC_MODE_TXCTS; | |
807 | } | |
1da177e4 LT |
808 | |
809 | baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16); | |
810 | quot = uart_get_divisor(port, baud); | |
811 | ctr = quot & 0xffff; | |
9b9129e7 | 812 | |
1da177e4 LT |
813 | /* Get the lock */ |
814 | spin_lock_irqsave(&port->lock, flags); | |
815 | ||
816 | /* Update the per-port timeout */ | |
817 | uart_update_timeout(port, new->c_cflag, baud); | |
818 | ||
c4f01240 NA |
819 | /* Do our best to flush TX & RX, so we don't lose anything */ |
820 | /* But we don't wait indefinitely ! */ | |
1da177e4 LT |
821 | j = 5000000; /* Maximum wait */ |
822 | /* FIXME Can't receive chars since set_termios might be called at early | |
823 | * boot for the console, all stuff is not yet ready to receive at that | |
824 | * time and that just makes the kernel oops */ | |
825 | /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ | |
599f030c | 826 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
827 | udelay(1); |
828 | ||
829 | if (!j) | |
406b7d4f | 830 | printk(KERN_ERR "mpc52xx_uart.c: " |
1da177e4 | 831 | "Unable to flush RX & TX fifos in-time in set_termios." |
406b7d4f | 832 | "Some chars may have been lost.\n"); |
1da177e4 LT |
833 | |
834 | /* Reset the TX & RX */ | |
406b7d4f JR |
835 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
836 | out_8(&psc->command, MPC52xx_PSC_RST_TX); | |
1da177e4 LT |
837 | |
838 | /* Send new mode settings */ | |
406b7d4f JR |
839 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); |
840 | out_8(&psc->mode, mr1); | |
841 | out_8(&psc->mode, mr2); | |
842 | out_8(&psc->ctur, ctr >> 8); | |
843 | out_8(&psc->ctlr, ctr & 0xff); | |
9b9129e7 | 844 | |
aec739e0 WS |
845 | if (UART_ENABLE_MS(port, new->c_cflag)) |
846 | mpc52xx_uart_enable_ms(port); | |
847 | ||
1da177e4 | 848 | /* Reenable TX & RX */ |
406b7d4f JR |
849 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE); |
850 | out_8(&psc->command, MPC52xx_PSC_RX_ENABLE); | |
1da177e4 LT |
851 | |
852 | /* We're all set, release the lock */ | |
853 | spin_unlock_irqrestore(&port->lock, flags); | |
854 | } | |
855 | ||
856 | static const char * | |
857 | mpc52xx_uart_type(struct uart_port *port) | |
858 | { | |
859 | return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL; | |
860 | } | |
861 | ||
862 | static void | |
863 | mpc52xx_uart_release_port(struct uart_port *port) | |
864 | { | |
406b7d4f JR |
865 | /* remapped by us ? */ |
866 | if (port->flags & UPF_IOREMAP) { | |
1da177e4 LT |
867 | iounmap(port->membase); |
868 | port->membase = NULL; | |
869 | } | |
870 | ||
b9272dfd | 871 | release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); |
1da177e4 LT |
872 | } |
873 | ||
874 | static int | |
875 | mpc52xx_uart_request_port(struct uart_port *port) | |
876 | { | |
be618f55 AL |
877 | int err; |
878 | ||
1da177e4 | 879 | if (port->flags & UPF_IOREMAP) /* Need to remap ? */ |
b9272dfd | 880 | port->membase = ioremap(port->mapbase, |
406b7d4f | 881 | sizeof(struct mpc52xx_psc)); |
1da177e4 LT |
882 | |
883 | if (!port->membase) | |
884 | return -EINVAL; | |
885 | ||
b9272dfd | 886 | err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc), |
1da177e4 | 887 | "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; |
be618f55 AL |
888 | |
889 | if (err && (port->flags & UPF_IOREMAP)) { | |
890 | iounmap(port->membase); | |
891 | port->membase = NULL; | |
892 | } | |
893 | ||
894 | return err; | |
1da177e4 LT |
895 | } |
896 | ||
897 | static void | |
898 | mpc52xx_uart_config_port(struct uart_port *port, int flags) | |
899 | { | |
406b7d4f JR |
900 | if ((flags & UART_CONFIG_TYPE) |
901 | && (mpc52xx_uart_request_port(port) == 0)) | |
902 | port->type = PORT_MPC52xx; | |
1da177e4 LT |
903 | } |
904 | ||
905 | static int | |
906 | mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) | |
907 | { | |
406b7d4f | 908 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx) |
1da177e4 LT |
909 | return -EINVAL; |
910 | ||
406b7d4f | 911 | if ((ser->irq != port->irq) || |
b7a8212c | 912 | (ser->io_type != UPIO_MEM) || |
406b7d4f JR |
913 | (ser->baud_base != port->uartclk) || |
914 | (ser->iomem_base != (void *)port->mapbase) || | |
915 | (ser->hub6 != 0)) | |
1da177e4 LT |
916 | return -EINVAL; |
917 | ||
918 | return 0; | |
919 | } | |
920 | ||
921 | ||
922 | static struct uart_ops mpc52xx_uart_ops = { | |
923 | .tx_empty = mpc52xx_uart_tx_empty, | |
924 | .set_mctrl = mpc52xx_uart_set_mctrl, | |
925 | .get_mctrl = mpc52xx_uart_get_mctrl, | |
926 | .stop_tx = mpc52xx_uart_stop_tx, | |
927 | .start_tx = mpc52xx_uart_start_tx, | |
928 | .send_xchar = mpc52xx_uart_send_xchar, | |
929 | .stop_rx = mpc52xx_uart_stop_rx, | |
930 | .enable_ms = mpc52xx_uart_enable_ms, | |
931 | .break_ctl = mpc52xx_uart_break_ctl, | |
932 | .startup = mpc52xx_uart_startup, | |
933 | .shutdown = mpc52xx_uart_shutdown, | |
934 | .set_termios = mpc52xx_uart_set_termios, | |
935 | /* .pm = mpc52xx_uart_pm, Not supported yet */ | |
936 | /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */ | |
937 | .type = mpc52xx_uart_type, | |
938 | .release_port = mpc52xx_uart_release_port, | |
939 | .request_port = mpc52xx_uart_request_port, | |
940 | .config_port = mpc52xx_uart_config_port, | |
941 | .verify_port = mpc52xx_uart_verify_port | |
942 | }; | |
943 | ||
9b9129e7 | 944 | |
1da177e4 LT |
945 | /* ======================================================================== */ |
946 | /* Interrupt handling */ | |
947 | /* ======================================================================== */ | |
9b9129e7 | 948 | |
1da177e4 | 949 | static inline int |
7d12e780 | 950 | mpc52xx_uart_int_rx_chars(struct uart_port *port) |
1da177e4 | 951 | { |
ebd2c8f6 | 952 | struct tty_struct *tty = port->state->port.tty; |
33f0f88f | 953 | unsigned char ch, flag; |
1da177e4 LT |
954 | unsigned short status; |
955 | ||
956 | /* While we can read, do so ! */ | |
599f030c | 957 | while (psc_ops->raw_rx_rdy(port)) { |
1da177e4 | 958 | /* Get the char */ |
599f030c | 959 | ch = psc_ops->read_char(port); |
1da177e4 LT |
960 | |
961 | /* Handle sysreq char */ | |
962 | #ifdef SUPPORT_SYSRQ | |
7d12e780 | 963 | if (uart_handle_sysrq_char(port, ch)) { |
1da177e4 LT |
964 | port->sysrq = 0; |
965 | continue; | |
966 | } | |
967 | #endif | |
968 | ||
969 | /* Store it */ | |
33f0f88f AC |
970 | |
971 | flag = TTY_NORMAL; | |
1da177e4 | 972 | port->icount.rx++; |
9b9129e7 | 973 | |
599f030c JR |
974 | status = in_be16(&PSC(port)->mpc52xx_psc_status); |
975 | ||
406b7d4f JR |
976 | if (status & (MPC52xx_PSC_SR_PE | |
977 | MPC52xx_PSC_SR_FE | | |
978 | MPC52xx_PSC_SR_RB)) { | |
9b9129e7 | 979 | |
1da177e4 | 980 | if (status & MPC52xx_PSC_SR_RB) { |
33f0f88f | 981 | flag = TTY_BREAK; |
1da177e4 | 982 | uart_handle_break(port); |
b6514988 RB |
983 | port->icount.brk++; |
984 | } else if (status & MPC52xx_PSC_SR_PE) { | |
33f0f88f | 985 | flag = TTY_PARITY; |
b6514988 RB |
986 | port->icount.parity++; |
987 | } | |
988 | else if (status & MPC52xx_PSC_SR_FE) { | |
33f0f88f | 989 | flag = TTY_FRAME; |
b6514988 RB |
990 | port->icount.frame++; |
991 | } | |
1da177e4 LT |
992 | |
993 | /* Clear error condition */ | |
406b7d4f | 994 | out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT); |
1da177e4 LT |
995 | |
996 | } | |
33f0f88f AC |
997 | tty_insert_flip_char(tty, ch, flag); |
998 | if (status & MPC52xx_PSC_SR_OE) { | |
999 | /* | |
1000 | * Overrun is special, since it's | |
1001 | * reported immediately, and doesn't | |
1002 | * affect the current character | |
1003 | */ | |
1004 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
b6514988 | 1005 | port->icount.overrun++; |
33f0f88f | 1006 | } |
1da177e4 LT |
1007 | } |
1008 | ||
fbe543b4 | 1009 | spin_unlock(&port->lock); |
1da177e4 | 1010 | tty_flip_buffer_push(tty); |
fbe543b4 | 1011 | spin_lock(&port->lock); |
9b9129e7 | 1012 | |
599f030c | 1013 | return psc_ops->raw_rx_rdy(port); |
1da177e4 LT |
1014 | } |
1015 | ||
1016 | static inline int | |
1017 | mpc52xx_uart_int_tx_chars(struct uart_port *port) | |
1018 | { | |
ebd2c8f6 | 1019 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
1020 | |
1021 | /* Process out of band chars */ | |
1022 | if (port->x_char) { | |
599f030c | 1023 | psc_ops->write_char(port, port->x_char); |
1da177e4 LT |
1024 | port->icount.tx++; |
1025 | port->x_char = 0; | |
1026 | return 1; | |
1027 | } | |
1028 | ||
1029 | /* Nothing to do ? */ | |
1030 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 1031 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
1032 | return 0; |
1033 | } | |
1034 | ||
1035 | /* Send chars */ | |
599f030c JR |
1036 | while (psc_ops->raw_tx_rdy(port)) { |
1037 | psc_ops->write_char(port, xmit->buf[xmit->tail]); | |
1da177e4 LT |
1038 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1039 | port->icount.tx++; | |
1040 | if (uart_circ_empty(xmit)) | |
1041 | break; | |
1042 | } | |
1043 | ||
1044 | /* Wake up */ | |
1045 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1046 | uart_write_wakeup(port); | |
1047 | ||
1048 | /* Maybe we're done after all */ | |
1049 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 1050 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
1051 | return 0; |
1052 | } | |
1053 | ||
1054 | return 1; | |
1055 | } | |
1056 | ||
9b9129e7 | 1057 | static irqreturn_t |
6acc6833 | 1058 | mpc5xxx_uart_process_int(struct uart_port *port) |
1da177e4 | 1059 | { |
1da177e4 LT |
1060 | unsigned long pass = ISR_PASS_LIMIT; |
1061 | unsigned int keepgoing; | |
aec739e0 | 1062 | u8 status; |
9b9129e7 | 1063 | |
1da177e4 LT |
1064 | /* While we have stuff to do, we continue */ |
1065 | do { | |
1066 | /* If we don't find anything to do, we stop */ | |
9b9129e7 GL |
1067 | keepgoing = 0; |
1068 | ||
599f030c JR |
1069 | psc_ops->rx_clr_irq(port); |
1070 | if (psc_ops->rx_rdy(port)) | |
7d12e780 | 1071 | keepgoing |= mpc52xx_uart_int_rx_chars(port); |
1da177e4 | 1072 | |
599f030c JR |
1073 | psc_ops->tx_clr_irq(port); |
1074 | if (psc_ops->tx_rdy(port)) | |
1da177e4 | 1075 | keepgoing |= mpc52xx_uart_int_tx_chars(port); |
9b9129e7 | 1076 | |
aec739e0 WS |
1077 | status = in_8(&PSC(port)->mpc52xx_psc_ipcr); |
1078 | if (status & MPC52xx_PSC_D_DCD) | |
1079 | uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD)); | |
1080 | ||
1081 | if (status & MPC52xx_PSC_D_CTS) | |
1082 | uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS)); | |
1083 | ||
1da177e4 | 1084 | /* Limit number of iteration */ |
406b7d4f | 1085 | if (!(--pass)) |
1da177e4 LT |
1086 | keepgoing = 0; |
1087 | ||
1088 | } while (keepgoing); | |
9b9129e7 | 1089 | |
1da177e4 LT |
1090 | return IRQ_HANDLED; |
1091 | } | |
1092 | ||
6acc6833 AG |
1093 | static irqreturn_t |
1094 | mpc52xx_uart_int(int irq, void *dev_id) | |
1095 | { | |
1096 | struct uart_port *port = dev_id; | |
1097 | irqreturn_t ret; | |
1098 | ||
1099 | spin_lock(&port->lock); | |
1100 | ||
1101 | ret = psc_ops->handle_irq(port); | |
1102 | ||
1103 | spin_unlock(&port->lock); | |
1104 | ||
1105 | return ret; | |
1106 | } | |
1da177e4 LT |
1107 | |
1108 | /* ======================================================================== */ | |
1109 | /* Console ( if applicable ) */ | |
1110 | /* ======================================================================== */ | |
1111 | ||
1112 | #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE | |
1113 | ||
1114 | static void __init | |
1115 | mpc52xx_console_get_options(struct uart_port *port, | |
406b7d4f | 1116 | int *baud, int *parity, int *bits, int *flow) |
1da177e4 LT |
1117 | { |
1118 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
1119 | unsigned char mr1; | |
1120 | ||
b9272dfd GL |
1121 | pr_debug("mpc52xx_console_get_options(port=%p)\n", port); |
1122 | ||
1da177e4 | 1123 | /* Read the mode registers */ |
406b7d4f | 1124 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); |
1da177e4 | 1125 | mr1 = in_8(&psc->mode); |
9b9129e7 | 1126 | |
1da177e4 | 1127 | /* CT{U,L}R are write-only ! */ |
b9272dfd | 1128 | *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; |
1da177e4 LT |
1129 | |
1130 | /* Parse them */ | |
1131 | switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { | |
406b7d4f JR |
1132 | case MPC52xx_PSC_MODE_5_BITS: |
1133 | *bits = 5; | |
1134 | break; | |
1135 | case MPC52xx_PSC_MODE_6_BITS: | |
1136 | *bits = 6; | |
1137 | break; | |
1138 | case MPC52xx_PSC_MODE_7_BITS: | |
1139 | *bits = 7; | |
1140 | break; | |
1141 | case MPC52xx_PSC_MODE_8_BITS: | |
1142 | default: | |
1143 | *bits = 8; | |
1da177e4 | 1144 | } |
9b9129e7 | 1145 | |
1da177e4 LT |
1146 | if (mr1 & MPC52xx_PSC_MODE_PARNONE) |
1147 | *parity = 'n'; | |
1148 | else | |
1149 | *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; | |
1150 | } | |
1151 | ||
9b9129e7 | 1152 | static void |
1da177e4 LT |
1153 | mpc52xx_console_write(struct console *co, const char *s, unsigned int count) |
1154 | { | |
1155 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
1da177e4 | 1156 | unsigned int i, j; |
9b9129e7 | 1157 | |
1da177e4 | 1158 | /* Disable interrupts */ |
599f030c | 1159 | psc_ops->cw_disable_ints(port); |
1da177e4 LT |
1160 | |
1161 | /* Wait the TX buffer to be empty */ | |
9b9129e7 | 1162 | j = 5000000; /* Maximum wait */ |
599f030c | 1163 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
1164 | udelay(1); |
1165 | ||
1166 | /* Write all the chars */ | |
d358788f | 1167 | for (i = 0; i < count; i++, s++) { |
1da177e4 | 1168 | /* Line return handling */ |
d358788f | 1169 | if (*s == '\n') |
599f030c | 1170 | psc_ops->write_char(port, '\r'); |
9b9129e7 | 1171 | |
d358788f | 1172 | /* Send the char */ |
599f030c | 1173 | psc_ops->write_char(port, *s); |
d358788f | 1174 | |
1da177e4 | 1175 | /* Wait the TX buffer to be empty */ |
9b9129e7 | 1176 | j = 20000; /* Maximum wait */ |
599f030c | 1177 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
1178 | udelay(1); |
1179 | } | |
1180 | ||
1181 | /* Restore interrupt state */ | |
599f030c | 1182 | psc_ops->cw_restore_ints(port); |
1da177e4 LT |
1183 | } |
1184 | ||
b9272dfd GL |
1185 | |
1186 | static int __init | |
1187 | mpc52xx_console_setup(struct console *co, char *options) | |
1188 | { | |
1189 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
1190 | struct device_node *np = mpc52xx_uart_nodes[co->index]; | |
599f030c | 1191 | unsigned int uartclk; |
b9272dfd GL |
1192 | struct resource res; |
1193 | int ret; | |
1194 | ||
1195 | int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; | |
1196 | int bits = 8; | |
1197 | int parity = 'n'; | |
1198 | int flow = 'n'; | |
1199 | ||
1200 | pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n", | |
1201 | co, co->index, options); | |
1202 | ||
b898f4f8 | 1203 | if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) { |
b9272dfd GL |
1204 | pr_debug("PSC%x out of range\n", co->index); |
1205 | return -EINVAL; | |
1206 | } | |
1207 | ||
1208 | if (!np) { | |
1209 | pr_debug("PSC%x not found in device tree\n", co->index); | |
1210 | return -EINVAL; | |
1211 | } | |
1212 | ||
1213 | pr_debug("Console on ttyPSC%x is %s\n", | |
406b7d4f | 1214 | co->index, mpc52xx_uart_nodes[co->index]->full_name); |
b9272dfd GL |
1215 | |
1216 | /* Fetch register locations */ | |
406b7d4f JR |
1217 | ret = of_address_to_resource(np, 0, &res); |
1218 | if (ret) { | |
b9272dfd GL |
1219 | pr_debug("Could not get resources for PSC%x\n", co->index); |
1220 | return ret; | |
1221 | } | |
1222 | ||
599f030c JR |
1223 | uartclk = psc_ops->getuartclk(np); |
1224 | if (uartclk == 0) { | |
1225 | pr_debug("Could not find uart clock frequency!\n"); | |
b9272dfd GL |
1226 | return -EINVAL; |
1227 | } | |
1228 | ||
1229 | /* Basic port init. Needed since we use some uart_??? func before | |
1230 | * real init for early access */ | |
1231 | spin_lock_init(&port->lock); | |
599f030c | 1232 | port->uartclk = uartclk; |
b9272dfd GL |
1233 | port->ops = &mpc52xx_uart_ops; |
1234 | port->mapbase = res.start; | |
1235 | port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); | |
1236 | port->irq = irq_of_parse_and_map(np, 0); | |
1237 | ||
1238 | if (port->membase == NULL) | |
1239 | return -EINVAL; | |
1240 | ||
5dd80d5d | 1241 | pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n", |
406b7d4f JR |
1242 | (void *)port->mapbase, port->membase, |
1243 | port->irq, port->uartclk); | |
b9272dfd GL |
1244 | |
1245 | /* Setup the port parameters accoding to options */ | |
1246 | if (options) | |
1247 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1248 | else | |
1249 | mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); | |
1250 | ||
1251 | pr_debug("Setting console parameters: %i %i%c1 flow=%c\n", | |
406b7d4f | 1252 | baud, bits, parity, flow); |
b9272dfd GL |
1253 | |
1254 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1255 | } | |
b9272dfd | 1256 | |
1da177e4 | 1257 | |
2d8179c0 | 1258 | static struct uart_driver mpc52xx_uart_driver; |
1da177e4 LT |
1259 | |
1260 | static struct console mpc52xx_console = { | |
d62de3aa | 1261 | .name = "ttyPSC", |
1da177e4 LT |
1262 | .write = mpc52xx_console_write, |
1263 | .device = uart_console_device, | |
1264 | .setup = mpc52xx_console_setup, | |
1265 | .flags = CON_PRINTBUFFER, | |
406b7d4f | 1266 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */ |
1da177e4 LT |
1267 | .data = &mpc52xx_uart_driver, |
1268 | }; | |
1269 | ||
9b9129e7 GL |
1270 | |
1271 | static int __init | |
1da177e4 LT |
1272 | mpc52xx_console_init(void) |
1273 | { | |
b9272dfd | 1274 | mpc52xx_uart_of_enumerate(); |
1da177e4 LT |
1275 | register_console(&mpc52xx_console); |
1276 | return 0; | |
1277 | } | |
1278 | ||
1279 | console_initcall(mpc52xx_console_init); | |
1280 | ||
1281 | #define MPC52xx_PSC_CONSOLE &mpc52xx_console | |
1282 | #else | |
1283 | #define MPC52xx_PSC_CONSOLE NULL | |
1284 | #endif | |
1285 | ||
1286 | ||
1287 | /* ======================================================================== */ | |
1288 | /* UART Driver */ | |
1289 | /* ======================================================================== */ | |
1290 | ||
1291 | static struct uart_driver mpc52xx_uart_driver = { | |
1da177e4 | 1292 | .driver_name = "mpc52xx_psc_uart", |
d62de3aa | 1293 | .dev_name = "ttyPSC", |
d62de3aa SM |
1294 | .major = SERIAL_PSC_MAJOR, |
1295 | .minor = SERIAL_PSC_MINOR, | |
1da177e4 LT |
1296 | .nr = MPC52xx_PSC_MAXNUM, |
1297 | .cons = MPC52xx_PSC_CONSOLE, | |
1298 | }; | |
1299 | ||
b9272dfd GL |
1300 | /* ======================================================================== */ |
1301 | /* OF Platform Driver */ | |
1302 | /* ======================================================================== */ | |
1303 | ||
52b80482 GL |
1304 | static struct of_device_id mpc52xx_uart_of_match[] = { |
1305 | #ifdef CONFIG_PPC_MPC52xx | |
1306 | { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, | |
1307 | /* binding used by old lite5200 device trees: */ | |
1308 | { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, | |
1309 | /* binding used by efika: */ | |
1310 | { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, }, | |
1311 | #endif | |
1312 | #ifdef CONFIG_PPC_MPC512x | |
1313 | { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, }, | |
52b80482 | 1314 | #endif |
bc775eac | 1315 | {}, |
52b80482 GL |
1316 | }; |
1317 | ||
b9272dfd GL |
1318 | static int __devinit |
1319 | mpc52xx_uart_of_probe(struct of_device *op, const struct of_device_id *match) | |
1320 | { | |
1321 | int idx = -1; | |
599f030c | 1322 | unsigned int uartclk; |
b9272dfd GL |
1323 | struct uart_port *port = NULL; |
1324 | struct resource res; | |
1325 | int ret; | |
1326 | ||
1327 | dev_dbg(&op->dev, "mpc52xx_uart_probe(op=%p, match=%p)\n", op, match); | |
1328 | ||
1329 | /* Check validity & presence */ | |
1330 | for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++) | |
61c7a080 | 1331 | if (mpc52xx_uart_nodes[idx] == op->dev.of_node) |
b9272dfd GL |
1332 | break; |
1333 | if (idx >= MPC52xx_PSC_MAXNUM) | |
1334 | return -EINVAL; | |
1335 | pr_debug("Found %s assigned to ttyPSC%x\n", | |
406b7d4f | 1336 | mpc52xx_uart_nodes[idx]->full_name, idx); |
b9272dfd | 1337 | |
61c7a080 | 1338 | uartclk = psc_ops->getuartclk(op->dev.of_node); |
599f030c JR |
1339 | if (uartclk == 0) { |
1340 | dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); | |
b9272dfd GL |
1341 | return -EINVAL; |
1342 | } | |
1343 | ||
1344 | /* Init the port structure */ | |
1345 | port = &mpc52xx_uart_ports[idx]; | |
1346 | ||
1347 | spin_lock_init(&port->lock); | |
599f030c | 1348 | port->uartclk = uartclk; |
b9272dfd GL |
1349 | port->fifosize = 512; |
1350 | port->iotype = UPIO_MEM; | |
1351 | port->flags = UPF_BOOT_AUTOCONF | | |
406b7d4f | 1352 | (uart_console(port) ? 0 : UPF_IOREMAP); |
b9272dfd GL |
1353 | port->line = idx; |
1354 | port->ops = &mpc52xx_uart_ops; | |
1355 | port->dev = &op->dev; | |
1356 | ||
1357 | /* Search for IRQ and mapbase */ | |
61c7a080 | 1358 | ret = of_address_to_resource(op->dev.of_node, 0, &res); |
406b7d4f | 1359 | if (ret) |
b9272dfd GL |
1360 | return ret; |
1361 | ||
1362 | port->mapbase = res.start; | |
418441d9 WS |
1363 | if (!port->mapbase) { |
1364 | dev_dbg(&op->dev, "Could not allocate resources for PSC\n"); | |
1365 | return -EINVAL; | |
1366 | } | |
1367 | ||
61c7a080 | 1368 | psc_ops->get_irq(port, op->dev.of_node); |
418441d9 WS |
1369 | if (port->irq == NO_IRQ) { |
1370 | dev_dbg(&op->dev, "Could not get irq\n"); | |
1371 | return -EINVAL; | |
1372 | } | |
b9272dfd | 1373 | |
5dd80d5d | 1374 | dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n", |
406b7d4f | 1375 | (void *)port->mapbase, port->irq, port->uartclk); |
b9272dfd | 1376 | |
b9272dfd GL |
1377 | /* Add the port to the uart sub-system */ |
1378 | ret = uart_add_one_port(&mpc52xx_uart_driver, port); | |
6acc6833 | 1379 | if (ret) |
418441d9 | 1380 | return ret; |
b9272dfd | 1381 | |
418441d9 WS |
1382 | dev_set_drvdata(&op->dev, (void *)port); |
1383 | return 0; | |
b9272dfd GL |
1384 | } |
1385 | ||
1386 | static int | |
1387 | mpc52xx_uart_of_remove(struct of_device *op) | |
1388 | { | |
1389 | struct uart_port *port = dev_get_drvdata(&op->dev); | |
1390 | dev_set_drvdata(&op->dev, NULL); | |
1391 | ||
6acc6833 | 1392 | if (port) |
b9272dfd GL |
1393 | uart_remove_one_port(&mpc52xx_uart_driver, port); |
1394 | ||
1395 | return 0; | |
1396 | } | |
1397 | ||
1398 | #ifdef CONFIG_PM | |
1399 | static int | |
1400 | mpc52xx_uart_of_suspend(struct of_device *op, pm_message_t state) | |
1401 | { | |
1402 | struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev); | |
1403 | ||
1404 | if (port) | |
1405 | uart_suspend_port(&mpc52xx_uart_driver, port); | |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | ||
1410 | static int | |
1411 | mpc52xx_uart_of_resume(struct of_device *op) | |
1412 | { | |
1413 | struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev); | |
1414 | ||
1415 | if (port) | |
1416 | uart_resume_port(&mpc52xx_uart_driver, port); | |
1417 | ||
1418 | return 0; | |
1419 | } | |
1420 | #endif | |
1421 | ||
1422 | static void | |
3b5ebf8e | 1423 | mpc52xx_uart_of_assign(struct device_node *np) |
b9272dfd | 1424 | { |
b9272dfd GL |
1425 | int i; |
1426 | ||
3b5ebf8e | 1427 | /* Find the first free PSC number */ |
b9272dfd GL |
1428 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { |
1429 | if (mpc52xx_uart_nodes[i] == NULL) { | |
3b5ebf8e GL |
1430 | of_node_get(np); |
1431 | mpc52xx_uart_nodes[i] = np; | |
1432 | return; | |
b9272dfd GL |
1433 | } |
1434 | } | |
b9272dfd GL |
1435 | } |
1436 | ||
1437 | static void | |
1438 | mpc52xx_uart_of_enumerate(void) | |
1439 | { | |
406b7d4f | 1440 | static int enum_done; |
b9272dfd | 1441 | struct device_node *np; |
25ae3a07 | 1442 | const struct of_device_id *match; |
b9272dfd GL |
1443 | int i; |
1444 | ||
1445 | if (enum_done) | |
1446 | return; | |
1447 | ||
3b5ebf8e GL |
1448 | /* Assign index to each PSC in device tree */ |
1449 | for_each_matching_node(np, mpc52xx_uart_of_match) { | |
25ae3a07 | 1450 | match = of_match_node(mpc52xx_uart_of_match, np); |
25ae3a07 | 1451 | psc_ops = match->data; |
3b5ebf8e | 1452 | mpc52xx_uart_of_assign(np); |
b9272dfd GL |
1453 | } |
1454 | ||
1455 | enum_done = 1; | |
1456 | ||
1457 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { | |
1458 | if (mpc52xx_uart_nodes[i]) | |
1459 | pr_debug("%s assigned to ttyPSC%x\n", | |
406b7d4f | 1460 | mpc52xx_uart_nodes[i]->full_name, i); |
b9272dfd GL |
1461 | } |
1462 | } | |
1463 | ||
1464 | MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match); | |
1465 | ||
1466 | static struct of_platform_driver mpc52xx_uart_of_driver = { | |
b9272dfd GL |
1467 | .probe = mpc52xx_uart_of_probe, |
1468 | .remove = mpc52xx_uart_of_remove, | |
1469 | #ifdef CONFIG_PM | |
1470 | .suspend = mpc52xx_uart_of_suspend, | |
1471 | .resume = mpc52xx_uart_of_resume, | |
1472 | #endif | |
4018294b GL |
1473 | .driver = { |
1474 | .name = "mpc52xx-psc-uart", | |
1475 | .owner = THIS_MODULE, | |
1476 | .of_match_table = mpc52xx_uart_of_match, | |
b9272dfd GL |
1477 | }, |
1478 | }; | |
1da177e4 LT |
1479 | |
1480 | ||
1481 | /* ======================================================================== */ | |
1482 | /* Module */ | |
1483 | /* ======================================================================== */ | |
1484 | ||
1485 | static int __init | |
1486 | mpc52xx_uart_init(void) | |
1487 | { | |
1488 | int ret; | |
1489 | ||
b9272dfd | 1490 | printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n"); |
1da177e4 | 1491 | |
406b7d4f JR |
1492 | ret = uart_register_driver(&mpc52xx_uart_driver); |
1493 | if (ret) { | |
b9272dfd GL |
1494 | printk(KERN_ERR "%s: uart_register_driver failed (%i)\n", |
1495 | __FILE__, ret); | |
1496 | return ret; | |
1da177e4 LT |
1497 | } |
1498 | ||
b9272dfd GL |
1499 | mpc52xx_uart_of_enumerate(); |
1500 | ||
6acc6833 AG |
1501 | /* |
1502 | * Map the PSC FIFO Controller and init if on MPC512x. | |
1503 | */ | |
1504 | if (psc_ops->fifoc_init) { | |
1505 | ret = psc_ops->fifoc_init(); | |
1506 | if (ret) | |
1507 | return ret; | |
1508 | } | |
1509 | ||
b9272dfd GL |
1510 | ret = of_register_platform_driver(&mpc52xx_uart_of_driver); |
1511 | if (ret) { | |
1512 | printk(KERN_ERR "%s: of_register_platform_driver failed (%i)\n", | |
1513 | __FILE__, ret); | |
1514 | uart_unregister_driver(&mpc52xx_uart_driver); | |
1515 | return ret; | |
1516 | } | |
b9272dfd GL |
1517 | |
1518 | return 0; | |
1da177e4 LT |
1519 | } |
1520 | ||
1521 | static void __exit | |
1522 | mpc52xx_uart_exit(void) | |
1523 | { | |
6acc6833 AG |
1524 | if (psc_ops->fifoc_uninit) |
1525 | psc_ops->fifoc_uninit(); | |
1526 | ||
b9272dfd | 1527 | of_unregister_platform_driver(&mpc52xx_uart_of_driver); |
1da177e4 LT |
1528 | uart_unregister_driver(&mpc52xx_uart_driver); |
1529 | } | |
1530 | ||
1531 | ||
1532 | module_init(mpc52xx_uart_init); | |
1533 | module_exit(mpc52xx_uart_exit); | |
1534 | ||
1535 | MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); | |
1536 | MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); | |
1537 | MODULE_LICENSE("GPL"); |