Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. |
3 | * | |
4 | * FIXME According to the usermanual the status bits in the status register | |
5 | * are only updated when the peripherals access the FIFO and not when the | |
6 | * CPU access them. So since we use this bits to know when we stop writing | |
7 | * and reading, they may not be updated in-time and a race condition may | |
8 | * exists. But I haven't be able to prove this and I don't care. But if | |
9 | * any problem arises, it might worth checking. The TX/RX FIFO Stats | |
10 | * registers should be used in addition. | |
11 | * Update: Actually, they seem updated ... At least the bits we use. | |
12 | * | |
13 | * | |
14 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | |
9b9129e7 | 15 | * |
1da177e4 LT |
16 | * Some of the code has been inspired/copied from the 2.4 code written |
17 | * by Dale Farnsworth <dfarnsworth@mvista.com>. | |
9b9129e7 | 18 | * |
1da177e4 LT |
19 | * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com> |
20 | * Copyright (C) 2003 MontaVista, Software, Inc. | |
9b9129e7 | 21 | * |
1da177e4 LT |
22 | * This file is licensed under the terms of the GNU General Public License |
23 | * version 2. This program is licensed "as is" without any warranty of any | |
24 | * kind, whether express or implied. | |
25 | */ | |
9b9129e7 | 26 | |
1da177e4 LT |
27 | /* Platform device Usage : |
28 | * | |
29 | * Since PSCs can have multiple function, the correct driver for each one | |
30 | * is selected by calling mpc52xx_match_psc_function(...). The function | |
31 | * handled by this driver is "uart". | |
32 | * | |
33 | * The driver init all necessary registers to place the PSC in uart mode without | |
34 | * DCD. However, the pin multiplexing aren't changed and should be set either | |
35 | * by the bootloader or in the platform init code. | |
36 | * | |
37 | * The idx field must be equal to the PSC index ( e.g. 0 for PSC1, 1 for PSC2, | |
d62de3aa SM |
38 | * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and |
39 | * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly | |
40 | * fpr the console code : without this 1:1 mapping, at early boot time, when we | |
c30fe7f7 | 41 | * are parsing the kernel args console=ttyPSC?, we wouldn't know which PSC it |
d62de3aa | 42 | * will be mapped to. |
1da177e4 LT |
43 | */ |
44 | ||
d052d1be | 45 | #include <linux/platform_device.h> |
1da177e4 LT |
46 | #include <linux/module.h> |
47 | #include <linux/tty.h> | |
48 | #include <linux/serial.h> | |
49 | #include <linux/sysrq.h> | |
50 | #include <linux/console.h> | |
51 | ||
52 | #include <asm/delay.h> | |
53 | #include <asm/io.h> | |
54 | ||
55 | #include <asm/mpc52xx.h> | |
56 | #include <asm/mpc52xx_psc.h> | |
57 | ||
58 | #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
59 | #define SUPPORT_SYSRQ | |
60 | #endif | |
61 | ||
62 | #include <linux/serial_core.h> | |
63 | ||
64 | ||
d62de3aa SM |
65 | /* We've been assigned a range on the "Low-density serial ports" major */ |
66 | #define SERIAL_PSC_MAJOR 204 | |
67 | #define SERIAL_PSC_MINOR 148 | |
68 | ||
1da177e4 LT |
69 | |
70 | #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ | |
71 | ||
72 | ||
73 | static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; | |
74 | /* Rem: - We use the read_status_mask as a shadow of | |
75 | * psc->mpc52xx_psc_imr | |
76 | * - It's important that is array is all zero on start as we | |
77 | * use it to know if it's initialized or not ! If it's not sure | |
78 | * it's cleared, then a memset(...,0,...) should be added to | |
79 | * the console_init | |
80 | */ | |
81 | ||
82 | #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) | |
83 | ||
84 | ||
85 | /* Forward declaration of the interruption handling routine */ | |
7d12e780 | 86 | static irqreturn_t mpc52xx_uart_int(int irq,void *dev_id); |
1da177e4 LT |
87 | |
88 | ||
89 | /* Simple macro to test if a port is console or not. This one is taken | |
90 | * for serial_core.c and maybe should be moved to serial_core.h ? */ | |
91 | #ifdef CONFIG_SERIAL_CORE_CONSOLE | |
92 | #define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line) | |
93 | #else | |
94 | #define uart_console(port) (0) | |
95 | #endif | |
96 | ||
97 | ||
98 | /* ======================================================================== */ | |
99 | /* UART operations */ | |
100 | /* ======================================================================== */ | |
101 | ||
9b9129e7 | 102 | static unsigned int |
1da177e4 LT |
103 | mpc52xx_uart_tx_empty(struct uart_port *port) |
104 | { | |
105 | int status = in_be16(&PSC(port)->mpc52xx_psc_status); | |
106 | return (status & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0; | |
107 | } | |
108 | ||
9b9129e7 | 109 | static void |
1da177e4 LT |
110 | mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
111 | { | |
112 | /* Not implemented */ | |
113 | } | |
114 | ||
9b9129e7 | 115 | static unsigned int |
1da177e4 LT |
116 | mpc52xx_uart_get_mctrl(struct uart_port *port) |
117 | { | |
118 | /* Not implemented */ | |
119 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
120 | } | |
121 | ||
9b9129e7 | 122 | static void |
b129a8cc | 123 | mpc52xx_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
124 | { |
125 | /* port->lock taken by caller */ | |
126 | port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; | |
127 | out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask); | |
128 | } | |
129 | ||
9b9129e7 | 130 | static void |
b129a8cc | 131 | mpc52xx_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
132 | { |
133 | /* port->lock taken by caller */ | |
134 | port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; | |
135 | out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask); | |
136 | } | |
137 | ||
9b9129e7 | 138 | static void |
1da177e4 LT |
139 | mpc52xx_uart_send_xchar(struct uart_port *port, char ch) |
140 | { | |
141 | unsigned long flags; | |
142 | spin_lock_irqsave(&port->lock, flags); | |
9b9129e7 | 143 | |
1da177e4 LT |
144 | port->x_char = ch; |
145 | if (ch) { | |
146 | /* Make sure tx interrupts are on */ | |
147 | /* Truly necessary ??? They should be anyway */ | |
148 | port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; | |
149 | out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask); | |
150 | } | |
9b9129e7 | 151 | |
1da177e4 LT |
152 | spin_unlock_irqrestore(&port->lock, flags); |
153 | } | |
154 | ||
155 | static void | |
156 | mpc52xx_uart_stop_rx(struct uart_port *port) | |
157 | { | |
158 | /* port->lock taken by caller */ | |
159 | port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; | |
160 | out_be16(&PSC(port)->mpc52xx_psc_imr,port->read_status_mask); | |
161 | } | |
162 | ||
163 | static void | |
164 | mpc52xx_uart_enable_ms(struct uart_port *port) | |
165 | { | |
166 | /* Not implemented */ | |
167 | } | |
168 | ||
169 | static void | |
170 | mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) | |
171 | { | |
172 | unsigned long flags; | |
173 | spin_lock_irqsave(&port->lock, flags); | |
174 | ||
175 | if ( ctl == -1 ) | |
176 | out_8(&PSC(port)->command,MPC52xx_PSC_START_BRK); | |
177 | else | |
178 | out_8(&PSC(port)->command,MPC52xx_PSC_STOP_BRK); | |
9b9129e7 | 179 | |
1da177e4 LT |
180 | spin_unlock_irqrestore(&port->lock, flags); |
181 | } | |
182 | ||
183 | static int | |
184 | mpc52xx_uart_startup(struct uart_port *port) | |
185 | { | |
186 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
187 | int ret; | |
188 | ||
189 | /* Request IRQ */ | |
190 | ret = request_irq(port->irq, mpc52xx_uart_int, | |
40663cc7 | 191 | IRQF_DISABLED | IRQF_SAMPLE_RANDOM, "mpc52xx_psc_uart", port); |
1da177e4 LT |
192 | if (ret) |
193 | return ret; | |
194 | ||
195 | /* Reset/activate the port, clear and enable interrupts */ | |
196 | out_8(&psc->command,MPC52xx_PSC_RST_RX); | |
197 | out_8(&psc->command,MPC52xx_PSC_RST_TX); | |
9b9129e7 | 198 | |
1da177e4 LT |
199 | out_be32(&psc->sicr,0); /* UART mode DCD ignored */ |
200 | ||
201 | out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00); /* /16 prescaler on */ | |
9b9129e7 | 202 | |
1da177e4 LT |
203 | out_8(&psc->rfcntl, 0x00); |
204 | out_be16(&psc->rfalarm, 0x1ff); | |
205 | out_8(&psc->tfcntl, 0x07); | |
206 | out_be16(&psc->tfalarm, 0x80); | |
207 | ||
208 | port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; | |
209 | out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask); | |
9b9129e7 | 210 | |
1da177e4 LT |
211 | out_8(&psc->command,MPC52xx_PSC_TX_ENABLE); |
212 | out_8(&psc->command,MPC52xx_PSC_RX_ENABLE); | |
9b9129e7 | 213 | |
1da177e4 LT |
214 | return 0; |
215 | } | |
216 | ||
217 | static void | |
218 | mpc52xx_uart_shutdown(struct uart_port *port) | |
219 | { | |
220 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
9b9129e7 | 221 | |
1da177e4 LT |
222 | /* Shut down the port, interrupt and all */ |
223 | out_8(&psc->command,MPC52xx_PSC_RST_RX); | |
224 | out_8(&psc->command,MPC52xx_PSC_RST_TX); | |
9b9129e7 GL |
225 | |
226 | port->read_status_mask = 0; | |
1da177e4 LT |
227 | out_be16(&psc->mpc52xx_psc_imr,port->read_status_mask); |
228 | ||
229 | /* Release interrupt */ | |
230 | free_irq(port->irq, port); | |
231 | } | |
232 | ||
9b9129e7 | 233 | static void |
1da177e4 LT |
234 | mpc52xx_uart_set_termios(struct uart_port *port, struct termios *new, |
235 | struct termios *old) | |
236 | { | |
237 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
238 | unsigned long flags; | |
239 | unsigned char mr1, mr2; | |
240 | unsigned short ctr; | |
241 | unsigned int j, baud, quot; | |
9b9129e7 | 242 | |
1da177e4 LT |
243 | /* Prepare what we're gonna write */ |
244 | mr1 = 0; | |
9b9129e7 | 245 | |
1da177e4 LT |
246 | switch (new->c_cflag & CSIZE) { |
247 | case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; | |
248 | break; | |
249 | case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; | |
250 | break; | |
251 | case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; | |
252 | break; | |
253 | case CS8: | |
254 | default: mr1 |= MPC52xx_PSC_MODE_8_BITS; | |
255 | } | |
256 | ||
257 | if (new->c_cflag & PARENB) { | |
258 | mr1 |= (new->c_cflag & PARODD) ? | |
259 | MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; | |
260 | } else | |
261 | mr1 |= MPC52xx_PSC_MODE_PARNONE; | |
9b9129e7 GL |
262 | |
263 | ||
1da177e4 LT |
264 | mr2 = 0; |
265 | ||
266 | if (new->c_cflag & CSTOPB) | |
267 | mr2 |= MPC52xx_PSC_MODE_TWO_STOP; | |
268 | else | |
269 | mr2 |= ((new->c_cflag & CSIZE) == CS5) ? | |
270 | MPC52xx_PSC_MODE_ONE_STOP_5_BITS : | |
271 | MPC52xx_PSC_MODE_ONE_STOP; | |
272 | ||
273 | ||
274 | baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16); | |
275 | quot = uart_get_divisor(port, baud); | |
276 | ctr = quot & 0xffff; | |
9b9129e7 | 277 | |
1da177e4 LT |
278 | /* Get the lock */ |
279 | spin_lock_irqsave(&port->lock, flags); | |
280 | ||
281 | /* Update the per-port timeout */ | |
282 | uart_update_timeout(port, new->c_cflag, baud); | |
283 | ||
284 | /* Do our best to flush TX & RX, so we don't loose anything */ | |
285 | /* But we don't wait indefinitly ! */ | |
286 | j = 5000000; /* Maximum wait */ | |
287 | /* FIXME Can't receive chars since set_termios might be called at early | |
288 | * boot for the console, all stuff is not yet ready to receive at that | |
289 | * time and that just makes the kernel oops */ | |
290 | /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ | |
9b9129e7 | 291 | while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) && |
1da177e4 LT |
292 | --j) |
293 | udelay(1); | |
294 | ||
295 | if (!j) | |
296 | printk( KERN_ERR "mpc52xx_uart.c: " | |
297 | "Unable to flush RX & TX fifos in-time in set_termios." | |
9b9129e7 | 298 | "Some chars may have been lost.\n" ); |
1da177e4 LT |
299 | |
300 | /* Reset the TX & RX */ | |
301 | out_8(&psc->command,MPC52xx_PSC_RST_RX); | |
302 | out_8(&psc->command,MPC52xx_PSC_RST_TX); | |
303 | ||
304 | /* Send new mode settings */ | |
305 | out_8(&psc->command,MPC52xx_PSC_SEL_MODE_REG_1); | |
306 | out_8(&psc->mode,mr1); | |
307 | out_8(&psc->mode,mr2); | |
308 | out_8(&psc->ctur,ctr >> 8); | |
309 | out_8(&psc->ctlr,ctr & 0xff); | |
9b9129e7 | 310 | |
1da177e4 LT |
311 | /* Reenable TX & RX */ |
312 | out_8(&psc->command,MPC52xx_PSC_TX_ENABLE); | |
313 | out_8(&psc->command,MPC52xx_PSC_RX_ENABLE); | |
314 | ||
315 | /* We're all set, release the lock */ | |
316 | spin_unlock_irqrestore(&port->lock, flags); | |
317 | } | |
318 | ||
319 | static const char * | |
320 | mpc52xx_uart_type(struct uart_port *port) | |
321 | { | |
322 | return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL; | |
323 | } | |
324 | ||
325 | static void | |
326 | mpc52xx_uart_release_port(struct uart_port *port) | |
327 | { | |
328 | if (port->flags & UPF_IOREMAP) { /* remapped by us ? */ | |
329 | iounmap(port->membase); | |
330 | port->membase = NULL; | |
331 | } | |
332 | ||
333 | release_mem_region(port->mapbase, MPC52xx_PSC_SIZE); | |
334 | } | |
335 | ||
336 | static int | |
337 | mpc52xx_uart_request_port(struct uart_port *port) | |
338 | { | |
be618f55 AL |
339 | int err; |
340 | ||
1da177e4 LT |
341 | if (port->flags & UPF_IOREMAP) /* Need to remap ? */ |
342 | port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE); | |
343 | ||
344 | if (!port->membase) | |
345 | return -EINVAL; | |
346 | ||
be618f55 | 347 | err = request_mem_region(port->mapbase, MPC52xx_PSC_SIZE, |
1da177e4 | 348 | "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; |
be618f55 AL |
349 | |
350 | if (err && (port->flags & UPF_IOREMAP)) { | |
351 | iounmap(port->membase); | |
352 | port->membase = NULL; | |
353 | } | |
354 | ||
355 | return err; | |
1da177e4 LT |
356 | } |
357 | ||
358 | static void | |
359 | mpc52xx_uart_config_port(struct uart_port *port, int flags) | |
360 | { | |
361 | if ( (flags & UART_CONFIG_TYPE) && | |
362 | (mpc52xx_uart_request_port(port) == 0) ) | |
363 | port->type = PORT_MPC52xx; | |
364 | } | |
365 | ||
366 | static int | |
367 | mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) | |
368 | { | |
369 | if ( ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx ) | |
370 | return -EINVAL; | |
371 | ||
372 | if ( (ser->irq != port->irq) || | |
373 | (ser->io_type != SERIAL_IO_MEM) || | |
9b9129e7 | 374 | (ser->baud_base != port->uartclk) || |
1da177e4 LT |
375 | (ser->iomem_base != (void*)port->mapbase) || |
376 | (ser->hub6 != 0 ) ) | |
377 | return -EINVAL; | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | ||
383 | static struct uart_ops mpc52xx_uart_ops = { | |
384 | .tx_empty = mpc52xx_uart_tx_empty, | |
385 | .set_mctrl = mpc52xx_uart_set_mctrl, | |
386 | .get_mctrl = mpc52xx_uart_get_mctrl, | |
387 | .stop_tx = mpc52xx_uart_stop_tx, | |
388 | .start_tx = mpc52xx_uart_start_tx, | |
389 | .send_xchar = mpc52xx_uart_send_xchar, | |
390 | .stop_rx = mpc52xx_uart_stop_rx, | |
391 | .enable_ms = mpc52xx_uart_enable_ms, | |
392 | .break_ctl = mpc52xx_uart_break_ctl, | |
393 | .startup = mpc52xx_uart_startup, | |
394 | .shutdown = mpc52xx_uart_shutdown, | |
395 | .set_termios = mpc52xx_uart_set_termios, | |
396 | /* .pm = mpc52xx_uart_pm, Not supported yet */ | |
397 | /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */ | |
398 | .type = mpc52xx_uart_type, | |
399 | .release_port = mpc52xx_uart_release_port, | |
400 | .request_port = mpc52xx_uart_request_port, | |
401 | .config_port = mpc52xx_uart_config_port, | |
402 | .verify_port = mpc52xx_uart_verify_port | |
403 | }; | |
404 | ||
9b9129e7 | 405 | |
1da177e4 LT |
406 | /* ======================================================================== */ |
407 | /* Interrupt handling */ | |
408 | /* ======================================================================== */ | |
9b9129e7 | 409 | |
1da177e4 | 410 | static inline int |
7d12e780 | 411 | mpc52xx_uart_int_rx_chars(struct uart_port *port) |
1da177e4 LT |
412 | { |
413 | struct tty_struct *tty = port->info->tty; | |
33f0f88f | 414 | unsigned char ch, flag; |
1da177e4 LT |
415 | unsigned short status; |
416 | ||
417 | /* While we can read, do so ! */ | |
418 | while ( (status = in_be16(&PSC(port)->mpc52xx_psc_status)) & | |
419 | MPC52xx_PSC_SR_RXRDY) { | |
420 | ||
1da177e4 LT |
421 | /* Get the char */ |
422 | ch = in_8(&PSC(port)->mpc52xx_psc_buffer_8); | |
423 | ||
424 | /* Handle sysreq char */ | |
425 | #ifdef SUPPORT_SYSRQ | |
7d12e780 | 426 | if (uart_handle_sysrq_char(port, ch)) { |
1da177e4 LT |
427 | port->sysrq = 0; |
428 | continue; | |
429 | } | |
430 | #endif | |
431 | ||
432 | /* Store it */ | |
33f0f88f AC |
433 | |
434 | flag = TTY_NORMAL; | |
1da177e4 | 435 | port->icount.rx++; |
9b9129e7 | 436 | |
1da177e4 LT |
437 | if ( status & (MPC52xx_PSC_SR_PE | |
438 | MPC52xx_PSC_SR_FE | | |
33f0f88f | 439 | MPC52xx_PSC_SR_RB) ) { |
9b9129e7 | 440 | |
1da177e4 | 441 | if (status & MPC52xx_PSC_SR_RB) { |
33f0f88f | 442 | flag = TTY_BREAK; |
1da177e4 LT |
443 | uart_handle_break(port); |
444 | } else if (status & MPC52xx_PSC_SR_PE) | |
33f0f88f | 445 | flag = TTY_PARITY; |
1da177e4 | 446 | else if (status & MPC52xx_PSC_SR_FE) |
33f0f88f | 447 | flag = TTY_FRAME; |
1da177e4 LT |
448 | |
449 | /* Clear error condition */ | |
450 | out_8(&PSC(port)->command,MPC52xx_PSC_RST_ERR_STAT); | |
451 | ||
452 | } | |
33f0f88f AC |
453 | tty_insert_flip_char(tty, ch, flag); |
454 | if (status & MPC52xx_PSC_SR_OE) { | |
455 | /* | |
456 | * Overrun is special, since it's | |
457 | * reported immediately, and doesn't | |
458 | * affect the current character | |
459 | */ | |
460 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
461 | } | |
1da177e4 LT |
462 | } |
463 | ||
464 | tty_flip_buffer_push(tty); | |
9b9129e7 | 465 | |
1da177e4 LT |
466 | return in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_RXRDY; |
467 | } | |
468 | ||
469 | static inline int | |
470 | mpc52xx_uart_int_tx_chars(struct uart_port *port) | |
471 | { | |
472 | struct circ_buf *xmit = &port->info->xmit; | |
473 | ||
474 | /* Process out of band chars */ | |
475 | if (port->x_char) { | |
476 | out_8(&PSC(port)->mpc52xx_psc_buffer_8, port->x_char); | |
477 | port->icount.tx++; | |
478 | port->x_char = 0; | |
479 | return 1; | |
480 | } | |
481 | ||
482 | /* Nothing to do ? */ | |
483 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 484 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
485 | return 0; |
486 | } | |
487 | ||
488 | /* Send chars */ | |
489 | while (in_be16(&PSC(port)->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXRDY) { | |
490 | out_8(&PSC(port)->mpc52xx_psc_buffer_8, xmit->buf[xmit->tail]); | |
491 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
492 | port->icount.tx++; | |
493 | if (uart_circ_empty(xmit)) | |
494 | break; | |
495 | } | |
496 | ||
497 | /* Wake up */ | |
498 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
499 | uart_write_wakeup(port); | |
500 | ||
501 | /* Maybe we're done after all */ | |
502 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 503 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
504 | return 0; |
505 | } | |
506 | ||
507 | return 1; | |
508 | } | |
509 | ||
9b9129e7 | 510 | static irqreturn_t |
7d12e780 | 511 | mpc52xx_uart_int(int irq, void *dev_id) |
1da177e4 | 512 | { |
c7bec5ab | 513 | struct uart_port *port = dev_id; |
1da177e4 LT |
514 | unsigned long pass = ISR_PASS_LIMIT; |
515 | unsigned int keepgoing; | |
516 | unsigned short status; | |
9b9129e7 | 517 | |
1da177e4 | 518 | spin_lock(&port->lock); |
9b9129e7 | 519 | |
1da177e4 LT |
520 | /* While we have stuff to do, we continue */ |
521 | do { | |
522 | /* If we don't find anything to do, we stop */ | |
9b9129e7 GL |
523 | keepgoing = 0; |
524 | ||
1da177e4 LT |
525 | /* Read status */ |
526 | status = in_be16(&PSC(port)->mpc52xx_psc_isr); | |
527 | status &= port->read_status_mask; | |
9b9129e7 | 528 | |
1da177e4 LT |
529 | /* Do we need to receive chars ? */ |
530 | /* For this RX interrupts must be on and some chars waiting */ | |
531 | if ( status & MPC52xx_PSC_IMR_RXRDY ) | |
7d12e780 | 532 | keepgoing |= mpc52xx_uart_int_rx_chars(port); |
1da177e4 LT |
533 | |
534 | /* Do we need to send chars ? */ | |
535 | /* For this, TX must be ready and TX interrupt enabled */ | |
536 | if ( status & MPC52xx_PSC_IMR_TXRDY ) | |
537 | keepgoing |= mpc52xx_uart_int_tx_chars(port); | |
9b9129e7 | 538 | |
1da177e4 LT |
539 | /* Limit number of iteration */ |
540 | if ( !(--pass) ) | |
541 | keepgoing = 0; | |
542 | ||
543 | } while (keepgoing); | |
9b9129e7 | 544 | |
1da177e4 | 545 | spin_unlock(&port->lock); |
9b9129e7 | 546 | |
1da177e4 LT |
547 | return IRQ_HANDLED; |
548 | } | |
549 | ||
550 | ||
551 | /* ======================================================================== */ | |
552 | /* Console ( if applicable ) */ | |
553 | /* ======================================================================== */ | |
554 | ||
555 | #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE | |
556 | ||
557 | static void __init | |
558 | mpc52xx_console_get_options(struct uart_port *port, | |
559 | int *baud, int *parity, int *bits, int *flow) | |
560 | { | |
561 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
562 | unsigned char mr1; | |
563 | ||
564 | /* Read the mode registers */ | |
565 | out_8(&psc->command,MPC52xx_PSC_SEL_MODE_REG_1); | |
566 | mr1 = in_8(&psc->mode); | |
9b9129e7 | 567 | |
1da177e4 LT |
568 | /* CT{U,L}R are write-only ! */ |
569 | *baud = __res.bi_baudrate ? | |
570 | __res.bi_baudrate : CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; | |
571 | ||
572 | /* Parse them */ | |
573 | switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { | |
574 | case MPC52xx_PSC_MODE_5_BITS: *bits = 5; break; | |
575 | case MPC52xx_PSC_MODE_6_BITS: *bits = 6; break; | |
576 | case MPC52xx_PSC_MODE_7_BITS: *bits = 7; break; | |
577 | case MPC52xx_PSC_MODE_8_BITS: | |
578 | default: *bits = 8; | |
579 | } | |
9b9129e7 | 580 | |
1da177e4 LT |
581 | if (mr1 & MPC52xx_PSC_MODE_PARNONE) |
582 | *parity = 'n'; | |
583 | else | |
584 | *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; | |
585 | } | |
586 | ||
9b9129e7 | 587 | static void |
1da177e4 LT |
588 | mpc52xx_console_write(struct console *co, const char *s, unsigned int count) |
589 | { | |
590 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
591 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
592 | unsigned int i, j; | |
9b9129e7 | 593 | |
1da177e4 LT |
594 | /* Disable interrupts */ |
595 | out_be16(&psc->mpc52xx_psc_imr, 0); | |
596 | ||
597 | /* Wait the TX buffer to be empty */ | |
9b9129e7 GL |
598 | j = 5000000; /* Maximum wait */ |
599 | while (!(in_be16(&psc->mpc52xx_psc_status) & MPC52xx_PSC_SR_TXEMP) && | |
1da177e4 LT |
600 | --j) |
601 | udelay(1); | |
602 | ||
603 | /* Write all the chars */ | |
d358788f | 604 | for (i = 0; i < count; i++, s++) { |
1da177e4 | 605 | /* Line return handling */ |
d358788f | 606 | if (*s == '\n') |
1da177e4 | 607 | out_8(&psc->mpc52xx_psc_buffer_8, '\r'); |
9b9129e7 | 608 | |
d358788f RK |
609 | /* Send the char */ |
610 | out_8(&psc->mpc52xx_psc_buffer_8, *s); | |
611 | ||
1da177e4 | 612 | /* Wait the TX buffer to be empty */ |
9b9129e7 GL |
613 | j = 20000; /* Maximum wait */ |
614 | while (!(in_be16(&psc->mpc52xx_psc_status) & | |
1da177e4 LT |
615 | MPC52xx_PSC_SR_TXEMP) && --j) |
616 | udelay(1); | |
617 | } | |
618 | ||
619 | /* Restore interrupt state */ | |
620 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
621 | } | |
622 | ||
623 | static int __init | |
624 | mpc52xx_console_setup(struct console *co, char *options) | |
625 | { | |
626 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
627 | ||
628 | int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; | |
629 | int bits = 8; | |
630 | int parity = 'n'; | |
631 | int flow = 'n'; | |
632 | ||
633 | if (co->index < 0 || co->index >= MPC52xx_PSC_MAXNUM) | |
634 | return -EINVAL; | |
9b9129e7 | 635 | |
1da177e4 LT |
636 | /* Basic port init. Needed since we use some uart_??? func before |
637 | * real init for early access */ | |
638 | spin_lock_init(&port->lock); | |
639 | port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */ | |
640 | port->ops = &mpc52xx_uart_ops; | |
641 | port->mapbase = MPC52xx_PA(MPC52xx_PSCx_OFFSET(co->index+1)); | |
642 | ||
643 | /* We ioremap ourself */ | |
644 | port->membase = ioremap(port->mapbase, MPC52xx_PSC_SIZE); | |
645 | if (port->membase == NULL) | |
646 | return -EINVAL; | |
647 | ||
648 | /* Setup the port parameters accoding to options */ | |
649 | if (options) | |
650 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
651 | else | |
652 | mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); | |
653 | ||
654 | return uart_set_options(port, co, baud, parity, bits, flow); | |
655 | } | |
656 | ||
657 | ||
2d8179c0 | 658 | static struct uart_driver mpc52xx_uart_driver; |
1da177e4 LT |
659 | |
660 | static struct console mpc52xx_console = { | |
d62de3aa | 661 | .name = "ttyPSC", |
1da177e4 LT |
662 | .write = mpc52xx_console_write, |
663 | .device = uart_console_device, | |
664 | .setup = mpc52xx_console_setup, | |
665 | .flags = CON_PRINTBUFFER, | |
d62de3aa | 666 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0 ) */ |
1da177e4 LT |
667 | .data = &mpc52xx_uart_driver, |
668 | }; | |
669 | ||
9b9129e7 GL |
670 | |
671 | static int __init | |
1da177e4 LT |
672 | mpc52xx_console_init(void) |
673 | { | |
674 | register_console(&mpc52xx_console); | |
675 | return 0; | |
676 | } | |
677 | ||
678 | console_initcall(mpc52xx_console_init); | |
679 | ||
680 | #define MPC52xx_PSC_CONSOLE &mpc52xx_console | |
681 | #else | |
682 | #define MPC52xx_PSC_CONSOLE NULL | |
683 | #endif | |
684 | ||
685 | ||
686 | /* ======================================================================== */ | |
687 | /* UART Driver */ | |
688 | /* ======================================================================== */ | |
689 | ||
690 | static struct uart_driver mpc52xx_uart_driver = { | |
691 | .owner = THIS_MODULE, | |
692 | .driver_name = "mpc52xx_psc_uart", | |
d62de3aa | 693 | .dev_name = "ttyPSC", |
d62de3aa SM |
694 | .major = SERIAL_PSC_MAJOR, |
695 | .minor = SERIAL_PSC_MINOR, | |
1da177e4 LT |
696 | .nr = MPC52xx_PSC_MAXNUM, |
697 | .cons = MPC52xx_PSC_CONSOLE, | |
698 | }; | |
699 | ||
700 | ||
701 | /* ======================================================================== */ | |
702 | /* Platform Driver */ | |
703 | /* ======================================================================== */ | |
704 | ||
705 | static int __devinit | |
3ae5eaec | 706 | mpc52xx_uart_probe(struct platform_device *dev) |
1da177e4 | 707 | { |
3ae5eaec | 708 | struct resource *res = dev->resource; |
1da177e4 LT |
709 | |
710 | struct uart_port *port = NULL; | |
711 | int i, idx, ret; | |
712 | ||
713 | /* Check validity & presence */ | |
38801e2e | 714 | idx = dev->id; |
1da177e4 LT |
715 | if (idx < 0 || idx >= MPC52xx_PSC_MAXNUM) |
716 | return -EINVAL; | |
717 | ||
718 | if (!mpc52xx_match_psc_function(idx,"uart")) | |
719 | return -ENODEV; | |
720 | ||
721 | /* Init the port structure */ | |
722 | port = &mpc52xx_uart_ports[idx]; | |
723 | ||
724 | memset(port, 0x00, sizeof(struct uart_port)); | |
725 | ||
726 | spin_lock_init(&port->lock); | |
727 | port->uartclk = __res.bi_ipbfreq / 2; /* Look at CTLR doc */ | |
947deee8 | 728 | port->fifosize = 512; |
1da177e4 LT |
729 | port->iotype = UPIO_MEM; |
730 | port->flags = UPF_BOOT_AUTOCONF | | |
731 | ( uart_console(port) ? 0 : UPF_IOREMAP ); | |
732 | port->line = idx; | |
733 | port->ops = &mpc52xx_uart_ops; | |
734 | ||
735 | /* Search for IRQ and mapbase */ | |
38801e2e | 736 | for (i=0 ; i<dev->num_resources ; i++, res++) { |
1da177e4 LT |
737 | if (res->flags & IORESOURCE_MEM) |
738 | port->mapbase = res->start; | |
739 | else if (res->flags & IORESOURCE_IRQ) | |
740 | port->irq = res->start; | |
741 | } | |
742 | if (!port->irq || !port->mapbase) | |
743 | return -EINVAL; | |
744 | ||
745 | /* Add the port to the uart sub-system */ | |
746 | ret = uart_add_one_port(&mpc52xx_uart_driver, port); | |
747 | if (!ret) | |
3ae5eaec | 748 | platform_set_drvdata(dev, (void*)port); |
1da177e4 LT |
749 | |
750 | return ret; | |
751 | } | |
752 | ||
753 | static int | |
3ae5eaec | 754 | mpc52xx_uart_remove(struct platform_device *dev) |
1da177e4 | 755 | { |
3ae5eaec | 756 | struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev); |
1da177e4 | 757 | |
3ae5eaec | 758 | platform_set_drvdata(dev, NULL); |
1da177e4 LT |
759 | |
760 | if (port) | |
761 | uart_remove_one_port(&mpc52xx_uart_driver, port); | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | #ifdef CONFIG_PM | |
767 | static int | |
3ae5eaec | 768 | mpc52xx_uart_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 769 | { |
3ae5eaec | 770 | struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev); |
1da177e4 | 771 | |
9b9129e7 | 772 | if (port) |
1da177e4 LT |
773 | uart_suspend_port(&mpc52xx_uart_driver, port); |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | static int | |
3ae5eaec | 779 | mpc52xx_uart_resume(struct platform_device *dev) |
1da177e4 | 780 | { |
3ae5eaec | 781 | struct uart_port *port = (struct uart_port *) platform_get_drvdata(dev); |
1da177e4 | 782 | |
9480e307 | 783 | if (port) |
1da177e4 LT |
784 | uart_resume_port(&mpc52xx_uart_driver, port); |
785 | ||
786 | return 0; | |
787 | } | |
788 | #endif | |
789 | ||
3ae5eaec | 790 | static struct platform_driver mpc52xx_uart_platform_driver = { |
1da177e4 LT |
791 | .probe = mpc52xx_uart_probe, |
792 | .remove = mpc52xx_uart_remove, | |
793 | #ifdef CONFIG_PM | |
794 | .suspend = mpc52xx_uart_suspend, | |
795 | .resume = mpc52xx_uart_resume, | |
796 | #endif | |
3ae5eaec RK |
797 | .driver = { |
798 | .name = "mpc52xx-psc", | |
799 | }, | |
1da177e4 LT |
800 | }; |
801 | ||
802 | ||
803 | /* ======================================================================== */ | |
804 | /* Module */ | |
805 | /* ======================================================================== */ | |
806 | ||
807 | static int __init | |
808 | mpc52xx_uart_init(void) | |
809 | { | |
810 | int ret; | |
811 | ||
812 | printk(KERN_INFO "Serial: MPC52xx PSC driver\n"); | |
813 | ||
814 | ret = uart_register_driver(&mpc52xx_uart_driver); | |
815 | if (ret == 0) { | |
3ae5eaec | 816 | ret = platform_driver_register(&mpc52xx_uart_platform_driver); |
1da177e4 LT |
817 | if (ret) |
818 | uart_unregister_driver(&mpc52xx_uart_driver); | |
819 | } | |
820 | ||
821 | return ret; | |
822 | } | |
823 | ||
824 | static void __exit | |
825 | mpc52xx_uart_exit(void) | |
826 | { | |
3ae5eaec | 827 | platform_driver_unregister(&mpc52xx_uart_platform_driver); |
1da177e4 LT |
828 | uart_unregister_driver(&mpc52xx_uart_driver); |
829 | } | |
830 | ||
831 | ||
832 | module_init(mpc52xx_uart_init); | |
833 | module_exit(mpc52xx_uart_exit); | |
834 | ||
835 | MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); | |
836 | MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); | |
837 | MODULE_LICENSE("GPL"); |