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[PATCH] TTY layer buffering revamp
[deliverable/linux.git] / drivers / serial / pxa.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/serial/pxa.c
3 *
4 * Based on drivers/serial/8250.c by Russell King.
5 *
6 * Author: Nicolas Pitre
7 * Created: Feb 20, 2003
8 * Copyright: (C) 2003 Monta Vista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * Note 1: This driver is made separate from the already too overloaded
16 * 8250.c because it needs some kirks of its own and that'll make it
17 * easier to add DMA support.
18 *
19 * Note 2: I'm too sick of device allocation policies for serial ports.
20 * If someone else wants to request an "official" allocation of major/minor
21 * for this driver please be my guest. And don't forget that new hardware
22 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
23 * hope for a better port registration and dynamic device allocation scheme
24 * with the serial core maintainer satisfaction to appear soon.
25 */
26
27#include <linux/config.h>
28
29#if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/ioport.h>
35#include <linux/init.h>
36#include <linux/console.h>
37#include <linux/sysrq.h>
38#include <linux/serial_reg.h>
39#include <linux/circ_buf.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
d052d1be 42#include <linux/platform_device.h>
1da177e4
LT		 43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46
47#include <asm/io.h>
48#include <asm/hardware.h>
49#include <asm/irq.h>
50#include <asm/arch/pxa-regs.h>
51
52
53struct uart_pxa_port {
54 struct uart_port port;
55 unsigned char ier;
56 unsigned char lcr;
57 unsigned char mcr;
58 unsigned int lsr_break_flag;
59 unsigned int cken;
60 char *name;
61};
62
63static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
64{
65 offset <<= 2;
66 return readl(up->port.membase + offset);
67}
68
69static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
70{
71 offset <<= 2;
72 writel(value, up->port.membase + offset);
73}
74
75static void serial_pxa_enable_ms(struct uart_port *port)
76{
77 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
78
79 up->ier |= UART_IER_MSI;
80 serial_out(up, UART_IER, up->ier);
81}
82
b129a8cc 83static void serial_pxa_stop_tx(struct uart_port *port)
1da177e4
LT		 84{
85 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
86
87 if (up->ier & UART_IER_THRI) {
88 up->ier &= ~UART_IER_THRI;
89 serial_out(up, UART_IER, up->ier);
90 }
91}
92
93static void serial_pxa_stop_rx(struct uart_port *port)
94{
95 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
96
97 up->ier &= ~UART_IER_RLSI;
98 up->port.read_status_mask &= ~UART_LSR_DR;
99 serial_out(up, UART_IER, up->ier);
100}
101
102static inline void
103receive_chars(struct uart_pxa_port *up, int *status, struct pt_regs *regs)
104{
105 struct tty_struct *tty = up->port.info->tty;
106 unsigned int ch, flag;
107 int max_count = 256;
108
109 do {
1da177e4
LT		 110 ch = serial_in(up, UART_RX);
111 flag = TTY_NORMAL;
112 up->port.icount.rx++;
113
114 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
115 UART_LSR_FE | UART_LSR_OE))) {
116 /*
117 * For statistics only
118 */
119 if (*status & UART_LSR_BI) {
120 *status &= ~(UART_LSR_FE | UART_LSR_PE);
121 up->port.icount.brk++;
122 /*
123 * We do the SysRQ and SAK checking
124 * here because otherwise the break
125 * may get masked by ignore_status_mask
126 * or read_status_mask.
127 */
128 if (uart_handle_break(&up->port))
129 goto ignore_char;
130 } else if (*status & UART_LSR_PE)
131 up->port.icount.parity++;
132 else if (*status & UART_LSR_FE)
133 up->port.icount.frame++;
134 if (*status & UART_LSR_OE)
135 up->port.icount.overrun++;
136
137 /*
138 * Mask off conditions which should be ignored.
139 */
140 *status &= up->port.read_status_mask;
141
142#ifdef CONFIG_SERIAL_PXA_CONSOLE
143 if (up->port.line == up->port.cons->index) {
144 /* Recover the break flag from console xmit */
145 *status |= up->lsr_break_flag;
146 up->lsr_break_flag = 0;
147 }
148#endif
149 if (*status & UART_LSR_BI) {
150 flag = TTY_BREAK;
151 } else if (*status & UART_LSR_PE)
152 flag = TTY_PARITY;
153 else if (*status & UART_LSR_FE)
154 flag = TTY_FRAME;
155 }
05ab3014 156
1da177e4
LT		 157 if (uart_handle_sysrq_char(&up->port, ch, regs))
158 goto ignore_char;
05ab3014
RK		 159
160 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
161
1da177e4
LT		 162 ignore_char:
163 *status = serial_in(up, UART_LSR);
164 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
165 tty_flip_buffer_push(tty);
166}
167
168static void transmit_chars(struct uart_pxa_port *up)
169{
170 struct circ_buf *xmit = &up->port.info->xmit;
171 int count;
172
173 if (up->port.x_char) {
174 serial_out(up, UART_TX, up->port.x_char);
175 up->port.icount.tx++;
176 up->port.x_char = 0;
177 return;
178 }
179 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
b129a8cc 180 serial_pxa_stop_tx(&up->port);
1da177e4
LT		 181 return;
182 }
183
184 count = up->port.fifosize / 2;
185 do {
186 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
187 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
188 up->port.icount.tx++;
189 if (uart_circ_empty(xmit))
190 break;
191 } while (--count > 0);
192
193 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
194 uart_write_wakeup(&up->port);
195
196
197 if (uart_circ_empty(xmit))
b129a8cc 198 serial_pxa_stop_tx(&up->port);
1da177e4
LT		 199}
200
b129a8cc 201static void serial_pxa_start_tx(struct uart_port *port)
1da177e4
LT		 202{
203 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
204
205 if (!(up->ier & UART_IER_THRI)) {
206 up->ier |= UART_IER_THRI;
207 serial_out(up, UART_IER, up->ier);
208 }
209}
210
211static inline void check_modem_status(struct uart_pxa_port *up)
212{
213 int status;
214
215 status = serial_in(up, UART_MSR);
216
217 if ((status & UART_MSR_ANY_DELTA) == 0)
218 return;
219
220 if (status & UART_MSR_TERI)
221 up->port.icount.rng++;
222 if (status & UART_MSR_DDSR)
223 up->port.icount.dsr++;
224 if (status & UART_MSR_DDCD)
225 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
226 if (status & UART_MSR_DCTS)
227 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
228
229 wake_up_interruptible(&up->port.info->delta_msr_wait);
230}
231
232/*
233 * This handles the interrupt from one port.
234 */
235static inline irqreturn_t
236serial_pxa_irq(int irq, void *dev_id, struct pt_regs *regs)
237{
238 struct uart_pxa_port *up = (struct uart_pxa_port *)dev_id;
239 unsigned int iir, lsr;
240
241 iir = serial_in(up, UART_IIR);
242 if (iir & UART_IIR_NO_INT)
243 return IRQ_NONE;
244 lsr = serial_in(up, UART_LSR);
245 if (lsr & UART_LSR_DR)
246 receive_chars(up, &lsr, regs);
247 check_modem_status(up);
248 if (lsr & UART_LSR_THRE)
249 transmit_chars(up);
250 return IRQ_HANDLED;
251}
252
253static unsigned int serial_pxa_tx_empty(struct uart_port *port)
254{
255 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
256 unsigned long flags;
257 unsigned int ret;
258
259 spin_lock_irqsave(&up->port.lock, flags);
260 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
261 spin_unlock_irqrestore(&up->port.lock, flags);
262
263 return ret;
264}
265
266static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
267{
268 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
1da177e4
LT		 269 unsigned char status;
270 unsigned int ret;
271
272return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1da177e4 273 status = serial_in(up, UART_MSR);
1da177e4
LT		 274
275 ret = 0;
276 if (status & UART_MSR_DCD)
277 ret |= TIOCM_CAR;
278 if (status & UART_MSR_RI)
279 ret |= TIOCM_RNG;
280 if (status & UART_MSR_DSR)
281 ret |= TIOCM_DSR;
282 if (status & UART_MSR_CTS)
283 ret |= TIOCM_CTS;
284 return ret;
285}
286
287static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
288{
289 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
290 unsigned char mcr = 0;
291
292 if (mctrl & TIOCM_RTS)
293 mcr |= UART_MCR_RTS;
294 if (mctrl & TIOCM_DTR)
295 mcr |= UART_MCR_DTR;
296 if (mctrl & TIOCM_OUT1)
297 mcr |= UART_MCR_OUT1;
298 if (mctrl & TIOCM_OUT2)
299 mcr |= UART_MCR_OUT2;
300 if (mctrl & TIOCM_LOOP)
301 mcr |= UART_MCR_LOOP;
302
303 mcr |= up->mcr;
304
305 serial_out(up, UART_MCR, mcr);
306}
307
308static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
309{
310 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
311 unsigned long flags;
312
313 spin_lock_irqsave(&up->port.lock, flags);
314 if (break_state == -1)
315 up->lcr |= UART_LCR_SBC;
316 else
317 up->lcr &= ~UART_LCR_SBC;
318 serial_out(up, UART_LCR, up->lcr);
319 spin_unlock_irqrestore(&up->port.lock, flags);
320}
321
322#if 0
323static void serial_pxa_dma_init(struct pxa_uart *up)
324{
325 up->rxdma =
326 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up);
327 if (up->rxdma < 0)
328 goto out;
329 up->txdma =
330 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up);
331 if (up->txdma < 0)
332 goto err_txdma;
333 up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL);
334 if (!up->dmadesc)
335 goto err_alloc;
336
337 /* ... */
338err_alloc:
339 pxa_free_dma(up->txdma);
340err_rxdma:
341 pxa_free_dma(up->rxdma);
342out:
343 return;
344}
345#endif
346
347static int serial_pxa_startup(struct uart_port *port)
348{
349 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
350 unsigned long flags;
351 int retval;
352
d9e29649
MR		 353 if (port->line == 3) /* HWUART */
354 up->mcr |= UART_MCR_AFE;
355 else
f02aa3f9 356 up->mcr = 0;
1da177e4
LT		 357
358 /*
359 * Allocate the IRQ
360 */
361 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
362 if (retval)
363 return retval;
364
365 /*
366 * Clear the FIFO buffers and disable them.
367 * (they will be reenabled in set_termios())
368 */
369 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
370 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
371 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
372 serial_out(up, UART_FCR, 0);
373
374 /*
375 * Clear the interrupt registers.
376 */
377 (void) serial_in(up, UART_LSR);
378 (void) serial_in(up, UART_RX);
379 (void) serial_in(up, UART_IIR);
380 (void) serial_in(up, UART_MSR);
381
382 /*
383 * Now, initialize the UART
384 */
385 serial_out(up, UART_LCR, UART_LCR_WLEN8);
386
387 spin_lock_irqsave(&up->port.lock, flags);
388 up->port.mctrl |= TIOCM_OUT2;
389 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
390 spin_unlock_irqrestore(&up->port.lock, flags);
391
392 /*
393 * Finally, enable interrupts. Note: Modem status interrupts
394 * are set via set_termios(), which will be occuring imminently
395 * anyway, so we don't enable them here.
396 */
397 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
398 serial_out(up, UART_IER, up->ier);
399
400 /*
401 * And clear the interrupt registers again for luck.
402 */
403 (void) serial_in(up, UART_LSR);
404 (void) serial_in(up, UART_RX);
405 (void) serial_in(up, UART_IIR);
406 (void) serial_in(up, UART_MSR);
407
408 return 0;
409}
410
411static void serial_pxa_shutdown(struct uart_port *port)
412{
413 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
414 unsigned long flags;
415
416 free_irq(up->port.irq, up);
417
418 /*
419 * Disable interrupts from this port
420 */
421 up->ier = 0;
422 serial_out(up, UART_IER, 0);
423
424 spin_lock_irqsave(&up->port.lock, flags);
425 up->port.mctrl &= ~TIOCM_OUT2;
426 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
427 spin_unlock_irqrestore(&up->port.lock, flags);
428
429 /*
430 * Disable break condition and FIFOs
431 */
432 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
433 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
434 UART_FCR_CLEAR_RCVR |
435 UART_FCR_CLEAR_XMIT);
436 serial_out(up, UART_FCR, 0);
437}
438
439static void
440serial_pxa_set_termios(struct uart_port *port, struct termios *termios,
441 struct termios *old)
442{
443 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
444 unsigned char cval, fcr = 0;
445 unsigned long flags;
446 unsigned int baud, quot;
447
448 switch (termios->c_cflag & CSIZE) {
449 case CS5:
0a8b80c5 450 cval = UART_LCR_WLEN5;
1da177e4
LT		 451 break;
452 case CS6:
0a8b80c5 453 cval = UART_LCR_WLEN6;
1da177e4
LT		 454 break;
455 case CS7:
0a8b80c5 456 cval = UART_LCR_WLEN7;
1da177e4
LT		 457 break;
458 default:
459 case CS8:
0a8b80c5 460 cval = UART_LCR_WLEN8;
1da177e4
LT		 461 break;
462 }
463
464 if (termios->c_cflag & CSTOPB)
0a8b80c5 465 cval |= UART_LCR_STOP;
1da177e4
LT		 466 if (termios->c_cflag & PARENB)
467 cval |= UART_LCR_PARITY;
468 if (!(termios->c_cflag & PARODD))
469 cval |= UART_LCR_EPAR;
470
471 /*
472 * Ask the core to calculate the divisor for us.
473 */
474 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
475 quot = uart_get_divisor(port, baud);
476
477 if ((up->port.uartclk / quot) < (2400 * 16))
478 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
d9e29649 479 else if ((up->port.uartclk / quot) < (230400 * 16))
1da177e4 480 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
d9e29649
MR		 481 else
482 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
1da177e4
LT		 483
484 /*
485 * Ok, we're now changing the port state. Do it with
486 * interrupts disabled.
487 */
488 spin_lock_irqsave(&up->port.lock, flags);
489
490 /*
491 * Ensure the port will be enabled.
492 * This is required especially for serial console.
493 */
494 up->ier |= IER_UUE;
495
496 /*
497 * Update the per-port timeout.
498 */
e6158b4a 499 uart_update_timeout(port, termios->c_cflag, baud);
1da177e4
LT		 500
501 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
502 if (termios->c_iflag & INPCK)
503 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
504 if (termios->c_iflag & (BRKINT | PARMRK))
505 up->port.read_status_mask |= UART_LSR_BI;
506
507 /*
508 * Characters to ignore
509 */
510 up->port.ignore_status_mask = 0;
511 if (termios->c_iflag & IGNPAR)
512 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
513 if (termios->c_iflag & IGNBRK) {
514 up->port.ignore_status_mask |= UART_LSR_BI;
515 /*
516 * If we're ignoring parity and break indicators,
517 * ignore overruns too (for real raw support).
518 */
519 if (termios->c_iflag & IGNPAR)
520 up->port.ignore_status_mask |= UART_LSR_OE;
521 }
522
523 /*
524 * ignore all characters if CREAD is not set
525 */
526 if ((termios->c_cflag & CREAD) == 0)
527 up->port.ignore_status_mask |= UART_LSR_DR;
528
529 /*
530 * CTS flow control flag and modem status interrupts
531 */
532 up->ier &= ~UART_IER_MSI;
533 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
534 up->ier |= UART_IER_MSI;
535
536 serial_out(up, UART_IER, up->ier);
537
538 serial_out(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
539 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
540 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
541 serial_out(up, UART_LCR, cval); /* reset DLAB */
542 up->lcr = cval; /* Save LCR */
543 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
544 serial_out(up, UART_FCR, fcr);
545 spin_unlock_irqrestore(&up->port.lock, flags);
546}
547
548static void
549serial_pxa_pm(struct uart_port *port, unsigned int state,
550 unsigned int oldstate)
551{
552 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
553 pxa_set_cken(up->cken, !state);
554 if (!state)
555 udelay(1);
556}
557
558static void serial_pxa_release_port(struct uart_port *port)
559{
560}
561
562static int serial_pxa_request_port(struct uart_port *port)
563{
564 return 0;
565}
566
567static void serial_pxa_config_port(struct uart_port *port, int flags)
568{
569 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
570 up->port.type = PORT_PXA;
571}
572
573static int
574serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
575{
576 /* we don't want the core code to modify any port params */
577 return -EINVAL;
578}
579
580static const char *
581serial_pxa_type(struct uart_port *port)
582{
583 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
584 return up->name;
585}
586
587#ifdef CONFIG_SERIAL_PXA_CONSOLE
588
2d93486c
VS		 589static struct uart_pxa_port serial_pxa_ports[];
590static struct uart_driver serial_pxa_reg;
1da177e4
LT		 591
592#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
593
594/*
595 * Wait for transmitter & holding register to empty
596 */
597static inline void wait_for_xmitr(struct uart_pxa_port *up)
598{
599 unsigned int status, tmout = 10000;
600
601 /* Wait up to 10ms for the character(s) to be sent. */
602 do {
603 status = serial_in(up, UART_LSR);
604
605 if (status & UART_LSR_BI)
606 up->lsr_break_flag = UART_LSR_BI;
607
608 if (--tmout == 0)
609 break;
610 udelay(1);
611 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
612
613 /* Wait up to 1s for flow control if necessary */
614 if (up->port.flags & UPF_CONS_FLOW) {
615 tmout = 1000000;
616 while (--tmout &&
617 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
618 udelay(1);
619 }
620}
621
622/*
623 * Print a string to the serial port trying not to disturb
624 * any possible real use of the port...
625 *
626 * The console_lock must be held when we get here.
627 */
628static void
629serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
630{
631 struct uart_pxa_port *up = &serial_pxa_ports[co->index];
632 unsigned int ier;
633 int i;
634
635 /*
f02aa3f9 636 * First save the IER then disable the interrupts
1da177e4
LT		 637 */
638 ier = serial_in(up, UART_IER);
639 serial_out(up, UART_IER, UART_IER_UUE);
640
641 /*
642 * Now, do each character
643 */
644 for (i = 0; i < count; i++, s++) {
645 wait_for_xmitr(up);
646
647 /*
648 * Send the character out.
649 * If a LF, also do CR...
650 */
651 serial_out(up, UART_TX, *s);
652 if (*s == 10) {
653 wait_for_xmitr(up);
654 serial_out(up, UART_TX, 13);
655 }
656 }
657
658 /*
659 * Finally, wait for transmitter to become empty
660 * and restore the IER
661 */
662 wait_for_xmitr(up);
663 serial_out(up, UART_IER, ier);
664}
665
666static int __init
667serial_pxa_console_setup(struct console *co, char *options)
668{
669 struct uart_pxa_port *up;
670 int baud = 9600;
671 int bits = 8;
672 int parity = 'n';
673 int flow = 'n';
674
675 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
676 co->index = 0;
677 up = &serial_pxa_ports[co->index];
678
679 if (options)
680 uart_parse_options(options, &baud, &parity, &bits, &flow);
681
682 return uart_set_options(&up->port, co, baud, parity, bits, flow);
683}
684
685static struct console serial_pxa_console = {
686 .name = "ttyS",
687 .write = serial_pxa_console_write,
688 .device = uart_console_device,
689 .setup = serial_pxa_console_setup,
690 .flags = CON_PRINTBUFFER,
691 .index = -1,
692 .data = &serial_pxa_reg,
693};
694
695static int __init
696serial_pxa_console_init(void)
697{
698 register_console(&serial_pxa_console);
699 return 0;
700}
701
702console_initcall(serial_pxa_console_init);
703
704#define PXA_CONSOLE &serial_pxa_console
705#else
706#define PXA_CONSOLE NULL
707#endif
708
709struct uart_ops serial_pxa_pops = {
710 .tx_empty = serial_pxa_tx_empty,
711 .set_mctrl = serial_pxa_set_mctrl,
712 .get_mctrl = serial_pxa_get_mctrl,
713 .stop_tx = serial_pxa_stop_tx,
714 .start_tx = serial_pxa_start_tx,
715 .stop_rx = serial_pxa_stop_rx,
716 .enable_ms = serial_pxa_enable_ms,
717 .break_ctl = serial_pxa_break_ctl,
718 .startup = serial_pxa_startup,
719 .shutdown = serial_pxa_shutdown,
720 .set_termios = serial_pxa_set_termios,
721 .pm = serial_pxa_pm,
722 .type = serial_pxa_type,
723 .release_port = serial_pxa_release_port,
724 .request_port = serial_pxa_request_port,
725 .config_port = serial_pxa_config_port,
726 .verify_port = serial_pxa_verify_port,
727};
728
729static struct uart_pxa_port serial_pxa_ports[] = {
730 { /* FFUART */
731 .name = "FFUART",
732 .cken = CKEN6_FFUART,
733 .port = {
734 .type = PORT_PXA,
735 .iotype = UPIO_MEM,
736 .membase = (void *)&FFUART,
737 .mapbase = __PREG(FFUART),
738 .irq = IRQ_FFUART,
739 .uartclk = 921600 * 16,
740 .fifosize = 64,
741 .ops = &serial_pxa_pops,
742 .line = 0,
743 },
744 }, { /* BTUART */
745 .name = "BTUART",
746 .cken = CKEN7_BTUART,
747 .port = {
748 .type = PORT_PXA,
749 .iotype = UPIO_MEM,
750 .membase = (void *)&BTUART,
751 .mapbase = __PREG(BTUART),
752 .irq = IRQ_BTUART,
753 .uartclk = 921600 * 16,
754 .fifosize = 64,
755 .ops = &serial_pxa_pops,
756 .line = 1,
757 },
758 }, { /* STUART */
759 .name = "STUART",
760 .cken = CKEN5_STUART,
761 .port = {
762 .type = PORT_PXA,
763 .iotype = UPIO_MEM,
764 .membase = (void *)&STUART,
765 .mapbase = __PREG(STUART),
766 .irq = IRQ_STUART,
767 .uartclk = 921600 * 16,
768 .fifosize = 64,
769 .ops = &serial_pxa_pops,
770 .line = 2,
771 },
d9e29649
MR		 772 }, { /* HWUART */
773 .name = "HWUART",
774 .cken = CKEN4_HWUART,
775 .port = {
776 .type = PORT_PXA,
777 .iotype = UPIO_MEM,
778 .membase = (void *)&HWUART,
779 .mapbase = __PREG(HWUART),
780 .irq = IRQ_HWUART,
781 .uartclk = 921600 * 16,
782 .fifosize = 64,
783 .ops = &serial_pxa_pops,
784 .line = 3,
785 },
1da177e4
LT		 786 }
787};
788
789static struct uart_driver serial_pxa_reg = {
790 .owner = THIS_MODULE,
791 .driver_name = "PXA serial",
792 .devfs_name = "tts/",
793 .dev_name = "ttyS",
794 .major = TTY_MAJOR,
795 .minor = 64,
796 .nr = ARRAY_SIZE(serial_pxa_ports),
797 .cons = PXA_CONSOLE,
798};
799
3ae5eaec 800static int serial_pxa_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 801{
3ae5eaec 802 struct uart_pxa_port *sport = platform_get_drvdata(dev);
1da177e4 803
9480e307 804 if (sport)
1da177e4
LT		 805 uart_suspend_port(&serial_pxa_reg, &sport->port);
806
807 return 0;
808}
809
3ae5eaec 810static int serial_pxa_resume(struct platform_device *dev)
1da177e4 811{
3ae5eaec 812 struct uart_pxa_port *sport = platform_get_drvdata(dev);
1da177e4 813
9480e307 814 if (sport)
1da177e4
LT		 815 uart_resume_port(&serial_pxa_reg, &sport->port);
816
817 return 0;
818}
819
3ae5eaec 820static int serial_pxa_probe(struct platform_device *dev)
1da177e4 821{
3ae5eaec 822 serial_pxa_ports[dev->id].port.dev = &dev->dev;
1da177e4 823 uart_add_one_port(&serial_pxa_reg, &serial_pxa_ports[dev->id].port);
3ae5eaec 824 platform_set_drvdata(dev, &serial_pxa_ports[dev->id]);
1da177e4
LT		 825 return 0;
826}
827
3ae5eaec 828static int serial_pxa_remove(struct platform_device *dev)
1da177e4 829{
3ae5eaec 830 struct uart_pxa_port *sport = platform_get_drvdata(dev);
1da177e4 831
3ae5eaec 832 platform_set_drvdata(dev, NULL);
1da177e4
LT		 833
834 if (sport)
835 uart_remove_one_port(&serial_pxa_reg, &sport->port);
836
837 return 0;
838}
839
3ae5eaec 840static struct platform_driver serial_pxa_driver = {
1da177e4
LT		 841 .probe = serial_pxa_probe,
842 .remove = serial_pxa_remove,
843
844 .suspend = serial_pxa_suspend,
845 .resume = serial_pxa_resume,
3ae5eaec
RK		 846 .driver = {
847 .name = "pxa2xx-uart",
848 },
1da177e4
LT		 849};
850
851int __init serial_pxa_init(void)
852{
853 int ret;
854
855 ret = uart_register_driver(&serial_pxa_reg);
856 if (ret != 0)
857 return ret;
858
3ae5eaec 859 ret = platform_driver_register(&serial_pxa_driver);
1da177e4
LT		 860 if (ret != 0)
861 uart_unregister_driver(&serial_pxa_reg);
862
863 return ret;
864}
865
866void __exit serial_pxa_exit(void)
867{
3ae5eaec 868 platform_driver_unregister(&serial_pxa_driver);
1da177e4
LT		 869 uart_unregister_driver(&serial_pxa_reg);
870}
871
872module_init(serial_pxa_init);
873module_exit(serial_pxa_exit);
874
875MODULE_LICENSE("GPL");
876
Linux kernel - Deliverables
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