projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge mulgrave-w:git/scsi-misc-2.6
[deliverable/linux.git] / drivers / serial / sh-sci.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002, 2003, 2004 Paul Mundt
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20
21#undef DEBUG
22
1da177e4
LT		 23#include <linux/module.h>
24#include <linux/errno.h>
25#include <linux/signal.h>
26#include <linux/sched.h>
27#include <linux/timer.h>
28#include <linux/interrupt.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/serial.h>
32#include <linux/major.h>
33#include <linux/string.h>
34#include <linux/sysrq.h>
35#include <linux/fcntl.h>
36#include <linux/ptrace.h>
37#include <linux/ioport.h>
38#include <linux/mm.h>
39#include <linux/slab.h>
40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
43#include <linux/bitops.h>
b7a76e4b 44#include <linux/generic_serial.h>
1da177e4
LT		 45
46#ifdef CONFIG_CPU_FREQ
47#include <linux/notifier.h>
48#include <linux/cpufreq.h>
49#endif
50
51#include <asm/system.h>
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
b7a76e4b
PM		 56#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
57#include <asm/clock.h>
58#endif
1da177e4
LT		 59
60#ifdef CONFIG_SH_STANDARD_BIOS
61#include <asm/sh_bios.h>
62#endif
63
64#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
65#define SUPPORT_SYSRQ
66#endif
67
68#include "sh-sci.h"
69
70#ifdef CONFIG_SH_KGDB
71#include <asm/kgdb.h>
72
73static int kgdb_get_char(struct sci_port *port);
74static void kgdb_put_char(struct sci_port *port, char c);
75static void kgdb_handle_error(struct sci_port *port);
76static struct sci_port *kgdb_sci_port;
77#endif /* CONFIG_SH_KGDB */
78
79#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
80static struct sci_port *serial_console_port = 0;
81#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
82
83/* Function prototypes */
b129a8cc
RK		 84static void sci_stop_tx(struct uart_port *port);
85static void sci_start_tx(struct uart_port *port);
1da177e4
LT		 86static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
87static void sci_stop_rx(struct uart_port *port);
88static int sci_request_irq(struct sci_port *port);
89static void sci_free_irq(struct sci_port *port);
90
b7a76e4b 91static struct sci_port sci_ports[];
1da177e4
LT		 92static struct uart_driver sci_uart_driver;
93
b7a76e4b
PM		 94#define SCI_NPORTS sci_uart_driver.nr
95
1da177e4
LT		 96#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
97
98static void handle_error(struct uart_port *port)
99{ /* Clear error flags */
100 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
101}
102
103static int get_char(struct uart_port *port)
104{
105 unsigned long flags;
106 unsigned short status;
107 int c;
108
109 local_irq_save(flags);
110 do {
111 status = sci_in(port, SCxSR);
112 if (status & SCxSR_ERRORS(port)) {
113 handle_error(port);
114 continue;
115 }
116 } while (!(status & SCxSR_RDxF(port)));
117 c = sci_in(port, SCxRDR);
118 sci_in(port, SCxSR); /* Dummy read */
119 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
120 local_irq_restore(flags);
121
122 return c;
123}
124
125/* Taken from sh-stub.c of GDB 4.18 */
126static const char hexchars[] = "0123456789abcdef";
127
128static __inline__ char highhex(int x)
129{
130 return hexchars[(x >> 4) & 0xf];
131}
132
133static __inline__ char lowhex(int x)
134{
135 return hexchars[x & 0xf];
136}
137
138#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
139
140/*
141 * Send the packet in buffer. The host gets one chance to read it.
142 * This routine does not wait for a positive acknowledge.
143 */
144
145#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
146static void put_char(struct uart_port *port, char c)
147{
148 unsigned long flags;
149 unsigned short status;
150
151 local_irq_save(flags);
152
153 do {
154 status = sci_in(port, SCxSR);
155 } while (!(status & SCxSR_TDxE(port)));
156
157 sci_out(port, SCxTDR, c);
158 sci_in(port, SCxSR); /* Dummy read */
159 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
160
161 local_irq_restore(flags);
162}
163
164static void put_string(struct sci_port *sci_port, const char *buffer, int count)
165{
166 struct uart_port *port = &sci_port->port;
167 const unsigned char *p = buffer;
168 int i;
169
170#if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
171 int checksum;
172 int usegdb=0;
173
174#ifdef CONFIG_SH_STANDARD_BIOS
b7a76e4b 175 /* This call only does a trap the first time it is
1da177e4
LT		 176 * called, and so is safe to do here unconditionally
177 */
178 usegdb |= sh_bios_in_gdb_mode();
179#endif
180#ifdef CONFIG_SH_KGDB
181 usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
182#endif
183
184 if (usegdb) {
185 /* $<packet info>#<checksum>. */
186 do {
187 unsigned char c;
188 put_char(port, '$');
189 put_char(port, 'O'); /* 'O'utput to console */
190 checksum = 'O';
191
192 for (i=0; i<count; i++) { /* Don't use run length encoding */
193 int h, l;
194
195 c = *p++;
196 h = highhex(c);
197 l = lowhex(c);
198 put_char(port, h);
199 put_char(port, l);
200 checksum += h + l;
201 }
202 put_char(port, '#');
203 put_char(port, highhex(checksum));
204 put_char(port, lowhex(checksum));
205 } while (get_char(port) != '+');
206 } else
207#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
208 for (i=0; i<count; i++) {
209 if (*p == 10)
210 put_char(port, '\r');
211 put_char(port, *p++);
212 }
213}
214#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
215
216
217#ifdef CONFIG_SH_KGDB
218
219/* Is the SCI ready, ie is there a char waiting? */
220static int kgdb_is_char_ready(struct sci_port *port)
221{
222 unsigned short status = sci_in(port, SCxSR);
223
224 if (status & (SCxSR_ERRORS(port) | SCxSR_BRK(port)))
225 kgdb_handle_error(port);
226
227 return (status & SCxSR_RDxF(port));
228}
229
230/* Write a char */
231static void kgdb_put_char(struct sci_port *port, char c)
232{
233 unsigned short status;
234
235 do
236 status = sci_in(port, SCxSR);
237 while (!(status & SCxSR_TDxE(port)));
238
239 sci_out(port, SCxTDR, c);
240 sci_in(port, SCxSR); /* Dummy read */
241 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
242}
243
244/* Get a char if there is one, else ret -1 */
245static int kgdb_get_char(struct sci_port *port)
246{
247 int c;
248
249 if (kgdb_is_char_ready(port) == 0)
250 c = -1;
251 else {
252 c = sci_in(port, SCxRDR);
253 sci_in(port, SCxSR); /* Dummy read */
254 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
255 }
256
257 return c;
258}
259
260/* Called from kgdbstub.c to get a character, i.e. is blocking */
261static int kgdb_sci_getchar(void)
262{
263 volatile int c;
264
265 /* Keep trying to read a character, this could be neater */
266 while ((c = kgdb_get_char(kgdb_sci_port)) < 0);
267
268 return c;
269}
270
271/* Called from kgdbstub.c to put a character, just a wrapper */
272static void kgdb_sci_putchar(int c)
273{
274
275 kgdb_put_char(kgdb_sci_port, c);
276}
277
278/* Clear any errors on the SCI */
279static void kgdb_handle_error(struct sci_port *port)
280{
281 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); /* Clear error flags */
282}
283
284/* Breakpoint if there's a break sent on the serial port */
285static void kgdb_break_interrupt(int irq, void *ptr, struct pt_regs *regs)
286{
287 struct sci_port *port = ptr;
288 unsigned short status = sci_in(port, SCxSR);
289
290 if (status & SCxSR_BRK(port)) {
291
292 /* Break into the debugger if a break is detected */
293 BREAKPOINT();
294
295 /* Clear */
296 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
297 }
298}
299
300#endif /* CONFIG_SH_KGDB */
301
302#if defined(__H8300S__)
303enum { sci_disable, sci_enable };
304
305static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl)
306{
307 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
308 int ch = (port->mapbase - SMR0) >> 3;
309 unsigned char mask = 1 << (ch+1);
310
311 if (ctrl == sci_disable) {
312 *mstpcrl |= mask;
313 } else {
314 *mstpcrl &= ~mask;
315 }
316}
317#endif
318
319#if defined(SCI_ONLY) || defined(SCI_AND_SCIF)
320#if defined(__H8300H__) || defined(__H8300S__)
321static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
322{
323 int ch = (port->mapbase - SMR0) >> 3;
324
325 /* set DDR regs */
326 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].rx,H8300_GPIO_INPUT);
327 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].tx,H8300_GPIO_OUTPUT);
328 /* tx mark output*/
329 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
330}
1da177e4
LT		 331#endif
332#endif
333
334#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
b7a76e4b
PM		 335#if defined(CONFIG_CPU_SUBTYPE_SH7300)
336/* SH7300 doesn't use RTS/CTS */
337static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
338{
339 sci_out(port, SCFCR, 0);
340}
341#elif defined(CONFIG_CPU_SH3)
342/* For SH7705, SH7707, SH7709, SH7709A, SH7729 */
1da177e4
LT		 343static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
344{
345 unsigned int fcr_val = 0;
b7a76e4b
PM		 346 unsigned short data;
347
348 /* We need to set SCPCR to enable RTS/CTS */
349 data = ctrl_inw(SCPCR);
350 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
351 ctrl_outw(data & 0x0fcf, SCPCR);
1da177e4 352
1da177e4
LT		 353 if (cflag & CRTSCTS)
354 fcr_val |= SCFCR_MCE;
355 else {
1da177e4
LT		 356 /* We need to set SCPCR to enable RTS/CTS */
357 data = ctrl_inw(SCPCR);
358 /* Clear out SCP7MD1,0, SCP4MD1,0,
359 Set SCP6MD1,0 = {01} (output) */
b7a76e4b 360 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
1da177e4
LT		 361
362 data = ctrl_inb(SCPDR);
363 /* Set /RTS2 (bit6) = 0 */
b7a76e4b 364 ctrl_outb(data & 0xbf, SCPDR);
1da177e4 365 }
b7a76e4b 366
1da177e4
LT		 367 sci_out(port, SCFCR, fcr_val);
368}
369
b7a76e4b 370#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 371static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
372{
373 unsigned int fcr_val = 0;
374
375 if (cflag & CRTSCTS)
376 fcr_val |= SCFCR_MCE;
377
378 sci_out(port, SCFCR, fcr_val);
379}
b7a76e4b 380#endif
1da177e4
LT		 381#else
382
383/* For SH7750 */
384static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
385{
386 unsigned int fcr_val = 0;
387
388 if (cflag & CRTSCTS) {
389 fcr_val |= SCFCR_MCE;
390 } else {
b7a76e4b
PM		 391#ifdef CONFIG_CPU_SUBTYPE_SH7780
392 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
393#else
1da177e4 394 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
b7a76e4b 395#endif
1da177e4
LT		 396 }
397 sci_out(port, SCFCR, fcr_val);
398}
399
400#endif
401#endif /* SCIF_ONLY || SCI_AND_SCIF */
402
403/* ********************************************************************** *
404 * the interrupt related routines *
405 * ********************************************************************** */
406
407static void sci_transmit_chars(struct uart_port *port)
408{
409 struct circ_buf *xmit = &port->info->xmit;
410 unsigned int stopped = uart_tx_stopped(port);
411 unsigned long flags;
412 unsigned short status;
413 unsigned short ctrl;
414 int count, txroom;
415
416 status = sci_in(port, SCxSR);
417 if (!(status & SCxSR_TDxE(port))) {
418 local_irq_save(flags);
419 ctrl = sci_in(port, SCSCR);
420 if (uart_circ_empty(xmit)) {
421 ctrl &= ~SCI_CTRL_FLAGS_TIE;
422 } else {
423 ctrl |= SCI_CTRL_FLAGS_TIE;
424 }
425 sci_out(port, SCSCR, ctrl);
426 local_irq_restore(flags);
427 return;
428 }
429
430#if !defined(SCI_ONLY)
431 if (port->type == PORT_SCIF) {
b7a76e4b
PM		 432#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
433 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
434#else
1da177e4 435 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8);
b7a76e4b 436#endif
1da177e4
LT		 437 } else {
438 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
439 }
440#else
441 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
442#endif
443
444 count = txroom;
445
446 do {
447 unsigned char c;
448
449 if (port->x_char) {
450 c = port->x_char;
451 port->x_char = 0;
452 } else if (!uart_circ_empty(xmit) && !stopped) {
453 c = xmit->buf[xmit->tail];
454 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
455 } else {
456 break;
457 }
458
459 sci_out(port, SCxTDR, c);
460
461 port->icount.tx++;
462 } while (--count > 0);
463
464 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
465
466 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
467 uart_write_wakeup(port);
468 if (uart_circ_empty(xmit)) {
b129a8cc 469 sci_stop_tx(port);
1da177e4
LT		 470 } else {
471 local_irq_save(flags);
472 ctrl = sci_in(port, SCSCR);
473
474#if !defined(SCI_ONLY)
475 if (port->type == PORT_SCIF) {
476 sci_in(port, SCxSR); /* Dummy read */
477 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
478 }
479#endif
480
481 ctrl |= SCI_CTRL_FLAGS_TIE;
482 sci_out(port, SCSCR, ctrl);
483 local_irq_restore(flags);
484 }
485}
486
487/* On SH3, SCIF may read end-of-break as a space->mark char */
488#define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
489
490static inline void sci_receive_chars(struct uart_port *port,
491 struct pt_regs *regs)
492{
493 struct tty_struct *tty = port->info->tty;
494 int i, count, copied = 0;
495 unsigned short status;
33f0f88f 496 unsigned char flag;
1da177e4
LT		 497
498 status = sci_in(port, SCxSR);
499 if (!(status & SCxSR_RDxF(port)))
500 return;
501
502 while (1) {
503#if !defined(SCI_ONLY)
504 if (port->type == PORT_SCIF) {
b7a76e4b
PM		 505#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
506 count = sci_in(port, SCRFDR) & 0x7f;
507#else
1da177e4 508 count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ;
b7a76e4b 509#endif
1da177e4
LT		 510 } else {
511 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
512 }
513#else
514 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
515#endif
516
517 /* Don't copy more bytes than there is room for in the buffer */
33f0f88f 518 count = tty_buffer_request_room(tty, count);
1da177e4
LT		 519
520 /* If for any reason we can't copy more data, we're done! */
521 if (count == 0)
522 break;
523
524 if (port->type == PORT_SCI) {
525 char c = sci_in(port, SCxRDR);
526 if(((struct sci_port *)port)->break_flag
527 || uart_handle_sysrq_char(port, c, regs)) {
528 count = 0;
529 } else {
33f0f88f 530 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4
LT		 531 }
532 } else {
533 for (i=0; i<count; i++) {
534 char c = sci_in(port, SCxRDR);
535 status = sci_in(port, SCxSR);
536#if defined(CONFIG_CPU_SH3)
537 /* Skip "chars" during break */
538 if (((struct sci_port *)port)->break_flag) {
539 if ((c == 0) &&
540 (status & SCxSR_FER(port))) {
541 count--; i--;
542 continue;
543 }
544 /* Nonzero => end-of-break */
545 pr_debug("scif: debounce<%02x>\n", c);
546 ((struct sci_port *)port)->break_flag = 0;
547 if (STEPFN(c)) {
548 count--; i--;
549 continue;
550 }
551 }
552#endif /* CONFIG_CPU_SH3 */
553 if (uart_handle_sysrq_char(port, c, regs)) {
554 count--; i--;
555 continue;
556 }
557
558 /* Store data and status */
1da177e4 559 if (status&SCxSR_FER(port)) {
33f0f88f 560 flag = TTY_FRAME;
1da177e4
LT		 561 pr_debug("sci: frame error\n");
562 } else if (status&SCxSR_PER(port)) {
33f0f88f 563 flag = TTY_PARITY;
1da177e4 564 pr_debug("sci: parity error\n");
33f0f88f
AC		 565 } else
566 flag = TTY_NORMAL;
567 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 568 }
569 }
570
571 sci_in(port, SCxSR); /* dummy read */
572 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
573
1da177e4
LT		 574 copied += count;
575 port->icount.rx += count;
576 }
577
578 if (copied) {
579 /* Tell the rest of the system the news. New characters! */
580 tty_flip_buffer_push(tty);
581 } else {
582 sci_in(port, SCxSR); /* dummy read */
583 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
584 }
585}
586
587#define SCI_BREAK_JIFFIES (HZ/20)
588/* The sci generates interrupts during the break,
589 * 1 per millisecond or so during the break period, for 9600 baud.
590 * So dont bother disabling interrupts.
591 * But dont want more than 1 break event.
592 * Use a kernel timer to periodically poll the rx line until
593 * the break is finished.
594 */
595static void sci_schedule_break_timer(struct sci_port *port)
596{
597 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
598 add_timer(&port->break_timer);
599}
600/* Ensure that two consecutive samples find the break over. */
601static void sci_break_timer(unsigned long data)
602{
603 struct sci_port * port = (struct sci_port *)data;
604 if(sci_rxd_in(&port->port) == 0) {
605 port->break_flag = 1;
606 sci_schedule_break_timer(port);
607 } else if(port->break_flag == 1){
608 /* break is over. */
609 port->break_flag = 2;
610 sci_schedule_break_timer(port);
611 } else port->break_flag = 0;
612}
613
614static inline int sci_handle_errors(struct uart_port *port)
615{
616 int copied = 0;
617 unsigned short status = sci_in(port, SCxSR);
618 struct tty_struct *tty = port->info->tty;
619
33f0f88f 620 if (status&SCxSR_ORER(port)) {
1da177e4 621 /* overrun error */
33f0f88f
AC		 622 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN))
623 copied++;
1da177e4
LT		 624 pr_debug("sci: overrun error\n");
625 }
626
33f0f88f 627 if (status&SCxSR_FER(port)) {
1da177e4
LT		 628 if (sci_rxd_in(port) == 0) {
629 /* Notify of BREAK */
630 struct sci_port * sci_port = (struct sci_port *)port;
33f0f88f
AC		 631 if(!sci_port->break_flag) {
632 sci_port->break_flag = 1;
633 sci_schedule_break_timer((struct sci_port *)port);
1da177e4 634 /* Do sysrq handling. */
33f0f88f 635 if(uart_handle_break(port))
1da177e4 636 return 0;
1da177e4 637 pr_debug("sci: BREAK detected\n");
33f0f88f
AC		 638 if(tty_insert_flip_char(tty, 0, TTY_BREAK))
639 copied++;
1da177e4
LT		 640 }
641 }
642 else {
643 /* frame error */
33f0f88f
AC		 644 if(tty_insert_flip_char(tty, 0, TTY_FRAME))
645 copied++;
1da177e4
LT		 646 pr_debug("sci: frame error\n");
647 }
648 }
649
33f0f88f
AC		 650 if (status&SCxSR_PER(port)) {
651 if(tty_insert_flip_char(tty, 0, TTY_PARITY))
652 copied++;
1da177e4 653 /* parity error */
1da177e4
LT		 654 pr_debug("sci: parity error\n");
655 }
656
33f0f88f 657 if (copied)
1da177e4 658 tty_flip_buffer_push(tty);
1da177e4
LT		 659
660 return copied;
661}
662
663static inline int sci_handle_breaks(struct uart_port *port)
664{
665 int copied = 0;
666 unsigned short status = sci_in(port, SCxSR);
667 struct tty_struct *tty = port->info->tty;
668 struct sci_port *s = &sci_ports[port->line];
669
b7a76e4b 670 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 671#if defined(CONFIG_CPU_SH3)
672 /* Debounce break */
673 s->break_flag = 1;
674#endif
675 /* Notify of BREAK */
33f0f88f
AC		 676 if(tty_insert_flip_char(tty, 0, TTY_BREAK))
677 copied++;
1da177e4
LT		 678 pr_debug("sci: BREAK detected\n");
679 }
680
681#if defined(SCIF_ORER)
682 /* XXX: Handle SCIF overrun error */
683 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
684 sci_out(port, SCLSR, 0);
33f0f88f 685 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
1da177e4 686 copied++;
1da177e4
LT		 687 pr_debug("sci: overrun error\n");
688 }
689 }
690#endif
691
33f0f88f 692 if (copied)
1da177e4 693 tty_flip_buffer_push(tty);
1da177e4
LT		 694 return copied;
695}
696
697static irqreturn_t sci_rx_interrupt(int irq, void *ptr, struct pt_regs *regs)
698{
699 struct uart_port *port = ptr;
700
701 /* I think sci_receive_chars has to be called irrespective
702 * of whether the I_IXOFF is set, otherwise, how is the interrupt
703 * to be disabled?
704 */
705 sci_receive_chars(port, regs);
706
707 return IRQ_HANDLED;
708}
709
710static irqreturn_t sci_tx_interrupt(int irq, void *ptr, struct pt_regs *regs)
711{
712 struct uart_port *port = ptr;
713
714 sci_transmit_chars(port);
715
716 return IRQ_HANDLED;
717}
718
719static irqreturn_t sci_er_interrupt(int irq, void *ptr, struct pt_regs *regs)
720{
721 struct uart_port *port = ptr;
722
723 /* Handle errors */
724 if (port->type == PORT_SCI) {
725 if (sci_handle_errors(port)) {
726 /* discard character in rx buffer */
727 sci_in(port, SCxSR);
728 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
729 }
730 } else {
731#if defined(SCIF_ORER)
732 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
733 struct tty_struct *tty = port->info->tty;
734
735 sci_out(port, SCLSR, 0);
33f0f88f
AC		 736 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
737 tty_flip_buffer_push(tty);
738 pr_debug("scif: overrun error\n");
1da177e4
LT		 739 }
740#endif
741 sci_rx_interrupt(irq, ptr, regs);
742 }
743
744 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
745
746 /* Kick the transmission */
747 sci_tx_interrupt(irq, ptr, regs);
748
749 return IRQ_HANDLED;
750}
751
752static irqreturn_t sci_br_interrupt(int irq, void *ptr, struct pt_regs *regs)
753{
754 struct uart_port *port = ptr;
755
756 /* Handle BREAKs */
757 sci_handle_breaks(port);
758 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
759
760 return IRQ_HANDLED;
761}
762
763static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
764{
765 unsigned short ssr_status, scr_status;
766 struct uart_port *port = ptr;
767
768 ssr_status = sci_in(port,SCxSR);
769 scr_status = sci_in(port,SCSCR);
770
771 /* Tx Interrupt */
772 if ((ssr_status&0x0020) && (scr_status&0x0080))
773 sci_tx_interrupt(irq, ptr, regs);
774 /* Rx Interrupt */
775 if ((ssr_status&0x0002) && (scr_status&0x0040))
776 sci_rx_interrupt(irq, ptr, regs);
777 /* Error Interrupt */
778 if ((ssr_status&0x0080) && (scr_status&0x0400))
779 sci_er_interrupt(irq, ptr, regs);
780 /* Break Interrupt */
781 if ((ssr_status&0x0010) && (scr_status&0x0200))
782 sci_br_interrupt(irq, ptr, regs);
783
784 return IRQ_HANDLED;
785}
786
787#ifdef CONFIG_CPU_FREQ
788/*
789 * Here we define a transistion notifier so that we can update all of our
790 * ports' baud rate when the peripheral clock changes.
791 */
792static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p)
793{
794 struct cpufreq_freqs *freqs = p;
795 int i;
796
797 if ((phase == CPUFREQ_POSTCHANGE) ||
798 (phase == CPUFREQ_RESUMECHANGE)){
799 for (i = 0; i < SCI_NPORTS; i++) {
800 struct uart_port *port = &sci_ports[i].port;
b7a76e4b 801 struct clk *clk;
1da177e4
LT		 802
803 /*
804 * Update the uartclk per-port if frequency has
805 * changed, since it will no longer necessarily be
806 * consistent with the old frequency.
807 *
808 * Really we want to be able to do something like
809 * uart_change_speed() or something along those lines
810 * here to implicitly reset the per-port baud rate..
811 *
812 * Clean this up later..
813 */
b7a76e4b
PM		 814 clk = clk_get("module_clk");
815 port->uartclk = clk_get_rate(clk) * 16;
816 clk_put(clk);
1da177e4
LT		 817 }
818
819 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n",
820 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
821 }
822
823 return NOTIFY_OK;
824}
825
826static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
827#endif /* CONFIG_CPU_FREQ */
828
829static int sci_request_irq(struct sci_port *port)
830{
831 int i;
832 irqreturn_t (*handlers[4])(int irq, void *ptr, struct pt_regs *regs) = {
833 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
834 sci_br_interrupt,
835 };
836 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
837 "SCI Transmit Data Empty", "SCI Break" };
838
839 if (port->irqs[0] == port->irqs[1]) {
840 if (!port->irqs[0]) {
841 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
842 return -ENODEV;
843 }
40663cc7 844 if (request_irq(port->irqs[0], sci_mpxed_interrupt, IRQF_DISABLED,
1da177e4
LT		 845 "sci", port)) {
846 printk(KERN_ERR "sci: Cannot allocate irq.\n");
847 return -ENODEV;
848 }
849 } else {
850 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
851 if (!port->irqs[i])
852 continue;
40663cc7 853 if (request_irq(port->irqs[i], handlers[i], IRQF_DISABLED,
1da177e4
LT		 854 desc[i], port)) {
855 printk(KERN_ERR "sci: Cannot allocate irq.\n");
856 return -ENODEV;
857 }
858 }
859 }
860
861 return 0;
862}
863
864static void sci_free_irq(struct sci_port *port)
865{
866 int i;
867
868 if (port->irqs[0] == port->irqs[1]) {
869 if (!port->irqs[0])
870 printk("sci: sci_free_irq error\n");
871 else
872 free_irq(port->irqs[0], port);
873 } else {
874 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
875 if (!port->irqs[i])
876 continue;
877
878 free_irq(port->irqs[i], port);
879 }
880 }
881}
882
883static unsigned int sci_tx_empty(struct uart_port *port)
884{
885 /* Can't detect */
886 return TIOCSER_TEMT;
887}
888
889static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
890{
891 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
892 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
893 /* If you have signals for DTR and DCD, please implement here. */
894}
895
896static unsigned int sci_get_mctrl(struct uart_port *port)
897{
898 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
899 and CTS/RTS */
900
901 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
902}
903
b129a8cc 904static void sci_start_tx(struct uart_port *port)
1da177e4
LT		 905{
906 struct sci_port *s = &sci_ports[port->line];
907
908 disable_irq(s->irqs[SCIx_TXI_IRQ]);
909 sci_transmit_chars(port);
910 enable_irq(s->irqs[SCIx_TXI_IRQ]);
911}
912
b129a8cc 913static void sci_stop_tx(struct uart_port *port)
1da177e4
LT		 914{
915 unsigned long flags;
916 unsigned short ctrl;
917
918 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
919 local_irq_save(flags);
920 ctrl = sci_in(port, SCSCR);
921 ctrl &= ~SCI_CTRL_FLAGS_TIE;
922 sci_out(port, SCSCR, ctrl);
923 local_irq_restore(flags);
924}
925
926static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
927{
928 unsigned long flags;
929 unsigned short ctrl;
930
931 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
932 local_irq_save(flags);
933 ctrl = sci_in(port, SCSCR);
934 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
935 sci_out(port, SCSCR, ctrl);
936 local_irq_restore(flags);
937}
938
939static void sci_stop_rx(struct uart_port *port)
940{
941 unsigned long flags;
942 unsigned short ctrl;
943
944 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
945 local_irq_save(flags);
946 ctrl = sci_in(port, SCSCR);
947 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
948 sci_out(port, SCSCR, ctrl);
949 local_irq_restore(flags);
950}
951
952static void sci_enable_ms(struct uart_port *port)
953{
954 /* Nothing here yet .. */
955}
956
957static void sci_break_ctl(struct uart_port *port, int break_state)
958{
959 /* Nothing here yet .. */
960}
961
962static int sci_startup(struct uart_port *port)
963{
964 struct sci_port *s = &sci_ports[port->line];
965
966#if defined(__H8300S__)
967 h8300_sci_enable(port, sci_enable);
968#endif
969
970 sci_request_irq(s);
d656901b 971 sci_start_tx(port);
1da177e4
LT		 972 sci_start_rx(port, 1);
973
974 return 0;
975}
976
977static void sci_shutdown(struct uart_port *port)
978{
979 struct sci_port *s = &sci_ports[port->line];
980
981 sci_stop_rx(port);
b129a8cc 982 sci_stop_tx(port);
1da177e4
LT		 983 sci_free_irq(s);
984
985#if defined(__H8300S__)
986 h8300_sci_enable(port, sci_disable);
987#endif
988}
989
990static void sci_set_termios(struct uart_port *port, struct termios *termios,
991 struct termios *old)
992{
993 struct sci_port *s = &sci_ports[port->line];
994 unsigned int status, baud, smr_val;
995 unsigned long flags;
996 int t;
997
998 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
999
1000 spin_lock_irqsave(&port->lock, flags);
1001
1002 do {
1003 status = sci_in(port, SCxSR);
1004 } while (!(status & SCxSR_TEND(port)));
1005
1006 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1007
1008#if !defined(SCI_ONLY)
1009 if (port->type == PORT_SCIF) {
1010 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1011 }
1012#endif
1013
1014 smr_val = sci_in(port, SCSMR) & 3;
1015 if ((termios->c_cflag & CSIZE) == CS7)
1016 smr_val |= 0x40;
1017 if (termios->c_cflag & PARENB)
1018 smr_val |= 0x20;
1019 if (termios->c_cflag & PARODD)
1020 smr_val |= 0x30;
1021 if (termios->c_cflag & CSTOPB)
1022 smr_val |= 0x08;
1023
1024 uart_update_timeout(port, termios->c_cflag, baud);
1025
1026 sci_out(port, SCSMR, smr_val);
1027
1028 switch (baud) {
b7a76e4b
PM		 1029 case 0:
1030 t = -1;
1031 break;
1032 default:
1033 {
1034#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1035 struct clk *clk = clk_get("module_clk");
1036 t = SCBRR_VALUE(baud, clk_get_rate(clk));
1037 clk_put(clk);
1038#else
1039 t = SCBRR_VALUE(baud);
1040#endif
1041 }
1042 break;
1da177e4
LT		 1043 }
1044
1045 if (t > 0) {
1046 if(t >= 256) {
1047 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1048 t >>= 2;
1049 } else {
1050 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1051 }
1052 sci_out(port, SCBRR, t);
1053 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1054 }
1055
b7a76e4b
PM		 1056 if (likely(s->init_pins))
1057 s->init_pins(port, termios->c_cflag);
1058
1da177e4
LT		 1059 sci_out(port, SCSCR, SCSCR_INIT(port));
1060
1061 if ((termios->c_cflag & CREAD) != 0)
1062 sci_start_rx(port,0);
1063
1064 spin_unlock_irqrestore(&port->lock, flags);
1065}
1066
1067static const char *sci_type(struct uart_port *port)
1068{
1069 switch (port->type) {
1070 case PORT_SCI: return "sci";
1071 case PORT_SCIF: return "scif";
1072 case PORT_IRDA: return "irda";
1073 }
1074
1075 return 0;
1076}
1077
1078static void sci_release_port(struct uart_port *port)
1079{
1080 /* Nothing here yet .. */
1081}
1082
1083static int sci_request_port(struct uart_port *port)
1084{
1085 /* Nothing here yet .. */
1086 return 0;
1087}
1088
1089static void sci_config_port(struct uart_port *port, int flags)
1090{
1091 struct sci_port *s = &sci_ports[port->line];
1092
1093 port->type = s->type;
1094
1095#if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1096 if (port->mapbase == 0)
1097 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1098
1099 port->membase = (void *)port->mapbase;
1100#endif
1101}
1102
1103static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1104{
1105 struct sci_port *s = &sci_ports[port->line];
1106
1107 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1108 return -EINVAL;
1109 if (ser->baud_base < 2400)
1110 /* No paper tape reader for Mitch.. */
1111 return -EINVAL;
1112
1113 return 0;
1114}
1115
1116static struct uart_ops sci_uart_ops = {
1117 .tx_empty = sci_tx_empty,
1118 .set_mctrl = sci_set_mctrl,
1119 .get_mctrl = sci_get_mctrl,
1120 .start_tx = sci_start_tx,
1121 .stop_tx = sci_stop_tx,
1122 .stop_rx = sci_stop_rx,
1123 .enable_ms = sci_enable_ms,
1124 .break_ctl = sci_break_ctl,
1125 .startup = sci_startup,
1126 .shutdown = sci_shutdown,
1127 .set_termios = sci_set_termios,
1128 .type = sci_type,
1129 .release_port = sci_release_port,
1130 .request_port = sci_request_port,
1131 .config_port = sci_config_port,
1132 .verify_port = sci_verify_port,
1133};
1134
b7a76e4b 1135static struct sci_port sci_ports[] = {
1da177e4
LT		 1136#if defined(CONFIG_CPU_SUBTYPE_SH7708)
1137 {
1138 .port = {
1139 .membase = (void *)0xfffffe80,
1140 .mapbase = 0xfffffe80,
ce8337cb 1141 .iotype = UPIO_MEM,
1da177e4
LT		 1142 .irq = 25,
1143 .ops = &sci_uart_ops,
ce8337cb 1144 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1145 .line = 0,
1146 },
1147 .type = PORT_SCI,
1148 .irqs = SCI_IRQS,
1da177e4
LT		 1149 },
1150#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
1151 {
1152 .port = {
1153 .membase = (void *)SCIF0,
1154 .mapbase = SCIF0,
ce8337cb 1155 .iotype = UPIO_MEM,
1da177e4
LT		 1156 .irq = 55,
1157 .ops = &sci_uart_ops,
ce8337cb 1158 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1159 .line = 0,
1160 },
1161 .type = PORT_SCIF,
1162 .irqs = SH3_IRDA_IRQS,
1163 .init_pins = sci_init_pins_scif,
1164 },
1165 {
1166 .port = {
1167 .membase = (void *)SCIF2,
1168 .mapbase = SCIF2,
ce8337cb 1169 .iotype = UPIO_MEM,
1da177e4
LT		 1170 .irq = 59,
1171 .ops = &sci_uart_ops,
ce8337cb 1172 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1173 .line = 1,
1174 },
1175 .type = PORT_SCIF,
1176 .irqs = SH3_SCIF_IRQS,
1177 .init_pins = sci_init_pins_scif,
1178 }
1179#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1180 {
1181 .port = {
1182 .membase = (void *)0xfffffe80,
1183 .mapbase = 0xfffffe80,
ce8337cb 1184 .iotype = UPIO_MEM,
1da177e4
LT		 1185 .irq = 25,
1186 .ops = &sci_uart_ops,
ce8337cb 1187 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1188 .line = 0,
1189 },
1190 .type = PORT_SCI,
1191 .irqs = SCI_IRQS,
1da177e4
LT		 1192 },
1193 {
1194 .port = {
1195 .membase = (void *)0xa4000150,
1196 .mapbase = 0xa4000150,
ce8337cb 1197 .iotype = UPIO_MEM,
1da177e4
LT		 1198 .irq = 59,
1199 .ops = &sci_uart_ops,
ce8337cb 1200 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1201 .line = 1,
1202 },
1203 .type = PORT_SCIF,
1204 .irqs = SH3_SCIF_IRQS,
1205 .init_pins = sci_init_pins_scif,
1206 },
1207 {
1208 .port = {
1209 .membase = (void *)0xa4000140,
1210 .mapbase = 0xa4000140,
ce8337cb 1211 .iotype = UPIO_MEM,
1da177e4
LT		 1212 .irq = 55,
1213 .ops = &sci_uart_ops,
ce8337cb 1214 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1215 .line = 2,
1216 },
1217 .type = PORT_IRDA,
1218 .irqs = SH3_IRDA_IRQS,
1219 .init_pins = sci_init_pins_irda,
1220 }
1221#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
1222 {
1223 .port = {
1224 .membase = (void *)0xA4430000,
1225 .mapbase = 0xA4430000,
ce8337cb 1226 .iotype = UPIO_MEM,
1da177e4
LT		 1227 .irq = 25,
1228 .ops = &sci_uart_ops,
ce8337cb 1229 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1230 .line = 0,
1231 },
1232 .type = PORT_SCIF,
1233 .irqs = SH7300_SCIF0_IRQS,
1234 .init_pins = sci_init_pins_scif,
1235 },
1236#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
1237 {
1238 .port = {
1239 .membase = (void *)0xffe00000,
1240 .mapbase = 0xffe00000,
ce8337cb 1241 .iotype = UPIO_MEM,
1da177e4
LT		 1242 .irq = 25,
1243 .ops = &sci_uart_ops,
ce8337cb 1244 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1245 .line = 0,
1246 },
1247 .type = PORT_SCIF,
1248 .irqs = SH73180_SCIF_IRQS,
1249 .init_pins = sci_init_pins_scif,
1250 },
b7a76e4b 1251#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1da177e4
LT		 1252 {
1253 .port = {
1254 .membase = (void *)0xffe80000,
1255 .mapbase = 0xffe80000,
ce8337cb 1256 .iotype = UPIO_MEM,
1da177e4
LT		 1257 .irq = 43,
1258 .ops = &sci_uart_ops,
ce8337cb 1259 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1260 .line = 0,
1261 },
1262 .type = PORT_SCIF,
1263 .irqs = SH4_SCIF_IRQS,
1264 .init_pins = sci_init_pins_scif,
1265 },
1266#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1267 {
1268 .port = {
1269 .membase = (void *)0xffe00000,
1270 .mapbase = 0xffe00000,
ce8337cb 1271 .iotype = UPIO_MEM,
1da177e4
LT		 1272 .irq = 25,
1273 .ops = &sci_uart_ops,
ce8337cb 1274 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1275 .line = 0,
1276 },
1277 .type = PORT_SCI,
1278 .irqs = SCI_IRQS,
1da177e4
LT		 1279 },
1280 {
1281 .port = {
1282 .membase = (void *)0xffe80000,
1283 .mapbase = 0xffe80000,
ce8337cb 1284 .iotype = UPIO_MEM,
1da177e4
LT		 1285 .irq = 43,
1286 .ops = &sci_uart_ops,
ce8337cb 1287 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1288 .line = 1,
1289 },
1290 .type = PORT_SCIF,
1291 .irqs = SH4_SCIF_IRQS,
1292 .init_pins = sci_init_pins_scif,
1293 },
1294#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
1295 {
1296 .port = {
1297 .membase = (void *)0xfe600000,
1298 .mapbase = 0xfe600000,
ce8337cb 1299 .iotype = UPIO_MEM,
1da177e4
LT		 1300 .irq = 55,
1301 .ops = &sci_uart_ops,
ce8337cb 1302 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1303 .line = 0,
1304 },
1305 .type = PORT_SCIF,
1306 .irqs = SH7760_SCIF0_IRQS,
1307 .init_pins = sci_init_pins_scif,
1308 },
1309 {
1310 .port = {
1311 .membase = (void *)0xfe610000,
1312 .mapbase = 0xfe610000,
ce8337cb 1313 .iotype = UPIO_MEM,
1da177e4
LT		 1314 .irq = 75,
1315 .ops = &sci_uart_ops,
ce8337cb 1316 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1317 .line = 1,
1318 },
1319 .type = PORT_SCIF,
1320 .irqs = SH7760_SCIF1_IRQS,
1321 .init_pins = sci_init_pins_scif,
1322 },
1323 {
1324 .port = {
1325 .membase = (void *)0xfe620000,
1326 .mapbase = 0xfe620000,
ce8337cb 1327 .iotype = UPIO_MEM,
1da177e4
LT		 1328 .irq = 79,
1329 .ops = &sci_uart_ops,
ce8337cb 1330 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1331 .line = 2,
1332 },
1333 .type = PORT_SCIF,
1334 .irqs = SH7760_SCIF2_IRQS,
1335 .init_pins = sci_init_pins_scif,
1336 },
1da177e4
LT		 1337#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1338 {
1339 .port = {
1340 .membase = (void *)0xffe00000,
1341 .mapbase = 0xffe00000,
ce8337cb 1342 .iotype = UPIO_MEM,
1da177e4
LT		 1343 .irq = 26,
1344 .ops = &sci_uart_ops,
ce8337cb 1345 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1346 .line = 0,
1347 },
1348 .type = PORT_SCIF,
1349 .irqs = STB1_SCIF1_IRQS,
1350 .init_pins = sci_init_pins_scif,
1351 },
1352 {
1353 .port = {
1354 .membase = (void *)0xffe80000,
1355 .mapbase = 0xffe80000,
ce8337cb 1356 .iotype = UPIO_MEM,
1da177e4
LT		 1357 .irq = 43,
1358 .ops = &sci_uart_ops,
ce8337cb 1359 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1360 .line = 1,
1361 },
1362 .type = PORT_SCIF,
1363 .irqs = SH4_SCIF_IRQS,
1364 .init_pins = sci_init_pins_scif,
1365 },
1366#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1367 {
1368 .port = {
ce8337cb 1369 .iotype = UPIO_MEM,
1da177e4
LT		 1370 .irq = 42,
1371 .ops = &sci_uart_ops,
ce8337cb 1372 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1373 .line = 0,
1374 },
1375 .type = PORT_SCIF,
1376 .irqs = SH5_SCIF_IRQS,
1377 .init_pins = sci_init_pins_scif,
1378 },
1379#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1380 {
1381 .port = {
1382 .membase = (void *)0x00ffffb0,
1383 .mapbase = 0x00ffffb0,
ce8337cb 1384 .iotype = UPIO_MEM,
1da177e4
LT		 1385 .irq = 54,
1386 .ops = &sci_uart_ops,
ce8337cb 1387 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1388 .line = 0,
1389 },
1390 .type = PORT_SCI,
1391 .irqs = H8300H_SCI_IRQS0,
1392 .init_pins = sci_init_pins_sci,
1393 },
1394 {
1395 .port = {
1396 .membase = (void *)0x00ffffb8,
1397 .mapbase = 0x00ffffb8,
ce8337cb 1398 .iotype = UPIO_MEM,
1da177e4
LT		 1399 .irq = 58,
1400 .ops = &sci_uart_ops,
ce8337cb 1401 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1402 .line = 1,
1403 },
1404 .type = PORT_SCI,
1405 .irqs = H8300H_SCI_IRQS1,
1406 .init_pins = sci_init_pins_sci,
1407 },
1408 {
1409 .port = {
1410 .membase = (void *)0x00ffffc0,
1411 .mapbase = 0x00ffffc0,
ce8337cb 1412 .iotype = UPIO_MEM,
1da177e4
LT		 1413 .irq = 62,
1414 .ops = &sci_uart_ops,
ce8337cb 1415 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1416 .line = 2,
1417 },
1418 .type = PORT_SCI,
1419 .irqs = H8300H_SCI_IRQS2,
1420 .init_pins = sci_init_pins_sci,
1421 },
1422#elif defined(CONFIG_H8S2678)
1423 {
1424 .port = {
1425 .membase = (void *)0x00ffff78,
1426 .mapbase = 0x00ffff78,
ce8337cb 1427 .iotype = UPIO_MEM,
1da177e4
LT		 1428 .irq = 90,
1429 .ops = &sci_uart_ops,
ce8337cb 1430 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1431 .line = 0,
1432 },
1433 .type = PORT_SCI,
1434 .irqs = H8S_SCI_IRQS0,
1435 .init_pins = sci_init_pins_sci,
1436 },
1437 {
1438 .port = {
1439 .membase = (void *)0x00ffff80,
1440 .mapbase = 0x00ffff80,
ce8337cb 1441 .iotype = UPIO_MEM,
1da177e4
LT		 1442 .irq = 94,
1443 .ops = &sci_uart_ops,
ce8337cb 1444 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1445 .line = 1,
1446 },
1447 .type = PORT_SCI,
1448 .irqs = H8S_SCI_IRQS1,
1449 .init_pins = sci_init_pins_sci,
1450 },
1451 {
1452 .port = {
1453 .membase = (void *)0x00ffff88,
1454 .mapbase = 0x00ffff88,
ce8337cb 1455 .iotype = UPIO_MEM,
1da177e4
LT		 1456 .irq = 98,
1457 .ops = &sci_uart_ops,
ce8337cb 1458 .flags = UPF_BOOT_AUTOCONF,
1da177e4
LT		 1459 .line = 2,
1460 },
1461 .type = PORT_SCI,
1462 .irqs = H8S_SCI_IRQS2,
1463 .init_pins = sci_init_pins_sci,
1464 },
b7a76e4b
PM		 1465#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
1466 {
1467 .port = {
1468 .membase = (void *)0xff923000,
1469 .mapbase = 0xff923000,
9b4a1617 1470 .iotype = UPIO_MEM,
b7a76e4b
PM		 1471 .irq = 61,
1472 .ops = &sci_uart_ops,
59a675b2 1473 .flags = UPF_BOOT_AUTOCONF,
b7a76e4b
PM		 1474 .line = 0,
1475 },
1476 .type = PORT_SCIF,
1477 .irqs = SH7770_SCIF0_IRQS,
1478 .init_pins = sci_init_pins_scif,
1479 },
1480 {
1481 .port = {
1482 .membase = (void *)0xff924000,
1483 .mapbase = 0xff924000,
9b4a1617 1484 .iotype = UPIO_MEM,
b7a76e4b
PM		 1485 .irq = 62,
1486 .ops = &sci_uart_ops,
59a675b2 1487 .flags = UPF_BOOT_AUTOCONF,
b7a76e4b
PM		 1488 .line = 1,
1489 },
1490 .type = PORT_SCIF,
1491 .irqs = SH7770_SCIF1_IRQS,
1492 .init_pins = sci_init_pins_scif,
1493 },
1494 {
1495 .port = {
1496 .membase = (void *)0xff925000,
1497 .mapbase = 0xff925000,
9b4a1617 1498 .iotype = UPIO_MEM,
b7a76e4b
PM		 1499 .irq = 63,
1500 .ops = &sci_uart_ops,
59a675b2 1501 .flags = UPF_BOOT_AUTOCONF,
b7a76e4b
PM		 1502 .line = 2,
1503 },
1504 .type = PORT_SCIF,
1505 .irqs = SH7770_SCIF2_IRQS,
1506 .init_pins = sci_init_pins_scif,
1507 },
1508#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
1509 {
1510 .port = {
1511 .membase = (void *)0xffe00000,
1512 .mapbase = 0xffe00000,
9b4a1617 1513 .iotype = UPIO_MEM,
b7a76e4b
PM		 1514 .irq = 43,
1515 .ops = &sci_uart_ops,
59a675b2 1516 .flags = UPF_BOOT_AUTOCONF,
b7a76e4b
PM		 1517 .line = 0,
1518 },
1519 .type = PORT_SCIF,
1520 .irqs = SH7780_SCIF0_IRQS,
1521 .init_pins = sci_init_pins_scif,
1522 },
1523 {
1524 .port = {
1525 .membase = (void *)0xffe10000,
1526 .mapbase = 0xffe10000,
9b4a1617 1527 .iotype = UPIO_MEM,
b7a76e4b
PM		 1528 .irq = 79,
1529 .ops = &sci_uart_ops,
59a675b2 1530 .flags = UPF_BOOT_AUTOCONF,
b7a76e4b
PM		 1531 .line = 1,
1532 },
1533 .type = PORT_SCIF,
1534 .irqs = SH7780_SCIF1_IRQS,
1535 .init_pins = sci_init_pins_scif,
1536 },
1da177e4
LT		 1537#else
1538#error "CPU subtype not defined"
1539#endif
1540};
1541
1542#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1543/*
1544 * Print a string to the serial port trying not to disturb
1545 * any possible real use of the port...
1546 */
1547static void serial_console_write(struct console *co, const char *s,
1548 unsigned count)
1549{
1550 put_string(serial_console_port, s, count);
1551}
1552
1553static int __init serial_console_setup(struct console *co, char *options)
1554{
1555 struct uart_port *port;
1556 int baud = 115200;
1557 int bits = 8;
1558 int parity = 'n';
1559 int flow = 'n';
1560 int ret;
1561
1da177e4
LT		 1562 serial_console_port = &sci_ports[co->index];
1563 port = &serial_console_port->port;
1564 port->type = serial_console_port->type;
1565
1566#ifdef CONFIG_SUPERH64
1567 /* This is especially needed on sh64 to remap the SCIF */
1568 sci_config_port(port, 0);
1569#endif
1570
1571 /*
1572 * We need to set the initial uartclk here, since otherwise it will
1573 * only ever be setup at sci_init() time.
1574 */
b7a76e4b 1575#if defined(__H8300H__) || defined(__H8300S__)
1da177e4 1576 port->uartclk = CONFIG_CPU_CLOCK;
b7a76e4b 1577
1da177e4
LT		 1578#if defined(__H8300S__)
1579 h8300_sci_enable(port, sci_enable);
b7a76e4b
PM		 1580#endif
1581#elif defined(CONFIG_SUPERH64)
21264136 1582 port->uartclk = current_cpu_data.module_clock * 16;
b7a76e4b
PM		 1583#else
1584 {
1585 struct clk *clk = clk_get("module_clk");
1586 port->uartclk = clk_get_rate(clk) * 16;
1587 clk_put(clk);
1588 }
1da177e4
LT		 1589#endif
1590 if (options)
1591 uart_parse_options(options, &baud, &parity, &bits, &flow);
1592
1593 ret = uart_set_options(port, co, baud, parity, bits, flow);
1594#if defined(__H8300H__) || defined(__H8300S__)
1595 /* disable rx interrupt */
1596 if (ret == 0)
1597 sci_stop_rx(port);
1598#endif
1599 return ret;
1600}
1601
1602static struct console serial_console = {
1603 .name = "ttySC",
1604 .device = uart_console_device,
1605 .write = serial_console_write,
1606 .setup = serial_console_setup,
1607 .flags = CON_PRINTBUFFER,
1608 .index = -1,
1609 .data = &sci_uart_driver,
1610};
1611
1612static int __init sci_console_init(void)
1613{
1614 register_console(&serial_console);
1615 return 0;
1616}
1617
1618console_initcall(sci_console_init);
1619#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1620
1621#ifdef CONFIG_SH_KGDB
1622/*
1623 * FIXME: Most of this can go away.. at the moment, we rely on
1624 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1625 * most of that can easily be done here instead.
1626 *
1627 * For the time being, just accept the values that were parsed earlier..
1628 */
1629static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1630 int *parity, int *bits)
1631{
1632 *baud = kgdb_baud;
1633 *parity = tolower(kgdb_parity);
1634 *bits = kgdb_bits - '0';
1635}
1636
1637/*
1638 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1639 * care of the early-on initialization for kgdb, regardless of whether we
1640 * actually use kgdb as a console or not.
1641 *
1642 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1643 */
1644int __init kgdb_console_setup(struct console *co, char *options)
1645{
1646 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1647 int baud = 38400;
1648 int bits = 8;
1649 int parity = 'n';
1650 int flow = 'n';
1651
b7a76e4b 1652 if (co->index != kgdb_portnum)
1da177e4
LT		 1653 co->index = kgdb_portnum;
1654
1655 if (options)
1656 uart_parse_options(options, &baud, &parity, &bits, &flow);
1657 else
1658 kgdb_console_get_options(port, &baud, &parity, &bits);
1659
1660 kgdb_getchar = kgdb_sci_getchar;
1661 kgdb_putchar = kgdb_sci_putchar;
1662
1663 return uart_set_options(port, co, baud, parity, bits, flow);
1664}
1665#endif /* CONFIG_SH_KGDB */
1666
1667#ifdef CONFIG_SH_KGDB_CONSOLE
1668static struct console kgdb_console = {
1669 .name = "ttySC",
1670 .write = kgdb_console_write,
1671 .setup = kgdb_console_setup,
1672 .flags = CON_PRINTBUFFER | CON_ENABLED,
1673 .index = -1,
1674 .data = &sci_uart_driver,
1675};
1676
1677/* Register the KGDB console so we get messages (d'oh!) */
1678static int __init kgdb_console_init(void)
1679{
1680 register_console(&kgdb_console);
1681 return 0;
1682}
1683
1684console_initcall(kgdb_console_init);
1685#endif /* CONFIG_SH_KGDB_CONSOLE */
1686
1687#if defined(CONFIG_SH_KGDB_CONSOLE)
1688#define SCI_CONSOLE &kgdb_console
1689#elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1690#define SCI_CONSOLE &serial_console
1691#else
b7a76e4b 1692#define SCI_CONSOLE 0
1da177e4
LT		 1693#endif
1694
1695static char banner[] __initdata =
1696 KERN_INFO "SuperH SCI(F) driver initialized\n";
1697
1698static struct uart_driver sci_uart_driver = {
1699 .owner = THIS_MODULE,
1700 .driver_name = "sci",
1da177e4
LT		 1701 .dev_name = "ttySC",
1702 .major = SCI_MAJOR,
1703 .minor = SCI_MINOR_START,
1da177e4
LT		 1704 .cons = SCI_CONSOLE,
1705};
1706
1707static int __init sci_init(void)
1708{
1709 int chan, ret;
1710
1711 printk("%s", banner);
1712
b7a76e4b
PM		 1713 sci_uart_driver.nr = ARRAY_SIZE(sci_ports);
1714
1da177e4
LT		 1715 ret = uart_register_driver(&sci_uart_driver);
1716 if (ret == 0) {
1717 for (chan = 0; chan < SCI_NPORTS; chan++) {
1718 struct sci_port *sciport = &sci_ports[chan];
1719
b7a76e4b 1720#if defined(__H8300H__) || defined(__H8300S__)
1da177e4 1721 sciport->port.uartclk = CONFIG_CPU_CLOCK;
b7a76e4b 1722#elif defined(CONFIG_SUPERH64)
21264136 1723 sciport->port.uartclk = current_cpu_data.module_clock * 16;
b7a76e4b
PM		 1724#else
1725 struct clk *clk = clk_get("module_clk");
1726 sciport->port.uartclk = clk_get_rate(clk) * 16;
1727 clk_put(clk);
1da177e4
LT		 1728#endif
1729 uart_add_one_port(&sci_uart_driver, &sciport->port);
1730 sciport->break_timer.data = (unsigned long)sciport;
1731 sciport->break_timer.function = sci_break_timer;
1732 init_timer(&sciport->break_timer);
1733 }
1734 }
1735
1736#ifdef CONFIG_CPU_FREQ
1737 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1738 printk("sci: CPU frequency notifier registered\n");
1739#endif
1740
1741#ifdef CONFIG_SH_STANDARD_BIOS
1742 sh_bios_gdb_detach();
1743#endif
1744
1745 return ret;
1746}
1747
1748static void __exit sci_exit(void)
1749{
1750 int chan;
1751
1752 for (chan = 0; chan < SCI_NPORTS; chan++)
1753 uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port);
1754
1755 uart_unregister_driver(&sci_uart_driver);
1756}
1757
1758module_init(sci_init);
1759module_exit(sci_exit);
1760
Linux kernel - Deliverables
This page took 0.228112 seconds and 5 git commands to generate.