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serial: sh-sci: Fix up the cpufreq notifier to use the proper port clock.
[deliverable/linux.git] / drivers / serial / sh-sci.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
7ff731ae 6 * Copyright (C) 2002 - 2008 Paul Mundt
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
0b3d4ef6
PM		 22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
1da177e4
LT		 25
26#undef DEBUG
27
1da177e4
LT		 28#include <linux/module.h>
29#include <linux/errno.h>
1da177e4
LT		 30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial.h>
35#include <linux/major.h>
36#include <linux/string.h>
37#include <linux/sysrq.h>
1da177e4
LT		 38#include <linux/ioport.h>
39#include <linux/mm.h>
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
e108b2ca 43#include <linux/platform_device.h>
96de1a8f 44#include <linux/serial_sci.h>
1da177e4
LT		 45#include <linux/notifier.h>
46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
85f094ec
PM		 50
51#ifdef CONFIG_SUPERH
b7a76e4b 52#include <asm/clock.h>
1da177e4
LT		 53#include <asm/sh_bios.h>
54#endif
55
1da177e4
LT		 56#include "sh-sci.h"
57
e108b2ca
PM		 58struct sci_port {
59 struct uart_port port;
60
61 /* Port type */
62 unsigned int type;
63
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
32351a28 65 unsigned int irqs[SCIx_NR_IRQS];
e108b2ca
PM		 66
67 /* Port pin configuration */
68 void (*init_pins)(struct uart_port *port,
69 unsigned int cflag);
1da177e4 70
e108b2ca
PM		 71 /* Port enable callback */
72 void (*enable)(struct uart_port *port);
73
74 /* Port disable callback */
75 void (*disable)(struct uart_port *port);
76
77 /* Break timer */
78 struct timer_list break_timer;
79 int break_flag;
1534a3b3 80
a2159b52 81#ifdef CONFIG_HAVE_CLK
1534a3b3 82 /* Port clock */
83 struct clk *clk;
005a336e 84#endif
e108b2ca
PM		 85};
86
1da177e4 87#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
e108b2ca
PM		 88static struct sci_port *serial_console_port;
89#endif
1da177e4
LT		 90
91/* Function prototypes */
b129a8cc 92static void sci_stop_tx(struct uart_port *port);
1da177e4 93
e108b2ca 94#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 95
e108b2ca
PM		 96static struct sci_port sci_ports[SCI_NPORTS];
97static struct uart_driver sci_uart_driver;
1da177e4 98
e7c98dc7
MT		 99static inline struct sci_port *
100to_sci_port(struct uart_port *uart)
101{
102 return container_of(uart, struct sci_port, port);
103}
104
07d2a1a1 105#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
e108b2ca
PM		 106static inline void handle_error(struct uart_port *port)
107{
108 /* Clear error flags */
1da177e4
LT		 109 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
110}
111
07d2a1a1 112static int sci_poll_get_char(struct uart_port *port)
1da177e4 113{
1da177e4
LT		 114 unsigned short status;
115 int c;
116
e108b2ca 117 do {
1da177e4
LT		 118 status = sci_in(port, SCxSR);
119 if (status & SCxSR_ERRORS(port)) {
120 handle_error(port);
121 continue;
122 }
123 } while (!(status & SCxSR_RDxF(port)));
07d2a1a1 124
1da177e4 125 c = sci_in(port, SCxRDR);
07d2a1a1 126
e7c98dc7
MT		 127 /* Dummy read */
128 sci_in(port, SCxSR);
1da177e4 129 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 130
131 return c;
132}
1da177e4 133
07d2a1a1 134static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 135{
1da177e4
LT		 136 unsigned short status;
137
1da177e4
LT		 138 do {
139 status = sci_in(port, SCxSR);
140 } while (!(status & SCxSR_TDxE(port)));
141
1da177e4
LT		 142 sci_in(port, SCxSR); /* Dummy read */
143 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
272966c0 144 sci_out(port, SCxTDR, c);
1da177e4 145}
07d2a1a1 146#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 147
148#if defined(__H8300S__)
149enum { sci_disable, sci_enable };
150
e7c98dc7 151static void h8300_sci_config(struct uart_port *port, unsigned int ctrl)
1da177e4 152{
e7c98dc7 153 volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL;
1da177e4
LT		 154 int ch = (port->mapbase - SMR0) >> 3;
155 unsigned char mask = 1 << (ch+1);
156
e7c98dc7 157 if (ctrl == sci_disable)
1da177e4 158 *mstpcrl |= mask;
e7c98dc7 159 else
1da177e4 160 *mstpcrl &= ~mask;
1da177e4 161}
e108b2ca
PM		 162
163static inline void h8300_sci_enable(struct uart_port *port)
164{
165 h8300_sci_config(port, sci_enable);
166}
167
168static inline void h8300_sci_disable(struct uart_port *port)
169{
170 h8300_sci_config(port, sci_disable);
171}
1da177e4
LT		 172#endif
173
15c73aaa 174#if defined(__H8300H__) || defined(__H8300S__)
e7c98dc7 175static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
1da177e4
LT		 176{
177 int ch = (port->mapbase - SMR0) >> 3;
178
179 /* set DDR regs */
e108b2ca
PM		 180 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
181 h8300_sci_pins[ch].rx,
182 H8300_GPIO_INPUT);
183 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
184 h8300_sci_pins[ch].tx,
185 H8300_GPIO_OUTPUT);
186
1da177e4
LT		 187 /* tx mark output*/
188 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
189}
e108b2ca
PM		 190#else
191#define sci_init_pins_sci NULL
192#endif
193
194#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
195static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
196{
197 unsigned int fcr_val = 0;
198
199 if (cflag & CRTSCTS)
200 fcr_val |= SCFCR_MCE;
201
202 sci_out(port, SCFCR, fcr_val);
203}
204#else
205#define sci_init_pins_irda NULL
1da177e4 206#endif
e108b2ca 207
d89ddd1c 208#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e7c98dc7 209static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
9465a54f
NI		 210{
211 unsigned int fcr_val = 0;
212
213 set_sh771x_scif_pfc(port);
e7c98dc7 214 if (cflag & CRTSCTS)
9465a54f 215 fcr_val |= SCFCR_MCE;
9465a54f
NI		 216 sci_out(port, SCFCR, fcr_val);
217}
31a49c4b 218#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
3ea6bc3d
MB		 219static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
220{
221 unsigned int fcr_val = 0;
222 unsigned short data;
223
224 if (cflag & CRTSCTS) {
225 /* enable RTS/CTS */
226 if (port->mapbase == 0xa4430000) { /* SCIF0 */
227 /* Clear PTCR bit 9-2; enable all scif pins but sck */
228 data = ctrl_inw(PORT_PTCR);
229 ctrl_outw((data & 0xfc03), PORT_PTCR);
230 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
231 /* Clear PVCR bit 9-2 */
232 data = ctrl_inw(PORT_PVCR);
233 ctrl_outw((data & 0xfc03), PORT_PVCR);
234 }
235 fcr_val |= SCFCR_MCE;
236 } else {
237 if (port->mapbase == 0xa4430000) { /* SCIF0 */
238 /* Clear PTCR bit 5-2; enable only tx and rx */
239 data = ctrl_inw(PORT_PTCR);
240 ctrl_outw((data & 0xffc3), PORT_PTCR);
241 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
242 /* Clear PVCR bit 5-2 */
243 data = ctrl_inw(PORT_PVCR);
244 ctrl_outw((data & 0xffc3), PORT_PVCR);
245 }
246 }
247 sci_out(port, SCFCR, fcr_val);
248}
b7a76e4b 249#elif defined(CONFIG_CPU_SH3)
e108b2ca 250/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
1da177e4
LT		 251static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
252{
253 unsigned int fcr_val = 0;
b7a76e4b
PM		 254 unsigned short data;
255
256 /* We need to set SCPCR to enable RTS/CTS */
257 data = ctrl_inw(SCPCR);
258 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
259 ctrl_outw(data & 0x0fcf, SCPCR);
1da177e4 260
1da177e4
LT		 261 if (cflag & CRTSCTS)
262 fcr_val |= SCFCR_MCE;
263 else {
1da177e4
LT		 264 /* We need to set SCPCR to enable RTS/CTS */
265 data = ctrl_inw(SCPCR);
266 /* Clear out SCP7MD1,0, SCP4MD1,0,
267 Set SCP6MD1,0 = {01} (output) */
b7a76e4b 268 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
1da177e4
LT		 269
270 data = ctrl_inb(SCPDR);
271 /* Set /RTS2 (bit6) = 0 */
b7a76e4b 272 ctrl_outb(data & 0xbf, SCPDR);
1da177e4 273 }
b7a76e4b 274
1da177e4
LT		 275 sci_out(port, SCFCR, fcr_val);
276}
41504c39
PM		 277#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
278static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
279{
280 unsigned int fcr_val = 0;
346b7463 281 unsigned short data;
41504c39 282
346b7463
MD		 283 if (port->mapbase == 0xffe00000) {
284 data = ctrl_inw(PSCR);
285 data &= ~0x03cf;
286 if (cflag & CRTSCTS)
287 fcr_val |= SCFCR_MCE;
288 else
289 data |= 0x0340;
41504c39 290
346b7463 291 ctrl_outw(data, PSCR);
41504c39 292 }
346b7463 293 /* SCIF1 and SCIF2 should be setup by board code */
41504c39
PM		 294
295 sci_out(port, SCFCR, fcr_val);
296}
178dd0cd
PM		 297#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
298static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
299{
300 /* Nothing to do here.. */
301 sci_out(port, SCFCR, 0);
302}
1da177e4 303#else
1da177e4
LT		 304/* For SH7750 */
305static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
306{
307 unsigned int fcr_val = 0;
308
309 if (cflag & CRTSCTS) {
310 fcr_val |= SCFCR_MCE;
311 } else {
9109a30e 312#if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366)
e108b2ca 313 /* Nothing */
7d740a06
YS		 314#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
315 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac
PM		 316 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
317 defined(CONFIG_CPU_SUBTYPE_SHX3)
b7a76e4b
PM		 318 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
319#else
1da177e4 320 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
b7a76e4b 321#endif
1da177e4
LT		 322 }
323 sci_out(port, SCFCR, fcr_val);
324}
e108b2ca
PM		 325#endif
326
32351a28
PM		 327#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
328 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
329 defined(CONFIG_CPU_SUBTYPE_SH7785)
e108b2ca
PM		 330static inline int scif_txroom(struct uart_port *port)
331{
cae167d3 332 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
e108b2ca
PM		 333}
334
335static inline int scif_rxroom(struct uart_port *port)
336{
cae167d3 337 return sci_in(port, SCRFDR) & 0xff;
e108b2ca 338}
c63847a3
NI		 339#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
340static inline int scif_txroom(struct uart_port *port)
341{
e7c98dc7
MT		 342 if ((port->mapbase == 0xffe00000) ||
343 (port->mapbase == 0xffe08000)) {
344 /* SCIF0/1*/
c63847a3 345 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
e7c98dc7
MT		 346 } else {
347 /* SCIF2 */
c63847a3 348 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
e7c98dc7 349 }
c63847a3
NI		 350}
351
352static inline int scif_rxroom(struct uart_port *port)
353{
e7c98dc7
MT		 354 if ((port->mapbase == 0xffe00000) ||
355 (port->mapbase == 0xffe08000)) {
356 /* SCIF0/1*/
c63847a3 357 return sci_in(port, SCRFDR) & 0xff;
e7c98dc7
MT		 358 } else {
359 /* SCIF2 */
c63847a3 360 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
e7c98dc7 361 }
c63847a3 362}
e108b2ca
PM		 363#else
364static inline int scif_txroom(struct uart_port *port)
365{
366 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
367}
1da177e4 368
e108b2ca
PM		 369static inline int scif_rxroom(struct uart_port *port)
370{
371 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
372}
1da177e4 373#endif
1da177e4 374
e108b2ca
PM		 375static inline int sci_txroom(struct uart_port *port)
376{
e7c98dc7 377 return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
e108b2ca
PM		 378}
379
380static inline int sci_rxroom(struct uart_port *port)
381{
e7c98dc7 382 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 383}
384
1da177e4
LT		 385/* ********************************************************************** *
386 * the interrupt related routines *
387 * ********************************************************************** */
388
389static void sci_transmit_chars(struct uart_port *port)
390{
391 struct circ_buf *xmit = &port->info->xmit;
392 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 393 unsigned short status;
394 unsigned short ctrl;
e108b2ca 395 int count;
1da177e4
LT		 396
397 status = sci_in(port, SCxSR);
398 if (!(status & SCxSR_TDxE(port))) {
1da177e4 399 ctrl = sci_in(port, SCSCR);
e7c98dc7 400 if (uart_circ_empty(xmit))
1da177e4 401 ctrl &= ~SCI_CTRL_FLAGS_TIE;
e7c98dc7 402 else
1da177e4 403 ctrl |= SCI_CTRL_FLAGS_TIE;
1da177e4 404 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 405 return;
406 }
407
1a22f08d 408 if (port->type == PORT_SCI)
e108b2ca 409 count = sci_txroom(port);
1a22f08d
YS		 410 else
411 count = scif_txroom(port);
1da177e4
LT		 412
413 do {
414 unsigned char c;
415
416 if (port->x_char) {
417 c = port->x_char;
418 port->x_char = 0;
419 } else if (!uart_circ_empty(xmit) && !stopped) {
420 c = xmit->buf[xmit->tail];
421 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
422 } else {
423 break;
424 }
425
426 sci_out(port, SCxTDR, c);
427
428 port->icount.tx++;
429 } while (--count > 0);
430
431 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
432
433 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
434 uart_write_wakeup(port);
435 if (uart_circ_empty(xmit)) {
b129a8cc 436 sci_stop_tx(port);
1da177e4 437 } else {
1da177e4
LT		 438 ctrl = sci_in(port, SCSCR);
439
1a22f08d 440 if (port->type != PORT_SCI) {
1da177e4
LT		 441 sci_in(port, SCxSR); /* Dummy read */
442 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
443 }
1da177e4
LT		 444
445 ctrl |= SCI_CTRL_FLAGS_TIE;
446 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 447 }
448}
449
450/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 451#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 452
7d12e780 453static inline void sci_receive_chars(struct uart_port *port)
1da177e4 454{
e7c98dc7 455 struct sci_port *sci_port = to_sci_port(port);
a88487c7 456 struct tty_struct *tty = port->info->port.tty;
1da177e4
LT		 457 int i, count, copied = 0;
458 unsigned short status;
33f0f88f 459 unsigned char flag;
1da177e4
LT		 460
461 status = sci_in(port, SCxSR);
462 if (!(status & SCxSR_RDxF(port)))
463 return;
464
465 while (1) {
1a22f08d 466 if (port->type == PORT_SCI)
e108b2ca 467 count = sci_rxroom(port);
1a22f08d
YS		 468 else
469 count = scif_rxroom(port);
1da177e4
LT		 470
471 /* Don't copy more bytes than there is room for in the buffer */
33f0f88f 472 count = tty_buffer_request_room(tty, count);
1da177e4
LT		 473
474 /* If for any reason we can't copy more data, we're done! */
475 if (count == 0)
476 break;
477
478 if (port->type == PORT_SCI) {
479 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 480 if (uart_handle_sysrq_char(port, c) ||
481 sci_port->break_flag)
1da177e4 482 count = 0;
e7c98dc7 483 else
e108b2ca 484 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 485 } else {
e7c98dc7 486 for (i = 0; i < count; i++) {
1da177e4
LT		 487 char c = sci_in(port, SCxRDR);
488 status = sci_in(port, SCxSR);
489#if defined(CONFIG_CPU_SH3)
490 /* Skip "chars" during break */
e108b2ca 491 if (sci_port->break_flag) {
1da177e4
LT		 492 if ((c == 0) &&
493 (status & SCxSR_FER(port))) {
494 count--; i--;
495 continue;
496 }
e108b2ca 497
1da177e4
LT		 498 /* Nonzero => end-of-break */
499 pr_debug("scif: debounce<%02x>\n", c);
e108b2ca
PM		 500 sci_port->break_flag = 0;
501
1da177e4
LT		 502 if (STEPFN(c)) {
503 count--; i--;
504 continue;
505 }
506 }
507#endif /* CONFIG_CPU_SH3 */
7d12e780 508 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 509 count--; i--;
510 continue;
511 }
512
513 /* Store data and status */
1da177e4 514 if (status&SCxSR_FER(port)) {
33f0f88f 515 flag = TTY_FRAME;
1da177e4
LT		 516 pr_debug("sci: frame error\n");
517 } else if (status&SCxSR_PER(port)) {
33f0f88f 518 flag = TTY_PARITY;
1da177e4 519 pr_debug("sci: parity error\n");
33f0f88f
AC		 520 } else
521 flag = TTY_NORMAL;
522 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 523 }
524 }
525
526 sci_in(port, SCxSR); /* dummy read */
527 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
528
1da177e4
LT		 529 copied += count;
530 port->icount.rx += count;
531 }
532
533 if (copied) {
534 /* Tell the rest of the system the news. New characters! */
535 tty_flip_buffer_push(tty);
536 } else {
537 sci_in(port, SCxSR); /* dummy read */
538 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
539 }
540}
541
542#define SCI_BREAK_JIFFIES (HZ/20)
543/* The sci generates interrupts during the break,
544 * 1 per millisecond or so during the break period, for 9600 baud.
545 * So dont bother disabling interrupts.
546 * But dont want more than 1 break event.
547 * Use a kernel timer to periodically poll the rx line until
548 * the break is finished.
549 */
550static void sci_schedule_break_timer(struct sci_port *port)
551{
552 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
553 add_timer(&port->break_timer);
554}
555/* Ensure that two consecutive samples find the break over. */
556static void sci_break_timer(unsigned long data)
557{
e108b2ca
PM		 558 struct sci_port *port = (struct sci_port *)data;
559
560 if (sci_rxd_in(&port->port) == 0) {
1da177e4 561 port->break_flag = 1;
e108b2ca
PM		 562 sci_schedule_break_timer(port);
563 } else if (port->break_flag == 1) {
1da177e4
LT		 564 /* break is over. */
565 port->break_flag = 2;
e108b2ca
PM		 566 sci_schedule_break_timer(port);
567 } else
568 port->break_flag = 0;
1da177e4
LT		 569}
570
571static inline int sci_handle_errors(struct uart_port *port)
572{
573 int copied = 0;
574 unsigned short status = sci_in(port, SCxSR);
a88487c7 575 struct tty_struct *tty = port->info->port.tty;
1da177e4 576
e108b2ca 577 if (status & SCxSR_ORER(port)) {
1da177e4 578 /* overrun error */
e108b2ca 579 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
33f0f88f 580 copied++;
1da177e4
LT		 581 pr_debug("sci: overrun error\n");
582 }
583
e108b2ca 584 if (status & SCxSR_FER(port)) {
1da177e4
LT		 585 if (sci_rxd_in(port) == 0) {
586 /* Notify of BREAK */
e7c98dc7 587 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 588
589 if (!sci_port->break_flag) {
590 sci_port->break_flag = 1;
591 sci_schedule_break_timer(sci_port);
592
1da177e4 593 /* Do sysrq handling. */
e108b2ca 594 if (uart_handle_break(port))
1da177e4 595 return 0;
e7c98dc7 596 pr_debug("sci: BREAK detected\n");
e108b2ca 597 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 598 copied++;
599 }
600
e108b2ca 601 } else {
1da177e4 602 /* frame error */
e108b2ca 603 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 604 copied++;
1da177e4
LT		 605 pr_debug("sci: frame error\n");
606 }
607 }
608
e108b2ca 609 if (status & SCxSR_PER(port)) {
1da177e4 610 /* parity error */
e108b2ca
PM		 611 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
612 copied++;
1da177e4
LT		 613 pr_debug("sci: parity error\n");
614 }
615
33f0f88f 616 if (copied)
1da177e4 617 tty_flip_buffer_push(tty);
1da177e4
LT		 618
619 return copied;
620}
621
622static inline int sci_handle_breaks(struct uart_port *port)
623{
624 int copied = 0;
625 unsigned short status = sci_in(port, SCxSR);
a88487c7 626 struct tty_struct *tty = port->info->port.tty;
1da177e4
LT		 627 struct sci_port *s = &sci_ports[port->line];
628
0b3d4ef6
PM		 629 if (uart_handle_break(port))
630 return 0;
631
b7a76e4b 632 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 633#if defined(CONFIG_CPU_SH3)
634 /* Debounce break */
635 s->break_flag = 1;
636#endif
637 /* Notify of BREAK */
e108b2ca 638 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 639 copied++;
1da177e4
LT		 640 pr_debug("sci: BREAK detected\n");
641 }
642
643#if defined(SCIF_ORER)
644 /* XXX: Handle SCIF overrun error */
1a22f08d 645 if (port->type != PORT_SCI && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
1da177e4 646 sci_out(port, SCLSR, 0);
e108b2ca 647 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
1da177e4 648 copied++;
1da177e4
LT		 649 pr_debug("sci: overrun error\n");
650 }
651 }
652#endif
653
33f0f88f 654 if (copied)
1da177e4 655 tty_flip_buffer_push(tty);
e108b2ca 656
1da177e4
LT		 657 return copied;
658}
659
7d12e780 660static irqreturn_t sci_rx_interrupt(int irq, void *port)
1da177e4 661{
1da177e4
LT		 662 /* I think sci_receive_chars has to be called irrespective
663 * of whether the I_IXOFF is set, otherwise, how is the interrupt
664 * to be disabled?
665 */
7d12e780 666 sci_receive_chars(port);
1da177e4
LT		 667
668 return IRQ_HANDLED;
669}
670
7d12e780 671static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 672{
673 struct uart_port *port = ptr;
674
e108b2ca 675 spin_lock_irq(&port->lock);
1da177e4 676 sci_transmit_chars(port);
e108b2ca 677 spin_unlock_irq(&port->lock);
1da177e4
LT		 678
679 return IRQ_HANDLED;
680}
681
7d12e780 682static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 683{
684 struct uart_port *port = ptr;
685
686 /* Handle errors */
687 if (port->type == PORT_SCI) {
688 if (sci_handle_errors(port)) {
689 /* discard character in rx buffer */
690 sci_in(port, SCxSR);
691 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
692 }
693 } else {
694#if defined(SCIF_ORER)
e7c98dc7 695 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
a88487c7 696 struct tty_struct *tty = port->info->port.tty;
1da177e4
LT		 697
698 sci_out(port, SCLSR, 0);
33f0f88f
AC		 699 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
700 tty_flip_buffer_push(tty);
701 pr_debug("scif: overrun error\n");
1da177e4
LT		 702 }
703#endif
7d12e780 704 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 705 }
706
707 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
708
709 /* Kick the transmission */
7d12e780 710 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 711
712 return IRQ_HANDLED;
713}
714
7d12e780 715static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 716{
717 struct uart_port *port = ptr;
718
719 /* Handle BREAKs */
720 sci_handle_breaks(port);
721 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
722
723 return IRQ_HANDLED;
724}
725
7d12e780 726static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 727{
a8884e34
MT		 728 unsigned short ssr_status, scr_status;
729 struct uart_port *port = ptr;
730 irqreturn_t ret = IRQ_NONE;
1da177e4 731
e7c98dc7
MT		 732 ssr_status = sci_in(port, SCxSR);
733 scr_status = sci_in(port, SCSCR);
1da177e4
LT		 734
735 /* Tx Interrupt */
a8884e34
MT		 736 if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
737 ret = sci_tx_interrupt(irq, ptr);
1da177e4 738 /* Rx Interrupt */
a8884e34
MT		 739 if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
740 ret = sci_rx_interrupt(irq, ptr);
1da177e4 741 /* Error Interrupt */
a8884e34
MT		 742 if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
743 ret = sci_er_interrupt(irq, ptr);
1da177e4 744 /* Break Interrupt */
a8884e34
MT		 745 if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
746 ret = sci_br_interrupt(irq, ptr);
1da177e4 747
a8884e34 748 return ret;
1da177e4
LT		 749}
750
027e6872 751#ifdef CONFIG_HAVE_CLK
1da177e4
LT		 752/*
753 * Here we define a transistion notifier so that we can update all of our
754 * ports' baud rate when the peripheral clock changes.
755 */
e108b2ca
PM		 756static int sci_notifier(struct notifier_block *self,
757 unsigned long phase, void *p)
1da177e4 758{
1da177e4
LT		 759 int i;
760
761 if ((phase == CPUFREQ_POSTCHANGE) ||
027e6872 762 (phase == CPUFREQ_RESUMECHANGE))
1da177e4 763 for (i = 0; i < SCI_NPORTS; i++) {
027e6872
PM		 764 struct sci_port *s = &sci_ports[i];
765 s->port.uartclk = clk_get_rate(s->clk);
1da177e4
LT		 766 }
767
1da177e4
LT		 768 return NOTIFY_OK;
769}
770
771static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
027e6872 772#endif
1da177e4
LT		 773
774static int sci_request_irq(struct sci_port *port)
775{
776 int i;
7d12e780 777 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
1da177e4
LT		 778 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
779 sci_br_interrupt,
780 };
781 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
782 "SCI Transmit Data Empty", "SCI Break" };
783
784 if (port->irqs[0] == port->irqs[1]) {
785 if (!port->irqs[0]) {
786 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
787 return -ENODEV;
788 }
e108b2ca
PM		 789
790 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
35f3c518 791 IRQF_DISABLED, "sci", port)) {
1da177e4
LT		 792 printk(KERN_ERR "sci: Cannot allocate irq.\n");
793 return -ENODEV;
794 }
795 } else {
796 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
797 if (!port->irqs[i])
798 continue;
e108b2ca 799 if (request_irq(port->irqs[i], handlers[i],
35f3c518 800 IRQF_DISABLED, desc[i], port)) {
1da177e4
LT		 801 printk(KERN_ERR "sci: Cannot allocate irq.\n");
802 return -ENODEV;
803 }
804 }
805 }
806
807 return 0;
808}
809
810static void sci_free_irq(struct sci_port *port)
811{
812 int i;
813
e7c98dc7
MT		 814 if (port->irqs[0] == port->irqs[1]) {
815 if (!port->irqs[0])
816 printk(KERN_ERR "sci: sci_free_irq error\n");
1da177e4 817 else
e7c98dc7
MT		 818 free_irq(port->irqs[0], port);
819 } else {
1da177e4
LT		 820 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
821 if (!port->irqs[i])
822 continue;
823
824 free_irq(port->irqs[i], port);
825 }
826 }
827}
828
829static unsigned int sci_tx_empty(struct uart_port *port)
830{
831 /* Can't detect */
832 return TIOCSER_TEMT;
833}
834
835static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
836{
837 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
838 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
839 /* If you have signals for DTR and DCD, please implement here. */
840}
841
842static unsigned int sci_get_mctrl(struct uart_port *port)
843{
844 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
845 and CTS/RTS */
846
847 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
848}
849
b129a8cc 850static void sci_start_tx(struct uart_port *port)
1da177e4 851{
e108b2ca 852 unsigned short ctrl;
1da177e4 853
e108b2ca
PM		 854 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
855 ctrl = sci_in(port, SCSCR);
856 ctrl |= SCI_CTRL_FLAGS_TIE;
857 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 858}
859
b129a8cc 860static void sci_stop_tx(struct uart_port *port)
1da177e4 861{
1da177e4
LT		 862 unsigned short ctrl;
863
864 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4
LT		 865 ctrl = sci_in(port, SCSCR);
866 ctrl &= ~SCI_CTRL_FLAGS_TIE;
867 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 868}
869
870static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
871{
1da177e4
LT		 872 unsigned short ctrl;
873
874 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1da177e4
LT		 875 ctrl = sci_in(port, SCSCR);
876 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
877 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 878}
879
880static void sci_stop_rx(struct uart_port *port)
881{
1da177e4
LT		 882 unsigned short ctrl;
883
884 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1da177e4
LT		 885 ctrl = sci_in(port, SCSCR);
886 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
887 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 888}
889
890static void sci_enable_ms(struct uart_port *port)
891{
892 /* Nothing here yet .. */
893}
894
895static void sci_break_ctl(struct uart_port *port, int break_state)
896{
897 /* Nothing here yet .. */
898}
899
900static int sci_startup(struct uart_port *port)
901{
902 struct sci_port *s = &sci_ports[port->line];
903
e108b2ca
PM		 904 if (s->enable)
905 s->enable(port);
1da177e4 906
a2159b52 907#ifdef CONFIG_HAVE_CLK
1534a3b3 908 s->clk = clk_get(NULL, "module_clk");
005a336e 909#endif
1534a3b3 910
1da177e4 911 sci_request_irq(s);
d656901b 912 sci_start_tx(port);
1da177e4
LT		 913 sci_start_rx(port, 1);
914
915 return 0;
916}
917
918static void sci_shutdown(struct uart_port *port)
919{
920 struct sci_port *s = &sci_ports[port->line];
921
922 sci_stop_rx(port);
b129a8cc 923 sci_stop_tx(port);
1da177e4
LT		 924 sci_free_irq(s);
925
e108b2ca
PM		 926 if (s->disable)
927 s->disable(port);
1534a3b3 928
a2159b52 929#ifdef CONFIG_HAVE_CLK
1534a3b3 930 clk_put(s->clk);
931 s->clk = NULL;
005a336e 932#endif
1da177e4
LT		 933}
934
606d099c
AC		 935static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
936 struct ktermios *old)
1da177e4
LT		 937{
938 struct sci_port *s = &sci_ports[port->line];
939 unsigned int status, baud, smr_val;
a2159b52 940 int t = -1;
1da177e4
LT		 941
942 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
a2159b52
PM		 943 if (likely(baud))
944 t = SCBRR_VALUE(baud, port->uartclk);
e108b2ca 945
1da177e4
LT		 946 do {
947 status = sci_in(port, SCxSR);
948 } while (!(status & SCxSR_TEND(port)));
949
950 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
951
1a22f08d 952 if (port->type != PORT_SCI)
1da177e4 953 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 954
955 smr_val = sci_in(port, SCSMR) & 3;
956 if ((termios->c_cflag & CSIZE) == CS7)
957 smr_val |= 0x40;
958 if (termios->c_cflag & PARENB)
959 smr_val |= 0x20;
960 if (termios->c_cflag & PARODD)
961 smr_val |= 0x30;
962 if (termios->c_cflag & CSTOPB)
963 smr_val |= 0x08;
964
965 uart_update_timeout(port, termios->c_cflag, baud);
966
967 sci_out(port, SCSMR, smr_val);
968
1da177e4 969 if (t > 0) {
e7c98dc7 970 if (t >= 256) {
1da177e4
LT		 971 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
972 t >>= 2;
e7c98dc7 973 } else
1da177e4 974 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 975
1da177e4
LT		 976 sci_out(port, SCBRR, t);
977 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
978 }
979
b7a76e4b
PM		 980 if (likely(s->init_pins))
981 s->init_pins(port, termios->c_cflag);
982
1da177e4
LT		 983 sci_out(port, SCSCR, SCSCR_INIT(port));
984
985 if ((termios->c_cflag & CREAD) != 0)
e7c98dc7 986 sci_start_rx(port, 0);
1da177e4
LT		 987}
988
989static const char *sci_type(struct uart_port *port)
990{
991 switch (port->type) {
e7c98dc7
MT		 992 case PORT_IRDA:
993 return "irda";
994 case PORT_SCI:
995 return "sci";
996 case PORT_SCIF:
997 return "scif";
998 case PORT_SCIFA:
999 return "scifa";
1da177e4
LT		 1000 }
1001
fa43972f 1002 return NULL;
1da177e4
LT		 1003}
1004
1005static void sci_release_port(struct uart_port *port)
1006{
1007 /* Nothing here yet .. */
1008}
1009
1010static int sci_request_port(struct uart_port *port)
1011{
1012 /* Nothing here yet .. */
1013 return 0;
1014}
1015
1016static void sci_config_port(struct uart_port *port, int flags)
1017{
1018 struct sci_port *s = &sci_ports[port->line];
1019
1020 port->type = s->type;
1021
e108b2ca
PM		 1022 switch (port->type) {
1023 case PORT_SCI:
1024 s->init_pins = sci_init_pins_sci;
1025 break;
1026 case PORT_SCIF:
1a22f08d 1027 case PORT_SCIFA:
e108b2ca
PM		 1028 s->init_pins = sci_init_pins_scif;
1029 break;
1030 case PORT_IRDA:
1031 s->init_pins = sci_init_pins_irda;
1032 break;
1033 }
1034
7ff731ae
PM		 1035 if (port->flags & UPF_IOREMAP && !port->membase) {
1036#if defined(CONFIG_SUPERH64)
1da177e4 1037 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
7ff731ae
PM		 1038 port->membase = (void __iomem *)port->mapbase;
1039#else
1040 port->membase = ioremap_nocache(port->mapbase, 0x40);
1da177e4 1041#endif
7ff731ae
PM		 1042
1043 printk(KERN_ERR "sci: can't remap port#%d\n", port->line);
1044 }
1da177e4
LT		 1045}
1046
1047static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1048{
1049 struct sci_port *s = &sci_ports[port->line];
1050
a62c4133 1051 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1052 return -EINVAL;
1053 if (ser->baud_base < 2400)
1054 /* No paper tape reader for Mitch.. */
1055 return -EINVAL;
1056
1057 return 0;
1058}
1059
1060static struct uart_ops sci_uart_ops = {
1061 .tx_empty = sci_tx_empty,
1062 .set_mctrl = sci_set_mctrl,
1063 .get_mctrl = sci_get_mctrl,
1064 .start_tx = sci_start_tx,
1065 .stop_tx = sci_stop_tx,
1066 .stop_rx = sci_stop_rx,
1067 .enable_ms = sci_enable_ms,
1068 .break_ctl = sci_break_ctl,
1069 .startup = sci_startup,
1070 .shutdown = sci_shutdown,
1071 .set_termios = sci_set_termios,
1072 .type = sci_type,
1073 .release_port = sci_release_port,
1074 .request_port = sci_request_port,
1075 .config_port = sci_config_port,
1076 .verify_port = sci_verify_port,
07d2a1a1
PM		 1077#ifdef CONFIG_CONSOLE_POLL
1078 .poll_get_char = sci_poll_get_char,
1079 .poll_put_char = sci_poll_put_char,
1080#endif
1da177e4
LT		 1081};
1082
e108b2ca
PM		 1083static void __init sci_init_ports(void)
1084{
1085 static int first = 1;
1086 int i;
1087
1088 if (!first)
1089 return;
1090
1091 first = 0;
1092
1093 for (i = 0; i < SCI_NPORTS; i++) {
1094 sci_ports[i].port.ops = &sci_uart_ops;
1095 sci_ports[i].port.iotype = UPIO_MEM;
1096 sci_ports[i].port.line = i;
1097 sci_ports[i].port.fifosize = 1;
1098
1099#if defined(__H8300H__) || defined(__H8300S__)
1100#ifdef __H8300S__
1101 sci_ports[i].enable = h8300_sci_enable;
1102 sci_ports[i].disable = h8300_sci_disable;
1103#endif
1104 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
a2159b52 1105#elif defined(CONFIG_HAVE_CLK)
e108b2ca
PM		 1106 /*
1107 * XXX: We should use a proper SCI/SCIF clock
1108 */
1109 {
1d118562 1110 struct clk *clk = clk_get(NULL, "module_clk");
a2159b52 1111 sci_ports[i].port.uartclk = clk_get_rate(clk);
e108b2ca
PM		 1112 clk_put(clk);
1113 }
a2159b52
PM		 1114#else
1115#error "Need a valid uartclk"
1da177e4 1116#endif
e108b2ca
PM		 1117
1118 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1119 sci_ports[i].break_timer.function = sci_break_timer;
1120
1121 init_timer(&sci_ports[i].break_timer);
1122 }
1123}
1124
1125int __init early_sci_setup(struct uart_port *port)
1126{
1127 if (unlikely(port->line > SCI_NPORTS))
1128 return -ENODEV;
1129
1130 sci_init_ports();
1131
1132 sci_ports[port->line].port.membase = port->membase;
1133 sci_ports[port->line].port.mapbase = port->mapbase;
1134 sci_ports[port->line].port.type = port->type;
1135
1136 return 0;
1137}
1da177e4
LT		 1138
1139#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1140/*
1141 * Print a string to the serial port trying not to disturb
1142 * any possible real use of the port...
1143 */
1144static void serial_console_write(struct console *co, const char *s,
1145 unsigned count)
1146{
07d2a1a1
PM		 1147 struct uart_port *port = &serial_console_port->port;
1148 int i;
1149
1150 for (i = 0; i < count; i++) {
1151 if (*s == 10)
1152 sci_poll_put_char(port, '\r');
1153
1154 sci_poll_put_char(port, *s++);
1155 }
1da177e4
LT		 1156}
1157
1158static int __init serial_console_setup(struct console *co, char *options)
1159{
1160 struct uart_port *port;
1161 int baud = 115200;
1162 int bits = 8;
1163 int parity = 'n';
1164 int flow = 'n';
1165 int ret;
1166
e108b2ca
PM		 1167 /*
1168 * Check whether an invalid uart number has been specified, and
1169 * if so, search for the first available port that does have
1170 * console support.
1171 */
1172 if (co->index >= SCI_NPORTS)
1173 co->index = 0;
1174
1da177e4
LT		 1175 serial_console_port = &sci_ports[co->index];
1176 port = &serial_console_port->port;
1da177e4
LT		 1177
1178 /*
e108b2ca
PM		 1179 * Also need to check port->type, we don't actually have any
1180 * UPIO_PORT ports, but uart_report_port() handily misreports
1181 * it anyways if we don't have a port available by the time this is
1182 * called.
1da177e4 1183 */
e108b2ca
PM		 1184 if (!port->type)
1185 return -ENODEV;
1186 if (!port->membase || !port->mapbase)
1187 return -ENODEV;
1188
e108b2ca
PM		 1189 port->type = serial_console_port->type;
1190
a2159b52 1191#ifdef CONFIG_HAVE_CLK
005a336e
PM		 1192 if (!serial_console_port->clk)
1193 serial_console_port->clk = clk_get(NULL, "module_clk");
1194#endif
1195
e108b2ca
PM		 1196 if (port->flags & UPF_IOREMAP)
1197 sci_config_port(port, 0);
1198
1199 if (serial_console_port->enable)
1200 serial_console_port->enable(port);
b7a76e4b 1201
1da177e4
LT		 1202 if (options)
1203 uart_parse_options(options, &baud, &parity, &bits, &flow);
1204
1205 ret = uart_set_options(port, co, baud, parity, bits, flow);
1206#if defined(__H8300H__) || defined(__H8300S__)
1207 /* disable rx interrupt */
1208 if (ret == 0)
1209 sci_stop_rx(port);
1210#endif
1211 return ret;
1212}
1213
1214static struct console serial_console = {
1215 .name = "ttySC",
1216 .device = uart_console_device,
1217 .write = serial_console_write,
1218 .setup = serial_console_setup,
fa5da2f7 1219 .flags = CON_PRINTBUFFER,
1da177e4
LT		 1220 .index = -1,
1221 .data = &sci_uart_driver,
1222};
1223
1224static int __init sci_console_init(void)
1225{
e108b2ca 1226 sci_init_ports();
1da177e4
LT		 1227 register_console(&serial_console);
1228 return 0;
1229}
1da177e4
LT		 1230console_initcall(sci_console_init);
1231#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1232
07d2a1a1 1233#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
e7c98dc7 1234#define SCI_CONSOLE (&serial_console)
1da177e4 1235#else
b7a76e4b 1236#define SCI_CONSOLE 0
1da177e4
LT		 1237#endif
1238
1239static char banner[] __initdata =
1240 KERN_INFO "SuperH SCI(F) driver initialized\n";
1241
1242static struct uart_driver sci_uart_driver = {
1243 .owner = THIS_MODULE,
1244 .driver_name = "sci",
1da177e4
LT		 1245 .dev_name = "ttySC",
1246 .major = SCI_MAJOR,
1247 .minor = SCI_MINOR_START,
e108b2ca 1248 .nr = SCI_NPORTS,
1da177e4
LT		 1249 .cons = SCI_CONSOLE,
1250};
1251
e108b2ca
PM		 1252/*
1253 * Register a set of serial devices attached to a platform device. The
1254 * list is terminated with a zero flags entry, which means we expect
1255 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1256 * remapping (such as sh64) should also set UPF_IOREMAP.
1257 */
1258static int __devinit sci_probe(struct platform_device *dev)
1da177e4 1259{
e108b2ca 1260 struct plat_sci_port *p = dev->dev.platform_data;
7ff731ae 1261 int i, ret = -EINVAL;
1da177e4 1262
32351a28 1263 for (i = 0; p && p->flags != 0; p++, i++) {
e108b2ca 1264 struct sci_port *sciport = &sci_ports[i];
1da177e4 1265
32351a28
PM		 1266 /* Sanity check */
1267 if (unlikely(i == SCI_NPORTS)) {
1268 dev_notice(&dev->dev, "Attempting to register port "
1269 "%d when only %d are available.\n",
1270 i+1, SCI_NPORTS);
1271 dev_notice(&dev->dev, "Consider bumping "
1272 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1273 break;
1274 }
1275
e108b2ca 1276 sciport->port.mapbase = p->mapbase;
b7a76e4b 1277
7ff731ae
PM		 1278 if (p->mapbase && !p->membase) {
1279 if (p->flags & UPF_IOREMAP) {
1280 p->membase = ioremap_nocache(p->mapbase, 0x40);
1281 if (IS_ERR(p->membase)) {
1282 ret = PTR_ERR(p->membase);
1283 goto err_unreg;
1284 }
1285 } else {
1286 /*
1287 * For the simple (and majority of) cases
1288 * where we don't need to do any remapping,
1289 * just cast the cookie directly.
1290 */
1291 p->membase = (void __iomem *)p->mapbase;
1292 }
1293 }
1da177e4 1294
e108b2ca
PM		 1295 sciport->port.membase = p->membase;
1296
1297 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1298 sciport->port.flags = p->flags;
1299 sciport->port.dev = &dev->dev;
1300
1301 sciport->type = sciport->port.type = p->type;
1302
1303 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1304
1305 uart_add_one_port(&sci_uart_driver, &sciport->port);
1da177e4
LT		 1306 }
1307
027e6872 1308#ifdef CONFIG_HAVE_CLK
1da177e4 1309 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1da177e4
LT		 1310#endif
1311
1312#ifdef CONFIG_SH_STANDARD_BIOS
1313 sh_bios_gdb_detach();
1314#endif
1315
e108b2ca 1316 return 0;
7ff731ae
PM		 1317
1318err_unreg:
1319 for (i = i - 1; i >= 0; i--)
1320 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1321
1322 return ret;
1da177e4
LT		 1323}
1324
e108b2ca
PM		 1325static int __devexit sci_remove(struct platform_device *dev)
1326{
1327 int i;
1328
027e6872
PM		 1329#ifdef CONFIG_HAVE_CLK
1330 cpufreq_unregister_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1331#endif
1332
e108b2ca
PM		 1333 for (i = 0; i < SCI_NPORTS; i++)
1334 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1335
1336 return 0;
1337}
1338
1339static int sci_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1340{
e108b2ca
PM		 1341 int i;
1342
1343 for (i = 0; i < SCI_NPORTS; i++) {
1344 struct sci_port *p = &sci_ports[i];
1345
1346 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1347 uart_suspend_port(&sci_uart_driver, &p->port);
1348 }
1da177e4 1349
e108b2ca
PM		 1350 return 0;
1351}
1da177e4 1352
e108b2ca
PM		 1353static int sci_resume(struct platform_device *dev)
1354{
1355 int i;
1356
1357 for (i = 0; i < SCI_NPORTS; i++) {
1358 struct sci_port *p = &sci_ports[i];
1359
1360 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1361 uart_resume_port(&sci_uart_driver, &p->port);
1362 }
1363
1364 return 0;
1365}
1366
1367static struct platform_driver sci_driver = {
1368 .probe = sci_probe,
1369 .remove = __devexit_p(sci_remove),
1370 .suspend = sci_suspend,
1371 .resume = sci_resume,
1372 .driver = {
1373 .name = "sh-sci",
1374 .owner = THIS_MODULE,
1375 },
1376};
1377
1378static int __init sci_init(void)
1379{
1380 int ret;
1381
1382 printk(banner);
1383
1384 sci_init_ports();
1385
1386 ret = uart_register_driver(&sci_uart_driver);
1387 if (likely(ret == 0)) {
1388 ret = platform_driver_register(&sci_driver);
1389 if (unlikely(ret))
1390 uart_unregister_driver(&sci_uart_driver);
1391 }
1392
1393 return ret;
1394}
1395
1396static void __exit sci_exit(void)
1397{
1398 platform_driver_unregister(&sci_driver);
1da177e4
LT		 1399 uart_unregister_driver(&sci_uart_driver);
1400}
1401
1402module_init(sci_init);
1403module_exit(sci_exit);
1404
e108b2ca 1405MODULE_LICENSE("GPL");
e169c139 1406MODULE_ALIAS("platform:sh-sci");
Linux kernel - Deliverables
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