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sh: Kill off cf-enabler with extreme prejudice.
[deliverable/linux.git] / drivers / serial / sh-sci.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
7ff731ae 6 * Copyright (C) 2002 - 2008 Paul Mundt
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
0b3d4ef6
PM		 22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
1da177e4
LT		 25
26#undef DEBUG
27
1da177e4
LT		 28#include <linux/module.h>
29#include <linux/errno.h>
1da177e4
LT		 30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial.h>
35#include <linux/major.h>
36#include <linux/string.h>
37#include <linux/sysrq.h>
1da177e4
LT		 38#include <linux/ioport.h>
39#include <linux/mm.h>
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
e108b2ca 43#include <linux/platform_device.h>
96de1a8f 44#include <linux/serial_sci.h>
1da177e4
LT		 45#include <linux/notifier.h>
46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
85f094ec
PM		 50
51#ifdef CONFIG_SUPERH
b7a76e4b 52#include <asm/clock.h>
1da177e4
LT		 53#include <asm/sh_bios.h>
54#endif
55
1da177e4
LT		 56#include "sh-sci.h"
57
e108b2ca
PM		 58struct sci_port {
59 struct uart_port port;
60
61 /* Port type */
62 unsigned int type;
63
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
32351a28 65 unsigned int irqs[SCIx_NR_IRQS];
e108b2ca 66
e108b2ca
PM		 67 /* Port enable callback */
68 void (*enable)(struct uart_port *port);
69
70 /* Port disable callback */
71 void (*disable)(struct uart_port *port);
72
73 /* Break timer */
74 struct timer_list break_timer;
75 int break_flag;
1534a3b3 76
a2159b52 77#ifdef CONFIG_HAVE_CLK
1534a3b3 78 /* Port clock */
79 struct clk *clk;
005a336e 80#endif
e108b2ca
PM		 81};
82
1da177e4 83#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
e108b2ca
PM		 84static struct sci_port *serial_console_port;
85#endif
1da177e4
LT		 86
87/* Function prototypes */
b129a8cc 88static void sci_stop_tx(struct uart_port *port);
1da177e4 89
e108b2ca 90#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 91
e108b2ca
PM		 92static struct sci_port sci_ports[SCI_NPORTS];
93static struct uart_driver sci_uart_driver;
1da177e4 94
e7c98dc7
MT		 95static inline struct sci_port *
96to_sci_port(struct uart_port *uart)
97{
98 return container_of(uart, struct sci_port, port);
99}
100
07d2a1a1 101#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
e108b2ca
PM		 102static inline void handle_error(struct uart_port *port)
103{
104 /* Clear error flags */
1da177e4
LT		 105 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
106}
107
07d2a1a1 108static int sci_poll_get_char(struct uart_port *port)
1da177e4 109{
1da177e4
LT		 110 unsigned short status;
111 int c;
112
e108b2ca 113 do {
1da177e4
LT		 114 status = sci_in(port, SCxSR);
115 if (status & SCxSR_ERRORS(port)) {
116 handle_error(port);
117 continue;
118 }
119 } while (!(status & SCxSR_RDxF(port)));
07d2a1a1 120
1da177e4 121 c = sci_in(port, SCxRDR);
07d2a1a1 122
e7c98dc7
MT		 123 /* Dummy read */
124 sci_in(port, SCxSR);
1da177e4 125 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 126
127 return c;
128}
1da177e4 129
07d2a1a1 130static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 131{
1da177e4
LT		 132 unsigned short status;
133
1da177e4
LT		 134 do {
135 status = sci_in(port, SCxSR);
136 } while (!(status & SCxSR_TDxE(port)));
137
1da177e4
LT		 138 sci_in(port, SCxSR); /* Dummy read */
139 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
272966c0 140 sci_out(port, SCxTDR, c);
1da177e4 141}
07d2a1a1 142#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 143
144#if defined(__H8300S__)
145enum { sci_disable, sci_enable };
146
e7c98dc7 147static void h8300_sci_config(struct uart_port *port, unsigned int ctrl)
1da177e4 148{
e7c98dc7 149 volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL;
1da177e4
LT		 150 int ch = (port->mapbase - SMR0) >> 3;
151 unsigned char mask = 1 << (ch+1);
152
e7c98dc7 153 if (ctrl == sci_disable)
1da177e4 154 *mstpcrl |= mask;
e7c98dc7 155 else
1da177e4 156 *mstpcrl &= ~mask;
1da177e4 157}
e108b2ca
PM		 158
159static inline void h8300_sci_enable(struct uart_port *port)
160{
161 h8300_sci_config(port, sci_enable);
162}
163
164static inline void h8300_sci_disable(struct uart_port *port)
165{
166 h8300_sci_config(port, sci_disable);
167}
1da177e4
LT		 168#endif
169
15c73aaa 170#if defined(__H8300H__) || defined(__H8300S__)
d5701647 171static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4
LT		 172{
173 int ch = (port->mapbase - SMR0) >> 3;
174
175 /* set DDR regs */
e108b2ca
PM		 176 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
177 h8300_sci_pins[ch].rx,
178 H8300_GPIO_INPUT);
179 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
180 h8300_sci_pins[ch].tx,
181 H8300_GPIO_OUTPUT);
182
1da177e4
LT		 183 /* tx mark output*/
184 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
185}
d5701647
PM		 186#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
187static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
e108b2ca 188{
d5701647
PM		 189 if (port->mapbase == 0xA4400000) {
190 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
191 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
192 } else if (port->mapbase == 0xA4410000)
193 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
9465a54f 194}
31a49c4b 195#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
d5701647 196static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
3ea6bc3d 197{
3ea6bc3d
MB		 198 unsigned short data;
199
200 if (cflag & CRTSCTS) {
201 /* enable RTS/CTS */
202 if (port->mapbase == 0xa4430000) { /* SCIF0 */
203 /* Clear PTCR bit 9-2; enable all scif pins but sck */
d5701647
PM		 204 data = __raw_readw(PORT_PTCR);
205 __raw_writew((data & 0xfc03), PORT_PTCR);
3ea6bc3d
MB		 206 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
207 /* Clear PVCR bit 9-2 */
d5701647
PM		 208 data = __raw_readw(PORT_PVCR);
209 __raw_writew((data & 0xfc03), PORT_PVCR);
3ea6bc3d 210 }
3ea6bc3d
MB		 211 } else {
212 if (port->mapbase == 0xa4430000) { /* SCIF0 */
213 /* Clear PTCR bit 5-2; enable only tx and rx */
d5701647
PM		 214 data = __raw_readw(PORT_PTCR);
215 __raw_writew((data & 0xffc3), PORT_PTCR);
3ea6bc3d
MB		 216 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
217 /* Clear PVCR bit 5-2 */
d5701647
PM		 218 data = __raw_readw(PORT_PVCR);
219 __raw_writew((data & 0xffc3), PORT_PVCR);
3ea6bc3d
MB		 220 }
221 }
3ea6bc3d 222}
b7a76e4b 223#elif defined(CONFIG_CPU_SH3)
e108b2ca 224/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
d5701647 225static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 226{
b7a76e4b
PM		 227 unsigned short data;
228
229 /* We need to set SCPCR to enable RTS/CTS */
d5701647 230 data = __raw_readw(SCPCR);
b7a76e4b 231 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
d5701647 232 __raw_writew(data & 0x0fcf, SCPCR);
1da177e4 233
d5701647 234 if (!(cflag & CRTSCTS)) {
1da177e4 235 /* We need to set SCPCR to enable RTS/CTS */
d5701647 236 data = __raw_readw(SCPCR);
1da177e4
LT		 237 /* Clear out SCP7MD1,0, SCP4MD1,0,
238 Set SCP6MD1,0 = {01} (output) */
d5701647 239 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
1da177e4
LT		 240
241 data = ctrl_inb(SCPDR);
242 /* Set /RTS2 (bit6) = 0 */
b7a76e4b 243 ctrl_outb(data & 0xbf, SCPDR);
1da177e4 244 }
1da177e4 245}
41504c39 246#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
d5701647 247static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
41504c39 248{
346b7463 249 unsigned short data;
41504c39 250
346b7463 251 if (port->mapbase == 0xffe00000) {
d5701647 252 data = __raw_readw(PSCR);
346b7463 253 data &= ~0x03cf;
d5701647 254 if (!(cflag & CRTSCTS))
346b7463 255 data |= 0x0340;
41504c39 256
d5701647 257 __raw_writew(data, PSCR);
41504c39 258 }
178dd0cd 259}
7d740a06
YS		 260#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
261 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac
PM		 262 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
263 defined(CONFIG_CPU_SUBTYPE_SHX3)
d5701647
PM		 264static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
265{
266 if (!(cflag & CRTSCTS))
267 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
268}
269#elif defined(CONFIG_CPU_SH4)
270static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
271{
272 if (!(cflag & CRTSCTS))
273 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
274}
b7a76e4b 275#else
d5701647
PM		 276static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
277{
278 /* Nothing to do */
1da177e4 279}
e108b2ca
PM		 280#endif
281
32351a28
PM		 282#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
284 defined(CONFIG_CPU_SUBTYPE_SH7785)
e108b2ca
PM		 285static inline int scif_txroom(struct uart_port *port)
286{
cae167d3 287 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
e108b2ca
PM		 288}
289
290static inline int scif_rxroom(struct uart_port *port)
291{
cae167d3 292 return sci_in(port, SCRFDR) & 0xff;
e108b2ca 293}
c63847a3
NI		 294#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
295static inline int scif_txroom(struct uart_port *port)
296{
e7c98dc7
MT		 297 if ((port->mapbase == 0xffe00000) ||
298 (port->mapbase == 0xffe08000)) {
299 /* SCIF0/1*/
c63847a3 300 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
e7c98dc7
MT		 301 } else {
302 /* SCIF2 */
c63847a3 303 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
e7c98dc7 304 }
c63847a3
NI		 305}
306
307static inline int scif_rxroom(struct uart_port *port)
308{
e7c98dc7
MT		 309 if ((port->mapbase == 0xffe00000) ||
310 (port->mapbase == 0xffe08000)) {
311 /* SCIF0/1*/
c63847a3 312 return sci_in(port, SCRFDR) & 0xff;
e7c98dc7
MT		 313 } else {
314 /* SCIF2 */
c63847a3 315 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
e7c98dc7 316 }
c63847a3 317}
e108b2ca
PM		 318#else
319static inline int scif_txroom(struct uart_port *port)
320{
321 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
322}
1da177e4 323
e108b2ca
PM		 324static inline int scif_rxroom(struct uart_port *port)
325{
326 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
327}
1da177e4 328#endif
1da177e4 329
e108b2ca
PM		 330static inline int sci_txroom(struct uart_port *port)
331{
e7c98dc7 332 return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
e108b2ca
PM		 333}
334
335static inline int sci_rxroom(struct uart_port *port)
336{
e7c98dc7 337 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 338}
339
1da177e4
LT		 340/* ********************************************************************** *
341 * the interrupt related routines *
342 * ********************************************************************** */
343
344static void sci_transmit_chars(struct uart_port *port)
345{
346 struct circ_buf *xmit = &port->info->xmit;
347 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 348 unsigned short status;
349 unsigned short ctrl;
e108b2ca 350 int count;
1da177e4
LT		 351
352 status = sci_in(port, SCxSR);
353 if (!(status & SCxSR_TDxE(port))) {
1da177e4 354 ctrl = sci_in(port, SCSCR);
e7c98dc7 355 if (uart_circ_empty(xmit))
1da177e4 356 ctrl &= ~SCI_CTRL_FLAGS_TIE;
e7c98dc7 357 else
1da177e4 358 ctrl |= SCI_CTRL_FLAGS_TIE;
1da177e4 359 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 360 return;
361 }
362
1a22f08d 363 if (port->type == PORT_SCI)
e108b2ca 364 count = sci_txroom(port);
1a22f08d
YS		 365 else
366 count = scif_txroom(port);
1da177e4
LT		 367
368 do {
369 unsigned char c;
370
371 if (port->x_char) {
372 c = port->x_char;
373 port->x_char = 0;
374 } else if (!uart_circ_empty(xmit) && !stopped) {
375 c = xmit->buf[xmit->tail];
376 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
377 } else {
378 break;
379 }
380
381 sci_out(port, SCxTDR, c);
382
383 port->icount.tx++;
384 } while (--count > 0);
385
386 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
387
388 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
389 uart_write_wakeup(port);
390 if (uart_circ_empty(xmit)) {
b129a8cc 391 sci_stop_tx(port);
1da177e4 392 } else {
1da177e4
LT		 393 ctrl = sci_in(port, SCSCR);
394
1a22f08d 395 if (port->type != PORT_SCI) {
1da177e4
LT		 396 sci_in(port, SCxSR); /* Dummy read */
397 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
398 }
1da177e4
LT		 399
400 ctrl |= SCI_CTRL_FLAGS_TIE;
401 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 402 }
403}
404
405/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 406#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 407
7d12e780 408static inline void sci_receive_chars(struct uart_port *port)
1da177e4 409{
e7c98dc7 410 struct sci_port *sci_port = to_sci_port(port);
a88487c7 411 struct tty_struct *tty = port->info->port.tty;
1da177e4
LT		 412 int i, count, copied = 0;
413 unsigned short status;
33f0f88f 414 unsigned char flag;
1da177e4
LT		 415
416 status = sci_in(port, SCxSR);
417 if (!(status & SCxSR_RDxF(port)))
418 return;
419
420 while (1) {
1a22f08d 421 if (port->type == PORT_SCI)
e108b2ca 422 count = sci_rxroom(port);
1a22f08d
YS		 423 else
424 count = scif_rxroom(port);
1da177e4
LT		 425
426 /* Don't copy more bytes than there is room for in the buffer */
33f0f88f 427 count = tty_buffer_request_room(tty, count);
1da177e4
LT		 428
429 /* If for any reason we can't copy more data, we're done! */
430 if (count == 0)
431 break;
432
433 if (port->type == PORT_SCI) {
434 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 435 if (uart_handle_sysrq_char(port, c) ||
436 sci_port->break_flag)
1da177e4 437 count = 0;
e7c98dc7 438 else
e108b2ca 439 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 440 } else {
e7c98dc7 441 for (i = 0; i < count; i++) {
1da177e4
LT		 442 char c = sci_in(port, SCxRDR);
443 status = sci_in(port, SCxSR);
444#if defined(CONFIG_CPU_SH3)
445 /* Skip "chars" during break */
e108b2ca 446 if (sci_port->break_flag) {
1da177e4
LT		 447 if ((c == 0) &&
448 (status & SCxSR_FER(port))) {
449 count--; i--;
450 continue;
451 }
e108b2ca 452
1da177e4 453 /* Nonzero => end-of-break */
762c69e3 454 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 455 sci_port->break_flag = 0;
456
1da177e4
LT		 457 if (STEPFN(c)) {
458 count--; i--;
459 continue;
460 }
461 }
462#endif /* CONFIG_CPU_SH3 */
7d12e780 463 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 464 count--; i--;
465 continue;
466 }
467
468 /* Store data and status */
1da177e4 469 if (status&SCxSR_FER(port)) {
33f0f88f 470 flag = TTY_FRAME;
762c69e3 471 dev_notice(port->dev, "frame error\n");
1da177e4 472 } else if (status&SCxSR_PER(port)) {
33f0f88f 473 flag = TTY_PARITY;
762c69e3 474 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 475 } else
476 flag = TTY_NORMAL;
762c69e3 477
33f0f88f 478 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 479 }
480 }
481
482 sci_in(port, SCxSR); /* dummy read */
483 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
484
1da177e4
LT		 485 copied += count;
486 port->icount.rx += count;
487 }
488
489 if (copied) {
490 /* Tell the rest of the system the news. New characters! */
491 tty_flip_buffer_push(tty);
492 } else {
493 sci_in(port, SCxSR); /* dummy read */
494 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
495 }
496}
497
498#define SCI_BREAK_JIFFIES (HZ/20)
499/* The sci generates interrupts during the break,
500 * 1 per millisecond or so during the break period, for 9600 baud.
501 * So dont bother disabling interrupts.
502 * But dont want more than 1 break event.
503 * Use a kernel timer to periodically poll the rx line until
504 * the break is finished.
505 */
506static void sci_schedule_break_timer(struct sci_port *port)
507{
508 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
509 add_timer(&port->break_timer);
510}
511/* Ensure that two consecutive samples find the break over. */
512static void sci_break_timer(unsigned long data)
513{
e108b2ca
PM		 514 struct sci_port *port = (struct sci_port *)data;
515
516 if (sci_rxd_in(&port->port) == 0) {
1da177e4 517 port->break_flag = 1;
e108b2ca
PM		 518 sci_schedule_break_timer(port);
519 } else if (port->break_flag == 1) {
1da177e4
LT		 520 /* break is over. */
521 port->break_flag = 2;
e108b2ca
PM		 522 sci_schedule_break_timer(port);
523 } else
524 port->break_flag = 0;
1da177e4
LT		 525}
526
527static inline int sci_handle_errors(struct uart_port *port)
528{
529 int copied = 0;
530 unsigned short status = sci_in(port, SCxSR);
a88487c7 531 struct tty_struct *tty = port->info->port.tty;
1da177e4 532
e108b2ca 533 if (status & SCxSR_ORER(port)) {
1da177e4 534 /* overrun error */
e108b2ca 535 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
33f0f88f 536 copied++;
762c69e3
PM		 537
538 dev_notice(port->dev, "overrun error");
1da177e4
LT		 539 }
540
e108b2ca 541 if (status & SCxSR_FER(port)) {
1da177e4
LT		 542 if (sci_rxd_in(port) == 0) {
543 /* Notify of BREAK */
e7c98dc7 544 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 545
546 if (!sci_port->break_flag) {
547 sci_port->break_flag = 1;
548 sci_schedule_break_timer(sci_port);
549
1da177e4 550 /* Do sysrq handling. */
e108b2ca 551 if (uart_handle_break(port))
1da177e4 552 return 0;
762c69e3
PM		 553
554 dev_dbg(port->dev, "BREAK detected\n");
555
e108b2ca 556 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 557 copied++;
558 }
559
e108b2ca 560 } else {
1da177e4 561 /* frame error */
e108b2ca 562 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 563 copied++;
762c69e3
PM		 564
565 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 566 }
567 }
568
e108b2ca 569 if (status & SCxSR_PER(port)) {
1da177e4 570 /* parity error */
e108b2ca
PM		 571 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
572 copied++;
762c69e3
PM		 573
574 dev_notice(port->dev, "parity error");
1da177e4
LT		 575 }
576
33f0f88f 577 if (copied)
1da177e4 578 tty_flip_buffer_push(tty);
1da177e4
LT		 579
580 return copied;
581}
582
d830fa45
PM		 583static inline int sci_handle_fifo_overrun(struct uart_port *port)
584{
585 struct tty_struct *tty = port->info->port.tty;
586 int copied = 0;
587
588 if (port->type != PORT_SCIF)
589 return 0;
590
591 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
592 sci_out(port, SCLSR, 0);
593
594 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
595 tty_flip_buffer_push(tty);
596
597 dev_notice(port->dev, "overrun error\n");
598 copied++;
599 }
600
601 return copied;
602}
603
1da177e4
LT		 604static inline int sci_handle_breaks(struct uart_port *port)
605{
606 int copied = 0;
607 unsigned short status = sci_in(port, SCxSR);
a88487c7 608 struct tty_struct *tty = port->info->port.tty;
1da177e4
LT		 609 struct sci_port *s = &sci_ports[port->line];
610
0b3d4ef6
PM		 611 if (uart_handle_break(port))
612 return 0;
613
b7a76e4b 614 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 615#if defined(CONFIG_CPU_SH3)
616 /* Debounce break */
617 s->break_flag = 1;
618#endif
619 /* Notify of BREAK */
e108b2ca 620 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 621 copied++;
762c69e3
PM		 622
623 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 624 }
625
33f0f88f 626 if (copied)
1da177e4 627 tty_flip_buffer_push(tty);
e108b2ca 628
d830fa45
PM		 629 copied += sci_handle_fifo_overrun(port);
630
1da177e4
LT		 631 return copied;
632}
633
7d12e780 634static irqreturn_t sci_rx_interrupt(int irq, void *port)
1da177e4 635{
1da177e4
LT		 636 /* I think sci_receive_chars has to be called irrespective
637 * of whether the I_IXOFF is set, otherwise, how is the interrupt
638 * to be disabled?
639 */
7d12e780 640 sci_receive_chars(port);
1da177e4
LT		 641
642 return IRQ_HANDLED;
643}
644
7d12e780 645static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 646{
647 struct uart_port *port = ptr;
648
e108b2ca 649 spin_lock_irq(&port->lock);
1da177e4 650 sci_transmit_chars(port);
e108b2ca 651 spin_unlock_irq(&port->lock);
1da177e4
LT		 652
653 return IRQ_HANDLED;
654}
655
7d12e780 656static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 657{
658 struct uart_port *port = ptr;
659
660 /* Handle errors */
661 if (port->type == PORT_SCI) {
662 if (sci_handle_errors(port)) {
663 /* discard character in rx buffer */
664 sci_in(port, SCxSR);
665 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
666 }
667 } else {
d830fa45 668 sci_handle_fifo_overrun(port);
7d12e780 669 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 670 }
671
672 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
673
674 /* Kick the transmission */
7d12e780 675 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 676
677 return IRQ_HANDLED;
678}
679
7d12e780 680static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 681{
682 struct uart_port *port = ptr;
683
684 /* Handle BREAKs */
685 sci_handle_breaks(port);
686 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
687
688 return IRQ_HANDLED;
689}
690
7d12e780 691static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 692{
a8884e34
MT		 693 unsigned short ssr_status, scr_status;
694 struct uart_port *port = ptr;
695 irqreturn_t ret = IRQ_NONE;
1da177e4 696
e7c98dc7
MT		 697 ssr_status = sci_in(port, SCxSR);
698 scr_status = sci_in(port, SCSCR);
1da177e4
LT		 699
700 /* Tx Interrupt */
a8884e34
MT		 701 if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
702 ret = sci_tx_interrupt(irq, ptr);
1da177e4 703 /* Rx Interrupt */
a8884e34
MT		 704 if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
705 ret = sci_rx_interrupt(irq, ptr);
1da177e4 706 /* Error Interrupt */
a8884e34
MT		 707 if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
708 ret = sci_er_interrupt(irq, ptr);
1da177e4 709 /* Break Interrupt */
a8884e34
MT		 710 if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
711 ret = sci_br_interrupt(irq, ptr);
1da177e4 712
a8884e34 713 return ret;
1da177e4
LT		 714}
715
027e6872 716#ifdef CONFIG_HAVE_CLK
1da177e4
LT		 717/*
718 * Here we define a transistion notifier so that we can update all of our
719 * ports' baud rate when the peripheral clock changes.
720 */
e108b2ca
PM		 721static int sci_notifier(struct notifier_block *self,
722 unsigned long phase, void *p)
1da177e4 723{
1da177e4
LT		 724 int i;
725
726 if ((phase == CPUFREQ_POSTCHANGE) ||
027e6872 727 (phase == CPUFREQ_RESUMECHANGE))
1da177e4 728 for (i = 0; i < SCI_NPORTS; i++) {
027e6872
PM		 729 struct sci_port *s = &sci_ports[i];
730 s->port.uartclk = clk_get_rate(s->clk);
1da177e4
LT		 731 }
732
1da177e4
LT		 733 return NOTIFY_OK;
734}
735
736static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
027e6872 737#endif
1da177e4
LT		 738
739static int sci_request_irq(struct sci_port *port)
740{
741 int i;
7d12e780 742 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
1da177e4
LT		 743 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
744 sci_br_interrupt,
745 };
746 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
747 "SCI Transmit Data Empty", "SCI Break" };
748
749 if (port->irqs[0] == port->irqs[1]) {
762c69e3 750 if (unlikely(!port->irqs[0]))
1da177e4 751 return -ENODEV;
e108b2ca
PM		 752
753 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
35f3c518 754 IRQF_DISABLED, "sci", port)) {
762c69e3 755 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 756 return -ENODEV;
757 }
758 } else {
759 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
762c69e3 760 if (unlikely(!port->irqs[i]))
1da177e4 761 continue;
762c69e3 762
e108b2ca 763 if (request_irq(port->irqs[i], handlers[i],
35f3c518 764 IRQF_DISABLED, desc[i], port)) {
762c69e3 765 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 766 return -ENODEV;
767 }
768 }
769 }
770
771 return 0;
772}
773
774static void sci_free_irq(struct sci_port *port)
775{
776 int i;
777
762c69e3
PM		 778 if (port->irqs[0] == port->irqs[1])
779 free_irq(port->irqs[0], port);
780 else {
1da177e4
LT		 781 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
782 if (!port->irqs[i])
783 continue;
784
785 free_irq(port->irqs[i], port);
786 }
787 }
788}
789
790static unsigned int sci_tx_empty(struct uart_port *port)
791{
792 /* Can't detect */
793 return TIOCSER_TEMT;
794}
795
796static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
797{
798 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
799 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
800 /* If you have signals for DTR and DCD, please implement here. */
801}
802
803static unsigned int sci_get_mctrl(struct uart_port *port)
804{
805 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
806 and CTS/RTS */
807
808 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
809}
810
b129a8cc 811static void sci_start_tx(struct uart_port *port)
1da177e4 812{
e108b2ca 813 unsigned short ctrl;
1da177e4 814
e108b2ca
PM		 815 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
816 ctrl = sci_in(port, SCSCR);
817 ctrl |= SCI_CTRL_FLAGS_TIE;
818 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 819}
820
b129a8cc 821static void sci_stop_tx(struct uart_port *port)
1da177e4 822{
1da177e4
LT		 823 unsigned short ctrl;
824
825 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4
LT		 826 ctrl = sci_in(port, SCSCR);
827 ctrl &= ~SCI_CTRL_FLAGS_TIE;
828 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 829}
830
831static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
832{
1da177e4
LT		 833 unsigned short ctrl;
834
835 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1da177e4
LT		 836 ctrl = sci_in(port, SCSCR);
837 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
838 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 839}
840
841static void sci_stop_rx(struct uart_port *port)
842{
1da177e4
LT		 843 unsigned short ctrl;
844
845 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1da177e4
LT		 846 ctrl = sci_in(port, SCSCR);
847 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
848 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 849}
850
851static void sci_enable_ms(struct uart_port *port)
852{
853 /* Nothing here yet .. */
854}
855
856static void sci_break_ctl(struct uart_port *port, int break_state)
857{
858 /* Nothing here yet .. */
859}
860
861static int sci_startup(struct uart_port *port)
862{
863 struct sci_port *s = &sci_ports[port->line];
864
e108b2ca
PM		 865 if (s->enable)
866 s->enable(port);
1da177e4 867
a2159b52 868#ifdef CONFIG_HAVE_CLK
1534a3b3 869 s->clk = clk_get(NULL, "module_clk");
005a336e 870#endif
1534a3b3 871
1da177e4 872 sci_request_irq(s);
d656901b 873 sci_start_tx(port);
1da177e4
LT		 874 sci_start_rx(port, 1);
875
876 return 0;
877}
878
879static void sci_shutdown(struct uart_port *port)
880{
881 struct sci_port *s = &sci_ports[port->line];
882
883 sci_stop_rx(port);
b129a8cc 884 sci_stop_tx(port);
1da177e4
LT		 885 sci_free_irq(s);
886
e108b2ca
PM		 887 if (s->disable)
888 s->disable(port);
1534a3b3 889
a2159b52 890#ifdef CONFIG_HAVE_CLK
1534a3b3 891 clk_put(s->clk);
892 s->clk = NULL;
005a336e 893#endif
1da177e4
LT		 894}
895
606d099c
AC		 896static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
897 struct ktermios *old)
1da177e4 898{
1da177e4 899 unsigned int status, baud, smr_val;
a2159b52 900 int t = -1;
1da177e4
LT		 901
902 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
a2159b52
PM		 903 if (likely(baud))
904 t = SCBRR_VALUE(baud, port->uartclk);
e108b2ca 905
1da177e4
LT		 906 do {
907 status = sci_in(port, SCxSR);
908 } while (!(status & SCxSR_TEND(port)));
909
910 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
911
1a22f08d 912 if (port->type != PORT_SCI)
1da177e4 913 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 914
915 smr_val = sci_in(port, SCSMR) & 3;
916 if ((termios->c_cflag & CSIZE) == CS7)
917 smr_val |= 0x40;
918 if (termios->c_cflag & PARENB)
919 smr_val |= 0x20;
920 if (termios->c_cflag & PARODD)
921 smr_val |= 0x30;
922 if (termios->c_cflag & CSTOPB)
923 smr_val |= 0x08;
924
925 uart_update_timeout(port, termios->c_cflag, baud);
926
927 sci_out(port, SCSMR, smr_val);
928
1da177e4 929 if (t > 0) {
e7c98dc7 930 if (t >= 256) {
1da177e4
LT		 931 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
932 t >>= 2;
e7c98dc7 933 } else
1da177e4 934 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 935
1da177e4
LT		 936 sci_out(port, SCBRR, t);
937 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
938 }
939
d5701647
PM		 940 sci_init_pins(port, termios->c_cflag);
941 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
b7a76e4b 942
1da177e4
LT		 943 sci_out(port, SCSCR, SCSCR_INIT(port));
944
945 if ((termios->c_cflag & CREAD) != 0)
e7c98dc7 946 sci_start_rx(port, 0);
1da177e4
LT		 947}
948
949static const char *sci_type(struct uart_port *port)
950{
951 switch (port->type) {
e7c98dc7
MT		 952 case PORT_IRDA:
953 return "irda";
954 case PORT_SCI:
955 return "sci";
956 case PORT_SCIF:
957 return "scif";
958 case PORT_SCIFA:
959 return "scifa";
1da177e4
LT		 960 }
961
fa43972f 962 return NULL;
1da177e4
LT		 963}
964
965static void sci_release_port(struct uart_port *port)
966{
967 /* Nothing here yet .. */
968}
969
970static int sci_request_port(struct uart_port *port)
971{
972 /* Nothing here yet .. */
973 return 0;
974}
975
976static void sci_config_port(struct uart_port *port, int flags)
977{
978 struct sci_port *s = &sci_ports[port->line];
979
980 port->type = s->type;
981
7ff731ae
PM		 982 if (port->flags & UPF_IOREMAP && !port->membase) {
983#if defined(CONFIG_SUPERH64)
1da177e4 984 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
7ff731ae
PM		 985 port->membase = (void __iomem *)port->mapbase;
986#else
987 port->membase = ioremap_nocache(port->mapbase, 0x40);
1da177e4 988#endif
7ff731ae 989
762c69e3 990 dev_err(port->dev, "can't remap port#%d\n", port->line);
7ff731ae 991 }
1da177e4
LT		 992}
993
994static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
995{
996 struct sci_port *s = &sci_ports[port->line];
997
a62c4133 998 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 999 return -EINVAL;
1000 if (ser->baud_base < 2400)
1001 /* No paper tape reader for Mitch.. */
1002 return -EINVAL;
1003
1004 return 0;
1005}
1006
1007static struct uart_ops sci_uart_ops = {
1008 .tx_empty = sci_tx_empty,
1009 .set_mctrl = sci_set_mctrl,
1010 .get_mctrl = sci_get_mctrl,
1011 .start_tx = sci_start_tx,
1012 .stop_tx = sci_stop_tx,
1013 .stop_rx = sci_stop_rx,
1014 .enable_ms = sci_enable_ms,
1015 .break_ctl = sci_break_ctl,
1016 .startup = sci_startup,
1017 .shutdown = sci_shutdown,
1018 .set_termios = sci_set_termios,
1019 .type = sci_type,
1020 .release_port = sci_release_port,
1021 .request_port = sci_request_port,
1022 .config_port = sci_config_port,
1023 .verify_port = sci_verify_port,
07d2a1a1
PM		 1024#ifdef CONFIG_CONSOLE_POLL
1025 .poll_get_char = sci_poll_get_char,
1026 .poll_put_char = sci_poll_put_char,
1027#endif
1da177e4
LT		 1028};
1029
e108b2ca
PM		 1030static void __init sci_init_ports(void)
1031{
1032 static int first = 1;
1033 int i;
1034
1035 if (!first)
1036 return;
1037
1038 first = 0;
1039
1040 for (i = 0; i < SCI_NPORTS; i++) {
1041 sci_ports[i].port.ops = &sci_uart_ops;
1042 sci_ports[i].port.iotype = UPIO_MEM;
1043 sci_ports[i].port.line = i;
1044 sci_ports[i].port.fifosize = 1;
1045
1046#if defined(__H8300H__) || defined(__H8300S__)
1047#ifdef __H8300S__
1048 sci_ports[i].enable = h8300_sci_enable;
1049 sci_ports[i].disable = h8300_sci_disable;
1050#endif
1051 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
a2159b52 1052#elif defined(CONFIG_HAVE_CLK)
e108b2ca
PM		 1053 /*
1054 * XXX: We should use a proper SCI/SCIF clock
1055 */
1056 {
1d118562 1057 struct clk *clk = clk_get(NULL, "module_clk");
a2159b52 1058 sci_ports[i].port.uartclk = clk_get_rate(clk);
e108b2ca
PM		 1059 clk_put(clk);
1060 }
a2159b52
PM		 1061#else
1062#error "Need a valid uartclk"
1da177e4 1063#endif
e108b2ca
PM		 1064
1065 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1066 sci_ports[i].break_timer.function = sci_break_timer;
1067
1068 init_timer(&sci_ports[i].break_timer);
1069 }
1070}
1071
1072int __init early_sci_setup(struct uart_port *port)
1073{
1074 if (unlikely(port->line > SCI_NPORTS))
1075 return -ENODEV;
1076
1077 sci_init_ports();
1078
1079 sci_ports[port->line].port.membase = port->membase;
1080 sci_ports[port->line].port.mapbase = port->mapbase;
1081 sci_ports[port->line].port.type = port->type;
1082
1083 return 0;
1084}
1da177e4
LT		 1085
1086#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1087/*
1088 * Print a string to the serial port trying not to disturb
1089 * any possible real use of the port...
1090 */
1091static void serial_console_write(struct console *co, const char *s,
1092 unsigned count)
1093{
07d2a1a1
PM		 1094 struct uart_port *port = &serial_console_port->port;
1095 int i;
1096
1097 for (i = 0; i < count; i++) {
1098 if (*s == 10)
1099 sci_poll_put_char(port, '\r');
1100
1101 sci_poll_put_char(port, *s++);
1102 }
1da177e4
LT		 1103}
1104
1105static int __init serial_console_setup(struct console *co, char *options)
1106{
1107 struct uart_port *port;
1108 int baud = 115200;
1109 int bits = 8;
1110 int parity = 'n';
1111 int flow = 'n';
1112 int ret;
1113
e108b2ca
PM		 1114 /*
1115 * Check whether an invalid uart number has been specified, and
1116 * if so, search for the first available port that does have
1117 * console support.
1118 */
1119 if (co->index >= SCI_NPORTS)
1120 co->index = 0;
1121
1da177e4
LT		 1122 serial_console_port = &sci_ports[co->index];
1123 port = &serial_console_port->port;
1da177e4
LT		 1124
1125 /*
e108b2ca
PM		 1126 * Also need to check port->type, we don't actually have any
1127 * UPIO_PORT ports, but uart_report_port() handily misreports
1128 * it anyways if we don't have a port available by the time this is
1129 * called.
1da177e4 1130 */
e108b2ca
PM		 1131 if (!port->type)
1132 return -ENODEV;
1133 if (!port->membase || !port->mapbase)
1134 return -ENODEV;
1135
e108b2ca
PM		 1136 port->type = serial_console_port->type;
1137
a2159b52 1138#ifdef CONFIG_HAVE_CLK
005a336e
PM		 1139 if (!serial_console_port->clk)
1140 serial_console_port->clk = clk_get(NULL, "module_clk");
1141#endif
1142
e108b2ca
PM		 1143 if (port->flags & UPF_IOREMAP)
1144 sci_config_port(port, 0);
1145
1146 if (serial_console_port->enable)
1147 serial_console_port->enable(port);
b7a76e4b 1148
1da177e4
LT		 1149 if (options)
1150 uart_parse_options(options, &baud, &parity, &bits, &flow);
1151
1152 ret = uart_set_options(port, co, baud, parity, bits, flow);
1153#if defined(__H8300H__) || defined(__H8300S__)
1154 /* disable rx interrupt */
1155 if (ret == 0)
1156 sci_stop_rx(port);
1157#endif
1158 return ret;
1159}
1160
1161static struct console serial_console = {
1162 .name = "ttySC",
1163 .device = uart_console_device,
1164 .write = serial_console_write,
1165 .setup = serial_console_setup,
fa5da2f7 1166 .flags = CON_PRINTBUFFER,
1da177e4
LT		 1167 .index = -1,
1168 .data = &sci_uart_driver,
1169};
1170
1171static int __init sci_console_init(void)
1172{
e108b2ca 1173 sci_init_ports();
1da177e4
LT		 1174 register_console(&serial_console);
1175 return 0;
1176}
1da177e4
LT		 1177console_initcall(sci_console_init);
1178#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1179
07d2a1a1 1180#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
e7c98dc7 1181#define SCI_CONSOLE (&serial_console)
1da177e4 1182#else
b7a76e4b 1183#define SCI_CONSOLE 0
1da177e4
LT		 1184#endif
1185
1186static char banner[] __initdata =
1187 KERN_INFO "SuperH SCI(F) driver initialized\n";
1188
1189static struct uart_driver sci_uart_driver = {
1190 .owner = THIS_MODULE,
1191 .driver_name = "sci",
1da177e4
LT		 1192 .dev_name = "ttySC",
1193 .major = SCI_MAJOR,
1194 .minor = SCI_MINOR_START,
e108b2ca 1195 .nr = SCI_NPORTS,
1da177e4
LT		 1196 .cons = SCI_CONSOLE,
1197};
1198
e108b2ca
PM		 1199/*
1200 * Register a set of serial devices attached to a platform device. The
1201 * list is terminated with a zero flags entry, which means we expect
1202 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1203 * remapping (such as sh64) should also set UPF_IOREMAP.
1204 */
1205static int __devinit sci_probe(struct platform_device *dev)
1da177e4 1206{
e108b2ca 1207 struct plat_sci_port *p = dev->dev.platform_data;
7ff731ae 1208 int i, ret = -EINVAL;
1da177e4 1209
32351a28 1210 for (i = 0; p && p->flags != 0; p++, i++) {
e108b2ca 1211 struct sci_port *sciport = &sci_ports[i];
1da177e4 1212
32351a28
PM		 1213 /* Sanity check */
1214 if (unlikely(i == SCI_NPORTS)) {
1215 dev_notice(&dev->dev, "Attempting to register port "
1216 "%d when only %d are available.\n",
1217 i+1, SCI_NPORTS);
1218 dev_notice(&dev->dev, "Consider bumping "
1219 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1220 break;
1221 }
1222
e108b2ca 1223 sciport->port.mapbase = p->mapbase;
b7a76e4b 1224
7ff731ae
PM		 1225 if (p->mapbase && !p->membase) {
1226 if (p->flags & UPF_IOREMAP) {
1227 p->membase = ioremap_nocache(p->mapbase, 0x40);
1228 if (IS_ERR(p->membase)) {
1229 ret = PTR_ERR(p->membase);
1230 goto err_unreg;
1231 }
1232 } else {
1233 /*
1234 * For the simple (and majority of) cases
1235 * where we don't need to do any remapping,
1236 * just cast the cookie directly.
1237 */
1238 p->membase = (void __iomem *)p->mapbase;
1239 }
1240 }
1da177e4 1241
e108b2ca
PM		 1242 sciport->port.membase = p->membase;
1243
1244 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1245 sciport->port.flags = p->flags;
1246 sciport->port.dev = &dev->dev;
1247
1248 sciport->type = sciport->port.type = p->type;
1249
1250 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1251
1252 uart_add_one_port(&sci_uart_driver, &sciport->port);
1da177e4
LT		 1253 }
1254
027e6872 1255#ifdef CONFIG_HAVE_CLK
1da177e4 1256 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1da177e4
LT		 1257#endif
1258
1259#ifdef CONFIG_SH_STANDARD_BIOS
1260 sh_bios_gdb_detach();
1261#endif
1262
e108b2ca 1263 return 0;
7ff731ae
PM		 1264
1265err_unreg:
1266 for (i = i - 1; i >= 0; i--)
1267 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1268
1269 return ret;
1da177e4
LT		 1270}
1271
e108b2ca
PM		 1272static int __devexit sci_remove(struct platform_device *dev)
1273{
1274 int i;
1275
027e6872
PM		 1276#ifdef CONFIG_HAVE_CLK
1277 cpufreq_unregister_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1278#endif
1279
e108b2ca
PM		 1280 for (i = 0; i < SCI_NPORTS; i++)
1281 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1282
1283 return 0;
1284}
1285
1286static int sci_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1287{
e108b2ca
PM		 1288 int i;
1289
1290 for (i = 0; i < SCI_NPORTS; i++) {
1291 struct sci_port *p = &sci_ports[i];
1292
1293 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1294 uart_suspend_port(&sci_uart_driver, &p->port);
1295 }
1da177e4 1296
e108b2ca
PM		 1297 return 0;
1298}
1da177e4 1299
e108b2ca
PM		 1300static int sci_resume(struct platform_device *dev)
1301{
1302 int i;
1303
1304 for (i = 0; i < SCI_NPORTS; i++) {
1305 struct sci_port *p = &sci_ports[i];
1306
1307 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1308 uart_resume_port(&sci_uart_driver, &p->port);
1309 }
1310
1311 return 0;
1312}
1313
1314static struct platform_driver sci_driver = {
1315 .probe = sci_probe,
1316 .remove = __devexit_p(sci_remove),
1317 .suspend = sci_suspend,
1318 .resume = sci_resume,
1319 .driver = {
1320 .name = "sh-sci",
1321 .owner = THIS_MODULE,
1322 },
1323};
1324
1325static int __init sci_init(void)
1326{
1327 int ret;
1328
1329 printk(banner);
1330
1331 sci_init_ports();
1332
1333 ret = uart_register_driver(&sci_uart_driver);
1334 if (likely(ret == 0)) {
1335 ret = platform_driver_register(&sci_driver);
1336 if (unlikely(ret))
1337 uart_unregister_driver(&sci_uart_driver);
1338 }
1339
1340 return ret;
1341}
1342
1343static void __exit sci_exit(void)
1344{
1345 platform_driver_unregister(&sci_driver);
1da177e4
LT		 1346 uart_unregister_driver(&sci_uart_driver);
1347}
1348
1349module_init(sci_init);
1350module_exit(sci_exit);
1351
e108b2ca 1352MODULE_LICENSE("GPL");
e169c139 1353MODULE_ALIAS("platform:sh-sci");
Linux kernel - Deliverables
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