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serial: sh-sci: Kill off some DMA ifdeffery.
[deliverable/linux.git] / drivers / serial / sh-sci.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
f43dc23d 6 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
0b3d4ef6
PM		 22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
1da177e4
LT		 25
26#undef DEBUG
27
1da177e4
LT		 28#include <linux/module.h>
29#include <linux/errno.h>
1da177e4
LT		 30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial.h>
35#include <linux/major.h>
36#include <linux/string.h>
37#include <linux/sysrq.h>
1da177e4
LT		 38#include <linux/ioport.h>
39#include <linux/mm.h>
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
e108b2ca 43#include <linux/platform_device.h>
96de1a8f 44#include <linux/serial_sci.h>
1da177e4
LT		 45#include <linux/notifier.h>
46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
e552de24 50#include <linux/list.h>
73a19e4c
GL		 51#include <linux/dmaengine.h>
52#include <linux/scatterlist.h>
5a0e3ad6 53#include <linux/slab.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
168f3623
YS		 59#ifdef CONFIG_H8300
60#include <asm/gpio.h>
61#endif
62
1da177e4
LT		 63#include "sh-sci.h"
64
e108b2ca
PM		 65struct sci_port {
66 struct uart_port port;
67
ce6738b6
PM		 68 /* Platform configuration */
69 struct plat_sci_port *cfg;
e108b2ca 70
e108b2ca
PM		 71 /* Port enable callback */
72 void (*enable)(struct uart_port *port);
73
74 /* Port disable callback */
75 void (*disable)(struct uart_port *port);
76
77 /* Break timer */
78 struct timer_list break_timer;
79 int break_flag;
1534a3b3 80
501b825d
MD		 81 /* Interface clock */
82 struct clk *iclk;
c7ed1ab3
PM		 83 /* Function clock */
84 struct clk *fclk;
edad1f20 85
e552de24 86 struct list_head node;
f43dc23d 87
73a19e4c
GL		 88 struct dma_chan *chan_tx;
89 struct dma_chan *chan_rx;
f43dc23d 90
73a19e4c 91#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 92 struct dma_async_tx_descriptor *desc_tx;
93 struct dma_async_tx_descriptor *desc_rx[2];
94 dma_cookie_t cookie_tx;
95 dma_cookie_t cookie_rx[2];
96 dma_cookie_t active_rx;
97 struct scatterlist sg_tx;
98 unsigned int sg_len_tx;
99 struct scatterlist sg_rx[2];
100 size_t buf_len_rx;
101 struct sh_dmae_slave param_tx;
102 struct sh_dmae_slave param_rx;
103 struct work_struct work_tx;
104 struct work_struct work_rx;
105 struct timer_list rx_timer;
3089f381 106 unsigned int rx_timeout;
73a19e4c 107#endif
e552de24
MD		 108};
109
110struct sh_sci_priv {
111 spinlock_t lock;
112 struct list_head ports;
e552de24 113 struct notifier_block clk_nb;
e108b2ca
PM		 114};
115
1da177e4 116/* Function prototypes */
b129a8cc 117static void sci_stop_tx(struct uart_port *port);
1da177e4 118
e108b2ca 119#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 120
e108b2ca
PM		 121static struct sci_port sci_ports[SCI_NPORTS];
122static struct uart_driver sci_uart_driver;
1da177e4 123
e7c98dc7
MT		 124static inline struct sci_port *
125to_sci_port(struct uart_port *uart)
126{
127 return container_of(uart, struct sci_port, port);
128}
129
07d2a1a1 130#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 131
132#ifdef CONFIG_CONSOLE_POLL
e108b2ca
PM		 133static inline void handle_error(struct uart_port *port)
134{
135 /* Clear error flags */
1da177e4
LT		 136 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
137}
138
07d2a1a1 139static int sci_poll_get_char(struct uart_port *port)
1da177e4 140{
1da177e4
LT		 141 unsigned short status;
142 int c;
143
e108b2ca 144 do {
1da177e4
LT		 145 status = sci_in(port, SCxSR);
146 if (status & SCxSR_ERRORS(port)) {
147 handle_error(port);
148 continue;
149 }
3f255eb3
JW		 150 break;
151 } while (1);
152
153 if (!(status & SCxSR_RDxF(port)))
154 return NO_POLL_CHAR;
07d2a1a1 155
1da177e4 156 c = sci_in(port, SCxRDR);
07d2a1a1 157
e7c98dc7
MT		 158 /* Dummy read */
159 sci_in(port, SCxSR);
1da177e4 160 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 161
162 return c;
163}
1f6fd5c9 164#endif
1da177e4 165
07d2a1a1 166static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 167{
1da177e4
LT		 168 unsigned short status;
169
1da177e4
LT		 170 do {
171 status = sci_in(port, SCxSR);
172 } while (!(status & SCxSR_TDxE(port)));
173
272966c0 174 sci_out(port, SCxTDR, c);
dd0a3e77 175 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 176}
07d2a1a1 177#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 178
15c73aaa 179#if defined(__H8300H__) || defined(__H8300S__)
d5701647 180static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4
LT		 181{
182 int ch = (port->mapbase - SMR0) >> 3;
183
184 /* set DDR regs */
e108b2ca
PM		 185 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
186 h8300_sci_pins[ch].rx,
187 H8300_GPIO_INPUT);
188 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
189 h8300_sci_pins[ch].tx,
190 H8300_GPIO_OUTPUT);
191
1da177e4
LT		 192 /* tx mark output*/
193 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
194}
d5701647
PM		 195#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
196static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
e108b2ca 197{
d5701647
PM		 198 if (port->mapbase == 0xA4400000) {
199 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
200 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
201 } else if (port->mapbase == 0xA4410000)
202 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
9465a54f 203}
31a49c4b 204#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
d5701647 205static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
3ea6bc3d 206{
3ea6bc3d
MB		 207 unsigned short data;
208
209 if (cflag & CRTSCTS) {
210 /* enable RTS/CTS */
211 if (port->mapbase == 0xa4430000) { /* SCIF0 */
212 /* Clear PTCR bit 9-2; enable all scif pins but sck */
d5701647
PM		 213 data = __raw_readw(PORT_PTCR);
214 __raw_writew((data & 0xfc03), PORT_PTCR);
3ea6bc3d
MB		 215 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
216 /* Clear PVCR bit 9-2 */
d5701647
PM		 217 data = __raw_readw(PORT_PVCR);
218 __raw_writew((data & 0xfc03), PORT_PVCR);
3ea6bc3d 219 }
3ea6bc3d
MB		 220 } else {
221 if (port->mapbase == 0xa4430000) { /* SCIF0 */
222 /* Clear PTCR bit 5-2; enable only tx and rx */
d5701647
PM		 223 data = __raw_readw(PORT_PTCR);
224 __raw_writew((data & 0xffc3), PORT_PTCR);
3ea6bc3d
MB		 225 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
226 /* Clear PVCR bit 5-2 */
d5701647
PM		 227 data = __raw_readw(PORT_PVCR);
228 __raw_writew((data & 0xffc3), PORT_PVCR);
3ea6bc3d
MB		 229 }
230 }
3ea6bc3d 231}
b7a76e4b 232#elif defined(CONFIG_CPU_SH3)
e108b2ca 233/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
d5701647 234static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 235{
b7a76e4b
PM		 236 unsigned short data;
237
238 /* We need to set SCPCR to enable RTS/CTS */
d5701647 239 data = __raw_readw(SCPCR);
b7a76e4b 240 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
d5701647 241 __raw_writew(data & 0x0fcf, SCPCR);
1da177e4 242
d5701647 243 if (!(cflag & CRTSCTS)) {
1da177e4 244 /* We need to set SCPCR to enable RTS/CTS */
d5701647 245 data = __raw_readw(SCPCR);
1da177e4
LT		 246 /* Clear out SCP7MD1,0, SCP4MD1,0,
247 Set SCP6MD1,0 = {01} (output) */
d5701647 248 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
1da177e4 249
32b53076 250 data = __raw_readb(SCPDR);
1da177e4 251 /* Set /RTS2 (bit6) = 0 */
32b53076 252 __raw_writeb(data & 0xbf, SCPDR);
1da177e4 253 }
1da177e4 254}
41504c39 255#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
d5701647 256static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
41504c39 257{
346b7463 258 unsigned short data;
41504c39 259
346b7463 260 if (port->mapbase == 0xffe00000) {
d5701647 261 data = __raw_readw(PSCR);
346b7463 262 data &= ~0x03cf;
d5701647 263 if (!(cflag & CRTSCTS))
346b7463 264 data |= 0x0340;
41504c39 265
d5701647 266 __raw_writew(data, PSCR);
41504c39 267 }
178dd0cd 268}
c01f0f1a
YS		 269#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
270 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
7d740a06 271 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac 272 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
55ba99eb 273 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
2b1bd1ac 274 defined(CONFIG_CPU_SUBTYPE_SHX3)
d5701647
PM		 275static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
276{
277 if (!(cflag & CRTSCTS))
278 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
279}
b0c50ad7 280#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
d5701647
PM		 281static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
282{
283 if (!(cflag & CRTSCTS))
284 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
285}
b7a76e4b 286#else
d5701647
PM		 287static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
288{
289 /* Nothing to do */
1da177e4 290}
e108b2ca
PM		 291#endif
292
32351a28
PM		 293#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
294 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 295 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
296 defined(CONFIG_CPU_SUBTYPE_SH7786)
73a19e4c 297static int scif_txfill(struct uart_port *port)
e108b2ca 298{
73a19e4c 299 return sci_in(port, SCTFDR) & 0xff;
e108b2ca
PM		 300}
301
73a19e4c 302static int scif_txroom(struct uart_port *port)
e108b2ca 303{
73a19e4c 304 return SCIF_TXROOM_MAX - scif_txfill(port);
e108b2ca
PM		 305}
306
73a19e4c 307static int scif_rxfill(struct uart_port *port)
e108b2ca 308{
cae167d3 309 return sci_in(port, SCRFDR) & 0xff;
e108b2ca 310}
c63847a3 311#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
73a19e4c 312static int scif_txfill(struct uart_port *port)
c63847a3 313{
73a19e4c
GL		 314 if (port->mapbase == 0xffe00000 ||
315 port->mapbase == 0xffe08000)
e7c98dc7 316 /* SCIF0/1*/
73a19e4c
GL		 317 return sci_in(port, SCTFDR) & 0xff;
318 else
e7c98dc7 319 /* SCIF2 */
73a19e4c 320 return sci_in(port, SCFDR) >> 8;
c63847a3
NI		 321}
322
73a19e4c
GL		 323static int scif_txroom(struct uart_port *port)
324{
325 if (port->mapbase == 0xffe00000 ||
326 port->mapbase == 0xffe08000)
327 /* SCIF0/1*/
328 return SCIF_TXROOM_MAX - scif_txfill(port);
329 else
330 /* SCIF2 */
331 return SCIF2_TXROOM_MAX - scif_txfill(port);
c63847a3
NI		 332}
333
73a19e4c 334static int scif_rxfill(struct uart_port *port)
c63847a3 335{
e7c98dc7
MT		 336 if ((port->mapbase == 0xffe00000) ||
337 (port->mapbase == 0xffe08000)) {
338 /* SCIF0/1*/
c63847a3 339 return sci_in(port, SCRFDR) & 0xff;
e7c98dc7
MT		 340 } else {
341 /* SCIF2 */
c63847a3 342 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
e7c98dc7 343 }
c63847a3 344}
d1d4b10c
GL		 345#elif defined(CONFIG_ARCH_SH7372)
346static int scif_txfill(struct uart_port *port)
347{
348 if (port->type == PORT_SCIFA)
349 return sci_in(port, SCFDR) >> 8;
350 else
351 return sci_in(port, SCTFDR);
352}
353
354static int scif_txroom(struct uart_port *port)
355{
356 return port->fifosize - scif_txfill(port);
357}
358
359static int scif_rxfill(struct uart_port *port)
360{
361 if (port->type == PORT_SCIFA)
362 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
363 else
364 return sci_in(port, SCRFDR);
365}
e108b2ca 366#else
73a19e4c 367static int scif_txfill(struct uart_port *port)
e108b2ca 368{
73a19e4c 369 return sci_in(port, SCFDR) >> 8;
e108b2ca 370}
1da177e4 371
73a19e4c 372static int scif_txroom(struct uart_port *port)
e108b2ca 373{
73a19e4c 374 return SCIF_TXROOM_MAX - scif_txfill(port);
e108b2ca 375}
1da177e4 376
73a19e4c 377static int scif_rxfill(struct uart_port *port)
e108b2ca
PM		 378{
379 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
380}
1da177e4 381#endif
1da177e4 382
73a19e4c 383static int sci_txfill(struct uart_port *port)
e108b2ca 384{
73a19e4c 385 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 386}
387
73a19e4c
GL		 388static int sci_txroom(struct uart_port *port)
389{
390 return !sci_txfill(port);
391}
392
393static int sci_rxfill(struct uart_port *port)
e108b2ca 394{
e7c98dc7 395 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 396}
397
1da177e4
LT		 398/* ********************************************************************** *
399 * the interrupt related routines *
400 * ********************************************************************** */
401
402static void sci_transmit_chars(struct uart_port *port)
403{
ebd2c8f6 404 struct circ_buf *xmit = &port->state->xmit;
1da177e4 405 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 406 unsigned short status;
407 unsigned short ctrl;
e108b2ca 408 int count;
1da177e4
LT		 409
410 status = sci_in(port, SCxSR);
411 if (!(status & SCxSR_TDxE(port))) {
1da177e4 412 ctrl = sci_in(port, SCSCR);
e7c98dc7 413 if (uart_circ_empty(xmit))
8e698614 414 ctrl &= ~SCSCR_TIE;
e7c98dc7 415 else
8e698614 416 ctrl |= SCSCR_TIE;
1da177e4 417 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 418 return;
419 }
420
1a22f08d 421 if (port->type == PORT_SCI)
e108b2ca 422 count = sci_txroom(port);
1a22f08d
YS		 423 else
424 count = scif_txroom(port);
1da177e4
LT		 425
426 do {
427 unsigned char c;
428
429 if (port->x_char) {
430 c = port->x_char;
431 port->x_char = 0;
432 } else if (!uart_circ_empty(xmit) && !stopped) {
433 c = xmit->buf[xmit->tail];
434 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
435 } else {
436 break;
437 }
438
439 sci_out(port, SCxTDR, c);
440
441 port->icount.tx++;
442 } while (--count > 0);
443
444 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
445
446 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
447 uart_write_wakeup(port);
448 if (uart_circ_empty(xmit)) {
b129a8cc 449 sci_stop_tx(port);
1da177e4 450 } else {
1da177e4
LT		 451 ctrl = sci_in(port, SCSCR);
452
1a22f08d 453 if (port->type != PORT_SCI) {
1da177e4
LT		 454 sci_in(port, SCxSR); /* Dummy read */
455 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
456 }
1da177e4 457
8e698614 458 ctrl |= SCSCR_TIE;
1da177e4 459 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 460 }
461}
462
463/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 464#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 465
7d12e780 466static inline void sci_receive_chars(struct uart_port *port)
1da177e4 467{
e7c98dc7 468 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 469 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 470 int i, count, copied = 0;
471 unsigned short status;
33f0f88f 472 unsigned char flag;
1da177e4
LT		 473
474 status = sci_in(port, SCxSR);
475 if (!(status & SCxSR_RDxF(port)))
476 return;
477
478 while (1) {
1a22f08d 479 if (port->type == PORT_SCI)
73a19e4c 480 count = sci_rxfill(port);
1a22f08d 481 else
73a19e4c 482 count = scif_rxfill(port);
1da177e4
LT		 483
484 /* Don't copy more bytes than there is room for in the buffer */
33f0f88f 485 count = tty_buffer_request_room(tty, count);
1da177e4
LT		 486
487 /* If for any reason we can't copy more data, we're done! */
488 if (count == 0)
489 break;
490
491 if (port->type == PORT_SCI) {
492 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 493 if (uart_handle_sysrq_char(port, c) ||
494 sci_port->break_flag)
1da177e4 495 count = 0;
e7c98dc7 496 else
e108b2ca 497 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 498 } else {
e7c98dc7 499 for (i = 0; i < count; i++) {
1da177e4
LT		 500 char c = sci_in(port, SCxRDR);
501 status = sci_in(port, SCxSR);
502#if defined(CONFIG_CPU_SH3)
503 /* Skip "chars" during break */
e108b2ca 504 if (sci_port->break_flag) {
1da177e4
LT		 505 if ((c == 0) &&
506 (status & SCxSR_FER(port))) {
507 count--; i--;
508 continue;
509 }
e108b2ca 510
1da177e4 511 /* Nonzero => end-of-break */
762c69e3 512 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 513 sci_port->break_flag = 0;
514
1da177e4
LT		 515 if (STEPFN(c)) {
516 count--; i--;
517 continue;
518 }
519 }
520#endif /* CONFIG_CPU_SH3 */
7d12e780 521 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 522 count--; i--;
523 continue;
524 }
525
526 /* Store data and status */
73a19e4c 527 if (status & SCxSR_FER(port)) {
33f0f88f 528 flag = TTY_FRAME;
762c69e3 529 dev_notice(port->dev, "frame error\n");
73a19e4c 530 } else if (status & SCxSR_PER(port)) {
33f0f88f 531 flag = TTY_PARITY;
762c69e3 532 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 533 } else
534 flag = TTY_NORMAL;
762c69e3 535
33f0f88f 536 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 537 }
538 }
539
540 sci_in(port, SCxSR); /* dummy read */
541 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
542
1da177e4
LT		 543 copied += count;
544 port->icount.rx += count;
545 }
546
547 if (copied) {
548 /* Tell the rest of the system the news. New characters! */
549 tty_flip_buffer_push(tty);
550 } else {
551 sci_in(port, SCxSR); /* dummy read */
552 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
553 }
554}
555
556#define SCI_BREAK_JIFFIES (HZ/20)
557/* The sci generates interrupts during the break,
558 * 1 per millisecond or so during the break period, for 9600 baud.
559 * So dont bother disabling interrupts.
560 * But dont want more than 1 break event.
561 * Use a kernel timer to periodically poll the rx line until
562 * the break is finished.
563 */
564static void sci_schedule_break_timer(struct sci_port *port)
565{
566 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
567 add_timer(&port->break_timer);
568}
569/* Ensure that two consecutive samples find the break over. */
570static void sci_break_timer(unsigned long data)
571{
e108b2ca
PM		 572 struct sci_port *port = (struct sci_port *)data;
573
574 if (sci_rxd_in(&port->port) == 0) {
1da177e4 575 port->break_flag = 1;
e108b2ca
PM		 576 sci_schedule_break_timer(port);
577 } else if (port->break_flag == 1) {
1da177e4
LT		 578 /* break is over. */
579 port->break_flag = 2;
e108b2ca
PM		 580 sci_schedule_break_timer(port);
581 } else
582 port->break_flag = 0;
1da177e4
LT		 583}
584
585static inline int sci_handle_errors(struct uart_port *port)
586{
587 int copied = 0;
588 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 589 struct tty_struct *tty = port->state->port.tty;
1da177e4 590
e108b2ca 591 if (status & SCxSR_ORER(port)) {
1da177e4 592 /* overrun error */
e108b2ca 593 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
33f0f88f 594 copied++;
762c69e3
PM		 595
596 dev_notice(port->dev, "overrun error");
1da177e4
LT		 597 }
598
e108b2ca 599 if (status & SCxSR_FER(port)) {
1da177e4
LT		 600 if (sci_rxd_in(port) == 0) {
601 /* Notify of BREAK */
e7c98dc7 602 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 603
604 if (!sci_port->break_flag) {
605 sci_port->break_flag = 1;
606 sci_schedule_break_timer(sci_port);
607
1da177e4 608 /* Do sysrq handling. */
e108b2ca 609 if (uart_handle_break(port))
1da177e4 610 return 0;
762c69e3
PM		 611
612 dev_dbg(port->dev, "BREAK detected\n");
613
e108b2ca 614 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 615 copied++;
616 }
617
e108b2ca 618 } else {
1da177e4 619 /* frame error */
e108b2ca 620 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 621 copied++;
762c69e3
PM		 622
623 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 624 }
625 }
626
e108b2ca 627 if (status & SCxSR_PER(port)) {
1da177e4 628 /* parity error */
e108b2ca
PM		 629 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
630 copied++;
762c69e3
PM		 631
632 dev_notice(port->dev, "parity error");
1da177e4
LT		 633 }
634
33f0f88f 635 if (copied)
1da177e4 636 tty_flip_buffer_push(tty);
1da177e4
LT		 637
638 return copied;
639}
640
d830fa45
PM		 641static inline int sci_handle_fifo_overrun(struct uart_port *port)
642{
ebd2c8f6 643 struct tty_struct *tty = port->state->port.tty;
d830fa45
PM		 644 int copied = 0;
645
646 if (port->type != PORT_SCIF)
647 return 0;
648
649 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
650 sci_out(port, SCLSR, 0);
651
652 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
653 tty_flip_buffer_push(tty);
654
655 dev_notice(port->dev, "overrun error\n");
656 copied++;
657 }
658
659 return copied;
660}
661
1da177e4
LT		 662static inline int sci_handle_breaks(struct uart_port *port)
663{
664 int copied = 0;
665 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 666 struct tty_struct *tty = port->state->port.tty;
a5660ada 667 struct sci_port *s = to_sci_port(port);
1da177e4 668
0b3d4ef6
PM		 669 if (uart_handle_break(port))
670 return 0;
671
b7a76e4b 672 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 673#if defined(CONFIG_CPU_SH3)
674 /* Debounce break */
675 s->break_flag = 1;
676#endif
677 /* Notify of BREAK */
e108b2ca 678 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 679 copied++;
762c69e3
PM		 680
681 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 682 }
683
33f0f88f 684 if (copied)
1da177e4 685 tty_flip_buffer_push(tty);
e108b2ca 686
d830fa45
PM		 687 copied += sci_handle_fifo_overrun(port);
688
1da177e4
LT		 689 return copied;
690}
691
73a19e4c 692static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 693{
73a19e4c
GL		 694#ifdef CONFIG_SERIAL_SH_SCI_DMA
695 struct uart_port *port = ptr;
696 struct sci_port *s = to_sci_port(port);
697
698 if (s->chan_rx) {
73a19e4c
GL		 699 u16 scr = sci_in(port, SCSCR);
700 u16 ssr = sci_in(port, SCxSR);
701
702 /* Disable future Rx interrupts */
d1d4b10c 703 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 704 disable_irq_nosync(irq);
705 scr |= 0x4000;
706 } else {
f43dc23d 707 scr &= ~SCSCR_RIE;
3089f381
GL		 708 }
709 sci_out(port, SCSCR, scr);
73a19e4c
GL		 710 /* Clear current interrupt */
711 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 712 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
713 jiffies, s->rx_timeout);
714 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 715
716 return IRQ_HANDLED;
717 }
718#endif
719
1da177e4
LT		 720 /* I think sci_receive_chars has to be called irrespective
721 * of whether the I_IXOFF is set, otherwise, how is the interrupt
722 * to be disabled?
723 */
73a19e4c 724 sci_receive_chars(ptr);
1da177e4
LT		 725
726 return IRQ_HANDLED;
727}
728
7d12e780 729static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 730{
731 struct uart_port *port = ptr;
fd78a76a 732 unsigned long flags;
1da177e4 733
fd78a76a 734 spin_lock_irqsave(&port->lock, flags);
1da177e4 735 sci_transmit_chars(port);
fd78a76a 736 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 737
738 return IRQ_HANDLED;
739}
740
7d12e780 741static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 742{
743 struct uart_port *port = ptr;
744
745 /* Handle errors */
746 if (port->type == PORT_SCI) {
747 if (sci_handle_errors(port)) {
748 /* discard character in rx buffer */
749 sci_in(port, SCxSR);
750 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
751 }
752 } else {
d830fa45 753 sci_handle_fifo_overrun(port);
7d12e780 754 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 755 }
756
757 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
758
759 /* Kick the transmission */
7d12e780 760 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 761
762 return IRQ_HANDLED;
763}
764
7d12e780 765static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 766{
767 struct uart_port *port = ptr;
768
769 /* Handle BREAKs */
770 sci_handle_breaks(port);
771 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
772
773 return IRQ_HANDLED;
774}
775
f43dc23d
PM		 776static inline unsigned long port_rx_irq_mask(struct uart_port *port)
777{
778 /*
779 * Not all ports (such as SCIFA) will support REIE. Rather than
780 * special-casing the port type, we check the port initialization
781 * IRQ enable mask to see whether the IRQ is desired at all. If
782 * it's unset, it's logically inferred that there's no point in
783 * testing for it.
784 */
ce6738b6 785 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 786}
787
7d12e780 788static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 789{
44e18e9e 790 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 791 struct uart_port *port = ptr;
73a19e4c 792 struct sci_port *s = to_sci_port(port);
a8884e34 793 irqreturn_t ret = IRQ_NONE;
1da177e4 794
e7c98dc7
MT		 795 ssr_status = sci_in(port, SCxSR);
796 scr_status = sci_in(port, SCSCR);
f43dc23d 797 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 798
799 /* Tx Interrupt */
f43dc23d 800 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 801 !s->chan_tx)
a8884e34 802 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 803
73a19e4c
GL		 804 /*
805 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
806 * DR flags
807 */
808 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 809 (scr_status & SCSCR_RIE))
a8884e34 810 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 811
1da177e4 812 /* Error Interrupt */
dd4da3a5 813 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 814 ret = sci_er_interrupt(irq, ptr);
f43dc23d 815
1da177e4 816 /* Break Interrupt */
dd4da3a5 817 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 818 ret = sci_br_interrupt(irq, ptr);
1da177e4 819
a8884e34 820 return ret;
1da177e4
LT		 821}
822
1da177e4
LT		 823/*
824 * Here we define a transistion notifier so that we can update all of our
825 * ports' baud rate when the peripheral clock changes.
826 */
e108b2ca
PM		 827static int sci_notifier(struct notifier_block *self,
828 unsigned long phase, void *p)
1da177e4 829{
e552de24
MD		 830 struct sh_sci_priv *priv = container_of(self,
831 struct sh_sci_priv, clk_nb);
832 struct sci_port *sci_port;
833 unsigned long flags;
1da177e4
LT		 834
835 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24
MD		 836 (phase == CPUFREQ_RESUMECHANGE)) {
837 spin_lock_irqsave(&priv->lock, flags);
838 list_for_each_entry(sci_port, &priv->ports, node)
c7ed1ab3 839 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
e552de24
MD		 840 spin_unlock_irqrestore(&priv->lock, flags);
841 }
1da177e4 842
1da177e4
LT		 843 return NOTIFY_OK;
844}
501b825d
MD		 845
846static void sci_clk_enable(struct uart_port *port)
847{
848 struct sci_port *sci_port = to_sci_port(port);
849
c7ed1ab3
PM		 850 clk_enable(sci_port->iclk);
851 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
852 clk_enable(sci_port->fclk);
501b825d
MD		 853}
854
855static void sci_clk_disable(struct uart_port *port)
856{
857 struct sci_port *sci_port = to_sci_port(port);
858
c7ed1ab3
PM		 859 clk_disable(sci_port->fclk);
860 clk_disable(sci_port->iclk);
501b825d 861}
1da177e4
LT		 862
863static int sci_request_irq(struct sci_port *port)
864{
865 int i;
7d12e780 866 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
1da177e4
LT		 867 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
868 sci_br_interrupt,
869 };
870 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
871 "SCI Transmit Data Empty", "SCI Break" };
872
ce6738b6
PM		 873 if (port->cfg->irqs[0] == port->cfg->irqs[1]) {
874 if (unlikely(!port->cfg->irqs[0]))
1da177e4 875 return -ENODEV;
e108b2ca 876
ce6738b6 877 if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt,
35f3c518 878 IRQF_DISABLED, "sci", port)) {
762c69e3 879 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 880 return -ENODEV;
881 }
882 } else {
883 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
ce6738b6 884 if (unlikely(!port->cfg->irqs[i]))
1da177e4 885 continue;
762c69e3 886
ce6738b6 887 if (request_irq(port->cfg->irqs[i], handlers[i],
35f3c518 888 IRQF_DISABLED, desc[i], port)) {
762c69e3 889 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 890 return -ENODEV;
891 }
892 }
893 }
894
895 return 0;
896}
897
898static void sci_free_irq(struct sci_port *port)
899{
900 int i;
901
ce6738b6
PM		 902 if (port->cfg->irqs[0] == port->cfg->irqs[1])
903 free_irq(port->cfg->irqs[0], port);
762c69e3 904 else {
ce6738b6
PM		 905 for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) {
906 if (!port->cfg->irqs[i])
1da177e4
LT		 907 continue;
908
ce6738b6 909 free_irq(port->cfg->irqs[i], port);
1da177e4
LT		 910 }
911 }
912}
913
914static unsigned int sci_tx_empty(struct uart_port *port)
915{
b1516803 916 unsigned short status = sci_in(port, SCxSR);
73a19e4c
GL		 917 unsigned short in_tx_fifo = scif_txfill(port);
918
919 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 920}
921
922static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
923{
924 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
925 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
926 /* If you have signals for DTR and DCD, please implement here. */
927}
928
929static unsigned int sci_get_mctrl(struct uart_port *port)
930{
73a19e4c 931 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1da177e4
LT		 932 and CTS/RTS */
933
934 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
935}
936
73a19e4c
GL		 937#ifdef CONFIG_SERIAL_SH_SCI_DMA
938static void sci_dma_tx_complete(void *arg)
939{
940 struct sci_port *s = arg;
941 struct uart_port *port = &s->port;
942 struct circ_buf *xmit = &port->state->xmit;
943 unsigned long flags;
944
945 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
946
947 spin_lock_irqsave(&port->lock, flags);
948
f354a381 949 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 950 xmit->tail &= UART_XMIT_SIZE - 1;
951
f354a381 952 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 953
954 async_tx_ack(s->desc_tx);
955 s->cookie_tx = -EINVAL;
956 s->desc_tx = NULL;
957
73a19e4c
GL		 958 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
959 uart_write_wakeup(port);
960
3089f381 961 if (!uart_circ_empty(xmit)) {
73a19e4c 962 schedule_work(&s->work_tx);
d1d4b10c 963 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 964 u16 ctrl = sci_in(port, SCSCR);
f43dc23d 965 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
3089f381
GL		 966 }
967
968 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 969}
970
971/* Locking: called with port lock held */
972static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
973 size_t count)
974{
975 struct uart_port *port = &s->port;
976 int i, active, room;
977
978 room = tty_buffer_request_room(tty, count);
979
980 if (s->active_rx == s->cookie_rx[0]) {
981 active = 0;
982 } else if (s->active_rx == s->cookie_rx[1]) {
983 active = 1;
984 } else {
985 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
986 return 0;
987 }
988
989 if (room < count)
990 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
991 count - room);
992 if (!room)
993 return room;
994
995 for (i = 0; i < room; i++)
996 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
997 TTY_NORMAL);
998
999 port->icount.rx += room;
1000
1001 return room;
1002}
1003
1004static void sci_dma_rx_complete(void *arg)
1005{
1006 struct sci_port *s = arg;
1007 struct uart_port *port = &s->port;
1008 struct tty_struct *tty = port->state->port.tty;
1009 unsigned long flags;
1010 int count;
1011
3089f381 1012 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1013
1014 spin_lock_irqsave(&port->lock, flags);
1015
1016 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1017
3089f381 1018 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1019
1020 spin_unlock_irqrestore(&port->lock, flags);
1021
1022 if (count)
1023 tty_flip_buffer_push(tty);
1024
1025 schedule_work(&s->work_rx);
1026}
1027
1028static void sci_start_rx(struct uart_port *port);
1029static void sci_start_tx(struct uart_port *port);
1030
1031static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1032{
1033 struct dma_chan *chan = s->chan_rx;
1034 struct uart_port *port = &s->port;
73a19e4c
GL		 1035
1036 s->chan_rx = NULL;
1037 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1038 dma_release_channel(chan);
85b8e3ff
GL		 1039 if (sg_dma_address(&s->sg_rx[0]))
1040 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1041 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1042 if (enable_pio)
1043 sci_start_rx(port);
1044}
1045
1046static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1047{
1048 struct dma_chan *chan = s->chan_tx;
1049 struct uart_port *port = &s->port;
73a19e4c
GL		 1050
1051 s->chan_tx = NULL;
1052 s->cookie_tx = -EINVAL;
1053 dma_release_channel(chan);
1054 if (enable_pio)
1055 sci_start_tx(port);
1056}
1057
1058static void sci_submit_rx(struct sci_port *s)
1059{
1060 struct dma_chan *chan = s->chan_rx;
1061 int i;
1062
1063 for (i = 0; i < 2; i++) {
1064 struct scatterlist *sg = &s->sg_rx[i];
1065 struct dma_async_tx_descriptor *desc;
1066
1067 desc = chan->device->device_prep_slave_sg(chan,
1068 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1069
1070 if (desc) {
1071 s->desc_rx[i] = desc;
1072 desc->callback = sci_dma_rx_complete;
1073 desc->callback_param = s;
1074 s->cookie_rx[i] = desc->tx_submit(desc);
1075 }
1076
1077 if (!desc || s->cookie_rx[i] < 0) {
1078 if (i) {
1079 async_tx_ack(s->desc_rx[0]);
1080 s->cookie_rx[0] = -EINVAL;
1081 }
1082 if (desc) {
1083 async_tx_ack(desc);
1084 s->cookie_rx[i] = -EINVAL;
1085 }
1086 dev_warn(s->port.dev,
1087 "failed to re-start DMA, using PIO\n");
1088 sci_rx_dma_release(s, true);
1089 return;
1090 }
3089f381
GL		 1091 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1092 s->cookie_rx[i], i);
73a19e4c
GL		 1093 }
1094
1095 s->active_rx = s->cookie_rx[0];
1096
1097 dma_async_issue_pending(chan);
1098}
1099
1100static void work_fn_rx(struct work_struct *work)
1101{
1102 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1103 struct uart_port *port = &s->port;
1104 struct dma_async_tx_descriptor *desc;
1105 int new;
1106
1107 if (s->active_rx == s->cookie_rx[0]) {
1108 new = 0;
1109 } else if (s->active_rx == s->cookie_rx[1]) {
1110 new = 1;
1111 } else {
1112 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1113 return;
1114 }
1115 desc = s->desc_rx[new];
1116
1117 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1118 DMA_SUCCESS) {
1119 /* Handle incomplete DMA receive */
1120 struct tty_struct *tty = port->state->port.tty;
1121 struct dma_chan *chan = s->chan_rx;
1122 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1123 async_tx);
1124 unsigned long flags;
1125 int count;
1126
05827630 1127 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1128 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1129 sh_desc->partial, sh_desc->cookie);
1130
1131 spin_lock_irqsave(&port->lock, flags);
1132 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1133 spin_unlock_irqrestore(&port->lock, flags);
1134
1135 if (count)
1136 tty_flip_buffer_push(tty);
1137
1138 sci_submit_rx(s);
1139
1140 return;
1141 }
1142
1143 s->cookie_rx[new] = desc->tx_submit(desc);
1144 if (s->cookie_rx[new] < 0) {
1145 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1146 sci_rx_dma_release(s, true);
1147 return;
1148 }
1149
73a19e4c 1150 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1151
1152 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1153 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1154}
1155
1156static void work_fn_tx(struct work_struct *work)
1157{
1158 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1159 struct dma_async_tx_descriptor *desc;
1160 struct dma_chan *chan = s->chan_tx;
1161 struct uart_port *port = &s->port;
1162 struct circ_buf *xmit = &port->state->xmit;
1163 struct scatterlist *sg = &s->sg_tx;
1164
1165 /*
1166 * DMA is idle now.
1167 * Port xmit buffer is already mapped, and it is one page... Just adjust
1168 * offsets and lengths. Since it is a circular buffer, we have to
1169 * transmit till the end, and then the rest. Take the port lock to get a
1170 * consistent xmit buffer state.
1171 */
1172 spin_lock_irq(&port->lock);
1173 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1174 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1175 sg->offset;
f354a381 1176 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1177 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1178 spin_unlock_irq(&port->lock);
1179
f354a381 1180 BUG_ON(!sg_dma_len(sg));
73a19e4c
GL		 1181
1182 desc = chan->device->device_prep_slave_sg(chan,
1183 sg, s->sg_len_tx, DMA_TO_DEVICE,
1184 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1185 if (!desc) {
1186 /* switch to PIO */
1187 sci_tx_dma_release(s, true);
1188 return;
1189 }
1190
1191 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1192
1193 spin_lock_irq(&port->lock);
1194 s->desc_tx = desc;
1195 desc->callback = sci_dma_tx_complete;
1196 desc->callback_param = s;
1197 spin_unlock_irq(&port->lock);
1198 s->cookie_tx = desc->tx_submit(desc);
1199 if (s->cookie_tx < 0) {
1200 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1201 /* switch to PIO */
1202 sci_tx_dma_release(s, true);
1203 return;
1204 }
1205
1206 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1207 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1208
1209 dma_async_issue_pending(chan);
1210}
1211#endif
1212
b129a8cc 1213static void sci_start_tx(struct uart_port *port)
1da177e4 1214{
3089f381 1215 struct sci_port *s = to_sci_port(port);
e108b2ca 1216 unsigned short ctrl;
1da177e4 1217
73a19e4c 1218#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1219 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1220 u16 new, scr = sci_in(port, SCSCR);
1221 if (s->chan_tx)
1222 new = scr | 0x8000;
1223 else
1224 new = scr & ~0x8000;
1225 if (new != scr)
1226 sci_out(port, SCSCR, new);
73a19e4c 1227 }
f43dc23d 1228
3089f381
GL		 1229 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1230 s->cookie_tx < 0)
1231 schedule_work(&s->work_tx);
73a19e4c 1232#endif
f43dc23d 1233
d1d4b10c 1234 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1235 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1236 ctrl = sci_in(port, SCSCR);
f43dc23d 1237 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1238 }
1da177e4
LT		 1239}
1240
b129a8cc 1241static void sci_stop_tx(struct uart_port *port)
1da177e4 1242{
1da177e4
LT		 1243 unsigned short ctrl;
1244
1245 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4 1246 ctrl = sci_in(port, SCSCR);
f43dc23d 1247
d1d4b10c 1248 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1249 ctrl &= ~0x8000;
f43dc23d 1250
8e698614 1251 ctrl &= ~SCSCR_TIE;
f43dc23d 1252
1da177e4 1253 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1254}
1255
73a19e4c 1256static void sci_start_rx(struct uart_port *port)
1da177e4 1257{
1da177e4
LT		 1258 unsigned short ctrl;
1259
f43dc23d 1260 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1261
d1d4b10c 1262 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1263 ctrl &= ~0x4000;
f43dc23d 1264
1da177e4 1265 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1266}
1267
1268static void sci_stop_rx(struct uart_port *port)
1269{
1da177e4
LT		 1270 unsigned short ctrl;
1271
1da177e4 1272 ctrl = sci_in(port, SCSCR);
f43dc23d 1273
d1d4b10c 1274 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1275 ctrl &= ~0x4000;
f43dc23d
PM		 1276
1277 ctrl &= ~port_rx_irq_mask(port);
1278
1da177e4 1279 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1280}
1281
1282static void sci_enable_ms(struct uart_port *port)
1283{
1284 /* Nothing here yet .. */
1285}
1286
1287static void sci_break_ctl(struct uart_port *port, int break_state)
1288{
1289 /* Nothing here yet .. */
1290}
1291
73a19e4c
GL		 1292#ifdef CONFIG_SERIAL_SH_SCI_DMA
1293static bool filter(struct dma_chan *chan, void *slave)
1294{
1295 struct sh_dmae_slave *param = slave;
1296
1297 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1298 param->slave_id);
1299
1300 if (param->dma_dev == chan->device->dev) {
1301 chan->private = param;
1302 return true;
1303 } else {
1304 return false;
1305 }
1306}
1307
1308static void rx_timer_fn(unsigned long arg)
1309{
1310 struct sci_port *s = (struct sci_port *)arg;
1311 struct uart_port *port = &s->port;
73a19e4c 1312 u16 scr = sci_in(port, SCSCR);
3089f381 1313
d1d4b10c 1314 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1315 scr &= ~0x4000;
ce6738b6 1316 enable_irq(s->cfg->irqs[1]);
3089f381 1317 }
f43dc23d 1318 sci_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1319 dev_dbg(port->dev, "DMA Rx timed out\n");
1320 schedule_work(&s->work_rx);
1321}
1322
1323static void sci_request_dma(struct uart_port *port)
1324{
1325 struct sci_port *s = to_sci_port(port);
1326 struct sh_dmae_slave *param;
1327 struct dma_chan *chan;
1328 dma_cap_mask_t mask;
1329 int nent;
1330
1331 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
ce6738b6 1332 port->line, s->cfg->dma_dev);
73a19e4c 1333
ce6738b6 1334 if (!s->cfg->dma_dev)
73a19e4c
GL		 1335 return;
1336
1337 dma_cap_zero(mask);
1338 dma_cap_set(DMA_SLAVE, mask);
1339
1340 param = &s->param_tx;
1341
1342 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
ce6738b6
PM		 1343 param->slave_id = s->cfg->dma_slave_tx;
1344 param->dma_dev = s->cfg->dma_dev;
73a19e4c
GL		 1345
1346 s->cookie_tx = -EINVAL;
1347 chan = dma_request_channel(mask, filter, param);
1348 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1349 if (chan) {
1350 s->chan_tx = chan;
1351 sg_init_table(&s->sg_tx, 1);
1352 /* UART circular tx buffer is an aligned page. */
1353 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1354 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1355 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1356 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1357 if (!nent)
1358 sci_tx_dma_release(s, false);
1359 else
1360 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1361 sg_dma_len(&s->sg_tx),
1362 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1363
1364 s->sg_len_tx = nent;
1365
1366 INIT_WORK(&s->work_tx, work_fn_tx);
1367 }
1368
1369 param = &s->param_rx;
1370
1371 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
ce6738b6
PM		 1372 param->slave_id = s->cfg->dma_slave_rx;
1373 param->dma_dev = s->cfg->dma_dev;
73a19e4c
GL		 1374
1375 chan = dma_request_channel(mask, filter, param);
1376 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1377 if (chan) {
1378 dma_addr_t dma[2];
1379 void *buf[2];
1380 int i;
1381
1382 s->chan_rx = chan;
1383
1384 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1385 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1386 &dma[0], GFP_KERNEL);
1387
1388 if (!buf[0]) {
1389 dev_warn(port->dev,
1390 "failed to allocate dma buffer, using PIO\n");
1391 sci_rx_dma_release(s, true);
1392 return;
1393 }
1394
1395 buf[1] = buf[0] + s->buf_len_rx;
1396 dma[1] = dma[0] + s->buf_len_rx;
1397
1398 for (i = 0; i < 2; i++) {
1399 struct scatterlist *sg = &s->sg_rx[i];
1400
1401 sg_init_table(sg, 1);
1402 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1403 (int)buf[i] & ~PAGE_MASK);
f354a381 1404 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1405 }
1406
1407 INIT_WORK(&s->work_rx, work_fn_rx);
1408 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1409
1410 sci_submit_rx(s);
1411 }
1412}
1413
1414static void sci_free_dma(struct uart_port *port)
1415{
1416 struct sci_port *s = to_sci_port(port);
1417
ce6738b6 1418 if (!s->cfg->dma_dev)
73a19e4c
GL		 1419 return;
1420
1421 if (s->chan_tx)
1422 sci_tx_dma_release(s, false);
1423 if (s->chan_rx)
1424 sci_rx_dma_release(s, false);
1425}
27bd1075
PM		 1426#else
1427static inline void sci_request_dma(struct uart_port *port)
1428{
1429}
1430
1431static inline void sci_free_dma(struct uart_port *port)
1432{
1433}
73a19e4c
GL		 1434#endif
1435
1da177e4
LT		 1436static int sci_startup(struct uart_port *port)
1437{
a5660ada 1438 struct sci_port *s = to_sci_port(port);
1da177e4 1439
73a19e4c
GL		 1440 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1441
e108b2ca
PM		 1442 if (s->enable)
1443 s->enable(port);
1da177e4
LT		 1444
1445 sci_request_irq(s);
73a19e4c 1446 sci_request_dma(port);
d656901b 1447 sci_start_tx(port);
73a19e4c 1448 sci_start_rx(port);
1da177e4
LT		 1449
1450 return 0;
1451}
1452
1453static void sci_shutdown(struct uart_port *port)
1454{
a5660ada 1455 struct sci_port *s = to_sci_port(port);
1da177e4 1456
73a19e4c
GL		 1457 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1458
1da177e4 1459 sci_stop_rx(port);
b129a8cc 1460 sci_stop_tx(port);
73a19e4c 1461 sci_free_dma(port);
1da177e4
LT		 1462 sci_free_irq(s);
1463
e108b2ca
PM		 1464 if (s->disable)
1465 s->disable(port);
1da177e4
LT		 1466}
1467
26c92f37
PM		 1468static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1469 unsigned long freq)
1470{
1471 switch (algo_id) {
1472 case SCBRR_ALGO_1:
1473 return ((freq + 16 * bps) / (16 * bps) - 1);
1474 case SCBRR_ALGO_2:
1475 return ((freq + 16 * bps) / (32 * bps) - 1);
1476 case SCBRR_ALGO_3:
1477 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1478 case SCBRR_ALGO_4:
1479 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1480 case SCBRR_ALGO_5:
1481 return (((freq * 1000 / 32) / bps) - 1);
1482 }
1483
1484 /* Warn, but use a safe default */
1485 WARN_ON(1);
1486 return ((freq + 16 * bps) / (32 * bps) - 1);
1487}
1488
606d099c
AC		 1489static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1490 struct ktermios *old)
1da177e4 1491{
00b9de9c 1492 struct sci_port *s = to_sci_port(port);
154280fd 1493 unsigned int status, baud, smr_val, max_baud;
a2159b52 1494 int t = -1;
3089f381 1495 u16 scfcr = 0;
1da177e4 1496
154280fd
MD		 1497 /*
1498 * earlyprintk comes here early on with port->uartclk set to zero.
1499 * the clock framework is not up and running at this point so here
1500 * we assume that 115200 is the maximum baud rate. please note that
1501 * the baud rate is not programmed during earlyprintk - it is assumed
1502 * that the previous boot loader has enabled required clocks and
1503 * setup the baud rate generator hardware for us already.
1504 */
1505 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1506
154280fd
MD		 1507 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1508 if (likely(baud && port->uartclk))
ce6738b6 1509 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1510
1da177e4
LT		 1511 do {
1512 status = sci_in(port, SCxSR);
1513 } while (!(status & SCxSR_TEND(port)));
1514
1515 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1516
1a22f08d 1517 if (port->type != PORT_SCI)
3089f381 1518 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 1519
1520 smr_val = sci_in(port, SCSMR) & 3;
1521 if ((termios->c_cflag & CSIZE) == CS7)
1522 smr_val |= 0x40;
1523 if (termios->c_cflag & PARENB)
1524 smr_val |= 0x20;
1525 if (termios->c_cflag & PARODD)
1526 smr_val |= 0x30;
1527 if (termios->c_cflag & CSTOPB)
1528 smr_val |= 0x08;
1529
1530 uart_update_timeout(port, termios->c_cflag, baud);
1531
1532 sci_out(port, SCSMR, smr_val);
1533
73a19e4c 1534 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
ce6738b6 1535 s->cfg->scscr);
73a19e4c 1536
1da177e4 1537 if (t > 0) {
e7c98dc7 1538 if (t >= 256) {
1da177e4
LT		 1539 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1540 t >>= 2;
e7c98dc7 1541 } else
1da177e4 1542 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1543
1da177e4
LT		 1544 sci_out(port, SCBRR, t);
1545 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1546 }
1547
d5701647 1548 sci_init_pins(port, termios->c_cflag);
3089f381 1549 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
b7a76e4b 1550
ce6738b6 1551 sci_out(port, SCSCR, s->cfg->scscr);
1da177e4 1552
3089f381
GL		 1553#ifdef CONFIG_SERIAL_SH_SCI_DMA
1554 /*
1555 * Calculate delay for 1.5 DMA buffers: see
1556 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1557 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1558 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1559 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1560 * sizes), but it has been found out experimentally, that this is not
1561 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1562 * as a minimum seem to work perfectly.
1563 */
1564 if (s->chan_rx) {
1565 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1566 port->fifosize / 2;
1567 dev_dbg(port->dev,
1568 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1569 s->rx_timeout * 1000 / HZ, port->timeout);
1570 if (s->rx_timeout < msecs_to_jiffies(20))
1571 s->rx_timeout = msecs_to_jiffies(20);
1572 }
1573#endif
1574
1da177e4 1575 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1576 sci_start_rx(port);
1da177e4
LT		 1577}
1578
1579static const char *sci_type(struct uart_port *port)
1580{
1581 switch (port->type) {
e7c98dc7
MT		 1582 case PORT_IRDA:
1583 return "irda";
1584 case PORT_SCI:
1585 return "sci";
1586 case PORT_SCIF:
1587 return "scif";
1588 case PORT_SCIFA:
1589 return "scifa";
d1d4b10c
GL		 1590 case PORT_SCIFB:
1591 return "scifb";
1da177e4
LT		 1592 }
1593
fa43972f 1594 return NULL;
1da177e4
LT		 1595}
1596
1597static void sci_release_port(struct uart_port *port)
1598{
1599 /* Nothing here yet .. */
1600}
1601
1602static int sci_request_port(struct uart_port *port)
1603{
1604 /* Nothing here yet .. */
1605 return 0;
1606}
1607
1608static void sci_config_port(struct uart_port *port, int flags)
1609{
a5660ada 1610 struct sci_port *s = to_sci_port(port);
1da177e4 1611
ce6738b6 1612 port->type = s->cfg->type;
1da177e4 1613
08f8cb31 1614 if (port->flags & UPF_IOREMAP) {
7ff731ae 1615 port->membase = ioremap_nocache(port->mapbase, 0x40);
08f8cb31
MD		 1616
1617 if (IS_ERR(port->membase))
1618 dev_err(port->dev, "can't remap port#%d\n", port->line);
1619 } else {
1620 /*
1621 * For the simple (and majority of) cases where we don't
1622 * need to do any remapping, just cast the cookie
1623 * directly.
1624 */
1625 port->membase = (void __iomem *)port->mapbase;
7ff731ae 1626 }
1da177e4
LT		 1627}
1628
1629static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1630{
a5660ada 1631 struct sci_port *s = to_sci_port(port);
1da177e4 1632
ce6738b6 1633 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1634 return -EINVAL;
1635 if (ser->baud_base < 2400)
1636 /* No paper tape reader for Mitch.. */
1637 return -EINVAL;
1638
1639 return 0;
1640}
1641
1642static struct uart_ops sci_uart_ops = {
1643 .tx_empty = sci_tx_empty,
1644 .set_mctrl = sci_set_mctrl,
1645 .get_mctrl = sci_get_mctrl,
1646 .start_tx = sci_start_tx,
1647 .stop_tx = sci_stop_tx,
1648 .stop_rx = sci_stop_rx,
1649 .enable_ms = sci_enable_ms,
1650 .break_ctl = sci_break_ctl,
1651 .startup = sci_startup,
1652 .shutdown = sci_shutdown,
1653 .set_termios = sci_set_termios,
1654 .type = sci_type,
1655 .release_port = sci_release_port,
1656 .request_port = sci_request_port,
1657 .config_port = sci_config_port,
1658 .verify_port = sci_verify_port,
07d2a1a1
PM		 1659#ifdef CONFIG_CONSOLE_POLL
1660 .poll_get_char = sci_poll_get_char,
1661 .poll_put_char = sci_poll_put_char,
1662#endif
1da177e4
LT		 1663};
1664
c7ed1ab3
PM		 1665static int __devinit sci_init_single(struct platform_device *dev,
1666 struct sci_port *sci_port,
1667 unsigned int index,
1668 struct plat_sci_port *p)
e108b2ca 1669{
73a19e4c 1670 struct uart_port *port = &sci_port->port;
e108b2ca 1671
73a19e4c
GL		 1672 port->ops = &sci_uart_ops;
1673 port->iotype = UPIO_MEM;
1674 port->line = index;
75136d48
MP		 1675
1676 switch (p->type) {
d1d4b10c
GL		 1677 case PORT_SCIFB:
1678 port->fifosize = 256;
1679 break;
75136d48 1680 case PORT_SCIFA:
73a19e4c 1681 port->fifosize = 64;
75136d48
MP		 1682 break;
1683 case PORT_SCIF:
73a19e4c 1684 port->fifosize = 16;
75136d48
MP		 1685 break;
1686 default:
73a19e4c 1687 port->fifosize = 1;
75136d48
MP		 1688 break;
1689 }
7b6fd3bf
MD		 1690
1691 if (dev) {
c7ed1ab3
PM		 1692 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1693 if (IS_ERR(sci_port->iclk)) {
1694 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1695 if (IS_ERR(sci_port->iclk)) {
1696 dev_err(&dev->dev, "can't get iclk\n");
1697 return PTR_ERR(sci_port->iclk);
1698 }
1699 }
1700
1701 /*
1702 * The function clock is optional, ignore it if we can't
1703 * find it.
1704 */
1705 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1706 if (IS_ERR(sci_port->fclk))
1707 sci_port->fclk = NULL;
1708
7b6fd3bf
MD		 1709 sci_port->enable = sci_clk_enable;
1710 sci_port->disable = sci_clk_disable;
73a19e4c 1711 port->dev = &dev->dev;
7b6fd3bf 1712 }
e108b2ca 1713
7ed7e071
MD		 1714 sci_port->break_timer.data = (unsigned long)sci_port;
1715 sci_port->break_timer.function = sci_break_timer;
1716 init_timer(&sci_port->break_timer);
1717
ce6738b6 1718 sci_port->cfg = p;
7ed7e071 1719
ce6738b6
PM		 1720 port->mapbase = p->mapbase;
1721 port->type = p->type;
f43dc23d 1722 port->flags = p->flags;
73a19e4c 1723
ce6738b6
PM		 1724 /*
1725 * The UART port needs an IRQ value, so we peg this to the TX IRQ
1726 * for the multi-IRQ ports, which is where we are primarily
1727 * concerned with the shutdown path synchronization.
1728 *
1729 * For the muxed case there's nothing more to do.
1730 */
1731 port->irq = p->irqs[SCIx_TXI_IRQ];
73a19e4c 1732
ce6738b6
PM		 1733 if (p->dma_dev)
1734 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
1735 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 1736
c7ed1ab3 1737 return 0;
e108b2ca
PM		 1738}
1739
1da177e4 1740#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 1741static struct tty_driver *serial_console_device(struct console *co, int *index)
1742{
1743 struct uart_driver *p = &sci_uart_driver;
1744 *index = co->index;
1745 return p->tty_driver;
1746}
1747
1748static void serial_console_putchar(struct uart_port *port, int ch)
1749{
1750 sci_poll_put_char(port, ch);
1751}
1752
1da177e4
LT		 1753/*
1754 * Print a string to the serial port trying not to disturb
1755 * any possible real use of the port...
1756 */
1757static void serial_console_write(struct console *co, const char *s,
1758 unsigned count)
1759{
dc8e6f5b 1760 struct uart_port *port = co->data;
501b825d 1761 struct sci_port *sci_port = to_sci_port(port);
973e5d52 1762 unsigned short bits;
07d2a1a1 1763
501b825d
MD		 1764 if (sci_port->enable)
1765 sci_port->enable(port);
1766
1767 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 1768
1769 /* wait until fifo is empty and last bit has been transmitted */
1770 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1771 while ((sci_in(port, SCxSR) & bits) != bits)
1772 cpu_relax();
501b825d 1773
345e5a76 1774 if (sci_port->disable)
501b825d 1775 sci_port->disable(port);
1da177e4
LT		 1776}
1777
7b6fd3bf 1778static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 1779{
dc8e6f5b 1780 struct sci_port *sci_port;
1da177e4
LT		 1781 struct uart_port *port;
1782 int baud = 115200;
1783 int bits = 8;
1784 int parity = 'n';
1785 int flow = 'n';
1786 int ret;
1787
e108b2ca
PM		 1788 /*
1789 * Check whether an invalid uart number has been specified, and
1790 * if so, search for the first available port that does have
1791 * console support.
1792 */
1793 if (co->index >= SCI_NPORTS)
1794 co->index = 0;
1795
7b6fd3bf
MD		 1796 if (co->data) {
1797 port = co->data;
1798 sci_port = to_sci_port(port);
1799 } else {
1800 sci_port = &sci_ports[co->index];
1801 port = &sci_port->port;
1802 co->data = port;
1803 }
1da177e4
LT		 1804
1805 /*
e108b2ca
PM		 1806 * Also need to check port->type, we don't actually have any
1807 * UPIO_PORT ports, but uart_report_port() handily misreports
1808 * it anyways if we don't have a port available by the time this is
1809 * called.
1da177e4 1810 */
e108b2ca
PM		 1811 if (!port->type)
1812 return -ENODEV;
e108b2ca 1813
08f8cb31 1814 sci_config_port(port, 0);
e108b2ca 1815
dc8e6f5b
MD		 1816 if (sci_port->enable)
1817 sci_port->enable(port);
b7a76e4b 1818
1da177e4
LT		 1819 if (options)
1820 uart_parse_options(options, &baud, &parity, &bits, &flow);
1821
1822 ret = uart_set_options(port, co, baud, parity, bits, flow);
1823#if defined(__H8300H__) || defined(__H8300S__)
1824 /* disable rx interrupt */
1825 if (ret == 0)
1826 sci_stop_rx(port);
1827#endif
501b825d 1828 /* TODO: disable clock */
1da177e4
LT		 1829 return ret;
1830}
1831
1832static struct console serial_console = {
1833 .name = "ttySC",
dc8e6f5b 1834 .device = serial_console_device,
1da177e4
LT		 1835 .write = serial_console_write,
1836 .setup = serial_console_setup,
fa5da2f7 1837 .flags = CON_PRINTBUFFER,
1da177e4 1838 .index = -1,
1da177e4
LT		 1839};
1840
1841static int __init sci_console_init(void)
1842{
1843 register_console(&serial_console);
1844 return 0;
1845}
1da177e4 1846console_initcall(sci_console_init);
7b6fd3bf
MD		 1847
1848static struct sci_port early_serial_port;
1849static struct console early_serial_console = {
1850 .name = "early_ttySC",
1851 .write = serial_console_write,
1852 .flags = CON_PRINTBUFFER,
1853};
1854static char early_serial_buf[32];
1855
1da177e4
LT		 1856#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1857
07d2a1a1 1858#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
e7c98dc7 1859#define SCI_CONSOLE (&serial_console)
1da177e4 1860#else
b7a76e4b 1861#define SCI_CONSOLE 0
1da177e4
LT		 1862#endif
1863
1864static char banner[] __initdata =
1865 KERN_INFO "SuperH SCI(F) driver initialized\n";
1866
1867static struct uart_driver sci_uart_driver = {
1868 .owner = THIS_MODULE,
1869 .driver_name = "sci",
1da177e4
LT		 1870 .dev_name = "ttySC",
1871 .major = SCI_MAJOR,
1872 .minor = SCI_MINOR_START,
e108b2ca 1873 .nr = SCI_NPORTS,
1da177e4
LT		 1874 .cons = SCI_CONSOLE,
1875};
1876
e552de24 1877
54507f6e 1878static int sci_remove(struct platform_device *dev)
e552de24
MD		 1879{
1880 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1881 struct sci_port *p;
1882 unsigned long flags;
1883
e552de24 1884 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
e552de24
MD		 1885
1886 spin_lock_irqsave(&priv->lock, flags);
c7ed1ab3 1887 list_for_each_entry(p, &priv->ports, node) {
e552de24 1888 uart_remove_one_port(&sci_uart_driver, &p->port);
c7ed1ab3
PM		 1889 clk_put(p->iclk);
1890 clk_put(p->fclk);
1891 }
e552de24
MD		 1892 spin_unlock_irqrestore(&priv->lock, flags);
1893
1894 kfree(priv);
1895 return 0;
1896}
1897
0ee70712
MD		 1898static int __devinit sci_probe_single(struct platform_device *dev,
1899 unsigned int index,
1900 struct plat_sci_port *p,
1901 struct sci_port *sciport)
1902{
1903 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1904 unsigned long flags;
1905 int ret;
1906
1907 /* Sanity check */
1908 if (unlikely(index >= SCI_NPORTS)) {
1909 dev_notice(&dev->dev, "Attempting to register port "
1910 "%d when only %d are available.\n",
1911 index+1, SCI_NPORTS);
1912 dev_notice(&dev->dev, "Consider bumping "
1913 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1914 return 0;
1915 }
1916
c7ed1ab3
PM		 1917 ret = sci_init_single(dev, sciport, index, p);
1918 if (ret)
1919 return ret;
0ee70712
MD		 1920
1921 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
08f8cb31 1922 if (ret)
0ee70712 1923 return ret;
0ee70712
MD		 1924
1925 INIT_LIST_HEAD(&sciport->node);
1926
1927 spin_lock_irqsave(&priv->lock, flags);
1928 list_add(&sciport->node, &priv->ports);
1929 spin_unlock_irqrestore(&priv->lock, flags);
1930
1931 return 0;
1932}
1933
e108b2ca
PM		 1934/*
1935 * Register a set of serial devices attached to a platform device. The
1936 * list is terminated with a zero flags entry, which means we expect
1937 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1938 * remapping (such as sh64) should also set UPF_IOREMAP.
1939 */
1940static int __devinit sci_probe(struct platform_device *dev)
1da177e4 1941{
e108b2ca 1942 struct plat_sci_port *p = dev->dev.platform_data;
e552de24 1943 struct sh_sci_priv *priv;
7ff731ae 1944 int i, ret = -EINVAL;
e552de24 1945
7b6fd3bf
MD		 1946#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1947 if (is_early_platform_device(dev)) {
1948 if (dev->id == -1)
1949 return -ENOTSUPP;
1950 early_serial_console.index = dev->id;
1951 early_serial_console.data = &early_serial_port.port;
1952 sci_init_single(NULL, &early_serial_port, dev->id, p);
1953 serial_console_setup(&early_serial_console, early_serial_buf);
1954 if (!strstr(early_serial_buf, "keep"))
1955 early_serial_console.flags |= CON_BOOT;
1956 register_console(&early_serial_console);
1957 return 0;
1958 }
1959#endif
1960
e552de24
MD		 1961 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1962 if (!priv)
1963 return -ENOMEM;
1964
1965 INIT_LIST_HEAD(&priv->ports);
1966 spin_lock_init(&priv->lock);
1967 platform_set_drvdata(dev, priv);
1968
e552de24
MD		 1969 priv->clk_nb.notifier_call = sci_notifier;
1970 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1da177e4 1971
0ee70712
MD		 1972 if (dev->id != -1) {
1973 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1974 if (ret)
e552de24 1975 goto err_unreg;
0ee70712
MD		 1976 } else {
1977 for (i = 0; p && p->flags != 0; p++, i++) {
1978 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1979 if (ret)
1980 goto err_unreg;
e552de24 1981 }
e552de24 1982 }
1da177e4
LT		 1983
1984#ifdef CONFIG_SH_STANDARD_BIOS
1985 sh_bios_gdb_detach();
1986#endif
1987
e108b2ca 1988 return 0;
7ff731ae
PM		 1989
1990err_unreg:
e552de24 1991 sci_remove(dev);
7ff731ae 1992 return ret;
1da177e4
LT		 1993}
1994
6daa79b3 1995static int sci_suspend(struct device *dev)
1da177e4 1996{
6daa79b3 1997 struct sh_sci_priv *priv = dev_get_drvdata(dev);
e552de24
MD		 1998 struct sci_port *p;
1999 unsigned long flags;
e108b2ca 2000
e552de24
MD		 2001 spin_lock_irqsave(&priv->lock, flags);
2002 list_for_each_entry(p, &priv->ports, node)
2003 uart_suspend_port(&sci_uart_driver, &p->port);
e552de24 2004 spin_unlock_irqrestore(&priv->lock, flags);
1da177e4 2005
e108b2ca
PM		 2006 return 0;
2007}
1da177e4 2008
6daa79b3 2009static int sci_resume(struct device *dev)
e108b2ca 2010{
6daa79b3 2011 struct sh_sci_priv *priv = dev_get_drvdata(dev);
e552de24
MD		 2012 struct sci_port *p;
2013 unsigned long flags;
e108b2ca 2014
e552de24
MD		 2015 spin_lock_irqsave(&priv->lock, flags);
2016 list_for_each_entry(p, &priv->ports, node)
2017 uart_resume_port(&sci_uart_driver, &p->port);
e552de24 2018 spin_unlock_irqrestore(&priv->lock, flags);
e108b2ca
PM		 2019
2020 return 0;
2021}
2022
47145210 2023static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2024 .suspend = sci_suspend,
2025 .resume = sci_resume,
2026};
2027
e108b2ca
PM		 2028static struct platform_driver sci_driver = {
2029 .probe = sci_probe,
b9e39c89 2030 .remove = sci_remove,
e108b2ca
PM		 2031 .driver = {
2032 .name = "sh-sci",
2033 .owner = THIS_MODULE,
6daa79b3 2034 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2035 },
2036};
2037
2038static int __init sci_init(void)
2039{
2040 int ret;
2041
2042 printk(banner);
2043
e108b2ca
PM		 2044 ret = uart_register_driver(&sci_uart_driver);
2045 if (likely(ret == 0)) {
2046 ret = platform_driver_register(&sci_driver);
2047 if (unlikely(ret))
2048 uart_unregister_driver(&sci_uart_driver);
2049 }
2050
2051 return ret;
2052}
2053
2054static void __exit sci_exit(void)
2055{
2056 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2057 uart_unregister_driver(&sci_uart_driver);
2058}
2059
7b6fd3bf
MD		 2060#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2061early_platform_init_buffer("earlyprintk", &sci_driver,
2062 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2063#endif
1da177e4
LT		 2064module_init(sci_init);
2065module_exit(sci_exit);
2066
e108b2ca 2067MODULE_LICENSE("GPL");
e169c139 2068MODULE_ALIAS("platform:sh-sci");
Linux kernel - Deliverables
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