Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/serial/sh-sci.c | |
3 | * | |
4 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
5 | * | |
7ff731ae | 6 | * Copyright (C) 2002 - 2008 Paul Mundt |
3ea6bc3d | 7 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
8 | * |
9 | * based off of the old drivers/char/sh-sci.c by: | |
10 | * | |
11 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
12 | * Copyright (C) 2000 Sugioka Toshinobu | |
13 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
14 | * Modified to support SecureEdge. David McCullough (2002) | |
15 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 16 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
17 | * |
18 | * This file is subject to the terms and conditions of the GNU General Public | |
19 | * License. See the file "COPYING" in the main directory of this archive | |
20 | * for more details. | |
21 | */ | |
0b3d4ef6 PM |
22 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
23 | #define SUPPORT_SYSRQ | |
24 | #endif | |
1da177e4 LT |
25 | |
26 | #undef DEBUG | |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/errno.h> | |
1da177e4 LT |
30 | #include <linux/timer.h> |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/tty_flip.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/major.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/sysrq.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/mm.h> | |
1da177e4 LT |
40 | #include <linux/init.h> |
41 | #include <linux/delay.h> | |
42 | #include <linux/console.h> | |
e108b2ca | 43 | #include <linux/platform_device.h> |
96de1a8f | 44 | #include <linux/serial_sci.h> |
1da177e4 LT |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpufreq.h> | |
85f094ec | 47 | #include <linux/clk.h> |
fa5da2f7 | 48 | #include <linux/ctype.h> |
7ff731ae | 49 | #include <linux/err.h> |
85f094ec PM |
50 | |
51 | #ifdef CONFIG_SUPERH | |
b7a76e4b | 52 | #include <asm/clock.h> |
1da177e4 | 53 | #include <asm/sh_bios.h> |
e108b2ca | 54 | #include <asm/kgdb.h> |
1da177e4 LT |
55 | #endif |
56 | ||
1da177e4 LT |
57 | #include "sh-sci.h" |
58 | ||
e108b2ca PM |
59 | struct sci_port { |
60 | struct uart_port port; | |
61 | ||
62 | /* Port type */ | |
63 | unsigned int type; | |
64 | ||
65 | /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ | |
32351a28 | 66 | unsigned int irqs[SCIx_NR_IRQS]; |
e108b2ca PM |
67 | |
68 | /* Port pin configuration */ | |
69 | void (*init_pins)(struct uart_port *port, | |
70 | unsigned int cflag); | |
1da177e4 | 71 | |
e108b2ca PM |
72 | /* Port enable callback */ |
73 | void (*enable)(struct uart_port *port); | |
74 | ||
75 | /* Port disable callback */ | |
76 | void (*disable)(struct uart_port *port); | |
77 | ||
78 | /* Break timer */ | |
79 | struct timer_list break_timer; | |
80 | int break_flag; | |
1534a3b3 | 81 | |
a2159b52 | 82 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 83 | /* Port clock */ |
84 | struct clk *clk; | |
005a336e | 85 | #endif |
e108b2ca PM |
86 | }; |
87 | ||
88 | #ifdef CONFIG_SH_KGDB | |
1da177e4 | 89 | static struct sci_port *kgdb_sci_port; |
e108b2ca | 90 | #endif |
1da177e4 LT |
91 | |
92 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE | |
e108b2ca PM |
93 | static struct sci_port *serial_console_port; |
94 | #endif | |
1da177e4 LT |
95 | |
96 | /* Function prototypes */ | |
b129a8cc | 97 | static void sci_stop_tx(struct uart_port *port); |
1da177e4 | 98 | |
e108b2ca | 99 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 100 | |
e108b2ca PM |
101 | static struct sci_port sci_ports[SCI_NPORTS]; |
102 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 103 | |
e7c98dc7 MT |
104 | static inline struct sci_port * |
105 | to_sci_port(struct uart_port *uart) | |
106 | { | |
107 | return container_of(uart, struct sci_port, port); | |
108 | } | |
109 | ||
e108b2ca PM |
110 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \ |
111 | defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) | |
112 | static inline void handle_error(struct uart_port *port) | |
113 | { | |
114 | /* Clear error flags */ | |
1da177e4 LT |
115 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
116 | } | |
117 | ||
118 | static int get_char(struct uart_port *port) | |
119 | { | |
120 | unsigned long flags; | |
121 | unsigned short status; | |
122 | int c; | |
123 | ||
e108b2ca PM |
124 | spin_lock_irqsave(&port->lock, flags); |
125 | do { | |
1da177e4 LT |
126 | status = sci_in(port, SCxSR); |
127 | if (status & SCxSR_ERRORS(port)) { | |
128 | handle_error(port); | |
129 | continue; | |
130 | } | |
131 | } while (!(status & SCxSR_RDxF(port))); | |
132 | c = sci_in(port, SCxRDR); | |
e7c98dc7 MT |
133 | /* Dummy read */ |
134 | sci_in(port, SCxSR); | |
1da177e4 | 135 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); |
e108b2ca | 136 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
137 | |
138 | return c; | |
139 | } | |
1da177e4 LT |
140 | #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ |
141 | ||
e108b2ca | 142 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB) |
1da177e4 LT |
143 | static void put_char(struct uart_port *port, char c) |
144 | { | |
145 | unsigned long flags; | |
146 | unsigned short status; | |
147 | ||
e108b2ca | 148 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
149 | |
150 | do { | |
151 | status = sci_in(port, SCxSR); | |
152 | } while (!(status & SCxSR_TDxE(port))); | |
153 | ||
1da177e4 LT |
154 | sci_in(port, SCxSR); /* Dummy read */ |
155 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
272966c0 | 156 | sci_out(port, SCxTDR, c); |
1da177e4 | 157 | |
e108b2ca | 158 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 | 159 | } |
e108b2ca | 160 | #endif |
1da177e4 | 161 | |
e108b2ca | 162 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
1da177e4 LT |
163 | static void put_string(struct sci_port *sci_port, const char *buffer, int count) |
164 | { | |
165 | struct uart_port *port = &sci_port->port; | |
166 | const unsigned char *p = buffer; | |
167 | int i; | |
168 | ||
169 | #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) | |
170 | int checksum; | |
e7c98dc7 | 171 | int usegdb = 0; |
1da177e4 LT |
172 | |
173 | #ifdef CONFIG_SH_STANDARD_BIOS | |
b7a76e4b | 174 | /* This call only does a trap the first time it is |
1da177e4 LT |
175 | * called, and so is safe to do here unconditionally |
176 | */ | |
177 | usegdb |= sh_bios_in_gdb_mode(); | |
178 | #endif | |
179 | #ifdef CONFIG_SH_KGDB | |
fa5da2f7 | 180 | usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port)); |
1da177e4 LT |
181 | #endif |
182 | ||
183 | if (usegdb) { | |
184 | /* $<packet info>#<checksum>. */ | |
185 | do { | |
186 | unsigned char c; | |
187 | put_char(port, '$'); | |
188 | put_char(port, 'O'); /* 'O'utput to console */ | |
189 | checksum = 'O'; | |
190 | ||
e7c98dc7 MT |
191 | /* Don't use run length encoding */ |
192 | for (i = 0; i < count; i++) { | |
1da177e4 LT |
193 | int h, l; |
194 | ||
195 | c = *p++; | |
bfd3c7a7 HH |
196 | h = hex_asc_hi(c); |
197 | l = hex_asc_lo(c); | |
1da177e4 LT |
198 | put_char(port, h); |
199 | put_char(port, l); | |
200 | checksum += h + l; | |
201 | } | |
202 | put_char(port, '#'); | |
bfd3c7a7 HH |
203 | put_char(port, hex_asc_hi(checksum)); |
204 | put_char(port, hex_asc_lo(checksum)); | |
1da177e4 LT |
205 | } while (get_char(port) != '+'); |
206 | } else | |
207 | #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ | |
e7c98dc7 | 208 | for (i = 0; i < count; i++) { |
1da177e4 LT |
209 | if (*p == 10) |
210 | put_char(port, '\r'); | |
211 | put_char(port, *p++); | |
212 | } | |
213 | } | |
214 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
215 | ||
1da177e4 | 216 | #ifdef CONFIG_SH_KGDB |
1da177e4 LT |
217 | static int kgdb_sci_getchar(void) |
218 | { | |
e7c98dc7 | 219 | int c; |
1da177e4 | 220 | |
e7c98dc7 MT |
221 | /* Keep trying to read a character, this could be neater */ |
222 | while ((c = get_char(&kgdb_sci_port->port)) < 0) | |
e108b2ca | 223 | cpu_relax(); |
1da177e4 | 224 | |
e7c98dc7 | 225 | return c; |
1da177e4 LT |
226 | } |
227 | ||
e108b2ca | 228 | static inline void kgdb_sci_putchar(int c) |
1da177e4 | 229 | { |
e7c98dc7 | 230 | put_char(&kgdb_sci_port->port, c); |
1da177e4 | 231 | } |
1da177e4 LT |
232 | #endif /* CONFIG_SH_KGDB */ |
233 | ||
234 | #if defined(__H8300S__) | |
235 | enum { sci_disable, sci_enable }; | |
236 | ||
e7c98dc7 | 237 | static void h8300_sci_config(struct uart_port *port, unsigned int ctrl) |
1da177e4 | 238 | { |
e7c98dc7 | 239 | volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL; |
1da177e4 LT |
240 | int ch = (port->mapbase - SMR0) >> 3; |
241 | unsigned char mask = 1 << (ch+1); | |
242 | ||
e7c98dc7 | 243 | if (ctrl == sci_disable) |
1da177e4 | 244 | *mstpcrl |= mask; |
e7c98dc7 | 245 | else |
1da177e4 | 246 | *mstpcrl &= ~mask; |
1da177e4 | 247 | } |
e108b2ca PM |
248 | |
249 | static inline void h8300_sci_enable(struct uart_port *port) | |
250 | { | |
251 | h8300_sci_config(port, sci_enable); | |
252 | } | |
253 | ||
254 | static inline void h8300_sci_disable(struct uart_port *port) | |
255 | { | |
256 | h8300_sci_config(port, sci_disable); | |
257 | } | |
1da177e4 LT |
258 | #endif |
259 | ||
15c73aaa | 260 | #if defined(__H8300H__) || defined(__H8300S__) |
e7c98dc7 | 261 | static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag) |
1da177e4 LT |
262 | { |
263 | int ch = (port->mapbase - SMR0) >> 3; | |
264 | ||
265 | /* set DDR regs */ | |
e108b2ca PM |
266 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, |
267 | h8300_sci_pins[ch].rx, | |
268 | H8300_GPIO_INPUT); | |
269 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, | |
270 | h8300_sci_pins[ch].tx, | |
271 | H8300_GPIO_OUTPUT); | |
272 | ||
1da177e4 LT |
273 | /* tx mark output*/ |
274 | H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; | |
275 | } | |
e108b2ca PM |
276 | #else |
277 | #define sci_init_pins_sci NULL | |
278 | #endif | |
279 | ||
280 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) | |
281 | static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag) | |
282 | { | |
283 | unsigned int fcr_val = 0; | |
284 | ||
285 | if (cflag & CRTSCTS) | |
286 | fcr_val |= SCFCR_MCE; | |
287 | ||
288 | sci_out(port, SCFCR, fcr_val); | |
289 | } | |
290 | #else | |
291 | #define sci_init_pins_irda NULL | |
1da177e4 | 292 | #endif |
e108b2ca | 293 | |
d89ddd1c | 294 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
e7c98dc7 | 295 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) |
9465a54f NI |
296 | { |
297 | unsigned int fcr_val = 0; | |
298 | ||
299 | set_sh771x_scif_pfc(port); | |
e7c98dc7 | 300 | if (cflag & CRTSCTS) |
9465a54f | 301 | fcr_val |= SCFCR_MCE; |
9465a54f NI |
302 | sci_out(port, SCFCR, fcr_val); |
303 | } | |
31a49c4b | 304 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) |
3ea6bc3d MB |
305 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) |
306 | { | |
307 | unsigned int fcr_val = 0; | |
308 | unsigned short data; | |
309 | ||
310 | if (cflag & CRTSCTS) { | |
311 | /* enable RTS/CTS */ | |
312 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
313 | /* Clear PTCR bit 9-2; enable all scif pins but sck */ | |
314 | data = ctrl_inw(PORT_PTCR); | |
315 | ctrl_outw((data & 0xfc03), PORT_PTCR); | |
316 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ | |
317 | /* Clear PVCR bit 9-2 */ | |
318 | data = ctrl_inw(PORT_PVCR); | |
319 | ctrl_outw((data & 0xfc03), PORT_PVCR); | |
320 | } | |
321 | fcr_val |= SCFCR_MCE; | |
322 | } else { | |
323 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
324 | /* Clear PTCR bit 5-2; enable only tx and rx */ | |
325 | data = ctrl_inw(PORT_PTCR); | |
326 | ctrl_outw((data & 0xffc3), PORT_PTCR); | |
327 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ | |
328 | /* Clear PVCR bit 5-2 */ | |
329 | data = ctrl_inw(PORT_PVCR); | |
330 | ctrl_outw((data & 0xffc3), PORT_PVCR); | |
331 | } | |
332 | } | |
333 | sci_out(port, SCFCR, fcr_val); | |
334 | } | |
b7a76e4b | 335 | #elif defined(CONFIG_CPU_SH3) |
e108b2ca | 336 | /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ |
1da177e4 LT |
337 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) |
338 | { | |
339 | unsigned int fcr_val = 0; | |
b7a76e4b PM |
340 | unsigned short data; |
341 | ||
342 | /* We need to set SCPCR to enable RTS/CTS */ | |
343 | data = ctrl_inw(SCPCR); | |
344 | /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ | |
345 | ctrl_outw(data & 0x0fcf, SCPCR); | |
1da177e4 | 346 | |
1da177e4 LT |
347 | if (cflag & CRTSCTS) |
348 | fcr_val |= SCFCR_MCE; | |
349 | else { | |
1da177e4 LT |
350 | /* We need to set SCPCR to enable RTS/CTS */ |
351 | data = ctrl_inw(SCPCR); | |
352 | /* Clear out SCP7MD1,0, SCP4MD1,0, | |
353 | Set SCP6MD1,0 = {01} (output) */ | |
b7a76e4b | 354 | ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR); |
1da177e4 LT |
355 | |
356 | data = ctrl_inb(SCPDR); | |
357 | /* Set /RTS2 (bit6) = 0 */ | |
b7a76e4b | 358 | ctrl_outb(data & 0xbf, SCPDR); |
1da177e4 | 359 | } |
b7a76e4b | 360 | |
1da177e4 LT |
361 | sci_out(port, SCFCR, fcr_val); |
362 | } | |
41504c39 PM |
363 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
364 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) | |
365 | { | |
366 | unsigned int fcr_val = 0; | |
346b7463 | 367 | unsigned short data; |
41504c39 | 368 | |
346b7463 MD |
369 | if (port->mapbase == 0xffe00000) { |
370 | data = ctrl_inw(PSCR); | |
371 | data &= ~0x03cf; | |
372 | if (cflag & CRTSCTS) | |
373 | fcr_val |= SCFCR_MCE; | |
374 | else | |
375 | data |= 0x0340; | |
41504c39 | 376 | |
346b7463 | 377 | ctrl_outw(data, PSCR); |
41504c39 | 378 | } |
346b7463 | 379 | /* SCIF1 and SCIF2 should be setup by board code */ |
41504c39 PM |
380 | |
381 | sci_out(port, SCFCR, fcr_val); | |
382 | } | |
178dd0cd PM |
383 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
384 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) | |
385 | { | |
386 | /* Nothing to do here.. */ | |
387 | sci_out(port, SCFCR, 0); | |
388 | } | |
1da177e4 | 389 | #else |
1da177e4 LT |
390 | /* For SH7750 */ |
391 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) | |
392 | { | |
393 | unsigned int fcr_val = 0; | |
394 | ||
395 | if (cflag & CRTSCTS) { | |
396 | fcr_val |= SCFCR_MCE; | |
397 | } else { | |
9109a30e | 398 | #if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366) |
e108b2ca | 399 | /* Nothing */ |
7d740a06 YS |
400 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
401 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
2b1bd1ac PM |
402 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
403 | defined(CONFIG_CPU_SUBTYPE_SHX3) | |
b7a76e4b PM |
404 | ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ |
405 | #else | |
1da177e4 | 406 | ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ |
b7a76e4b | 407 | #endif |
1da177e4 LT |
408 | } |
409 | sci_out(port, SCFCR, fcr_val); | |
410 | } | |
e108b2ca PM |
411 | #endif |
412 | ||
32351a28 PM |
413 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
414 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
415 | defined(CONFIG_CPU_SUBTYPE_SH7785) | |
e108b2ca PM |
416 | static inline int scif_txroom(struct uart_port *port) |
417 | { | |
cae167d3 | 418 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e108b2ca PM |
419 | } |
420 | ||
421 | static inline int scif_rxroom(struct uart_port *port) | |
422 | { | |
cae167d3 | 423 | return sci_in(port, SCRFDR) & 0xff; |
e108b2ca | 424 | } |
c63847a3 NI |
425 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
426 | static inline int scif_txroom(struct uart_port *port) | |
427 | { | |
e7c98dc7 MT |
428 | if ((port->mapbase == 0xffe00000) || |
429 | (port->mapbase == 0xffe08000)) { | |
430 | /* SCIF0/1*/ | |
c63847a3 | 431 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e7c98dc7 MT |
432 | } else { |
433 | /* SCIF2 */ | |
c63847a3 | 434 | return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); |
e7c98dc7 | 435 | } |
c63847a3 NI |
436 | } |
437 | ||
438 | static inline int scif_rxroom(struct uart_port *port) | |
439 | { | |
e7c98dc7 MT |
440 | if ((port->mapbase == 0xffe00000) || |
441 | (port->mapbase == 0xffe08000)) { | |
442 | /* SCIF0/1*/ | |
c63847a3 | 443 | return sci_in(port, SCRFDR) & 0xff; |
e7c98dc7 MT |
444 | } else { |
445 | /* SCIF2 */ | |
c63847a3 | 446 | return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; |
e7c98dc7 | 447 | } |
c63847a3 | 448 | } |
e108b2ca PM |
449 | #else |
450 | static inline int scif_txroom(struct uart_port *port) | |
451 | { | |
452 | return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); | |
453 | } | |
1da177e4 | 454 | |
e108b2ca PM |
455 | static inline int scif_rxroom(struct uart_port *port) |
456 | { | |
457 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
458 | } | |
1da177e4 | 459 | #endif |
1da177e4 | 460 | |
e108b2ca PM |
461 | static inline int sci_txroom(struct uart_port *port) |
462 | { | |
e7c98dc7 | 463 | return (sci_in(port, SCxSR) & SCI_TDRE) != 0; |
e108b2ca PM |
464 | } |
465 | ||
466 | static inline int sci_rxroom(struct uart_port *port) | |
467 | { | |
e7c98dc7 | 468 | return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
469 | } |
470 | ||
1da177e4 LT |
471 | /* ********************************************************************** * |
472 | * the interrupt related routines * | |
473 | * ********************************************************************** */ | |
474 | ||
475 | static void sci_transmit_chars(struct uart_port *port) | |
476 | { | |
477 | struct circ_buf *xmit = &port->info->xmit; | |
478 | unsigned int stopped = uart_tx_stopped(port); | |
1da177e4 LT |
479 | unsigned short status; |
480 | unsigned short ctrl; | |
e108b2ca | 481 | int count; |
1da177e4 LT |
482 | |
483 | status = sci_in(port, SCxSR); | |
484 | if (!(status & SCxSR_TDxE(port))) { | |
1da177e4 | 485 | ctrl = sci_in(port, SCSCR); |
e7c98dc7 | 486 | if (uart_circ_empty(xmit)) |
1da177e4 | 487 | ctrl &= ~SCI_CTRL_FLAGS_TIE; |
e7c98dc7 | 488 | else |
1da177e4 | 489 | ctrl |= SCI_CTRL_FLAGS_TIE; |
1da177e4 | 490 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
491 | return; |
492 | } | |
493 | ||
1a22f08d | 494 | if (port->type == PORT_SCI) |
e108b2ca | 495 | count = sci_txroom(port); |
1a22f08d YS |
496 | else |
497 | count = scif_txroom(port); | |
1da177e4 LT |
498 | |
499 | do { | |
500 | unsigned char c; | |
501 | ||
502 | if (port->x_char) { | |
503 | c = port->x_char; | |
504 | port->x_char = 0; | |
505 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
506 | c = xmit->buf[xmit->tail]; | |
507 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
508 | } else { | |
509 | break; | |
510 | } | |
511 | ||
512 | sci_out(port, SCxTDR, c); | |
513 | ||
514 | port->icount.tx++; | |
515 | } while (--count > 0); | |
516 | ||
517 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
518 | ||
519 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
520 | uart_write_wakeup(port); | |
521 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 522 | sci_stop_tx(port); |
1da177e4 | 523 | } else { |
1da177e4 LT |
524 | ctrl = sci_in(port, SCSCR); |
525 | ||
1a22f08d | 526 | if (port->type != PORT_SCI) { |
1da177e4 LT |
527 | sci_in(port, SCxSR); /* Dummy read */ |
528 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
529 | } | |
1da177e4 LT |
530 | |
531 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
532 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
533 | } |
534 | } | |
535 | ||
536 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 537 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 538 | |
7d12e780 | 539 | static inline void sci_receive_chars(struct uart_port *port) |
1da177e4 | 540 | { |
e7c98dc7 | 541 | struct sci_port *sci_port = to_sci_port(port); |
a88487c7 | 542 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
543 | int i, count, copied = 0; |
544 | unsigned short status; | |
33f0f88f | 545 | unsigned char flag; |
1da177e4 LT |
546 | |
547 | status = sci_in(port, SCxSR); | |
548 | if (!(status & SCxSR_RDxF(port))) | |
549 | return; | |
550 | ||
551 | while (1) { | |
1a22f08d | 552 | if (port->type == PORT_SCI) |
e108b2ca | 553 | count = sci_rxroom(port); |
1a22f08d YS |
554 | else |
555 | count = scif_rxroom(port); | |
1da177e4 LT |
556 | |
557 | /* Don't copy more bytes than there is room for in the buffer */ | |
33f0f88f | 558 | count = tty_buffer_request_room(tty, count); |
1da177e4 LT |
559 | |
560 | /* If for any reason we can't copy more data, we're done! */ | |
561 | if (count == 0) | |
562 | break; | |
563 | ||
564 | if (port->type == PORT_SCI) { | |
565 | char c = sci_in(port, SCxRDR); | |
e7c98dc7 MT |
566 | if (uart_handle_sysrq_char(port, c) || |
567 | sci_port->break_flag) | |
1da177e4 | 568 | count = 0; |
e7c98dc7 | 569 | else |
e108b2ca | 570 | tty_insert_flip_char(tty, c, TTY_NORMAL); |
1da177e4 | 571 | } else { |
e7c98dc7 | 572 | for (i = 0; i < count; i++) { |
1da177e4 LT |
573 | char c = sci_in(port, SCxRDR); |
574 | status = sci_in(port, SCxSR); | |
575 | #if defined(CONFIG_CPU_SH3) | |
576 | /* Skip "chars" during break */ | |
e108b2ca | 577 | if (sci_port->break_flag) { |
1da177e4 LT |
578 | if ((c == 0) && |
579 | (status & SCxSR_FER(port))) { | |
580 | count--; i--; | |
581 | continue; | |
582 | } | |
e108b2ca | 583 | |
1da177e4 LT |
584 | /* Nonzero => end-of-break */ |
585 | pr_debug("scif: debounce<%02x>\n", c); | |
e108b2ca PM |
586 | sci_port->break_flag = 0; |
587 | ||
1da177e4 LT |
588 | if (STEPFN(c)) { |
589 | count--; i--; | |
590 | continue; | |
591 | } | |
592 | } | |
593 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 594 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
595 | count--; i--; |
596 | continue; | |
597 | } | |
598 | ||
599 | /* Store data and status */ | |
1da177e4 | 600 | if (status&SCxSR_FER(port)) { |
33f0f88f | 601 | flag = TTY_FRAME; |
1da177e4 LT |
602 | pr_debug("sci: frame error\n"); |
603 | } else if (status&SCxSR_PER(port)) { | |
33f0f88f | 604 | flag = TTY_PARITY; |
1da177e4 | 605 | pr_debug("sci: parity error\n"); |
33f0f88f AC |
606 | } else |
607 | flag = TTY_NORMAL; | |
608 | tty_insert_flip_char(tty, c, flag); | |
1da177e4 LT |
609 | } |
610 | } | |
611 | ||
612 | sci_in(port, SCxSR); /* dummy read */ | |
613 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
614 | ||
1da177e4 LT |
615 | copied += count; |
616 | port->icount.rx += count; | |
617 | } | |
618 | ||
619 | if (copied) { | |
620 | /* Tell the rest of the system the news. New characters! */ | |
621 | tty_flip_buffer_push(tty); | |
622 | } else { | |
623 | sci_in(port, SCxSR); /* dummy read */ | |
624 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
625 | } | |
626 | } | |
627 | ||
628 | #define SCI_BREAK_JIFFIES (HZ/20) | |
629 | /* The sci generates interrupts during the break, | |
630 | * 1 per millisecond or so during the break period, for 9600 baud. | |
631 | * So dont bother disabling interrupts. | |
632 | * But dont want more than 1 break event. | |
633 | * Use a kernel timer to periodically poll the rx line until | |
634 | * the break is finished. | |
635 | */ | |
636 | static void sci_schedule_break_timer(struct sci_port *port) | |
637 | { | |
638 | port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES; | |
639 | add_timer(&port->break_timer); | |
640 | } | |
641 | /* Ensure that two consecutive samples find the break over. */ | |
642 | static void sci_break_timer(unsigned long data) | |
643 | { | |
e108b2ca PM |
644 | struct sci_port *port = (struct sci_port *)data; |
645 | ||
646 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 647 | port->break_flag = 1; |
e108b2ca PM |
648 | sci_schedule_break_timer(port); |
649 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
650 | /* break is over. */ |
651 | port->break_flag = 2; | |
e108b2ca PM |
652 | sci_schedule_break_timer(port); |
653 | } else | |
654 | port->break_flag = 0; | |
1da177e4 LT |
655 | } |
656 | ||
657 | static inline int sci_handle_errors(struct uart_port *port) | |
658 | { | |
659 | int copied = 0; | |
660 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 661 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 | 662 | |
e108b2ca | 663 | if (status & SCxSR_ORER(port)) { |
1da177e4 | 664 | /* overrun error */ |
e108b2ca | 665 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) |
33f0f88f | 666 | copied++; |
1da177e4 LT |
667 | pr_debug("sci: overrun error\n"); |
668 | } | |
669 | ||
e108b2ca | 670 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
671 | if (sci_rxd_in(port) == 0) { |
672 | /* Notify of BREAK */ | |
e7c98dc7 | 673 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
674 | |
675 | if (!sci_port->break_flag) { | |
676 | sci_port->break_flag = 1; | |
677 | sci_schedule_break_timer(sci_port); | |
678 | ||
1da177e4 | 679 | /* Do sysrq handling. */ |
e108b2ca | 680 | if (uart_handle_break(port)) |
1da177e4 | 681 | return 0; |
e7c98dc7 | 682 | pr_debug("sci: BREAK detected\n"); |
e108b2ca | 683 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
e7c98dc7 MT |
684 | copied++; |
685 | } | |
686 | ||
e108b2ca | 687 | } else { |
1da177e4 | 688 | /* frame error */ |
e108b2ca | 689 | if (tty_insert_flip_char(tty, 0, TTY_FRAME)) |
33f0f88f | 690 | copied++; |
1da177e4 LT |
691 | pr_debug("sci: frame error\n"); |
692 | } | |
693 | } | |
694 | ||
e108b2ca | 695 | if (status & SCxSR_PER(port)) { |
1da177e4 | 696 | /* parity error */ |
e108b2ca PM |
697 | if (tty_insert_flip_char(tty, 0, TTY_PARITY)) |
698 | copied++; | |
1da177e4 LT |
699 | pr_debug("sci: parity error\n"); |
700 | } | |
701 | ||
33f0f88f | 702 | if (copied) |
1da177e4 | 703 | tty_flip_buffer_push(tty); |
1da177e4 LT |
704 | |
705 | return copied; | |
706 | } | |
707 | ||
708 | static inline int sci_handle_breaks(struct uart_port *port) | |
709 | { | |
710 | int copied = 0; | |
711 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 712 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
713 | struct sci_port *s = &sci_ports[port->line]; |
714 | ||
0b3d4ef6 PM |
715 | if (uart_handle_break(port)) |
716 | return 0; | |
717 | ||
b7a76e4b | 718 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
719 | #if defined(CONFIG_CPU_SH3) |
720 | /* Debounce break */ | |
721 | s->break_flag = 1; | |
722 | #endif | |
723 | /* Notify of BREAK */ | |
e108b2ca | 724 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
33f0f88f | 725 | copied++; |
1da177e4 LT |
726 | pr_debug("sci: BREAK detected\n"); |
727 | } | |
728 | ||
729 | #if defined(SCIF_ORER) | |
730 | /* XXX: Handle SCIF overrun error */ | |
1a22f08d | 731 | if (port->type != PORT_SCI && (sci_in(port, SCLSR) & SCIF_ORER) != 0) { |
1da177e4 | 732 | sci_out(port, SCLSR, 0); |
e108b2ca | 733 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) { |
1da177e4 | 734 | copied++; |
1da177e4 LT |
735 | pr_debug("sci: overrun error\n"); |
736 | } | |
737 | } | |
738 | #endif | |
739 | ||
33f0f88f | 740 | if (copied) |
1da177e4 | 741 | tty_flip_buffer_push(tty); |
e108b2ca | 742 | |
1da177e4 LT |
743 | return copied; |
744 | } | |
745 | ||
7d12e780 | 746 | static irqreturn_t sci_rx_interrupt(int irq, void *port) |
1da177e4 | 747 | { |
1da177e4 LT |
748 | /* I think sci_receive_chars has to be called irrespective |
749 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
750 | * to be disabled? | |
751 | */ | |
7d12e780 | 752 | sci_receive_chars(port); |
1da177e4 LT |
753 | |
754 | return IRQ_HANDLED; | |
755 | } | |
756 | ||
7d12e780 | 757 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
758 | { |
759 | struct uart_port *port = ptr; | |
760 | ||
e108b2ca | 761 | spin_lock_irq(&port->lock); |
1da177e4 | 762 | sci_transmit_chars(port); |
e108b2ca | 763 | spin_unlock_irq(&port->lock); |
1da177e4 LT |
764 | |
765 | return IRQ_HANDLED; | |
766 | } | |
767 | ||
7d12e780 | 768 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
769 | { |
770 | struct uart_port *port = ptr; | |
771 | ||
772 | /* Handle errors */ | |
773 | if (port->type == PORT_SCI) { | |
774 | if (sci_handle_errors(port)) { | |
775 | /* discard character in rx buffer */ | |
776 | sci_in(port, SCxSR); | |
777 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
778 | } | |
779 | } else { | |
780 | #if defined(SCIF_ORER) | |
e7c98dc7 | 781 | if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { |
a88487c7 | 782 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
783 | |
784 | sci_out(port, SCLSR, 0); | |
33f0f88f AC |
785 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); |
786 | tty_flip_buffer_push(tty); | |
787 | pr_debug("scif: overrun error\n"); | |
1da177e4 LT |
788 | } |
789 | #endif | |
7d12e780 | 790 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
791 | } |
792 | ||
793 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); | |
794 | ||
795 | /* Kick the transmission */ | |
7d12e780 | 796 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
797 | |
798 | return IRQ_HANDLED; | |
799 | } | |
800 | ||
7d12e780 | 801 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
802 | { |
803 | struct uart_port *port = ptr; | |
804 | ||
805 | /* Handle BREAKs */ | |
806 | sci_handle_breaks(port); | |
807 | sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); | |
808 | ||
809 | return IRQ_HANDLED; | |
810 | } | |
811 | ||
7d12e780 | 812 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 | 813 | { |
a8884e34 MT |
814 | unsigned short ssr_status, scr_status; |
815 | struct uart_port *port = ptr; | |
816 | irqreturn_t ret = IRQ_NONE; | |
1da177e4 | 817 | |
e7c98dc7 MT |
818 | ssr_status = sci_in(port, SCxSR); |
819 | scr_status = sci_in(port, SCSCR); | |
1da177e4 LT |
820 | |
821 | /* Tx Interrupt */ | |
a8884e34 MT |
822 | if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE)) |
823 | ret = sci_tx_interrupt(irq, ptr); | |
1da177e4 | 824 | /* Rx Interrupt */ |
a8884e34 MT |
825 | if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE)) |
826 | ret = sci_rx_interrupt(irq, ptr); | |
1da177e4 | 827 | /* Error Interrupt */ |
a8884e34 MT |
828 | if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE)) |
829 | ret = sci_er_interrupt(irq, ptr); | |
1da177e4 | 830 | /* Break Interrupt */ |
a8884e34 MT |
831 | if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE)) |
832 | ret = sci_br_interrupt(irq, ptr); | |
1da177e4 | 833 | |
a8884e34 | 834 | return ret; |
1da177e4 LT |
835 | } |
836 | ||
a2159b52 | 837 | #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK) |
1da177e4 LT |
838 | /* |
839 | * Here we define a transistion notifier so that we can update all of our | |
840 | * ports' baud rate when the peripheral clock changes. | |
841 | */ | |
e108b2ca PM |
842 | static int sci_notifier(struct notifier_block *self, |
843 | unsigned long phase, void *p) | |
1da177e4 LT |
844 | { |
845 | struct cpufreq_freqs *freqs = p; | |
846 | int i; | |
847 | ||
848 | if ((phase == CPUFREQ_POSTCHANGE) || | |
e7c98dc7 | 849 | (phase == CPUFREQ_RESUMECHANGE)) { |
1da177e4 LT |
850 | for (i = 0; i < SCI_NPORTS; i++) { |
851 | struct uart_port *port = &sci_ports[i].port; | |
b7a76e4b | 852 | struct clk *clk; |
1da177e4 LT |
853 | |
854 | /* | |
855 | * Update the uartclk per-port if frequency has | |
856 | * changed, since it will no longer necessarily be | |
857 | * consistent with the old frequency. | |
858 | * | |
859 | * Really we want to be able to do something like | |
860 | * uart_change_speed() or something along those lines | |
861 | * here to implicitly reset the per-port baud rate.. | |
862 | * | |
863 | * Clean this up later.. | |
864 | */ | |
1d118562 | 865 | clk = clk_get(NULL, "module_clk"); |
a2159b52 | 866 | port->uartclk = clk_get_rate(clk); |
b7a76e4b | 867 | clk_put(clk); |
1da177e4 LT |
868 | } |
869 | ||
e108b2ca PM |
870 | printk(KERN_INFO "%s: got a postchange notification " |
871 | "for cpu %d (old %d, new %d)\n", | |
71cc2c21 | 872 | __func__, freqs->cpu, freqs->old, freqs->new); |
1da177e4 LT |
873 | } |
874 | ||
875 | return NOTIFY_OK; | |
876 | } | |
877 | ||
878 | static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 }; | |
a2159b52 | 879 | #endif /* CONFIG_CPU_FREQ && CONFIG_HAVE_CLK */ |
1da177e4 LT |
880 | |
881 | static int sci_request_irq(struct sci_port *port) | |
882 | { | |
883 | int i; | |
7d12e780 | 884 | irqreturn_t (*handlers[4])(int irq, void *ptr) = { |
1da177e4 LT |
885 | sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, |
886 | sci_br_interrupt, | |
887 | }; | |
888 | const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", | |
889 | "SCI Transmit Data Empty", "SCI Break" }; | |
890 | ||
891 | if (port->irqs[0] == port->irqs[1]) { | |
892 | if (!port->irqs[0]) { | |
893 | printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n"); | |
894 | return -ENODEV; | |
895 | } | |
e108b2ca PM |
896 | |
897 | if (request_irq(port->irqs[0], sci_mpxed_interrupt, | |
35f3c518 | 898 | IRQF_DISABLED, "sci", port)) { |
1da177e4 LT |
899 | printk(KERN_ERR "sci: Cannot allocate irq.\n"); |
900 | return -ENODEV; | |
901 | } | |
902 | } else { | |
903 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { | |
904 | if (!port->irqs[i]) | |
905 | continue; | |
e108b2ca | 906 | if (request_irq(port->irqs[i], handlers[i], |
35f3c518 | 907 | IRQF_DISABLED, desc[i], port)) { |
1da177e4 LT |
908 | printk(KERN_ERR "sci: Cannot allocate irq.\n"); |
909 | return -ENODEV; | |
910 | } | |
911 | } | |
912 | } | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
917 | static void sci_free_irq(struct sci_port *port) | |
918 | { | |
919 | int i; | |
920 | ||
e7c98dc7 MT |
921 | if (port->irqs[0] == port->irqs[1]) { |
922 | if (!port->irqs[0]) | |
923 | printk(KERN_ERR "sci: sci_free_irq error\n"); | |
1da177e4 | 924 | else |
e7c98dc7 MT |
925 | free_irq(port->irqs[0], port); |
926 | } else { | |
1da177e4 LT |
927 | for (i = 0; i < ARRAY_SIZE(port->irqs); i++) { |
928 | if (!port->irqs[i]) | |
929 | continue; | |
930 | ||
931 | free_irq(port->irqs[i], port); | |
932 | } | |
933 | } | |
934 | } | |
935 | ||
936 | static unsigned int sci_tx_empty(struct uart_port *port) | |
937 | { | |
938 | /* Can't detect */ | |
939 | return TIOCSER_TEMT; | |
940 | } | |
941 | ||
942 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
943 | { | |
944 | /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ | |
945 | /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ | |
946 | /* If you have signals for DTR and DCD, please implement here. */ | |
947 | } | |
948 | ||
949 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
950 | { | |
951 | /* This routine is used for geting signals of: DTR, DCD, DSR, RI, | |
952 | and CTS/RTS */ | |
953 | ||
954 | return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; | |
955 | } | |
956 | ||
b129a8cc | 957 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 958 | { |
e108b2ca | 959 | unsigned short ctrl; |
1da177e4 | 960 | |
e108b2ca PM |
961 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
962 | ctrl = sci_in(port, SCSCR); | |
963 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
964 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
965 | } |
966 | ||
b129a8cc | 967 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 968 | { |
1da177e4 LT |
969 | unsigned short ctrl; |
970 | ||
971 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
972 | ctrl = sci_in(port, SCSCR); |
973 | ctrl &= ~SCI_CTRL_FLAGS_TIE; | |
974 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
975 | } |
976 | ||
977 | static void sci_start_rx(struct uart_port *port, unsigned int tty_start) | |
978 | { | |
1da177e4 LT |
979 | unsigned short ctrl; |
980 | ||
981 | /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
982 | ctrl = sci_in(port, SCSCR); |
983 | ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; | |
984 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
985 | } |
986 | ||
987 | static void sci_stop_rx(struct uart_port *port) | |
988 | { | |
1da177e4 LT |
989 | unsigned short ctrl; |
990 | ||
991 | /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
992 | ctrl = sci_in(port, SCSCR); |
993 | ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); | |
994 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
995 | } |
996 | ||
997 | static void sci_enable_ms(struct uart_port *port) | |
998 | { | |
999 | /* Nothing here yet .. */ | |
1000 | } | |
1001 | ||
1002 | static void sci_break_ctl(struct uart_port *port, int break_state) | |
1003 | { | |
1004 | /* Nothing here yet .. */ | |
1005 | } | |
1006 | ||
1007 | static int sci_startup(struct uart_port *port) | |
1008 | { | |
1009 | struct sci_port *s = &sci_ports[port->line]; | |
1010 | ||
e108b2ca PM |
1011 | if (s->enable) |
1012 | s->enable(port); | |
1da177e4 | 1013 | |
a2159b52 | 1014 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 1015 | s->clk = clk_get(NULL, "module_clk"); |
005a336e | 1016 | #endif |
1534a3b3 | 1017 | |
1da177e4 | 1018 | sci_request_irq(s); |
d656901b | 1019 | sci_start_tx(port); |
1da177e4 LT |
1020 | sci_start_rx(port, 1); |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | static void sci_shutdown(struct uart_port *port) | |
1026 | { | |
1027 | struct sci_port *s = &sci_ports[port->line]; | |
1028 | ||
1029 | sci_stop_rx(port); | |
b129a8cc | 1030 | sci_stop_tx(port); |
1da177e4 LT |
1031 | sci_free_irq(s); |
1032 | ||
e108b2ca PM |
1033 | if (s->disable) |
1034 | s->disable(port); | |
1534a3b3 | 1035 | |
a2159b52 | 1036 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 1037 | clk_put(s->clk); |
1038 | s->clk = NULL; | |
005a336e | 1039 | #endif |
1da177e4 LT |
1040 | } |
1041 | ||
606d099c AC |
1042 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
1043 | struct ktermios *old) | |
1da177e4 LT |
1044 | { |
1045 | struct sci_port *s = &sci_ports[port->line]; | |
1046 | unsigned int status, baud, smr_val; | |
a2159b52 | 1047 | int t = -1; |
1da177e4 LT |
1048 | |
1049 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
a2159b52 PM |
1050 | if (likely(baud)) |
1051 | t = SCBRR_VALUE(baud, port->uartclk); | |
e108b2ca | 1052 | |
1da177e4 LT |
1053 | do { |
1054 | status = sci_in(port, SCxSR); | |
1055 | } while (!(status & SCxSR_TEND(port))); | |
1056 | ||
1057 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ | |
1058 | ||
1a22f08d | 1059 | if (port->type != PORT_SCI) |
1da177e4 | 1060 | sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); |
1da177e4 LT |
1061 | |
1062 | smr_val = sci_in(port, SCSMR) & 3; | |
1063 | if ((termios->c_cflag & CSIZE) == CS7) | |
1064 | smr_val |= 0x40; | |
1065 | if (termios->c_cflag & PARENB) | |
1066 | smr_val |= 0x20; | |
1067 | if (termios->c_cflag & PARODD) | |
1068 | smr_val |= 0x30; | |
1069 | if (termios->c_cflag & CSTOPB) | |
1070 | smr_val |= 0x08; | |
1071 | ||
1072 | uart_update_timeout(port, termios->c_cflag, baud); | |
1073 | ||
1074 | sci_out(port, SCSMR, smr_val); | |
1075 | ||
1da177e4 | 1076 | if (t > 0) { |
e7c98dc7 | 1077 | if (t >= 256) { |
1da177e4 LT |
1078 | sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); |
1079 | t >>= 2; | |
e7c98dc7 | 1080 | } else |
1da177e4 | 1081 | sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); |
e7c98dc7 | 1082 | |
1da177e4 LT |
1083 | sci_out(port, SCBRR, t); |
1084 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ | |
1085 | } | |
1086 | ||
b7a76e4b PM |
1087 | if (likely(s->init_pins)) |
1088 | s->init_pins(port, termios->c_cflag); | |
1089 | ||
1da177e4 LT |
1090 | sci_out(port, SCSCR, SCSCR_INIT(port)); |
1091 | ||
1092 | if ((termios->c_cflag & CREAD) != 0) | |
e7c98dc7 | 1093 | sci_start_rx(port, 0); |
1da177e4 LT |
1094 | } |
1095 | ||
1096 | static const char *sci_type(struct uart_port *port) | |
1097 | { | |
1098 | switch (port->type) { | |
e7c98dc7 MT |
1099 | case PORT_IRDA: |
1100 | return "irda"; | |
1101 | case PORT_SCI: | |
1102 | return "sci"; | |
1103 | case PORT_SCIF: | |
1104 | return "scif"; | |
1105 | case PORT_SCIFA: | |
1106 | return "scifa"; | |
1da177e4 LT |
1107 | } |
1108 | ||
fa43972f | 1109 | return NULL; |
1da177e4 LT |
1110 | } |
1111 | ||
1112 | static void sci_release_port(struct uart_port *port) | |
1113 | { | |
1114 | /* Nothing here yet .. */ | |
1115 | } | |
1116 | ||
1117 | static int sci_request_port(struct uart_port *port) | |
1118 | { | |
1119 | /* Nothing here yet .. */ | |
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | static void sci_config_port(struct uart_port *port, int flags) | |
1124 | { | |
1125 | struct sci_port *s = &sci_ports[port->line]; | |
1126 | ||
1127 | port->type = s->type; | |
1128 | ||
e108b2ca PM |
1129 | switch (port->type) { |
1130 | case PORT_SCI: | |
1131 | s->init_pins = sci_init_pins_sci; | |
1132 | break; | |
1133 | case PORT_SCIF: | |
1a22f08d | 1134 | case PORT_SCIFA: |
e108b2ca PM |
1135 | s->init_pins = sci_init_pins_scif; |
1136 | break; | |
1137 | case PORT_IRDA: | |
1138 | s->init_pins = sci_init_pins_irda; | |
1139 | break; | |
1140 | } | |
1141 | ||
7ff731ae PM |
1142 | if (port->flags & UPF_IOREMAP && !port->membase) { |
1143 | #if defined(CONFIG_SUPERH64) | |
1da177e4 | 1144 | port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF"); |
7ff731ae PM |
1145 | port->membase = (void __iomem *)port->mapbase; |
1146 | #else | |
1147 | port->membase = ioremap_nocache(port->mapbase, 0x40); | |
1da177e4 | 1148 | #endif |
7ff731ae PM |
1149 | |
1150 | printk(KERN_ERR "sci: can't remap port#%d\n", port->line); | |
1151 | } | |
1da177e4 LT |
1152 | } |
1153 | ||
1154 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1155 | { | |
1156 | struct sci_port *s = &sci_ports[port->line]; | |
1157 | ||
a62c4133 | 1158 | if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) |
1da177e4 LT |
1159 | return -EINVAL; |
1160 | if (ser->baud_base < 2400) | |
1161 | /* No paper tape reader for Mitch.. */ | |
1162 | return -EINVAL; | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | static struct uart_ops sci_uart_ops = { | |
1168 | .tx_empty = sci_tx_empty, | |
1169 | .set_mctrl = sci_set_mctrl, | |
1170 | .get_mctrl = sci_get_mctrl, | |
1171 | .start_tx = sci_start_tx, | |
1172 | .stop_tx = sci_stop_tx, | |
1173 | .stop_rx = sci_stop_rx, | |
1174 | .enable_ms = sci_enable_ms, | |
1175 | .break_ctl = sci_break_ctl, | |
1176 | .startup = sci_startup, | |
1177 | .shutdown = sci_shutdown, | |
1178 | .set_termios = sci_set_termios, | |
1179 | .type = sci_type, | |
1180 | .release_port = sci_release_port, | |
1181 | .request_port = sci_request_port, | |
1182 | .config_port = sci_config_port, | |
1183 | .verify_port = sci_verify_port, | |
1184 | }; | |
1185 | ||
e108b2ca PM |
1186 | static void __init sci_init_ports(void) |
1187 | { | |
1188 | static int first = 1; | |
1189 | int i; | |
1190 | ||
1191 | if (!first) | |
1192 | return; | |
1193 | ||
1194 | first = 0; | |
1195 | ||
1196 | for (i = 0; i < SCI_NPORTS; i++) { | |
1197 | sci_ports[i].port.ops = &sci_uart_ops; | |
1198 | sci_ports[i].port.iotype = UPIO_MEM; | |
1199 | sci_ports[i].port.line = i; | |
1200 | sci_ports[i].port.fifosize = 1; | |
1201 | ||
1202 | #if defined(__H8300H__) || defined(__H8300S__) | |
1203 | #ifdef __H8300S__ | |
1204 | sci_ports[i].enable = h8300_sci_enable; | |
1205 | sci_ports[i].disable = h8300_sci_disable; | |
1206 | #endif | |
1207 | sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK; | |
a2159b52 | 1208 | #elif defined(CONFIG_HAVE_CLK) |
e108b2ca PM |
1209 | /* |
1210 | * XXX: We should use a proper SCI/SCIF clock | |
1211 | */ | |
1212 | { | |
1d118562 | 1213 | struct clk *clk = clk_get(NULL, "module_clk"); |
a2159b52 | 1214 | sci_ports[i].port.uartclk = clk_get_rate(clk); |
e108b2ca PM |
1215 | clk_put(clk); |
1216 | } | |
a2159b52 PM |
1217 | #else |
1218 | #error "Need a valid uartclk" | |
1da177e4 | 1219 | #endif |
e108b2ca PM |
1220 | |
1221 | sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i]; | |
1222 | sci_ports[i].break_timer.function = sci_break_timer; | |
1223 | ||
1224 | init_timer(&sci_ports[i].break_timer); | |
1225 | } | |
1226 | } | |
1227 | ||
1228 | int __init early_sci_setup(struct uart_port *port) | |
1229 | { | |
1230 | if (unlikely(port->line > SCI_NPORTS)) | |
1231 | return -ENODEV; | |
1232 | ||
1233 | sci_init_ports(); | |
1234 | ||
1235 | sci_ports[port->line].port.membase = port->membase; | |
1236 | sci_ports[port->line].port.mapbase = port->mapbase; | |
1237 | sci_ports[port->line].port.type = port->type; | |
1238 | ||
1239 | return 0; | |
1240 | } | |
1da177e4 LT |
1241 | |
1242 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE | |
1243 | /* | |
1244 | * Print a string to the serial port trying not to disturb | |
1245 | * any possible real use of the port... | |
1246 | */ | |
1247 | static void serial_console_write(struct console *co, const char *s, | |
1248 | unsigned count) | |
1249 | { | |
1250 | put_string(serial_console_port, s, count); | |
1251 | } | |
1252 | ||
1253 | static int __init serial_console_setup(struct console *co, char *options) | |
1254 | { | |
1255 | struct uart_port *port; | |
1256 | int baud = 115200; | |
1257 | int bits = 8; | |
1258 | int parity = 'n'; | |
1259 | int flow = 'n'; | |
1260 | int ret; | |
1261 | ||
e108b2ca PM |
1262 | /* |
1263 | * Check whether an invalid uart number has been specified, and | |
1264 | * if so, search for the first available port that does have | |
1265 | * console support. | |
1266 | */ | |
1267 | if (co->index >= SCI_NPORTS) | |
1268 | co->index = 0; | |
1269 | ||
1da177e4 LT |
1270 | serial_console_port = &sci_ports[co->index]; |
1271 | port = &serial_console_port->port; | |
1da177e4 LT |
1272 | |
1273 | /* | |
e108b2ca PM |
1274 | * Also need to check port->type, we don't actually have any |
1275 | * UPIO_PORT ports, but uart_report_port() handily misreports | |
1276 | * it anyways if we don't have a port available by the time this is | |
1277 | * called. | |
1da177e4 | 1278 | */ |
e108b2ca PM |
1279 | if (!port->type) |
1280 | return -ENODEV; | |
1281 | if (!port->membase || !port->mapbase) | |
1282 | return -ENODEV; | |
1283 | ||
e108b2ca PM |
1284 | port->type = serial_console_port->type; |
1285 | ||
a2159b52 | 1286 | #ifdef CONFIG_HAVE_CLK |
005a336e PM |
1287 | if (!serial_console_port->clk) |
1288 | serial_console_port->clk = clk_get(NULL, "module_clk"); | |
1289 | #endif | |
1290 | ||
e108b2ca PM |
1291 | if (port->flags & UPF_IOREMAP) |
1292 | sci_config_port(port, 0); | |
1293 | ||
1294 | if (serial_console_port->enable) | |
1295 | serial_console_port->enable(port); | |
b7a76e4b | 1296 | |
1da177e4 LT |
1297 | if (options) |
1298 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1299 | ||
1300 | ret = uart_set_options(port, co, baud, parity, bits, flow); | |
1301 | #if defined(__H8300H__) || defined(__H8300S__) | |
1302 | /* disable rx interrupt */ | |
1303 | if (ret == 0) | |
1304 | sci_stop_rx(port); | |
1305 | #endif | |
1306 | return ret; | |
1307 | } | |
1308 | ||
1309 | static struct console serial_console = { | |
1310 | .name = "ttySC", | |
1311 | .device = uart_console_device, | |
1312 | .write = serial_console_write, | |
1313 | .setup = serial_console_setup, | |
fa5da2f7 | 1314 | .flags = CON_PRINTBUFFER, |
1da177e4 LT |
1315 | .index = -1, |
1316 | .data = &sci_uart_driver, | |
1317 | }; | |
1318 | ||
1319 | static int __init sci_console_init(void) | |
1320 | { | |
e108b2ca | 1321 | sci_init_ports(); |
1da177e4 LT |
1322 | register_console(&serial_console); |
1323 | return 0; | |
1324 | } | |
1da177e4 LT |
1325 | console_initcall(sci_console_init); |
1326 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
1327 | ||
68362e08 | 1328 | #ifdef CONFIG_SH_KGDB_CONSOLE |
1da177e4 LT |
1329 | /* |
1330 | * FIXME: Most of this can go away.. at the moment, we rely on | |
1331 | * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though | |
1332 | * most of that can easily be done here instead. | |
1333 | * | |
1334 | * For the time being, just accept the values that were parsed earlier.. | |
1335 | */ | |
1336 | static void __init kgdb_console_get_options(struct uart_port *port, int *baud, | |
1337 | int *parity, int *bits) | |
1338 | { | |
1339 | *baud = kgdb_baud; | |
1340 | *parity = tolower(kgdb_parity); | |
1341 | *bits = kgdb_bits - '0'; | |
1342 | } | |
1343 | ||
1344 | /* | |
1345 | * The naming here is somewhat misleading, since kgdb_console_setup() takes | |
1346 | * care of the early-on initialization for kgdb, regardless of whether we | |
1347 | * actually use kgdb as a console or not. | |
1348 | * | |
1349 | * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense. | |
1350 | */ | |
1351 | int __init kgdb_console_setup(struct console *co, char *options) | |
1352 | { | |
1353 | struct uart_port *port = &sci_ports[kgdb_portnum].port; | |
1354 | int baud = 38400; | |
1355 | int bits = 8; | |
1356 | int parity = 'n'; | |
1357 | int flow = 'n'; | |
1358 | ||
b7a76e4b | 1359 | if (co->index != kgdb_portnum) |
1da177e4 LT |
1360 | co->index = kgdb_portnum; |
1361 | ||
fa5da2f7 PM |
1362 | kgdb_sci_port = &sci_ports[co->index]; |
1363 | port = &kgdb_sci_port->port; | |
1364 | ||
1365 | /* | |
1366 | * Also need to check port->type, we don't actually have any | |
1367 | * UPIO_PORT ports, but uart_report_port() handily misreports | |
1368 | * it anyways if we don't have a port available by the time this is | |
1369 | * called. | |
1370 | */ | |
1371 | if (!port->type) | |
1372 | return -ENODEV; | |
1373 | if (!port->membase || !port->mapbase) | |
1374 | return -ENODEV; | |
1375 | ||
1da177e4 LT |
1376 | if (options) |
1377 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1378 | else | |
1379 | kgdb_console_get_options(port, &baud, &parity, &bits); | |
1380 | ||
1381 | kgdb_getchar = kgdb_sci_getchar; | |
1382 | kgdb_putchar = kgdb_sci_putchar; | |
1383 | ||
1384 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1385 | } | |
1da177e4 | 1386 | |
1da177e4 | 1387 | static struct console kgdb_console = { |
fa5da2f7 PM |
1388 | .name = "ttySC", |
1389 | .device = uart_console_device, | |
1390 | .write = kgdb_console_write, | |
1391 | .setup = kgdb_console_setup, | |
1392 | .flags = CON_PRINTBUFFER, | |
1393 | .index = -1, | |
1da177e4 LT |
1394 | .data = &sci_uart_driver, |
1395 | }; | |
1396 | ||
1397 | /* Register the KGDB console so we get messages (d'oh!) */ | |
1398 | static int __init kgdb_console_init(void) | |
1399 | { | |
e108b2ca | 1400 | sci_init_ports(); |
1da177e4 LT |
1401 | register_console(&kgdb_console); |
1402 | return 0; | |
1403 | } | |
1da177e4 LT |
1404 | console_initcall(kgdb_console_init); |
1405 | #endif /* CONFIG_SH_KGDB_CONSOLE */ | |
1406 | ||
1407 | #if defined(CONFIG_SH_KGDB_CONSOLE) | |
e7c98dc7 | 1408 | #define SCI_CONSOLE (&kgdb_console) |
1da177e4 | 1409 | #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
e7c98dc7 | 1410 | #define SCI_CONSOLE (&serial_console) |
1da177e4 | 1411 | #else |
b7a76e4b | 1412 | #define SCI_CONSOLE 0 |
1da177e4 LT |
1413 | #endif |
1414 | ||
1415 | static char banner[] __initdata = | |
1416 | KERN_INFO "SuperH SCI(F) driver initialized\n"; | |
1417 | ||
1418 | static struct uart_driver sci_uart_driver = { | |
1419 | .owner = THIS_MODULE, | |
1420 | .driver_name = "sci", | |
1da177e4 LT |
1421 | .dev_name = "ttySC", |
1422 | .major = SCI_MAJOR, | |
1423 | .minor = SCI_MINOR_START, | |
e108b2ca | 1424 | .nr = SCI_NPORTS, |
1da177e4 LT |
1425 | .cons = SCI_CONSOLE, |
1426 | }; | |
1427 | ||
e108b2ca PM |
1428 | /* |
1429 | * Register a set of serial devices attached to a platform device. The | |
1430 | * list is terminated with a zero flags entry, which means we expect | |
1431 | * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need | |
1432 | * remapping (such as sh64) should also set UPF_IOREMAP. | |
1433 | */ | |
1434 | static int __devinit sci_probe(struct platform_device *dev) | |
1da177e4 | 1435 | { |
e108b2ca | 1436 | struct plat_sci_port *p = dev->dev.platform_data; |
7ff731ae | 1437 | int i, ret = -EINVAL; |
1da177e4 | 1438 | |
32351a28 | 1439 | for (i = 0; p && p->flags != 0; p++, i++) { |
e108b2ca | 1440 | struct sci_port *sciport = &sci_ports[i]; |
1da177e4 | 1441 | |
32351a28 PM |
1442 | /* Sanity check */ |
1443 | if (unlikely(i == SCI_NPORTS)) { | |
1444 | dev_notice(&dev->dev, "Attempting to register port " | |
1445 | "%d when only %d are available.\n", | |
1446 | i+1, SCI_NPORTS); | |
1447 | dev_notice(&dev->dev, "Consider bumping " | |
1448 | "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); | |
1449 | break; | |
1450 | } | |
1451 | ||
e108b2ca | 1452 | sciport->port.mapbase = p->mapbase; |
b7a76e4b | 1453 | |
7ff731ae PM |
1454 | if (p->mapbase && !p->membase) { |
1455 | if (p->flags & UPF_IOREMAP) { | |
1456 | p->membase = ioremap_nocache(p->mapbase, 0x40); | |
1457 | if (IS_ERR(p->membase)) { | |
1458 | ret = PTR_ERR(p->membase); | |
1459 | goto err_unreg; | |
1460 | } | |
1461 | } else { | |
1462 | /* | |
1463 | * For the simple (and majority of) cases | |
1464 | * where we don't need to do any remapping, | |
1465 | * just cast the cookie directly. | |
1466 | */ | |
1467 | p->membase = (void __iomem *)p->mapbase; | |
1468 | } | |
1469 | } | |
1da177e4 | 1470 | |
e108b2ca PM |
1471 | sciport->port.membase = p->membase; |
1472 | ||
1473 | sciport->port.irq = p->irqs[SCIx_TXI_IRQ]; | |
1474 | sciport->port.flags = p->flags; | |
1475 | sciport->port.dev = &dev->dev; | |
1476 | ||
1477 | sciport->type = sciport->port.type = p->type; | |
1478 | ||
1479 | memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs)); | |
1480 | ||
1481 | uart_add_one_port(&sci_uart_driver, &sciport->port); | |
1da177e4 LT |
1482 | } |
1483 | ||
fa5da2f7 PM |
1484 | #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE) |
1485 | kgdb_sci_port = &sci_ports[kgdb_portnum]; | |
1486 | kgdb_getchar = kgdb_sci_getchar; | |
1487 | kgdb_putchar = kgdb_sci_putchar; | |
1488 | #endif | |
1489 | ||
a2159b52 | 1490 | #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK) |
1da177e4 | 1491 | cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER); |
e289fd97 | 1492 | dev_info(&dev->dev, "CPU frequency notifier registered\n"); |
1da177e4 LT |
1493 | #endif |
1494 | ||
1495 | #ifdef CONFIG_SH_STANDARD_BIOS | |
1496 | sh_bios_gdb_detach(); | |
1497 | #endif | |
1498 | ||
e108b2ca | 1499 | return 0; |
7ff731ae PM |
1500 | |
1501 | err_unreg: | |
1502 | for (i = i - 1; i >= 0; i--) | |
1503 | uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port); | |
1504 | ||
1505 | return ret; | |
1da177e4 LT |
1506 | } |
1507 | ||
e108b2ca PM |
1508 | static int __devexit sci_remove(struct platform_device *dev) |
1509 | { | |
1510 | int i; | |
1511 | ||
1512 | for (i = 0; i < SCI_NPORTS; i++) | |
1513 | uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port); | |
1514 | ||
1515 | return 0; | |
1516 | } | |
1517 | ||
1518 | static int sci_suspend(struct platform_device *dev, pm_message_t state) | |
1da177e4 | 1519 | { |
e108b2ca PM |
1520 | int i; |
1521 | ||
1522 | for (i = 0; i < SCI_NPORTS; i++) { | |
1523 | struct sci_port *p = &sci_ports[i]; | |
1524 | ||
1525 | if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev) | |
1526 | uart_suspend_port(&sci_uart_driver, &p->port); | |
1527 | } | |
1da177e4 | 1528 | |
e108b2ca PM |
1529 | return 0; |
1530 | } | |
1da177e4 | 1531 | |
e108b2ca PM |
1532 | static int sci_resume(struct platform_device *dev) |
1533 | { | |
1534 | int i; | |
1535 | ||
1536 | for (i = 0; i < SCI_NPORTS; i++) { | |
1537 | struct sci_port *p = &sci_ports[i]; | |
1538 | ||
1539 | if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev) | |
1540 | uart_resume_port(&sci_uart_driver, &p->port); | |
1541 | } | |
1542 | ||
1543 | return 0; | |
1544 | } | |
1545 | ||
1546 | static struct platform_driver sci_driver = { | |
1547 | .probe = sci_probe, | |
1548 | .remove = __devexit_p(sci_remove), | |
1549 | .suspend = sci_suspend, | |
1550 | .resume = sci_resume, | |
1551 | .driver = { | |
1552 | .name = "sh-sci", | |
1553 | .owner = THIS_MODULE, | |
1554 | }, | |
1555 | }; | |
1556 | ||
1557 | static int __init sci_init(void) | |
1558 | { | |
1559 | int ret; | |
1560 | ||
1561 | printk(banner); | |
1562 | ||
1563 | sci_init_ports(); | |
1564 | ||
1565 | ret = uart_register_driver(&sci_uart_driver); | |
1566 | if (likely(ret == 0)) { | |
1567 | ret = platform_driver_register(&sci_driver); | |
1568 | if (unlikely(ret)) | |
1569 | uart_unregister_driver(&sci_uart_driver); | |
1570 | } | |
1571 | ||
1572 | return ret; | |
1573 | } | |
1574 | ||
1575 | static void __exit sci_exit(void) | |
1576 | { | |
1577 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
1578 | uart_unregister_driver(&sci_uart_driver); |
1579 | } | |
1580 | ||
1581 | module_init(sci_init); | |
1582 | module_exit(sci_exit); | |
1583 | ||
e108b2ca | 1584 | MODULE_LICENSE("GPL"); |
e169c139 | 1585 | MODULE_ALIAS("platform:sh-sci"); |