Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/serial/sh-sci.c | |
3 | * | |
4 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
5 | * | |
f43dc23d | 6 | * Copyright (C) 2002 - 2011 Paul Mundt |
3ea6bc3d | 7 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
8 | * |
9 | * based off of the old drivers/char/sh-sci.c by: | |
10 | * | |
11 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
12 | * Copyright (C) 2000 Sugioka Toshinobu | |
13 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
14 | * Modified to support SecureEdge. David McCullough (2002) | |
15 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 16 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
17 | * |
18 | * This file is subject to the terms and conditions of the GNU General Public | |
19 | * License. See the file "COPYING" in the main directory of this archive | |
20 | * for more details. | |
21 | */ | |
0b3d4ef6 PM |
22 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
23 | #define SUPPORT_SYSRQ | |
24 | #endif | |
1da177e4 LT |
25 | |
26 | #undef DEBUG | |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/errno.h> | |
1da177e4 LT |
30 | #include <linux/timer.h> |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/tty_flip.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/major.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/sysrq.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/mm.h> | |
1da177e4 LT |
40 | #include <linux/init.h> |
41 | #include <linux/delay.h> | |
42 | #include <linux/console.h> | |
e108b2ca | 43 | #include <linux/platform_device.h> |
96de1a8f | 44 | #include <linux/serial_sci.h> |
1da177e4 LT |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpufreq.h> | |
85f094ec | 47 | #include <linux/clk.h> |
fa5da2f7 | 48 | #include <linux/ctype.h> |
7ff731ae | 49 | #include <linux/err.h> |
73a19e4c GL |
50 | #include <linux/dmaengine.h> |
51 | #include <linux/scatterlist.h> | |
5a0e3ad6 | 52 | #include <linux/slab.h> |
85f094ec PM |
53 | |
54 | #ifdef CONFIG_SUPERH | |
1da177e4 LT |
55 | #include <asm/sh_bios.h> |
56 | #endif | |
57 | ||
168f3623 YS |
58 | #ifdef CONFIG_H8300 |
59 | #include <asm/gpio.h> | |
60 | #endif | |
61 | ||
1da177e4 LT |
62 | #include "sh-sci.h" |
63 | ||
e108b2ca PM |
64 | struct sci_port { |
65 | struct uart_port port; | |
66 | ||
ce6738b6 PM |
67 | /* Platform configuration */ |
68 | struct plat_sci_port *cfg; | |
e108b2ca | 69 | |
e108b2ca PM |
70 | /* Port enable callback */ |
71 | void (*enable)(struct uart_port *port); | |
72 | ||
73 | /* Port disable callback */ | |
74 | void (*disable)(struct uart_port *port); | |
75 | ||
76 | /* Break timer */ | |
77 | struct timer_list break_timer; | |
78 | int break_flag; | |
1534a3b3 | 79 | |
501b825d MD |
80 | /* Interface clock */ |
81 | struct clk *iclk; | |
c7ed1ab3 PM |
82 | /* Function clock */ |
83 | struct clk *fclk; | |
edad1f20 | 84 | |
73a19e4c GL |
85 | struct dma_chan *chan_tx; |
86 | struct dma_chan *chan_rx; | |
f43dc23d | 87 | |
73a19e4c | 88 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
73a19e4c GL |
89 | struct dma_async_tx_descriptor *desc_tx; |
90 | struct dma_async_tx_descriptor *desc_rx[2]; | |
91 | dma_cookie_t cookie_tx; | |
92 | dma_cookie_t cookie_rx[2]; | |
93 | dma_cookie_t active_rx; | |
94 | struct scatterlist sg_tx; | |
95 | unsigned int sg_len_tx; | |
96 | struct scatterlist sg_rx[2]; | |
97 | size_t buf_len_rx; | |
98 | struct sh_dmae_slave param_tx; | |
99 | struct sh_dmae_slave param_rx; | |
100 | struct work_struct work_tx; | |
101 | struct work_struct work_rx; | |
102 | struct timer_list rx_timer; | |
3089f381 | 103 | unsigned int rx_timeout; |
73a19e4c | 104 | #endif |
e552de24 | 105 | |
d535a230 | 106 | struct notifier_block freq_transition; |
e108b2ca PM |
107 | }; |
108 | ||
1da177e4 | 109 | /* Function prototypes */ |
d535a230 | 110 | static void sci_start_tx(struct uart_port *port); |
b129a8cc | 111 | static void sci_stop_tx(struct uart_port *port); |
d535a230 | 112 | static void sci_start_rx(struct uart_port *port); |
1da177e4 | 113 | |
e108b2ca | 114 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 115 | |
e108b2ca PM |
116 | static struct sci_port sci_ports[SCI_NPORTS]; |
117 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 118 | |
e7c98dc7 MT |
119 | static inline struct sci_port * |
120 | to_sci_port(struct uart_port *uart) | |
121 | { | |
122 | return container_of(uart, struct sci_port, port); | |
123 | } | |
124 | ||
07d2a1a1 | 125 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
1f6fd5c9 PM |
126 | |
127 | #ifdef CONFIG_CONSOLE_POLL | |
07d2a1a1 | 128 | static int sci_poll_get_char(struct uart_port *port) |
1da177e4 | 129 | { |
1da177e4 LT |
130 | unsigned short status; |
131 | int c; | |
132 | ||
e108b2ca | 133 | do { |
1da177e4 LT |
134 | status = sci_in(port, SCxSR); |
135 | if (status & SCxSR_ERRORS(port)) { | |
94c8b6db | 136 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
1da177e4 LT |
137 | continue; |
138 | } | |
3f255eb3 JW |
139 | break; |
140 | } while (1); | |
141 | ||
142 | if (!(status & SCxSR_RDxF(port))) | |
143 | return NO_POLL_CHAR; | |
07d2a1a1 | 144 | |
1da177e4 | 145 | c = sci_in(port, SCxRDR); |
07d2a1a1 | 146 | |
e7c98dc7 MT |
147 | /* Dummy read */ |
148 | sci_in(port, SCxSR); | |
1da177e4 | 149 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
150 | |
151 | return c; | |
152 | } | |
1f6fd5c9 | 153 | #endif |
1da177e4 | 154 | |
07d2a1a1 | 155 | static void sci_poll_put_char(struct uart_port *port, unsigned char c) |
1da177e4 | 156 | { |
1da177e4 LT |
157 | unsigned short status; |
158 | ||
1da177e4 LT |
159 | do { |
160 | status = sci_in(port, SCxSR); | |
161 | } while (!(status & SCxSR_TDxE(port))); | |
162 | ||
272966c0 | 163 | sci_out(port, SCxTDR, c); |
dd0a3e77 | 164 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); |
1da177e4 | 165 | } |
07d2a1a1 | 166 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1da177e4 | 167 | |
15c73aaa | 168 | #if defined(__H8300H__) || defined(__H8300S__) |
d5701647 | 169 | static void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 LT |
170 | { |
171 | int ch = (port->mapbase - SMR0) >> 3; | |
172 | ||
173 | /* set DDR regs */ | |
e108b2ca PM |
174 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, |
175 | h8300_sci_pins[ch].rx, | |
176 | H8300_GPIO_INPUT); | |
177 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, | |
178 | h8300_sci_pins[ch].tx, | |
179 | H8300_GPIO_OUTPUT); | |
180 | ||
1da177e4 LT |
181 | /* tx mark output*/ |
182 | H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; | |
183 | } | |
d5701647 PM |
184 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
185 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) | |
e108b2ca | 186 | { |
d5701647 PM |
187 | if (port->mapbase == 0xA4400000) { |
188 | __raw_writew(__raw_readw(PACR) & 0xffc0, PACR); | |
189 | __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); | |
190 | } else if (port->mapbase == 0xA4410000) | |
191 | __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); | |
9465a54f | 192 | } |
31a49c4b | 193 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) |
d5701647 | 194 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
3ea6bc3d | 195 | { |
3ea6bc3d MB |
196 | unsigned short data; |
197 | ||
198 | if (cflag & CRTSCTS) { | |
199 | /* enable RTS/CTS */ | |
200 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
201 | /* Clear PTCR bit 9-2; enable all scif pins but sck */ | |
d5701647 PM |
202 | data = __raw_readw(PORT_PTCR); |
203 | __raw_writew((data & 0xfc03), PORT_PTCR); | |
3ea6bc3d MB |
204 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
205 | /* Clear PVCR bit 9-2 */ | |
d5701647 PM |
206 | data = __raw_readw(PORT_PVCR); |
207 | __raw_writew((data & 0xfc03), PORT_PVCR); | |
3ea6bc3d | 208 | } |
3ea6bc3d MB |
209 | } else { |
210 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
211 | /* Clear PTCR bit 5-2; enable only tx and rx */ | |
d5701647 PM |
212 | data = __raw_readw(PORT_PTCR); |
213 | __raw_writew((data & 0xffc3), PORT_PTCR); | |
3ea6bc3d MB |
214 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
215 | /* Clear PVCR bit 5-2 */ | |
d5701647 PM |
216 | data = __raw_readw(PORT_PVCR); |
217 | __raw_writew((data & 0xffc3), PORT_PVCR); | |
3ea6bc3d MB |
218 | } |
219 | } | |
3ea6bc3d | 220 | } |
b7a76e4b | 221 | #elif defined(CONFIG_CPU_SH3) |
e108b2ca | 222 | /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ |
d5701647 | 223 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 | 224 | { |
b7a76e4b PM |
225 | unsigned short data; |
226 | ||
227 | /* We need to set SCPCR to enable RTS/CTS */ | |
d5701647 | 228 | data = __raw_readw(SCPCR); |
b7a76e4b | 229 | /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ |
d5701647 | 230 | __raw_writew(data & 0x0fcf, SCPCR); |
1da177e4 | 231 | |
d5701647 | 232 | if (!(cflag & CRTSCTS)) { |
1da177e4 | 233 | /* We need to set SCPCR to enable RTS/CTS */ |
d5701647 | 234 | data = __raw_readw(SCPCR); |
1da177e4 LT |
235 | /* Clear out SCP7MD1,0, SCP4MD1,0, |
236 | Set SCP6MD1,0 = {01} (output) */ | |
d5701647 | 237 | __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); |
1da177e4 | 238 | |
32b53076 | 239 | data = __raw_readb(SCPDR); |
1da177e4 | 240 | /* Set /RTS2 (bit6) = 0 */ |
32b53076 | 241 | __raw_writeb(data & 0xbf, SCPDR); |
1da177e4 | 242 | } |
1da177e4 | 243 | } |
41504c39 | 244 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
d5701647 | 245 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
41504c39 | 246 | { |
346b7463 | 247 | unsigned short data; |
41504c39 | 248 | |
346b7463 | 249 | if (port->mapbase == 0xffe00000) { |
d5701647 | 250 | data = __raw_readw(PSCR); |
346b7463 | 251 | data &= ~0x03cf; |
d5701647 | 252 | if (!(cflag & CRTSCTS)) |
346b7463 | 253 | data |= 0x0340; |
41504c39 | 254 | |
d5701647 | 255 | __raw_writew(data, PSCR); |
41504c39 | 256 | } |
178dd0cd | 257 | } |
c01f0f1a YS |
258 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \ |
259 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ | |
7d740a06 | 260 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
2b1bd1ac | 261 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
55ba99eb | 262 | defined(CONFIG_CPU_SUBTYPE_SH7786) || \ |
2b1bd1ac | 263 | defined(CONFIG_CPU_SUBTYPE_SHX3) |
d5701647 PM |
264 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
265 | { | |
266 | if (!(cflag & CRTSCTS)) | |
267 | __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */ | |
268 | } | |
b0c50ad7 | 269 | #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A) |
d5701647 PM |
270 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
271 | { | |
272 | if (!(cflag & CRTSCTS)) | |
273 | __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */ | |
274 | } | |
b7a76e4b | 275 | #else |
d5701647 PM |
276 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
277 | { | |
278 | /* Nothing to do */ | |
1da177e4 | 279 | } |
e108b2ca PM |
280 | #endif |
281 | ||
32351a28 PM |
282 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
283 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
55ba99eb KM |
284 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
285 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
73a19e4c | 286 | static int scif_txfill(struct uart_port *port) |
e108b2ca | 287 | { |
73a19e4c | 288 | return sci_in(port, SCTFDR) & 0xff; |
e108b2ca PM |
289 | } |
290 | ||
73a19e4c | 291 | static int scif_txroom(struct uart_port *port) |
e108b2ca | 292 | { |
73a19e4c | 293 | return SCIF_TXROOM_MAX - scif_txfill(port); |
e108b2ca PM |
294 | } |
295 | ||
73a19e4c | 296 | static int scif_rxfill(struct uart_port *port) |
e108b2ca | 297 | { |
cae167d3 | 298 | return sci_in(port, SCRFDR) & 0xff; |
e108b2ca | 299 | } |
c63847a3 | 300 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
73a19e4c | 301 | static int scif_txfill(struct uart_port *port) |
c63847a3 | 302 | { |
73a19e4c GL |
303 | if (port->mapbase == 0xffe00000 || |
304 | port->mapbase == 0xffe08000) | |
e7c98dc7 | 305 | /* SCIF0/1*/ |
73a19e4c GL |
306 | return sci_in(port, SCTFDR) & 0xff; |
307 | else | |
e7c98dc7 | 308 | /* SCIF2 */ |
73a19e4c | 309 | return sci_in(port, SCFDR) >> 8; |
c63847a3 NI |
310 | } |
311 | ||
73a19e4c GL |
312 | static int scif_txroom(struct uart_port *port) |
313 | { | |
314 | if (port->mapbase == 0xffe00000 || | |
315 | port->mapbase == 0xffe08000) | |
316 | /* SCIF0/1*/ | |
317 | return SCIF_TXROOM_MAX - scif_txfill(port); | |
318 | else | |
319 | /* SCIF2 */ | |
320 | return SCIF2_TXROOM_MAX - scif_txfill(port); | |
c63847a3 NI |
321 | } |
322 | ||
73a19e4c | 323 | static int scif_rxfill(struct uart_port *port) |
c63847a3 | 324 | { |
e7c98dc7 MT |
325 | if ((port->mapbase == 0xffe00000) || |
326 | (port->mapbase == 0xffe08000)) { | |
327 | /* SCIF0/1*/ | |
c63847a3 | 328 | return sci_in(port, SCRFDR) & 0xff; |
e7c98dc7 MT |
329 | } else { |
330 | /* SCIF2 */ | |
c63847a3 | 331 | return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; |
e7c98dc7 | 332 | } |
c63847a3 | 333 | } |
d1d4b10c GL |
334 | #elif defined(CONFIG_ARCH_SH7372) |
335 | static int scif_txfill(struct uart_port *port) | |
336 | { | |
337 | if (port->type == PORT_SCIFA) | |
338 | return sci_in(port, SCFDR) >> 8; | |
339 | else | |
340 | return sci_in(port, SCTFDR); | |
341 | } | |
342 | ||
343 | static int scif_txroom(struct uart_port *port) | |
344 | { | |
345 | return port->fifosize - scif_txfill(port); | |
346 | } | |
347 | ||
348 | static int scif_rxfill(struct uart_port *port) | |
349 | { | |
350 | if (port->type == PORT_SCIFA) | |
351 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
352 | else | |
353 | return sci_in(port, SCRFDR); | |
354 | } | |
e108b2ca | 355 | #else |
73a19e4c | 356 | static int scif_txfill(struct uart_port *port) |
e108b2ca | 357 | { |
73a19e4c | 358 | return sci_in(port, SCFDR) >> 8; |
e108b2ca | 359 | } |
1da177e4 | 360 | |
73a19e4c | 361 | static int scif_txroom(struct uart_port *port) |
e108b2ca | 362 | { |
73a19e4c | 363 | return SCIF_TXROOM_MAX - scif_txfill(port); |
e108b2ca | 364 | } |
1da177e4 | 365 | |
73a19e4c | 366 | static int scif_rxfill(struct uart_port *port) |
e108b2ca PM |
367 | { |
368 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
369 | } | |
1da177e4 | 370 | #endif |
1da177e4 | 371 | |
73a19e4c | 372 | static int sci_txfill(struct uart_port *port) |
e108b2ca | 373 | { |
73a19e4c | 374 | return !(sci_in(port, SCxSR) & SCI_TDRE); |
e108b2ca PM |
375 | } |
376 | ||
73a19e4c GL |
377 | static int sci_txroom(struct uart_port *port) |
378 | { | |
379 | return !sci_txfill(port); | |
380 | } | |
381 | ||
382 | static int sci_rxfill(struct uart_port *port) | |
e108b2ca | 383 | { |
e7c98dc7 | 384 | return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
385 | } |
386 | ||
1da177e4 LT |
387 | /* ********************************************************************** * |
388 | * the interrupt related routines * | |
389 | * ********************************************************************** */ | |
390 | ||
391 | static void sci_transmit_chars(struct uart_port *port) | |
392 | { | |
ebd2c8f6 | 393 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 | 394 | unsigned int stopped = uart_tx_stopped(port); |
1da177e4 LT |
395 | unsigned short status; |
396 | unsigned short ctrl; | |
e108b2ca | 397 | int count; |
1da177e4 LT |
398 | |
399 | status = sci_in(port, SCxSR); | |
400 | if (!(status & SCxSR_TDxE(port))) { | |
1da177e4 | 401 | ctrl = sci_in(port, SCSCR); |
e7c98dc7 | 402 | if (uart_circ_empty(xmit)) |
8e698614 | 403 | ctrl &= ~SCSCR_TIE; |
e7c98dc7 | 404 | else |
8e698614 | 405 | ctrl |= SCSCR_TIE; |
1da177e4 | 406 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
407 | return; |
408 | } | |
409 | ||
1a22f08d | 410 | if (port->type == PORT_SCI) |
e108b2ca | 411 | count = sci_txroom(port); |
1a22f08d YS |
412 | else |
413 | count = scif_txroom(port); | |
1da177e4 LT |
414 | |
415 | do { | |
416 | unsigned char c; | |
417 | ||
418 | if (port->x_char) { | |
419 | c = port->x_char; | |
420 | port->x_char = 0; | |
421 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
422 | c = xmit->buf[xmit->tail]; | |
423 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
424 | } else { | |
425 | break; | |
426 | } | |
427 | ||
428 | sci_out(port, SCxTDR, c); | |
429 | ||
430 | port->icount.tx++; | |
431 | } while (--count > 0); | |
432 | ||
433 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
434 | ||
435 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
436 | uart_write_wakeup(port); | |
437 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 438 | sci_stop_tx(port); |
1da177e4 | 439 | } else { |
1da177e4 LT |
440 | ctrl = sci_in(port, SCSCR); |
441 | ||
1a22f08d | 442 | if (port->type != PORT_SCI) { |
1da177e4 LT |
443 | sci_in(port, SCxSR); /* Dummy read */ |
444 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
445 | } | |
1da177e4 | 446 | |
8e698614 | 447 | ctrl |= SCSCR_TIE; |
1da177e4 | 448 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
449 | } |
450 | } | |
451 | ||
452 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 453 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 454 | |
94c8b6db | 455 | static void sci_receive_chars(struct uart_port *port) |
1da177e4 | 456 | { |
e7c98dc7 | 457 | struct sci_port *sci_port = to_sci_port(port); |
ebd2c8f6 | 458 | struct tty_struct *tty = port->state->port.tty; |
1da177e4 LT |
459 | int i, count, copied = 0; |
460 | unsigned short status; | |
33f0f88f | 461 | unsigned char flag; |
1da177e4 LT |
462 | |
463 | status = sci_in(port, SCxSR); | |
464 | if (!(status & SCxSR_RDxF(port))) | |
465 | return; | |
466 | ||
467 | while (1) { | |
1a22f08d | 468 | if (port->type == PORT_SCI) |
73a19e4c | 469 | count = sci_rxfill(port); |
1a22f08d | 470 | else |
73a19e4c | 471 | count = scif_rxfill(port); |
1da177e4 LT |
472 | |
473 | /* Don't copy more bytes than there is room for in the buffer */ | |
33f0f88f | 474 | count = tty_buffer_request_room(tty, count); |
1da177e4 LT |
475 | |
476 | /* If for any reason we can't copy more data, we're done! */ | |
477 | if (count == 0) | |
478 | break; | |
479 | ||
480 | if (port->type == PORT_SCI) { | |
481 | char c = sci_in(port, SCxRDR); | |
e7c98dc7 MT |
482 | if (uart_handle_sysrq_char(port, c) || |
483 | sci_port->break_flag) | |
1da177e4 | 484 | count = 0; |
e7c98dc7 | 485 | else |
e108b2ca | 486 | tty_insert_flip_char(tty, c, TTY_NORMAL); |
1da177e4 | 487 | } else { |
e7c98dc7 | 488 | for (i = 0; i < count; i++) { |
1da177e4 LT |
489 | char c = sci_in(port, SCxRDR); |
490 | status = sci_in(port, SCxSR); | |
491 | #if defined(CONFIG_CPU_SH3) | |
492 | /* Skip "chars" during break */ | |
e108b2ca | 493 | if (sci_port->break_flag) { |
1da177e4 LT |
494 | if ((c == 0) && |
495 | (status & SCxSR_FER(port))) { | |
496 | count--; i--; | |
497 | continue; | |
498 | } | |
e108b2ca | 499 | |
1da177e4 | 500 | /* Nonzero => end-of-break */ |
762c69e3 | 501 | dev_dbg(port->dev, "debounce<%02x>\n", c); |
e108b2ca PM |
502 | sci_port->break_flag = 0; |
503 | ||
1da177e4 LT |
504 | if (STEPFN(c)) { |
505 | count--; i--; | |
506 | continue; | |
507 | } | |
508 | } | |
509 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 510 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
511 | count--; i--; |
512 | continue; | |
513 | } | |
514 | ||
515 | /* Store data and status */ | |
73a19e4c | 516 | if (status & SCxSR_FER(port)) { |
33f0f88f | 517 | flag = TTY_FRAME; |
762c69e3 | 518 | dev_notice(port->dev, "frame error\n"); |
73a19e4c | 519 | } else if (status & SCxSR_PER(port)) { |
33f0f88f | 520 | flag = TTY_PARITY; |
762c69e3 | 521 | dev_notice(port->dev, "parity error\n"); |
33f0f88f AC |
522 | } else |
523 | flag = TTY_NORMAL; | |
762c69e3 | 524 | |
33f0f88f | 525 | tty_insert_flip_char(tty, c, flag); |
1da177e4 LT |
526 | } |
527 | } | |
528 | ||
529 | sci_in(port, SCxSR); /* dummy read */ | |
530 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
531 | ||
1da177e4 LT |
532 | copied += count; |
533 | port->icount.rx += count; | |
534 | } | |
535 | ||
536 | if (copied) { | |
537 | /* Tell the rest of the system the news. New characters! */ | |
538 | tty_flip_buffer_push(tty); | |
539 | } else { | |
540 | sci_in(port, SCxSR); /* dummy read */ | |
541 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
542 | } | |
543 | } | |
544 | ||
545 | #define SCI_BREAK_JIFFIES (HZ/20) | |
94c8b6db PM |
546 | |
547 | /* | |
548 | * The sci generates interrupts during the break, | |
1da177e4 LT |
549 | * 1 per millisecond or so during the break period, for 9600 baud. |
550 | * So dont bother disabling interrupts. | |
551 | * But dont want more than 1 break event. | |
552 | * Use a kernel timer to periodically poll the rx line until | |
553 | * the break is finished. | |
554 | */ | |
94c8b6db | 555 | static inline void sci_schedule_break_timer(struct sci_port *port) |
1da177e4 | 556 | { |
bc9b3f5c | 557 | mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); |
1da177e4 | 558 | } |
94c8b6db | 559 | |
1da177e4 LT |
560 | /* Ensure that two consecutive samples find the break over. */ |
561 | static void sci_break_timer(unsigned long data) | |
562 | { | |
e108b2ca PM |
563 | struct sci_port *port = (struct sci_port *)data; |
564 | ||
565 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 566 | port->break_flag = 1; |
e108b2ca PM |
567 | sci_schedule_break_timer(port); |
568 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
569 | /* break is over. */ |
570 | port->break_flag = 2; | |
e108b2ca PM |
571 | sci_schedule_break_timer(port); |
572 | } else | |
573 | port->break_flag = 0; | |
1da177e4 LT |
574 | } |
575 | ||
94c8b6db | 576 | static int sci_handle_errors(struct uart_port *port) |
1da177e4 LT |
577 | { |
578 | int copied = 0; | |
579 | unsigned short status = sci_in(port, SCxSR); | |
ebd2c8f6 | 580 | struct tty_struct *tty = port->state->port.tty; |
1da177e4 | 581 | |
e108b2ca | 582 | if (status & SCxSR_ORER(port)) { |
1da177e4 | 583 | /* overrun error */ |
e108b2ca | 584 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) |
33f0f88f | 585 | copied++; |
762c69e3 PM |
586 | |
587 | dev_notice(port->dev, "overrun error"); | |
1da177e4 LT |
588 | } |
589 | ||
e108b2ca | 590 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
591 | if (sci_rxd_in(port) == 0) { |
592 | /* Notify of BREAK */ | |
e7c98dc7 | 593 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
594 | |
595 | if (!sci_port->break_flag) { | |
596 | sci_port->break_flag = 1; | |
597 | sci_schedule_break_timer(sci_port); | |
598 | ||
1da177e4 | 599 | /* Do sysrq handling. */ |
e108b2ca | 600 | if (uart_handle_break(port)) |
1da177e4 | 601 | return 0; |
762c69e3 PM |
602 | |
603 | dev_dbg(port->dev, "BREAK detected\n"); | |
604 | ||
e108b2ca | 605 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
e7c98dc7 MT |
606 | copied++; |
607 | } | |
608 | ||
e108b2ca | 609 | } else { |
1da177e4 | 610 | /* frame error */ |
e108b2ca | 611 | if (tty_insert_flip_char(tty, 0, TTY_FRAME)) |
33f0f88f | 612 | copied++; |
762c69e3 PM |
613 | |
614 | dev_notice(port->dev, "frame error\n"); | |
1da177e4 LT |
615 | } |
616 | } | |
617 | ||
e108b2ca | 618 | if (status & SCxSR_PER(port)) { |
1da177e4 | 619 | /* parity error */ |
e108b2ca PM |
620 | if (tty_insert_flip_char(tty, 0, TTY_PARITY)) |
621 | copied++; | |
762c69e3 PM |
622 | |
623 | dev_notice(port->dev, "parity error"); | |
1da177e4 LT |
624 | } |
625 | ||
33f0f88f | 626 | if (copied) |
1da177e4 | 627 | tty_flip_buffer_push(tty); |
1da177e4 LT |
628 | |
629 | return copied; | |
630 | } | |
631 | ||
94c8b6db | 632 | static int sci_handle_fifo_overrun(struct uart_port *port) |
d830fa45 | 633 | { |
ebd2c8f6 | 634 | struct tty_struct *tty = port->state->port.tty; |
d830fa45 PM |
635 | int copied = 0; |
636 | ||
637 | if (port->type != PORT_SCIF) | |
638 | return 0; | |
639 | ||
640 | if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { | |
641 | sci_out(port, SCLSR, 0); | |
642 | ||
643 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
644 | tty_flip_buffer_push(tty); | |
645 | ||
646 | dev_notice(port->dev, "overrun error\n"); | |
647 | copied++; | |
648 | } | |
649 | ||
650 | return copied; | |
651 | } | |
652 | ||
94c8b6db | 653 | static int sci_handle_breaks(struct uart_port *port) |
1da177e4 LT |
654 | { |
655 | int copied = 0; | |
656 | unsigned short status = sci_in(port, SCxSR); | |
ebd2c8f6 | 657 | struct tty_struct *tty = port->state->port.tty; |
a5660ada | 658 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 659 | |
0b3d4ef6 PM |
660 | if (uart_handle_break(port)) |
661 | return 0; | |
662 | ||
b7a76e4b | 663 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
664 | #if defined(CONFIG_CPU_SH3) |
665 | /* Debounce break */ | |
666 | s->break_flag = 1; | |
667 | #endif | |
668 | /* Notify of BREAK */ | |
e108b2ca | 669 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
33f0f88f | 670 | copied++; |
762c69e3 PM |
671 | |
672 | dev_dbg(port->dev, "BREAK detected\n"); | |
1da177e4 LT |
673 | } |
674 | ||
33f0f88f | 675 | if (copied) |
1da177e4 | 676 | tty_flip_buffer_push(tty); |
e108b2ca | 677 | |
d830fa45 PM |
678 | copied += sci_handle_fifo_overrun(port); |
679 | ||
1da177e4 LT |
680 | return copied; |
681 | } | |
682 | ||
73a19e4c | 683 | static irqreturn_t sci_rx_interrupt(int irq, void *ptr) |
1da177e4 | 684 | { |
73a19e4c GL |
685 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
686 | struct uart_port *port = ptr; | |
687 | struct sci_port *s = to_sci_port(port); | |
688 | ||
689 | if (s->chan_rx) { | |
73a19e4c GL |
690 | u16 scr = sci_in(port, SCSCR); |
691 | u16 ssr = sci_in(port, SCxSR); | |
692 | ||
693 | /* Disable future Rx interrupts */ | |
d1d4b10c | 694 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 GL |
695 | disable_irq_nosync(irq); |
696 | scr |= 0x4000; | |
697 | } else { | |
f43dc23d | 698 | scr &= ~SCSCR_RIE; |
3089f381 GL |
699 | } |
700 | sci_out(port, SCSCR, scr); | |
73a19e4c GL |
701 | /* Clear current interrupt */ |
702 | sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); | |
3089f381 GL |
703 | dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", |
704 | jiffies, s->rx_timeout); | |
705 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); | |
73a19e4c GL |
706 | |
707 | return IRQ_HANDLED; | |
708 | } | |
709 | #endif | |
710 | ||
1da177e4 LT |
711 | /* I think sci_receive_chars has to be called irrespective |
712 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
713 | * to be disabled? | |
714 | */ | |
73a19e4c | 715 | sci_receive_chars(ptr); |
1da177e4 LT |
716 | |
717 | return IRQ_HANDLED; | |
718 | } | |
719 | ||
7d12e780 | 720 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
721 | { |
722 | struct uart_port *port = ptr; | |
fd78a76a | 723 | unsigned long flags; |
1da177e4 | 724 | |
fd78a76a | 725 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 726 | sci_transmit_chars(port); |
fd78a76a | 727 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
728 | |
729 | return IRQ_HANDLED; | |
730 | } | |
731 | ||
7d12e780 | 732 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
733 | { |
734 | struct uart_port *port = ptr; | |
735 | ||
736 | /* Handle errors */ | |
737 | if (port->type == PORT_SCI) { | |
738 | if (sci_handle_errors(port)) { | |
739 | /* discard character in rx buffer */ | |
740 | sci_in(port, SCxSR); | |
741 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
742 | } | |
743 | } else { | |
d830fa45 | 744 | sci_handle_fifo_overrun(port); |
7d12e780 | 745 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
746 | } |
747 | ||
748 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); | |
749 | ||
750 | /* Kick the transmission */ | |
7d12e780 | 751 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
752 | |
753 | return IRQ_HANDLED; | |
754 | } | |
755 | ||
7d12e780 | 756 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
757 | { |
758 | struct uart_port *port = ptr; | |
759 | ||
760 | /* Handle BREAKs */ | |
761 | sci_handle_breaks(port); | |
762 | sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); | |
763 | ||
764 | return IRQ_HANDLED; | |
765 | } | |
766 | ||
f43dc23d PM |
767 | static inline unsigned long port_rx_irq_mask(struct uart_port *port) |
768 | { | |
769 | /* | |
770 | * Not all ports (such as SCIFA) will support REIE. Rather than | |
771 | * special-casing the port type, we check the port initialization | |
772 | * IRQ enable mask to see whether the IRQ is desired at all. If | |
773 | * it's unset, it's logically inferred that there's no point in | |
774 | * testing for it. | |
775 | */ | |
ce6738b6 | 776 | return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); |
f43dc23d PM |
777 | } |
778 | ||
7d12e780 | 779 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 | 780 | { |
44e18e9e | 781 | unsigned short ssr_status, scr_status, err_enabled; |
a8884e34 | 782 | struct uart_port *port = ptr; |
73a19e4c | 783 | struct sci_port *s = to_sci_port(port); |
a8884e34 | 784 | irqreturn_t ret = IRQ_NONE; |
1da177e4 | 785 | |
e7c98dc7 MT |
786 | ssr_status = sci_in(port, SCxSR); |
787 | scr_status = sci_in(port, SCSCR); | |
f43dc23d | 788 | err_enabled = scr_status & port_rx_irq_mask(port); |
1da177e4 LT |
789 | |
790 | /* Tx Interrupt */ | |
f43dc23d | 791 | if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && |
73a19e4c | 792 | !s->chan_tx) |
a8884e34 | 793 | ret = sci_tx_interrupt(irq, ptr); |
f43dc23d | 794 | |
73a19e4c GL |
795 | /* |
796 | * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / | |
797 | * DR flags | |
798 | */ | |
799 | if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && | |
f43dc23d | 800 | (scr_status & SCSCR_RIE)) |
a8884e34 | 801 | ret = sci_rx_interrupt(irq, ptr); |
f43dc23d | 802 | |
1da177e4 | 803 | /* Error Interrupt */ |
dd4da3a5 | 804 | if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) |
a8884e34 | 805 | ret = sci_er_interrupt(irq, ptr); |
f43dc23d | 806 | |
1da177e4 | 807 | /* Break Interrupt */ |
dd4da3a5 | 808 | if ((ssr_status & SCxSR_BRK(port)) && err_enabled) |
a8884e34 | 809 | ret = sci_br_interrupt(irq, ptr); |
1da177e4 | 810 | |
a8884e34 | 811 | return ret; |
1da177e4 LT |
812 | } |
813 | ||
1da177e4 LT |
814 | /* |
815 | * Here we define a transistion notifier so that we can update all of our | |
816 | * ports' baud rate when the peripheral clock changes. | |
817 | */ | |
e108b2ca PM |
818 | static int sci_notifier(struct notifier_block *self, |
819 | unsigned long phase, void *p) | |
1da177e4 | 820 | { |
e552de24 MD |
821 | struct sci_port *sci_port; |
822 | unsigned long flags; | |
1da177e4 | 823 | |
d535a230 PM |
824 | sci_port = container_of(self, struct sci_port, freq_transition); |
825 | ||
1da177e4 | 826 | if ((phase == CPUFREQ_POSTCHANGE) || |
e552de24 | 827 | (phase == CPUFREQ_RESUMECHANGE)) { |
d535a230 | 828 | struct uart_port *port = &sci_port->port; |
073e84c9 | 829 | |
d535a230 PM |
830 | spin_lock_irqsave(&port->lock, flags); |
831 | port->uartclk = clk_get_rate(sci_port->iclk); | |
832 | spin_unlock_irqrestore(&port->lock, flags); | |
e552de24 | 833 | } |
1da177e4 | 834 | |
1da177e4 LT |
835 | return NOTIFY_OK; |
836 | } | |
501b825d MD |
837 | |
838 | static void sci_clk_enable(struct uart_port *port) | |
839 | { | |
840 | struct sci_port *sci_port = to_sci_port(port); | |
841 | ||
c7ed1ab3 PM |
842 | clk_enable(sci_port->iclk); |
843 | sci_port->port.uartclk = clk_get_rate(sci_port->iclk); | |
844 | clk_enable(sci_port->fclk); | |
501b825d MD |
845 | } |
846 | ||
847 | static void sci_clk_disable(struct uart_port *port) | |
848 | { | |
849 | struct sci_port *sci_port = to_sci_port(port); | |
850 | ||
c7ed1ab3 PM |
851 | clk_disable(sci_port->fclk); |
852 | clk_disable(sci_port->iclk); | |
501b825d | 853 | } |
1da177e4 LT |
854 | |
855 | static int sci_request_irq(struct sci_port *port) | |
856 | { | |
857 | int i; | |
7d12e780 | 858 | irqreturn_t (*handlers[4])(int irq, void *ptr) = { |
1da177e4 LT |
859 | sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, |
860 | sci_br_interrupt, | |
861 | }; | |
862 | const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", | |
863 | "SCI Transmit Data Empty", "SCI Break" }; | |
864 | ||
ce6738b6 PM |
865 | if (port->cfg->irqs[0] == port->cfg->irqs[1]) { |
866 | if (unlikely(!port->cfg->irqs[0])) | |
1da177e4 | 867 | return -ENODEV; |
e108b2ca | 868 | |
ce6738b6 | 869 | if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt, |
35f3c518 | 870 | IRQF_DISABLED, "sci", port)) { |
762c69e3 | 871 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
872 | return -ENODEV; |
873 | } | |
874 | } else { | |
875 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { | |
ce6738b6 | 876 | if (unlikely(!port->cfg->irqs[i])) |
1da177e4 | 877 | continue; |
762c69e3 | 878 | |
ce6738b6 | 879 | if (request_irq(port->cfg->irqs[i], handlers[i], |
35f3c518 | 880 | IRQF_DISABLED, desc[i], port)) { |
762c69e3 | 881 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
882 | return -ENODEV; |
883 | } | |
884 | } | |
885 | } | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
890 | static void sci_free_irq(struct sci_port *port) | |
891 | { | |
892 | int i; | |
893 | ||
ce6738b6 PM |
894 | if (port->cfg->irqs[0] == port->cfg->irqs[1]) |
895 | free_irq(port->cfg->irqs[0], port); | |
762c69e3 | 896 | else { |
ce6738b6 PM |
897 | for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) { |
898 | if (!port->cfg->irqs[i]) | |
1da177e4 LT |
899 | continue; |
900 | ||
ce6738b6 | 901 | free_irq(port->cfg->irqs[i], port); |
1da177e4 LT |
902 | } |
903 | } | |
904 | } | |
905 | ||
906 | static unsigned int sci_tx_empty(struct uart_port *port) | |
907 | { | |
b1516803 | 908 | unsigned short status = sci_in(port, SCxSR); |
73a19e4c GL |
909 | unsigned short in_tx_fifo = scif_txfill(port); |
910 | ||
911 | return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; | |
1da177e4 LT |
912 | } |
913 | ||
914 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
915 | { | |
916 | /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ | |
917 | /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ | |
918 | /* If you have signals for DTR and DCD, please implement here. */ | |
919 | } | |
920 | ||
921 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
922 | { | |
73a19e4c | 923 | /* This routine is used for getting signals of: DTR, DCD, DSR, RI, |
1da177e4 LT |
924 | and CTS/RTS */ |
925 | ||
926 | return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; | |
927 | } | |
928 | ||
73a19e4c GL |
929 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
930 | static void sci_dma_tx_complete(void *arg) | |
931 | { | |
932 | struct sci_port *s = arg; | |
933 | struct uart_port *port = &s->port; | |
934 | struct circ_buf *xmit = &port->state->xmit; | |
935 | unsigned long flags; | |
936 | ||
937 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); | |
938 | ||
939 | spin_lock_irqsave(&port->lock, flags); | |
940 | ||
f354a381 | 941 | xmit->tail += sg_dma_len(&s->sg_tx); |
73a19e4c GL |
942 | xmit->tail &= UART_XMIT_SIZE - 1; |
943 | ||
f354a381 | 944 | port->icount.tx += sg_dma_len(&s->sg_tx); |
73a19e4c GL |
945 | |
946 | async_tx_ack(s->desc_tx); | |
947 | s->cookie_tx = -EINVAL; | |
948 | s->desc_tx = NULL; | |
949 | ||
73a19e4c GL |
950 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
951 | uart_write_wakeup(port); | |
952 | ||
3089f381 | 953 | if (!uart_circ_empty(xmit)) { |
73a19e4c | 954 | schedule_work(&s->work_tx); |
d1d4b10c | 955 | } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 | 956 | u16 ctrl = sci_in(port, SCSCR); |
f43dc23d | 957 | sci_out(port, SCSCR, ctrl & ~SCSCR_TIE); |
3089f381 GL |
958 | } |
959 | ||
960 | spin_unlock_irqrestore(&port->lock, flags); | |
73a19e4c GL |
961 | } |
962 | ||
963 | /* Locking: called with port lock held */ | |
964 | static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty, | |
965 | size_t count) | |
966 | { | |
967 | struct uart_port *port = &s->port; | |
968 | int i, active, room; | |
969 | ||
970 | room = tty_buffer_request_room(tty, count); | |
971 | ||
972 | if (s->active_rx == s->cookie_rx[0]) { | |
973 | active = 0; | |
974 | } else if (s->active_rx == s->cookie_rx[1]) { | |
975 | active = 1; | |
976 | } else { | |
977 | dev_err(port->dev, "cookie %d not found!\n", s->active_rx); | |
978 | return 0; | |
979 | } | |
980 | ||
981 | if (room < count) | |
982 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", | |
983 | count - room); | |
984 | if (!room) | |
985 | return room; | |
986 | ||
987 | for (i = 0; i < room; i++) | |
988 | tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i], | |
989 | TTY_NORMAL); | |
990 | ||
991 | port->icount.rx += room; | |
992 | ||
993 | return room; | |
994 | } | |
995 | ||
996 | static void sci_dma_rx_complete(void *arg) | |
997 | { | |
998 | struct sci_port *s = arg; | |
999 | struct uart_port *port = &s->port; | |
1000 | struct tty_struct *tty = port->state->port.tty; | |
1001 | unsigned long flags; | |
1002 | int count; | |
1003 | ||
3089f381 | 1004 | dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); |
73a19e4c GL |
1005 | |
1006 | spin_lock_irqsave(&port->lock, flags); | |
1007 | ||
1008 | count = sci_dma_rx_push(s, tty, s->buf_len_rx); | |
1009 | ||
3089f381 | 1010 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); |
73a19e4c GL |
1011 | |
1012 | spin_unlock_irqrestore(&port->lock, flags); | |
1013 | ||
1014 | if (count) | |
1015 | tty_flip_buffer_push(tty); | |
1016 | ||
1017 | schedule_work(&s->work_rx); | |
1018 | } | |
1019 | ||
73a19e4c GL |
1020 | static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) |
1021 | { | |
1022 | struct dma_chan *chan = s->chan_rx; | |
1023 | struct uart_port *port = &s->port; | |
73a19e4c GL |
1024 | |
1025 | s->chan_rx = NULL; | |
1026 | s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; | |
1027 | dma_release_channel(chan); | |
85b8e3ff GL |
1028 | if (sg_dma_address(&s->sg_rx[0])) |
1029 | dma_free_coherent(port->dev, s->buf_len_rx * 2, | |
1030 | sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); | |
73a19e4c GL |
1031 | if (enable_pio) |
1032 | sci_start_rx(port); | |
1033 | } | |
1034 | ||
1035 | static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) | |
1036 | { | |
1037 | struct dma_chan *chan = s->chan_tx; | |
1038 | struct uart_port *port = &s->port; | |
73a19e4c GL |
1039 | |
1040 | s->chan_tx = NULL; | |
1041 | s->cookie_tx = -EINVAL; | |
1042 | dma_release_channel(chan); | |
1043 | if (enable_pio) | |
1044 | sci_start_tx(port); | |
1045 | } | |
1046 | ||
1047 | static void sci_submit_rx(struct sci_port *s) | |
1048 | { | |
1049 | struct dma_chan *chan = s->chan_rx; | |
1050 | int i; | |
1051 | ||
1052 | for (i = 0; i < 2; i++) { | |
1053 | struct scatterlist *sg = &s->sg_rx[i]; | |
1054 | struct dma_async_tx_descriptor *desc; | |
1055 | ||
1056 | desc = chan->device->device_prep_slave_sg(chan, | |
1057 | sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT); | |
1058 | ||
1059 | if (desc) { | |
1060 | s->desc_rx[i] = desc; | |
1061 | desc->callback = sci_dma_rx_complete; | |
1062 | desc->callback_param = s; | |
1063 | s->cookie_rx[i] = desc->tx_submit(desc); | |
1064 | } | |
1065 | ||
1066 | if (!desc || s->cookie_rx[i] < 0) { | |
1067 | if (i) { | |
1068 | async_tx_ack(s->desc_rx[0]); | |
1069 | s->cookie_rx[0] = -EINVAL; | |
1070 | } | |
1071 | if (desc) { | |
1072 | async_tx_ack(desc); | |
1073 | s->cookie_rx[i] = -EINVAL; | |
1074 | } | |
1075 | dev_warn(s->port.dev, | |
1076 | "failed to re-start DMA, using PIO\n"); | |
1077 | sci_rx_dma_release(s, true); | |
1078 | return; | |
1079 | } | |
3089f381 GL |
1080 | dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, |
1081 | s->cookie_rx[i], i); | |
73a19e4c GL |
1082 | } |
1083 | ||
1084 | s->active_rx = s->cookie_rx[0]; | |
1085 | ||
1086 | dma_async_issue_pending(chan); | |
1087 | } | |
1088 | ||
1089 | static void work_fn_rx(struct work_struct *work) | |
1090 | { | |
1091 | struct sci_port *s = container_of(work, struct sci_port, work_rx); | |
1092 | struct uart_port *port = &s->port; | |
1093 | struct dma_async_tx_descriptor *desc; | |
1094 | int new; | |
1095 | ||
1096 | if (s->active_rx == s->cookie_rx[0]) { | |
1097 | new = 0; | |
1098 | } else if (s->active_rx == s->cookie_rx[1]) { | |
1099 | new = 1; | |
1100 | } else { | |
1101 | dev_err(port->dev, "cookie %d not found!\n", s->active_rx); | |
1102 | return; | |
1103 | } | |
1104 | desc = s->desc_rx[new]; | |
1105 | ||
1106 | if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != | |
1107 | DMA_SUCCESS) { | |
1108 | /* Handle incomplete DMA receive */ | |
1109 | struct tty_struct *tty = port->state->port.tty; | |
1110 | struct dma_chan *chan = s->chan_rx; | |
1111 | struct sh_desc *sh_desc = container_of(desc, struct sh_desc, | |
1112 | async_tx); | |
1113 | unsigned long flags; | |
1114 | int count; | |
1115 | ||
05827630 | 1116 | chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); |
73a19e4c GL |
1117 | dev_dbg(port->dev, "Read %u bytes with cookie %d\n", |
1118 | sh_desc->partial, sh_desc->cookie); | |
1119 | ||
1120 | spin_lock_irqsave(&port->lock, flags); | |
1121 | count = sci_dma_rx_push(s, tty, sh_desc->partial); | |
1122 | spin_unlock_irqrestore(&port->lock, flags); | |
1123 | ||
1124 | if (count) | |
1125 | tty_flip_buffer_push(tty); | |
1126 | ||
1127 | sci_submit_rx(s); | |
1128 | ||
1129 | return; | |
1130 | } | |
1131 | ||
1132 | s->cookie_rx[new] = desc->tx_submit(desc); | |
1133 | if (s->cookie_rx[new] < 0) { | |
1134 | dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); | |
1135 | sci_rx_dma_release(s, true); | |
1136 | return; | |
1137 | } | |
1138 | ||
73a19e4c | 1139 | s->active_rx = s->cookie_rx[!new]; |
3089f381 GL |
1140 | |
1141 | dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, | |
1142 | s->cookie_rx[new], new, s->active_rx); | |
73a19e4c GL |
1143 | } |
1144 | ||
1145 | static void work_fn_tx(struct work_struct *work) | |
1146 | { | |
1147 | struct sci_port *s = container_of(work, struct sci_port, work_tx); | |
1148 | struct dma_async_tx_descriptor *desc; | |
1149 | struct dma_chan *chan = s->chan_tx; | |
1150 | struct uart_port *port = &s->port; | |
1151 | struct circ_buf *xmit = &port->state->xmit; | |
1152 | struct scatterlist *sg = &s->sg_tx; | |
1153 | ||
1154 | /* | |
1155 | * DMA is idle now. | |
1156 | * Port xmit buffer is already mapped, and it is one page... Just adjust | |
1157 | * offsets and lengths. Since it is a circular buffer, we have to | |
1158 | * transmit till the end, and then the rest. Take the port lock to get a | |
1159 | * consistent xmit buffer state. | |
1160 | */ | |
1161 | spin_lock_irq(&port->lock); | |
1162 | sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); | |
f354a381 | 1163 | sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + |
73a19e4c | 1164 | sg->offset; |
f354a381 | 1165 | sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), |
73a19e4c | 1166 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); |
73a19e4c GL |
1167 | spin_unlock_irq(&port->lock); |
1168 | ||
f354a381 | 1169 | BUG_ON(!sg_dma_len(sg)); |
73a19e4c GL |
1170 | |
1171 | desc = chan->device->device_prep_slave_sg(chan, | |
1172 | sg, s->sg_len_tx, DMA_TO_DEVICE, | |
1173 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1174 | if (!desc) { | |
1175 | /* switch to PIO */ | |
1176 | sci_tx_dma_release(s, true); | |
1177 | return; | |
1178 | } | |
1179 | ||
1180 | dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); | |
1181 | ||
1182 | spin_lock_irq(&port->lock); | |
1183 | s->desc_tx = desc; | |
1184 | desc->callback = sci_dma_tx_complete; | |
1185 | desc->callback_param = s; | |
1186 | spin_unlock_irq(&port->lock); | |
1187 | s->cookie_tx = desc->tx_submit(desc); | |
1188 | if (s->cookie_tx < 0) { | |
1189 | dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); | |
1190 | /* switch to PIO */ | |
1191 | sci_tx_dma_release(s, true); | |
1192 | return; | |
1193 | } | |
1194 | ||
1195 | dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, | |
1196 | xmit->buf, xmit->tail, xmit->head, s->cookie_tx); | |
1197 | ||
1198 | dma_async_issue_pending(chan); | |
1199 | } | |
1200 | #endif | |
1201 | ||
b129a8cc | 1202 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 1203 | { |
3089f381 | 1204 | struct sci_port *s = to_sci_port(port); |
e108b2ca | 1205 | unsigned short ctrl; |
1da177e4 | 1206 | |
73a19e4c | 1207 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
d1d4b10c | 1208 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 GL |
1209 | u16 new, scr = sci_in(port, SCSCR); |
1210 | if (s->chan_tx) | |
1211 | new = scr | 0x8000; | |
1212 | else | |
1213 | new = scr & ~0x8000; | |
1214 | if (new != scr) | |
1215 | sci_out(port, SCSCR, new); | |
73a19e4c | 1216 | } |
f43dc23d | 1217 | |
3089f381 GL |
1218 | if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && |
1219 | s->cookie_tx < 0) | |
1220 | schedule_work(&s->work_tx); | |
73a19e4c | 1221 | #endif |
f43dc23d | 1222 | |
d1d4b10c | 1223 | if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 GL |
1224 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
1225 | ctrl = sci_in(port, SCSCR); | |
f43dc23d | 1226 | sci_out(port, SCSCR, ctrl | SCSCR_TIE); |
3089f381 | 1227 | } |
1da177e4 LT |
1228 | } |
1229 | ||
b129a8cc | 1230 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 1231 | { |
1da177e4 LT |
1232 | unsigned short ctrl; |
1233 | ||
1234 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
1da177e4 | 1235 | ctrl = sci_in(port, SCSCR); |
f43dc23d | 1236 | |
d1d4b10c | 1237 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1238 | ctrl &= ~0x8000; |
f43dc23d | 1239 | |
8e698614 | 1240 | ctrl &= ~SCSCR_TIE; |
f43dc23d | 1241 | |
1da177e4 | 1242 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
1243 | } |
1244 | ||
73a19e4c | 1245 | static void sci_start_rx(struct uart_port *port) |
1da177e4 | 1246 | { |
1da177e4 LT |
1247 | unsigned short ctrl; |
1248 | ||
f43dc23d | 1249 | ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port); |
1da177e4 | 1250 | |
d1d4b10c | 1251 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1252 | ctrl &= ~0x4000; |
f43dc23d | 1253 | |
1da177e4 | 1254 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
1255 | } |
1256 | ||
1257 | static void sci_stop_rx(struct uart_port *port) | |
1258 | { | |
1da177e4 LT |
1259 | unsigned short ctrl; |
1260 | ||
1da177e4 | 1261 | ctrl = sci_in(port, SCSCR); |
f43dc23d | 1262 | |
d1d4b10c | 1263 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1264 | ctrl &= ~0x4000; |
f43dc23d PM |
1265 | |
1266 | ctrl &= ~port_rx_irq_mask(port); | |
1267 | ||
1da177e4 | 1268 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
1269 | } |
1270 | ||
1271 | static void sci_enable_ms(struct uart_port *port) | |
1272 | { | |
1273 | /* Nothing here yet .. */ | |
1274 | } | |
1275 | ||
1276 | static void sci_break_ctl(struct uart_port *port, int break_state) | |
1277 | { | |
1278 | /* Nothing here yet .. */ | |
1279 | } | |
1280 | ||
73a19e4c GL |
1281 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1282 | static bool filter(struct dma_chan *chan, void *slave) | |
1283 | { | |
1284 | struct sh_dmae_slave *param = slave; | |
1285 | ||
1286 | dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, | |
1287 | param->slave_id); | |
1288 | ||
1289 | if (param->dma_dev == chan->device->dev) { | |
1290 | chan->private = param; | |
1291 | return true; | |
1292 | } else { | |
1293 | return false; | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | static void rx_timer_fn(unsigned long arg) | |
1298 | { | |
1299 | struct sci_port *s = (struct sci_port *)arg; | |
1300 | struct uart_port *port = &s->port; | |
73a19e4c | 1301 | u16 scr = sci_in(port, SCSCR); |
3089f381 | 1302 | |
d1d4b10c | 1303 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 | 1304 | scr &= ~0x4000; |
ce6738b6 | 1305 | enable_irq(s->cfg->irqs[1]); |
3089f381 | 1306 | } |
f43dc23d | 1307 | sci_out(port, SCSCR, scr | SCSCR_RIE); |
73a19e4c GL |
1308 | dev_dbg(port->dev, "DMA Rx timed out\n"); |
1309 | schedule_work(&s->work_rx); | |
1310 | } | |
1311 | ||
1312 | static void sci_request_dma(struct uart_port *port) | |
1313 | { | |
1314 | struct sci_port *s = to_sci_port(port); | |
1315 | struct sh_dmae_slave *param; | |
1316 | struct dma_chan *chan; | |
1317 | dma_cap_mask_t mask; | |
1318 | int nent; | |
1319 | ||
1320 | dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__, | |
ce6738b6 | 1321 | port->line, s->cfg->dma_dev); |
73a19e4c | 1322 | |
ce6738b6 | 1323 | if (!s->cfg->dma_dev) |
73a19e4c GL |
1324 | return; |
1325 | ||
1326 | dma_cap_zero(mask); | |
1327 | dma_cap_set(DMA_SLAVE, mask); | |
1328 | ||
1329 | param = &s->param_tx; | |
1330 | ||
1331 | /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ | |
ce6738b6 PM |
1332 | param->slave_id = s->cfg->dma_slave_tx; |
1333 | param->dma_dev = s->cfg->dma_dev; | |
73a19e4c GL |
1334 | |
1335 | s->cookie_tx = -EINVAL; | |
1336 | chan = dma_request_channel(mask, filter, param); | |
1337 | dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); | |
1338 | if (chan) { | |
1339 | s->chan_tx = chan; | |
1340 | sg_init_table(&s->sg_tx, 1); | |
1341 | /* UART circular tx buffer is an aligned page. */ | |
1342 | BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); | |
1343 | sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), | |
1344 | UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); | |
1345 | nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); | |
1346 | if (!nent) | |
1347 | sci_tx_dma_release(s, false); | |
1348 | else | |
1349 | dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, | |
1350 | sg_dma_len(&s->sg_tx), | |
1351 | port->state->xmit.buf, sg_dma_address(&s->sg_tx)); | |
1352 | ||
1353 | s->sg_len_tx = nent; | |
1354 | ||
1355 | INIT_WORK(&s->work_tx, work_fn_tx); | |
1356 | } | |
1357 | ||
1358 | param = &s->param_rx; | |
1359 | ||
1360 | /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ | |
ce6738b6 PM |
1361 | param->slave_id = s->cfg->dma_slave_rx; |
1362 | param->dma_dev = s->cfg->dma_dev; | |
73a19e4c GL |
1363 | |
1364 | chan = dma_request_channel(mask, filter, param); | |
1365 | dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); | |
1366 | if (chan) { | |
1367 | dma_addr_t dma[2]; | |
1368 | void *buf[2]; | |
1369 | int i; | |
1370 | ||
1371 | s->chan_rx = chan; | |
1372 | ||
1373 | s->buf_len_rx = 2 * max(16, (int)port->fifosize); | |
1374 | buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, | |
1375 | &dma[0], GFP_KERNEL); | |
1376 | ||
1377 | if (!buf[0]) { | |
1378 | dev_warn(port->dev, | |
1379 | "failed to allocate dma buffer, using PIO\n"); | |
1380 | sci_rx_dma_release(s, true); | |
1381 | return; | |
1382 | } | |
1383 | ||
1384 | buf[1] = buf[0] + s->buf_len_rx; | |
1385 | dma[1] = dma[0] + s->buf_len_rx; | |
1386 | ||
1387 | for (i = 0; i < 2; i++) { | |
1388 | struct scatterlist *sg = &s->sg_rx[i]; | |
1389 | ||
1390 | sg_init_table(sg, 1); | |
1391 | sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, | |
1392 | (int)buf[i] & ~PAGE_MASK); | |
f354a381 | 1393 | sg_dma_address(sg) = dma[i]; |
73a19e4c GL |
1394 | } |
1395 | ||
1396 | INIT_WORK(&s->work_rx, work_fn_rx); | |
1397 | setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); | |
1398 | ||
1399 | sci_submit_rx(s); | |
1400 | } | |
1401 | } | |
1402 | ||
1403 | static void sci_free_dma(struct uart_port *port) | |
1404 | { | |
1405 | struct sci_port *s = to_sci_port(port); | |
1406 | ||
ce6738b6 | 1407 | if (!s->cfg->dma_dev) |
73a19e4c GL |
1408 | return; |
1409 | ||
1410 | if (s->chan_tx) | |
1411 | sci_tx_dma_release(s, false); | |
1412 | if (s->chan_rx) | |
1413 | sci_rx_dma_release(s, false); | |
1414 | } | |
27bd1075 PM |
1415 | #else |
1416 | static inline void sci_request_dma(struct uart_port *port) | |
1417 | { | |
1418 | } | |
1419 | ||
1420 | static inline void sci_free_dma(struct uart_port *port) | |
1421 | { | |
1422 | } | |
73a19e4c GL |
1423 | #endif |
1424 | ||
1da177e4 LT |
1425 | static int sci_startup(struct uart_port *port) |
1426 | { | |
a5660ada | 1427 | struct sci_port *s = to_sci_port(port); |
073e84c9 | 1428 | int ret; |
1da177e4 | 1429 | |
73a19e4c GL |
1430 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1431 | ||
e108b2ca PM |
1432 | if (s->enable) |
1433 | s->enable(port); | |
1da177e4 | 1434 | |
073e84c9 PM |
1435 | ret = sci_request_irq(s); |
1436 | if (unlikely(ret < 0)) | |
1437 | return ret; | |
1438 | ||
73a19e4c | 1439 | sci_request_dma(port); |
073e84c9 | 1440 | |
d656901b | 1441 | sci_start_tx(port); |
73a19e4c | 1442 | sci_start_rx(port); |
1da177e4 LT |
1443 | |
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | static void sci_shutdown(struct uart_port *port) | |
1448 | { | |
a5660ada | 1449 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1450 | |
73a19e4c GL |
1451 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1452 | ||
1da177e4 | 1453 | sci_stop_rx(port); |
b129a8cc | 1454 | sci_stop_tx(port); |
073e84c9 | 1455 | |
73a19e4c | 1456 | sci_free_dma(port); |
1da177e4 LT |
1457 | sci_free_irq(s); |
1458 | ||
e108b2ca PM |
1459 | if (s->disable) |
1460 | s->disable(port); | |
1da177e4 LT |
1461 | } |
1462 | ||
26c92f37 PM |
1463 | static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, |
1464 | unsigned long freq) | |
1465 | { | |
1466 | switch (algo_id) { | |
1467 | case SCBRR_ALGO_1: | |
1468 | return ((freq + 16 * bps) / (16 * bps) - 1); | |
1469 | case SCBRR_ALGO_2: | |
1470 | return ((freq + 16 * bps) / (32 * bps) - 1); | |
1471 | case SCBRR_ALGO_3: | |
1472 | return (((freq * 2) + 16 * bps) / (16 * bps) - 1); | |
1473 | case SCBRR_ALGO_4: | |
1474 | return (((freq * 2) + 16 * bps) / (32 * bps) - 1); | |
1475 | case SCBRR_ALGO_5: | |
1476 | return (((freq * 1000 / 32) / bps) - 1); | |
1477 | } | |
1478 | ||
1479 | /* Warn, but use a safe default */ | |
1480 | WARN_ON(1); | |
e8183a6c | 1481 | |
26c92f37 PM |
1482 | return ((freq + 16 * bps) / (32 * bps) - 1); |
1483 | } | |
1484 | ||
606d099c AC |
1485 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
1486 | struct ktermios *old) | |
1da177e4 | 1487 | { |
00b9de9c | 1488 | struct sci_port *s = to_sci_port(port); |
154280fd | 1489 | unsigned int status, baud, smr_val, max_baud; |
a2159b52 | 1490 | int t = -1; |
3089f381 | 1491 | u16 scfcr = 0; |
1da177e4 | 1492 | |
154280fd MD |
1493 | /* |
1494 | * earlyprintk comes here early on with port->uartclk set to zero. | |
1495 | * the clock framework is not up and running at this point so here | |
1496 | * we assume that 115200 is the maximum baud rate. please note that | |
1497 | * the baud rate is not programmed during earlyprintk - it is assumed | |
1498 | * that the previous boot loader has enabled required clocks and | |
1499 | * setup the baud rate generator hardware for us already. | |
1500 | */ | |
1501 | max_baud = port->uartclk ? port->uartclk / 16 : 115200; | |
1da177e4 | 1502 | |
154280fd MD |
1503 | baud = uart_get_baud_rate(port, termios, old, 0, max_baud); |
1504 | if (likely(baud && port->uartclk)) | |
ce6738b6 | 1505 | t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); |
e108b2ca | 1506 | |
1da177e4 LT |
1507 | do { |
1508 | status = sci_in(port, SCxSR); | |
1509 | } while (!(status & SCxSR_TEND(port))); | |
1510 | ||
1511 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ | |
1512 | ||
1a22f08d | 1513 | if (port->type != PORT_SCI) |
3089f381 | 1514 | sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST); |
1da177e4 LT |
1515 | |
1516 | smr_val = sci_in(port, SCSMR) & 3; | |
e8183a6c | 1517 | |
1da177e4 LT |
1518 | if ((termios->c_cflag & CSIZE) == CS7) |
1519 | smr_val |= 0x40; | |
1520 | if (termios->c_cflag & PARENB) | |
1521 | smr_val |= 0x20; | |
1522 | if (termios->c_cflag & PARODD) | |
1523 | smr_val |= 0x30; | |
1524 | if (termios->c_cflag & CSTOPB) | |
1525 | smr_val |= 0x08; | |
1526 | ||
1527 | uart_update_timeout(port, termios->c_cflag, baud); | |
1528 | ||
1529 | sci_out(port, SCSMR, smr_val); | |
1530 | ||
73a19e4c | 1531 | dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t, |
ce6738b6 | 1532 | s->cfg->scscr); |
73a19e4c | 1533 | |
1da177e4 | 1534 | if (t > 0) { |
e7c98dc7 | 1535 | if (t >= 256) { |
1da177e4 LT |
1536 | sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); |
1537 | t >>= 2; | |
e7c98dc7 | 1538 | } else |
1da177e4 | 1539 | sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); |
e7c98dc7 | 1540 | |
1da177e4 LT |
1541 | sci_out(port, SCBRR, t); |
1542 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ | |
1543 | } | |
1544 | ||
d5701647 | 1545 | sci_init_pins(port, termios->c_cflag); |
3089f381 | 1546 | sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0)); |
b7a76e4b | 1547 | |
ce6738b6 | 1548 | sci_out(port, SCSCR, s->cfg->scscr); |
1da177e4 | 1549 | |
3089f381 GL |
1550 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1551 | /* | |
1552 | * Calculate delay for 1.5 DMA buffers: see | |
1553 | * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits | |
1554 | * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function | |
1555 | * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." | |
1556 | * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO | |
1557 | * sizes), but it has been found out experimentally, that this is not | |
1558 | * enough: the driver too often needlessly runs on a DMA timeout. 20ms | |
1559 | * as a minimum seem to work perfectly. | |
1560 | */ | |
1561 | if (s->chan_rx) { | |
1562 | s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / | |
1563 | port->fifosize / 2; | |
1564 | dev_dbg(port->dev, | |
1565 | "DMA Rx t-out %ums, tty t-out %u jiffies\n", | |
1566 | s->rx_timeout * 1000 / HZ, port->timeout); | |
1567 | if (s->rx_timeout < msecs_to_jiffies(20)) | |
1568 | s->rx_timeout = msecs_to_jiffies(20); | |
1569 | } | |
1570 | #endif | |
1571 | ||
1da177e4 | 1572 | if ((termios->c_cflag & CREAD) != 0) |
73a19e4c | 1573 | sci_start_rx(port); |
1da177e4 LT |
1574 | } |
1575 | ||
1576 | static const char *sci_type(struct uart_port *port) | |
1577 | { | |
1578 | switch (port->type) { | |
e7c98dc7 MT |
1579 | case PORT_IRDA: |
1580 | return "irda"; | |
1581 | case PORT_SCI: | |
1582 | return "sci"; | |
1583 | case PORT_SCIF: | |
1584 | return "scif"; | |
1585 | case PORT_SCIFA: | |
1586 | return "scifa"; | |
d1d4b10c GL |
1587 | case PORT_SCIFB: |
1588 | return "scifb"; | |
1da177e4 LT |
1589 | } |
1590 | ||
fa43972f | 1591 | return NULL; |
1da177e4 LT |
1592 | } |
1593 | ||
e2651647 | 1594 | static inline unsigned long sci_port_size(struct uart_port *port) |
1da177e4 | 1595 | { |
e2651647 PM |
1596 | /* |
1597 | * Pick an arbitrary size that encapsulates all of the base | |
1598 | * registers by default. This can be optimized later, or derived | |
1599 | * from platform resource data at such a time that ports begin to | |
1600 | * behave more erratically. | |
1601 | */ | |
1602 | return 64; | |
1da177e4 LT |
1603 | } |
1604 | ||
e2651647 | 1605 | static void sci_release_port(struct uart_port *port) |
1da177e4 | 1606 | { |
e2651647 PM |
1607 | if (port->flags & UPF_IOREMAP) { |
1608 | iounmap(port->membase); | |
1609 | port->membase = NULL; | |
1610 | } | |
1611 | ||
1612 | release_mem_region(port->mapbase, sci_port_size(port)); | |
1da177e4 LT |
1613 | } |
1614 | ||
e2651647 | 1615 | static int sci_request_port(struct uart_port *port) |
1da177e4 | 1616 | { |
e2651647 PM |
1617 | unsigned long size = sci_port_size(port); |
1618 | struct resource *res; | |
1da177e4 | 1619 | |
e2651647 PM |
1620 | res = request_mem_region(port->mapbase, size, sci_type(port)); |
1621 | if (unlikely(res == NULL)) | |
1622 | return -EBUSY; | |
1da177e4 | 1623 | |
08f8cb31 | 1624 | if (port->flags & UPF_IOREMAP) { |
e2651647 PM |
1625 | port->membase = ioremap_nocache(port->mapbase, size); |
1626 | if (unlikely(!port->membase)) { | |
08f8cb31 | 1627 | dev_err(port->dev, "can't remap port#%d\n", port->line); |
e2651647 PM |
1628 | release_resource(res); |
1629 | return -ENXIO; | |
1630 | } | |
08f8cb31 MD |
1631 | } else { |
1632 | /* | |
1633 | * For the simple (and majority of) cases where we don't | |
1634 | * need to do any remapping, just cast the cookie | |
1635 | * directly. | |
1636 | */ | |
1637 | port->membase = (void __iomem *)port->mapbase; | |
7ff731ae | 1638 | } |
e2651647 PM |
1639 | |
1640 | return 0; | |
1641 | } | |
1642 | ||
1643 | static void sci_config_port(struct uart_port *port, int flags) | |
1644 | { | |
1645 | if (flags & UART_CONFIG_TYPE) { | |
1646 | struct sci_port *sport = to_sci_port(port); | |
1647 | ||
1648 | port->type = sport->cfg->type; | |
1649 | sci_request_port(port); | |
1650 | } | |
1da177e4 LT |
1651 | } |
1652 | ||
1653 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1654 | { | |
a5660ada | 1655 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1656 | |
ce6738b6 | 1657 | if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) |
1da177e4 LT |
1658 | return -EINVAL; |
1659 | if (ser->baud_base < 2400) | |
1660 | /* No paper tape reader for Mitch.. */ | |
1661 | return -EINVAL; | |
1662 | ||
1663 | return 0; | |
1664 | } | |
1665 | ||
1666 | static struct uart_ops sci_uart_ops = { | |
1667 | .tx_empty = sci_tx_empty, | |
1668 | .set_mctrl = sci_set_mctrl, | |
1669 | .get_mctrl = sci_get_mctrl, | |
1670 | .start_tx = sci_start_tx, | |
1671 | .stop_tx = sci_stop_tx, | |
1672 | .stop_rx = sci_stop_rx, | |
1673 | .enable_ms = sci_enable_ms, | |
1674 | .break_ctl = sci_break_ctl, | |
1675 | .startup = sci_startup, | |
1676 | .shutdown = sci_shutdown, | |
1677 | .set_termios = sci_set_termios, | |
1678 | .type = sci_type, | |
1679 | .release_port = sci_release_port, | |
1680 | .request_port = sci_request_port, | |
1681 | .config_port = sci_config_port, | |
1682 | .verify_port = sci_verify_port, | |
07d2a1a1 PM |
1683 | #ifdef CONFIG_CONSOLE_POLL |
1684 | .poll_get_char = sci_poll_get_char, | |
1685 | .poll_put_char = sci_poll_put_char, | |
1686 | #endif | |
1da177e4 LT |
1687 | }; |
1688 | ||
c7ed1ab3 PM |
1689 | static int __devinit sci_init_single(struct platform_device *dev, |
1690 | struct sci_port *sci_port, | |
1691 | unsigned int index, | |
1692 | struct plat_sci_port *p) | |
e108b2ca | 1693 | { |
73a19e4c | 1694 | struct uart_port *port = &sci_port->port; |
e108b2ca | 1695 | |
73a19e4c GL |
1696 | port->ops = &sci_uart_ops; |
1697 | port->iotype = UPIO_MEM; | |
1698 | port->line = index; | |
75136d48 MP |
1699 | |
1700 | switch (p->type) { | |
d1d4b10c GL |
1701 | case PORT_SCIFB: |
1702 | port->fifosize = 256; | |
1703 | break; | |
75136d48 | 1704 | case PORT_SCIFA: |
73a19e4c | 1705 | port->fifosize = 64; |
75136d48 MP |
1706 | break; |
1707 | case PORT_SCIF: | |
73a19e4c | 1708 | port->fifosize = 16; |
75136d48 MP |
1709 | break; |
1710 | default: | |
73a19e4c | 1711 | port->fifosize = 1; |
75136d48 MP |
1712 | break; |
1713 | } | |
7b6fd3bf MD |
1714 | |
1715 | if (dev) { | |
c7ed1ab3 PM |
1716 | sci_port->iclk = clk_get(&dev->dev, "sci_ick"); |
1717 | if (IS_ERR(sci_port->iclk)) { | |
1718 | sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); | |
1719 | if (IS_ERR(sci_port->iclk)) { | |
1720 | dev_err(&dev->dev, "can't get iclk\n"); | |
1721 | return PTR_ERR(sci_port->iclk); | |
1722 | } | |
1723 | } | |
1724 | ||
1725 | /* | |
1726 | * The function clock is optional, ignore it if we can't | |
1727 | * find it. | |
1728 | */ | |
1729 | sci_port->fclk = clk_get(&dev->dev, "sci_fck"); | |
1730 | if (IS_ERR(sci_port->fclk)) | |
1731 | sci_port->fclk = NULL; | |
1732 | ||
7b6fd3bf MD |
1733 | sci_port->enable = sci_clk_enable; |
1734 | sci_port->disable = sci_clk_disable; | |
73a19e4c | 1735 | port->dev = &dev->dev; |
7b6fd3bf | 1736 | } |
e108b2ca | 1737 | |
7ed7e071 MD |
1738 | sci_port->break_timer.data = (unsigned long)sci_port; |
1739 | sci_port->break_timer.function = sci_break_timer; | |
1740 | init_timer(&sci_port->break_timer); | |
1741 | ||
ce6738b6 | 1742 | sci_port->cfg = p; |
7ed7e071 | 1743 | |
ce6738b6 PM |
1744 | port->mapbase = p->mapbase; |
1745 | port->type = p->type; | |
f43dc23d | 1746 | port->flags = p->flags; |
73a19e4c | 1747 | |
ce6738b6 PM |
1748 | /* |
1749 | * The UART port needs an IRQ value, so we peg this to the TX IRQ | |
1750 | * for the multi-IRQ ports, which is where we are primarily | |
1751 | * concerned with the shutdown path synchronization. | |
1752 | * | |
1753 | * For the muxed case there's nothing more to do. | |
1754 | */ | |
1755 | port->irq = p->irqs[SCIx_TXI_IRQ]; | |
73a19e4c | 1756 | |
ce6738b6 PM |
1757 | if (p->dma_dev) |
1758 | dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n", | |
1759 | p->dma_dev, p->dma_slave_tx, p->dma_slave_rx); | |
7ed7e071 | 1760 | |
c7ed1ab3 | 1761 | return 0; |
e108b2ca PM |
1762 | } |
1763 | ||
1da177e4 | 1764 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
dc8e6f5b MD |
1765 | static struct tty_driver *serial_console_device(struct console *co, int *index) |
1766 | { | |
1767 | struct uart_driver *p = &sci_uart_driver; | |
1768 | *index = co->index; | |
1769 | return p->tty_driver; | |
1770 | } | |
1771 | ||
1772 | static void serial_console_putchar(struct uart_port *port, int ch) | |
1773 | { | |
1774 | sci_poll_put_char(port, ch); | |
1775 | } | |
1776 | ||
1da177e4 LT |
1777 | /* |
1778 | * Print a string to the serial port trying not to disturb | |
1779 | * any possible real use of the port... | |
1780 | */ | |
1781 | static void serial_console_write(struct console *co, const char *s, | |
1782 | unsigned count) | |
1783 | { | |
dc8e6f5b | 1784 | struct uart_port *port = co->data; |
501b825d | 1785 | struct sci_port *sci_port = to_sci_port(port); |
973e5d52 | 1786 | unsigned short bits; |
07d2a1a1 | 1787 | |
501b825d MD |
1788 | if (sci_port->enable) |
1789 | sci_port->enable(port); | |
1790 | ||
1791 | uart_console_write(port, s, count, serial_console_putchar); | |
973e5d52 MD |
1792 | |
1793 | /* wait until fifo is empty and last bit has been transmitted */ | |
1794 | bits = SCxSR_TDxE(port) | SCxSR_TEND(port); | |
1795 | while ((sci_in(port, SCxSR) & bits) != bits) | |
1796 | cpu_relax(); | |
501b825d | 1797 | |
345e5a76 | 1798 | if (sci_port->disable) |
501b825d | 1799 | sci_port->disable(port); |
1da177e4 LT |
1800 | } |
1801 | ||
7b6fd3bf | 1802 | static int __devinit serial_console_setup(struct console *co, char *options) |
1da177e4 | 1803 | { |
dc8e6f5b | 1804 | struct sci_port *sci_port; |
1da177e4 LT |
1805 | struct uart_port *port; |
1806 | int baud = 115200; | |
1807 | int bits = 8; | |
1808 | int parity = 'n'; | |
1809 | int flow = 'n'; | |
1810 | int ret; | |
1811 | ||
e108b2ca PM |
1812 | /* |
1813 | * Check whether an invalid uart number has been specified, and | |
1814 | * if so, search for the first available port that does have | |
1815 | * console support. | |
1816 | */ | |
1817 | if (co->index >= SCI_NPORTS) | |
1818 | co->index = 0; | |
1819 | ||
7b6fd3bf MD |
1820 | if (co->data) { |
1821 | port = co->data; | |
1822 | sci_port = to_sci_port(port); | |
1823 | } else { | |
1824 | sci_port = &sci_ports[co->index]; | |
1825 | port = &sci_port->port; | |
1826 | co->data = port; | |
1827 | } | |
1da177e4 LT |
1828 | |
1829 | /* | |
e108b2ca PM |
1830 | * Also need to check port->type, we don't actually have any |
1831 | * UPIO_PORT ports, but uart_report_port() handily misreports | |
1832 | * it anyways if we don't have a port available by the time this is | |
1833 | * called. | |
1da177e4 | 1834 | */ |
e108b2ca PM |
1835 | if (!port->type) |
1836 | return -ENODEV; | |
e108b2ca | 1837 | |
08f8cb31 | 1838 | sci_config_port(port, 0); |
e108b2ca | 1839 | |
dc8e6f5b MD |
1840 | if (sci_port->enable) |
1841 | sci_port->enable(port); | |
b7a76e4b | 1842 | |
1da177e4 LT |
1843 | if (options) |
1844 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1845 | ||
1846 | ret = uart_set_options(port, co, baud, parity, bits, flow); | |
1847 | #if defined(__H8300H__) || defined(__H8300S__) | |
1848 | /* disable rx interrupt */ | |
1849 | if (ret == 0) | |
1850 | sci_stop_rx(port); | |
1851 | #endif | |
501b825d | 1852 | /* TODO: disable clock */ |
1da177e4 LT |
1853 | return ret; |
1854 | } | |
1855 | ||
1856 | static struct console serial_console = { | |
1857 | .name = "ttySC", | |
dc8e6f5b | 1858 | .device = serial_console_device, |
1da177e4 LT |
1859 | .write = serial_console_write, |
1860 | .setup = serial_console_setup, | |
fa5da2f7 | 1861 | .flags = CON_PRINTBUFFER, |
1da177e4 | 1862 | .index = -1, |
1da177e4 LT |
1863 | }; |
1864 | ||
1865 | static int __init sci_console_init(void) | |
1866 | { | |
1867 | register_console(&serial_console); | |
1868 | return 0; | |
1869 | } | |
1da177e4 | 1870 | console_initcall(sci_console_init); |
7b6fd3bf MD |
1871 | |
1872 | static struct sci_port early_serial_port; | |
1873 | static struct console early_serial_console = { | |
1874 | .name = "early_ttySC", | |
1875 | .write = serial_console_write, | |
1876 | .flags = CON_PRINTBUFFER, | |
1877 | }; | |
1878 | static char early_serial_buf[32]; | |
1879 | ||
1da177e4 LT |
1880 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1881 | ||
07d2a1a1 | 1882 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
e7c98dc7 | 1883 | #define SCI_CONSOLE (&serial_console) |
1da177e4 | 1884 | #else |
b7a76e4b | 1885 | #define SCI_CONSOLE 0 |
1da177e4 LT |
1886 | #endif |
1887 | ||
1888 | static char banner[] __initdata = | |
1889 | KERN_INFO "SuperH SCI(F) driver initialized\n"; | |
1890 | ||
1891 | static struct uart_driver sci_uart_driver = { | |
1892 | .owner = THIS_MODULE, | |
1893 | .driver_name = "sci", | |
1da177e4 LT |
1894 | .dev_name = "ttySC", |
1895 | .major = SCI_MAJOR, | |
1896 | .minor = SCI_MINOR_START, | |
e108b2ca | 1897 | .nr = SCI_NPORTS, |
1da177e4 LT |
1898 | .cons = SCI_CONSOLE, |
1899 | }; | |
1900 | ||
54507f6e | 1901 | static int sci_remove(struct platform_device *dev) |
e552de24 | 1902 | { |
d535a230 | 1903 | struct sci_port *port = platform_get_drvdata(dev); |
e552de24 | 1904 | |
d535a230 PM |
1905 | cpufreq_unregister_notifier(&port->freq_transition, |
1906 | CPUFREQ_TRANSITION_NOTIFIER); | |
e552de24 | 1907 | |
d535a230 PM |
1908 | uart_remove_one_port(&sci_uart_driver, &port->port); |
1909 | ||
1910 | clk_put(port->iclk); | |
1911 | clk_put(port->fclk); | |
e552de24 | 1912 | |
e552de24 MD |
1913 | return 0; |
1914 | } | |
1915 | ||
0ee70712 MD |
1916 | static int __devinit sci_probe_single(struct platform_device *dev, |
1917 | unsigned int index, | |
1918 | struct plat_sci_port *p, | |
1919 | struct sci_port *sciport) | |
1920 | { | |
0ee70712 MD |
1921 | int ret; |
1922 | ||
1923 | /* Sanity check */ | |
1924 | if (unlikely(index >= SCI_NPORTS)) { | |
1925 | dev_notice(&dev->dev, "Attempting to register port " | |
1926 | "%d when only %d are available.\n", | |
1927 | index+1, SCI_NPORTS); | |
1928 | dev_notice(&dev->dev, "Consider bumping " | |
1929 | "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); | |
1930 | return 0; | |
1931 | } | |
1932 | ||
c7ed1ab3 PM |
1933 | ret = sci_init_single(dev, sciport, index, p); |
1934 | if (ret) | |
1935 | return ret; | |
0ee70712 | 1936 | |
d535a230 | 1937 | return uart_add_one_port(&sci_uart_driver, &sciport->port); |
0ee70712 MD |
1938 | } |
1939 | ||
e108b2ca PM |
1940 | /* |
1941 | * Register a set of serial devices attached to a platform device. The | |
1942 | * list is terminated with a zero flags entry, which means we expect | |
1943 | * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need | |
1944 | * remapping (such as sh64) should also set UPF_IOREMAP. | |
1945 | */ | |
1946 | static int __devinit sci_probe(struct platform_device *dev) | |
1da177e4 | 1947 | { |
e108b2ca | 1948 | struct plat_sci_port *p = dev->dev.platform_data; |
d535a230 PM |
1949 | struct sci_port *sp = &sci_ports[dev->id]; |
1950 | int ret = -EINVAL; | |
e552de24 | 1951 | |
7b6fd3bf MD |
1952 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
1953 | if (is_early_platform_device(dev)) { | |
7b6fd3bf MD |
1954 | early_serial_console.index = dev->id; |
1955 | early_serial_console.data = &early_serial_port.port; | |
d535a230 | 1956 | |
7b6fd3bf | 1957 | sci_init_single(NULL, &early_serial_port, dev->id, p); |
d535a230 | 1958 | |
7b6fd3bf | 1959 | serial_console_setup(&early_serial_console, early_serial_buf); |
d535a230 | 1960 | |
7b6fd3bf MD |
1961 | if (!strstr(early_serial_buf, "keep")) |
1962 | early_serial_console.flags |= CON_BOOT; | |
d535a230 | 1963 | |
7b6fd3bf MD |
1964 | register_console(&early_serial_console); |
1965 | return 0; | |
1966 | } | |
1967 | #endif | |
1968 | ||
d535a230 | 1969 | platform_set_drvdata(dev, sp); |
e552de24 | 1970 | |
d535a230 PM |
1971 | ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]); |
1972 | if (ret) | |
1973 | goto err_unreg; | |
e552de24 | 1974 | |
d535a230 | 1975 | sp->freq_transition.notifier_call = sci_notifier; |
1da177e4 | 1976 | |
d535a230 PM |
1977 | ret = cpufreq_register_notifier(&sp->freq_transition, |
1978 | CPUFREQ_TRANSITION_NOTIFIER); | |
1979 | if (unlikely(ret < 0)) | |
1980 | goto err_unreg; | |
1da177e4 LT |
1981 | |
1982 | #ifdef CONFIG_SH_STANDARD_BIOS | |
1983 | sh_bios_gdb_detach(); | |
1984 | #endif | |
1985 | ||
e108b2ca | 1986 | return 0; |
7ff731ae PM |
1987 | |
1988 | err_unreg: | |
e552de24 | 1989 | sci_remove(dev); |
7ff731ae | 1990 | return ret; |
1da177e4 LT |
1991 | } |
1992 | ||
6daa79b3 | 1993 | static int sci_suspend(struct device *dev) |
1da177e4 | 1994 | { |
d535a230 | 1995 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 1996 | |
d535a230 PM |
1997 | if (sport) |
1998 | uart_suspend_port(&sci_uart_driver, &sport->port); | |
1da177e4 | 1999 | |
e108b2ca PM |
2000 | return 0; |
2001 | } | |
1da177e4 | 2002 | |
6daa79b3 | 2003 | static int sci_resume(struct device *dev) |
e108b2ca | 2004 | { |
d535a230 | 2005 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 2006 | |
d535a230 PM |
2007 | if (sport) |
2008 | uart_resume_port(&sci_uart_driver, &sport->port); | |
e108b2ca PM |
2009 | |
2010 | return 0; | |
2011 | } | |
2012 | ||
47145210 | 2013 | static const struct dev_pm_ops sci_dev_pm_ops = { |
6daa79b3 PM |
2014 | .suspend = sci_suspend, |
2015 | .resume = sci_resume, | |
2016 | }; | |
2017 | ||
e108b2ca PM |
2018 | static struct platform_driver sci_driver = { |
2019 | .probe = sci_probe, | |
b9e39c89 | 2020 | .remove = sci_remove, |
e108b2ca PM |
2021 | .driver = { |
2022 | .name = "sh-sci", | |
2023 | .owner = THIS_MODULE, | |
6daa79b3 | 2024 | .pm = &sci_dev_pm_ops, |
e108b2ca PM |
2025 | }, |
2026 | }; | |
2027 | ||
2028 | static int __init sci_init(void) | |
2029 | { | |
2030 | int ret; | |
2031 | ||
2032 | printk(banner); | |
2033 | ||
e108b2ca PM |
2034 | ret = uart_register_driver(&sci_uart_driver); |
2035 | if (likely(ret == 0)) { | |
2036 | ret = platform_driver_register(&sci_driver); | |
2037 | if (unlikely(ret)) | |
2038 | uart_unregister_driver(&sci_uart_driver); | |
2039 | } | |
2040 | ||
2041 | return ret; | |
2042 | } | |
2043 | ||
2044 | static void __exit sci_exit(void) | |
2045 | { | |
2046 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
2047 | uart_unregister_driver(&sci_uart_driver); |
2048 | } | |
2049 | ||
7b6fd3bf MD |
2050 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
2051 | early_platform_init_buffer("earlyprintk", &sci_driver, | |
2052 | early_serial_buf, ARRAY_SIZE(early_serial_buf)); | |
2053 | #endif | |
1da177e4 LT |
2054 | module_init(sci_init); |
2055 | module_exit(sci_exit); | |
2056 | ||
e108b2ca | 2057 | MODULE_LICENSE("GPL"); |
e169c139 | 2058 | MODULE_ALIAS("platform:sh-sci"); |