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Merge branch 'sh/driver-core' into sh/clkfwk
[deliverable/linux.git] / drivers / serial / sh-sci.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
7ff731ae 6 * Copyright (C) 2002 - 2008 Paul Mundt
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
0b3d4ef6
PM		 22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
1da177e4
LT		 25
26#undef DEBUG
27
1da177e4
LT		 28#include <linux/module.h>
29#include <linux/errno.h>
1da177e4
LT		 30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial.h>
35#include <linux/major.h>
36#include <linux/string.h>
37#include <linux/sysrq.h>
1da177e4
LT		 38#include <linux/ioport.h>
39#include <linux/mm.h>
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
e108b2ca 43#include <linux/platform_device.h>
96de1a8f 44#include <linux/serial_sci.h>
1da177e4
LT		 45#include <linux/notifier.h>
46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
e552de24 50#include <linux/list.h>
73a19e4c
GL		 51#include <linux/dmaengine.h>
52#include <linux/scatterlist.h>
53#include <linux/timer.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
168f3623
YS		 59#ifdef CONFIG_H8300
60#include <asm/gpio.h>
61#endif
62
1da177e4
LT		 63#include "sh-sci.h"
64
e108b2ca
PM		 65struct sci_port {
66 struct uart_port port;
67
68 /* Port type */
69 unsigned int type;
70
71 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
32351a28 72 unsigned int irqs[SCIx_NR_IRQS];
e108b2ca 73
e108b2ca
PM		 74 /* Port enable callback */
75 void (*enable)(struct uart_port *port);
76
77 /* Port disable callback */
78 void (*disable)(struct uart_port *port);
79
80 /* Break timer */
81 struct timer_list break_timer;
82 int break_flag;
1534a3b3 83
501b825d
MD		 84 /* Interface clock */
85 struct clk *iclk;
86 /* Data clock */
87 struct clk *dclk;
edad1f20 88
e552de24 89 struct list_head node;
73a19e4c
GL		 90 struct dma_chan *chan_tx;
91 struct dma_chan *chan_rx;
92#ifdef CONFIG_SERIAL_SH_SCI_DMA
93 struct device *dma_dev;
94 enum sh_dmae_slave_chan_id slave_tx;
95 enum sh_dmae_slave_chan_id slave_rx;
96 struct dma_async_tx_descriptor *desc_tx;
97 struct dma_async_tx_descriptor *desc_rx[2];
98 dma_cookie_t cookie_tx;
99 dma_cookie_t cookie_rx[2];
100 dma_cookie_t active_rx;
101 struct scatterlist sg_tx;
102 unsigned int sg_len_tx;
103 struct scatterlist sg_rx[2];
104 size_t buf_len_rx;
105 struct sh_dmae_slave param_tx;
106 struct sh_dmae_slave param_rx;
107 struct work_struct work_tx;
108 struct work_struct work_rx;
109 struct timer_list rx_timer;
110#endif
e552de24
MD		 111};
112
113struct sh_sci_priv {
114 spinlock_t lock;
115 struct list_head ports;
e552de24 116 struct notifier_block clk_nb;
e108b2ca
PM		 117};
118
1da177e4 119/* Function prototypes */
b129a8cc 120static void sci_stop_tx(struct uart_port *port);
1da177e4 121
e108b2ca 122#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 123
e108b2ca
PM		 124static struct sci_port sci_ports[SCI_NPORTS];
125static struct uart_driver sci_uart_driver;
1da177e4 126
e7c98dc7
MT		 127static inline struct sci_port *
128to_sci_port(struct uart_port *uart)
129{
130 return container_of(uart, struct sci_port, port);
131}
132
07d2a1a1 133#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 134
135#ifdef CONFIG_CONSOLE_POLL
e108b2ca
PM		 136static inline void handle_error(struct uart_port *port)
137{
138 /* Clear error flags */
1da177e4
LT		 139 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
140}
141
07d2a1a1 142static int sci_poll_get_char(struct uart_port *port)
1da177e4 143{
1da177e4
LT		 144 unsigned short status;
145 int c;
146
e108b2ca 147 do {
1da177e4
LT		 148 status = sci_in(port, SCxSR);
149 if (status & SCxSR_ERRORS(port)) {
150 handle_error(port);
151 continue;
152 }
153 } while (!(status & SCxSR_RDxF(port)));
07d2a1a1 154
1da177e4 155 c = sci_in(port, SCxRDR);
07d2a1a1 156
e7c98dc7
MT		 157 /* Dummy read */
158 sci_in(port, SCxSR);
1da177e4 159 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 160
161 return c;
162}
1f6fd5c9 163#endif
1da177e4 164
07d2a1a1 165static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 166{
1da177e4
LT		 167 unsigned short status;
168
1da177e4
LT		 169 do {
170 status = sci_in(port, SCxSR);
171 } while (!(status & SCxSR_TDxE(port)));
172
272966c0 173 sci_out(port, SCxTDR, c);
dd0a3e77 174 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 175}
07d2a1a1 176#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 177
15c73aaa 178#if defined(__H8300H__) || defined(__H8300S__)
d5701647 179static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4
LT		 180{
181 int ch = (port->mapbase - SMR0) >> 3;
182
183 /* set DDR regs */
e108b2ca
PM		 184 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
185 h8300_sci_pins[ch].rx,
186 H8300_GPIO_INPUT);
187 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
188 h8300_sci_pins[ch].tx,
189 H8300_GPIO_OUTPUT);
190
1da177e4
LT		 191 /* tx mark output*/
192 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
193}
d5701647
PM		 194#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
195static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
e108b2ca 196{
d5701647
PM		 197 if (port->mapbase == 0xA4400000) {
198 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
199 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
200 } else if (port->mapbase == 0xA4410000)
201 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
9465a54f 202}
31a49c4b 203#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
d5701647 204static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
3ea6bc3d 205{
3ea6bc3d
MB		 206 unsigned short data;
207
208 if (cflag & CRTSCTS) {
209 /* enable RTS/CTS */
210 if (port->mapbase == 0xa4430000) { /* SCIF0 */
211 /* Clear PTCR bit 9-2; enable all scif pins but sck */
d5701647
PM		 212 data = __raw_readw(PORT_PTCR);
213 __raw_writew((data & 0xfc03), PORT_PTCR);
3ea6bc3d
MB		 214 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
215 /* Clear PVCR bit 9-2 */
d5701647
PM		 216 data = __raw_readw(PORT_PVCR);
217 __raw_writew((data & 0xfc03), PORT_PVCR);
3ea6bc3d 218 }
3ea6bc3d
MB		 219 } else {
220 if (port->mapbase == 0xa4430000) { /* SCIF0 */
221 /* Clear PTCR bit 5-2; enable only tx and rx */
d5701647
PM		 222 data = __raw_readw(PORT_PTCR);
223 __raw_writew((data & 0xffc3), PORT_PTCR);
3ea6bc3d
MB		 224 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
225 /* Clear PVCR bit 5-2 */
d5701647
PM		 226 data = __raw_readw(PORT_PVCR);
227 __raw_writew((data & 0xffc3), PORT_PVCR);
3ea6bc3d
MB		 228 }
229 }
3ea6bc3d 230}
b7a76e4b 231#elif defined(CONFIG_CPU_SH3)
e108b2ca 232/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
d5701647 233static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 234{
b7a76e4b
PM		 235 unsigned short data;
236
237 /* We need to set SCPCR to enable RTS/CTS */
d5701647 238 data = __raw_readw(SCPCR);
b7a76e4b 239 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
d5701647 240 __raw_writew(data & 0x0fcf, SCPCR);
1da177e4 241
d5701647 242 if (!(cflag & CRTSCTS)) {
1da177e4 243 /* We need to set SCPCR to enable RTS/CTS */
d5701647 244 data = __raw_readw(SCPCR);
1da177e4
LT		 245 /* Clear out SCP7MD1,0, SCP4MD1,0,
246 Set SCP6MD1,0 = {01} (output) */
d5701647 247 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
1da177e4 248
32b53076 249 data = __raw_readb(SCPDR);
1da177e4 250 /* Set /RTS2 (bit6) = 0 */
32b53076 251 __raw_writeb(data & 0xbf, SCPDR);
1da177e4 252 }
1da177e4 253}
41504c39 254#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
d5701647 255static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
41504c39 256{
346b7463 257 unsigned short data;
41504c39 258
346b7463 259 if (port->mapbase == 0xffe00000) {
d5701647 260 data = __raw_readw(PSCR);
346b7463 261 data &= ~0x03cf;
d5701647 262 if (!(cflag & CRTSCTS))
346b7463 263 data |= 0x0340;
41504c39 264
d5701647 265 __raw_writew(data, PSCR);
41504c39 266 }
178dd0cd 267}
c01f0f1a
YS		 268#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
269 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
7d740a06 270 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac 271 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
55ba99eb 272 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
2b1bd1ac 273 defined(CONFIG_CPU_SUBTYPE_SHX3)
d5701647
PM		 274static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
275{
276 if (!(cflag & CRTSCTS))
277 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
278}
b0c50ad7 279#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
d5701647
PM		 280static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
281{
282 if (!(cflag & CRTSCTS))
283 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
284}
b7a76e4b 285#else
d5701647
PM		 286static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
287{
288 /* Nothing to do */
1da177e4 289}
e108b2ca
PM		 290#endif
291
32351a28
PM		 292#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
293 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 294 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
295 defined(CONFIG_CPU_SUBTYPE_SH7786)
73a19e4c 296static int scif_txfill(struct uart_port *port)
e108b2ca 297{
73a19e4c 298 return sci_in(port, SCTFDR) & 0xff;
e108b2ca
PM		 299}
300
73a19e4c
GL		 301static int scif_txroom(struct uart_port *port)
302{
303 return SCIF_TXROOM_MAX - scif_txfill(port);
304}
305
306static int scif_rxfill(struct uart_port *port)
e108b2ca 307{
cae167d3 308 return sci_in(port, SCRFDR) & 0xff;
e108b2ca 309}
c63847a3 310#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
73a19e4c 311static int scif_txfill(struct uart_port *port)
c63847a3 312{
73a19e4c
GL		 313 if (port->mapbase == 0xffe00000 ||
314 port->mapbase == 0xffe08000)
e7c98dc7 315 /* SCIF0/1*/
73a19e4c
GL		 316 return sci_in(port, SCTFDR) & 0xff;
317 else
e7c98dc7 318 /* SCIF2 */
73a19e4c
GL		 319 return sci_in(port, SCFDR) >> 8;
320}
321
322static int scif_txroom(struct uart_port *port)
323{
324 if (port->mapbase == 0xffe00000 ||
325 port->mapbase == 0xffe08000)
326 /* SCIF0/1*/
327 return SCIF_TXROOM_MAX - scif_txfill(port);
328 else
329 /* SCIF2 */
330 return SCIF2_TXROOM_MAX - scif_txfill(port);
c63847a3
NI		 331}
332
73a19e4c 333static int scif_rxfill(struct uart_port *port)
c63847a3 334{
e7c98dc7
MT		 335 if ((port->mapbase == 0xffe00000) ||
336 (port->mapbase == 0xffe08000)) {
337 /* SCIF0/1*/
c63847a3 338 return sci_in(port, SCRFDR) & 0xff;
e7c98dc7
MT		 339 } else {
340 /* SCIF2 */
c63847a3 341 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
e7c98dc7 342 }
c63847a3 343}
e108b2ca 344#else
73a19e4c 345static int scif_txfill(struct uart_port *port)
e108b2ca 346{
73a19e4c 347 return sci_in(port, SCFDR) >> 8;
e108b2ca 348}
1da177e4 349
73a19e4c
GL		 350static int scif_txroom(struct uart_port *port)
351{
352 return SCIF_TXROOM_MAX - scif_txfill(port);
353}
354
355static int scif_rxfill(struct uart_port *port)
e108b2ca
PM		 356{
357 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
358}
1da177e4 359#endif
1da177e4 360
73a19e4c 361static int sci_txfill(struct uart_port *port)
e108b2ca 362{
73a19e4c 363 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 364}
365
73a19e4c
GL		 366static int sci_txroom(struct uart_port *port)
367{
368 return !sci_txfill(port);
369}
370
371static int sci_rxfill(struct uart_port *port)
e108b2ca 372{
e7c98dc7 373 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 374}
375
1da177e4
LT		 376/* ********************************************************************** *
377 * the interrupt related routines *
378 * ********************************************************************** */
379
380static void sci_transmit_chars(struct uart_port *port)
381{
ebd2c8f6 382 struct circ_buf *xmit = &port->state->xmit;
1da177e4 383 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 384 unsigned short status;
385 unsigned short ctrl;
e108b2ca 386 int count;
1da177e4
LT		 387
388 status = sci_in(port, SCxSR);
389 if (!(status & SCxSR_TDxE(port))) {
1da177e4 390 ctrl = sci_in(port, SCSCR);
e7c98dc7 391 if (uart_circ_empty(xmit))
1da177e4 392 ctrl &= ~SCI_CTRL_FLAGS_TIE;
e7c98dc7 393 else
1da177e4 394 ctrl |= SCI_CTRL_FLAGS_TIE;
1da177e4 395 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 396 return;
397 }
398
1a22f08d 399 if (port->type == PORT_SCI)
e108b2ca 400 count = sci_txroom(port);
1a22f08d
YS		 401 else
402 count = scif_txroom(port);
1da177e4
LT		 403
404 do {
405 unsigned char c;
406
407 if (port->x_char) {
408 c = port->x_char;
409 port->x_char = 0;
410 } else if (!uart_circ_empty(xmit) && !stopped) {
411 c = xmit->buf[xmit->tail];
412 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
413 } else {
414 break;
415 }
416
417 sci_out(port, SCxTDR, c);
418
419 port->icount.tx++;
420 } while (--count > 0);
421
422 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
423
424 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
425 uart_write_wakeup(port);
426 if (uart_circ_empty(xmit)) {
b129a8cc 427 sci_stop_tx(port);
1da177e4 428 } else {
1da177e4
LT		 429 ctrl = sci_in(port, SCSCR);
430
1a22f08d 431 if (port->type != PORT_SCI) {
1da177e4
LT		 432 sci_in(port, SCxSR); /* Dummy read */
433 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
434 }
1da177e4
LT		 435
436 ctrl |= SCI_CTRL_FLAGS_TIE;
437 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 438 }
439}
440
441/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 442#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 443
7d12e780 444static inline void sci_receive_chars(struct uart_port *port)
1da177e4 445{
e7c98dc7 446 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 447 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 448 int i, count, copied = 0;
449 unsigned short status;
33f0f88f 450 unsigned char flag;
1da177e4
LT		 451
452 status = sci_in(port, SCxSR);
453 if (!(status & SCxSR_RDxF(port)))
454 return;
455
456 while (1) {
1a22f08d 457 if (port->type == PORT_SCI)
73a19e4c 458 count = sci_rxfill(port);
1a22f08d 459 else
73a19e4c 460 count = scif_rxfill(port);
1da177e4
LT		 461
462 /* Don't copy more bytes than there is room for in the buffer */
33f0f88f 463 count = tty_buffer_request_room(tty, count);
1da177e4
LT		 464
465 /* If for any reason we can't copy more data, we're done! */
466 if (count == 0)
467 break;
468
469 if (port->type == PORT_SCI) {
470 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 471 if (uart_handle_sysrq_char(port, c) ||
472 sci_port->break_flag)
1da177e4 473 count = 0;
e7c98dc7 474 else
e108b2ca 475 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 476 } else {
e7c98dc7 477 for (i = 0; i < count; i++) {
1da177e4
LT		 478 char c = sci_in(port, SCxRDR);
479 status = sci_in(port, SCxSR);
480#if defined(CONFIG_CPU_SH3)
481 /* Skip "chars" during break */
e108b2ca 482 if (sci_port->break_flag) {
1da177e4
LT		 483 if ((c == 0) &&
484 (status & SCxSR_FER(port))) {
485 count--; i--;
486 continue;
487 }
e108b2ca 488
1da177e4 489 /* Nonzero => end-of-break */
762c69e3 490 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 491 sci_port->break_flag = 0;
492
1da177e4
LT		 493 if (STEPFN(c)) {
494 count--; i--;
495 continue;
496 }
497 }
498#endif /* CONFIG_CPU_SH3 */
7d12e780 499 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 500 count--; i--;
501 continue;
502 }
503
504 /* Store data and status */
73a19e4c 505 if (status & SCxSR_FER(port)) {
33f0f88f 506 flag = TTY_FRAME;
762c69e3 507 dev_notice(port->dev, "frame error\n");
73a19e4c 508 } else if (status & SCxSR_PER(port)) {
33f0f88f 509 flag = TTY_PARITY;
762c69e3 510 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 511 } else
512 flag = TTY_NORMAL;
762c69e3 513
33f0f88f 514 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 515 }
516 }
517
518 sci_in(port, SCxSR); /* dummy read */
519 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
520
1da177e4
LT		 521 copied += count;
522 port->icount.rx += count;
523 }
524
525 if (copied) {
526 /* Tell the rest of the system the news. New characters! */
527 tty_flip_buffer_push(tty);
528 } else {
529 sci_in(port, SCxSR); /* dummy read */
530 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
531 }
532}
533
534#define SCI_BREAK_JIFFIES (HZ/20)
535/* The sci generates interrupts during the break,
536 * 1 per millisecond or so during the break period, for 9600 baud.
537 * So dont bother disabling interrupts.
538 * But dont want more than 1 break event.
539 * Use a kernel timer to periodically poll the rx line until
540 * the break is finished.
541 */
542static void sci_schedule_break_timer(struct sci_port *port)
543{
544 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
545 add_timer(&port->break_timer);
546}
547/* Ensure that two consecutive samples find the break over. */
548static void sci_break_timer(unsigned long data)
549{
e108b2ca
PM		 550 struct sci_port *port = (struct sci_port *)data;
551
552 if (sci_rxd_in(&port->port) == 0) {
1da177e4 553 port->break_flag = 1;
e108b2ca
PM		 554 sci_schedule_break_timer(port);
555 } else if (port->break_flag == 1) {
1da177e4
LT		 556 /* break is over. */
557 port->break_flag = 2;
e108b2ca
PM		 558 sci_schedule_break_timer(port);
559 } else
560 port->break_flag = 0;
1da177e4
LT		 561}
562
563static inline int sci_handle_errors(struct uart_port *port)
564{
565 int copied = 0;
566 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 567 struct tty_struct *tty = port->state->port.tty;
1da177e4 568
e108b2ca 569 if (status & SCxSR_ORER(port)) {
1da177e4 570 /* overrun error */
e108b2ca 571 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
33f0f88f 572 copied++;
762c69e3
PM		 573
574 dev_notice(port->dev, "overrun error");
1da177e4
LT		 575 }
576
e108b2ca 577 if (status & SCxSR_FER(port)) {
1da177e4
LT		 578 if (sci_rxd_in(port) == 0) {
579 /* Notify of BREAK */
e7c98dc7 580 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 581
582 if (!sci_port->break_flag) {
583 sci_port->break_flag = 1;
584 sci_schedule_break_timer(sci_port);
585
1da177e4 586 /* Do sysrq handling. */
e108b2ca 587 if (uart_handle_break(port))
1da177e4 588 return 0;
762c69e3
PM		 589
590 dev_dbg(port->dev, "BREAK detected\n");
591
e108b2ca 592 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 593 copied++;
594 }
595
e108b2ca 596 } else {
1da177e4 597 /* frame error */
e108b2ca 598 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 599 copied++;
762c69e3
PM		 600
601 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 602 }
603 }
604
e108b2ca 605 if (status & SCxSR_PER(port)) {
1da177e4 606 /* parity error */
e108b2ca
PM		 607 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
608 copied++;
762c69e3
PM		 609
610 dev_notice(port->dev, "parity error");
1da177e4
LT		 611 }
612
33f0f88f 613 if (copied)
1da177e4 614 tty_flip_buffer_push(tty);
1da177e4
LT		 615
616 return copied;
617}
618
d830fa45
PM		 619static inline int sci_handle_fifo_overrun(struct uart_port *port)
620{
ebd2c8f6 621 struct tty_struct *tty = port->state->port.tty;
d830fa45
PM		 622 int copied = 0;
623
624 if (port->type != PORT_SCIF)
625 return 0;
626
627 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
628 sci_out(port, SCLSR, 0);
629
630 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
631 tty_flip_buffer_push(tty);
632
633 dev_notice(port->dev, "overrun error\n");
634 copied++;
635 }
636
637 return copied;
638}
639
1da177e4
LT		 640static inline int sci_handle_breaks(struct uart_port *port)
641{
642 int copied = 0;
643 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 644 struct tty_struct *tty = port->state->port.tty;
a5660ada 645 struct sci_port *s = to_sci_port(port);
1da177e4 646
0b3d4ef6
PM		 647 if (uart_handle_break(port))
648 return 0;
649
b7a76e4b 650 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 651#if defined(CONFIG_CPU_SH3)
652 /* Debounce break */
653 s->break_flag = 1;
654#endif
655 /* Notify of BREAK */
e108b2ca 656 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 657 copied++;
762c69e3
PM		 658
659 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 660 }
661
33f0f88f 662 if (copied)
1da177e4 663 tty_flip_buffer_push(tty);
e108b2ca 664
d830fa45
PM		 665 copied += sci_handle_fifo_overrun(port);
666
1da177e4
LT		 667 return copied;
668}
669
73a19e4c 670static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 671{
73a19e4c
GL		 672#ifdef CONFIG_SERIAL_SH_SCI_DMA
673 struct uart_port *port = ptr;
674 struct sci_port *s = to_sci_port(port);
675
676 if (s->chan_rx) {
677 unsigned long tout;
678 u16 scr = sci_in(port, SCSCR);
679 u16 ssr = sci_in(port, SCxSR);
680
681 /* Disable future Rx interrupts */
682 sci_out(port, SCSCR, scr & ~SCI_CTRL_FLAGS_RIE);
683 /* Clear current interrupt */
684 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
685 /* Calculate delay for 1.5 DMA buffers */
686 tout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
687 port->fifosize / 2;
c6efd46b 688 dev_dbg(port->dev, "Rx IRQ: setup timeout in %lu ms\n",
73a19e4c
GL		 689 tout * 1000 / HZ);
690 if (tout < 2)
691 tout = 2;
692 mod_timer(&s->rx_timer, jiffies + tout);
693
694 return IRQ_HANDLED;
695 }
696#endif
697
1da177e4
LT		 698 /* I think sci_receive_chars has to be called irrespective
699 * of whether the I_IXOFF is set, otherwise, how is the interrupt
700 * to be disabled?
701 */
73a19e4c 702 sci_receive_chars(ptr);
1da177e4
LT		 703
704 return IRQ_HANDLED;
705}
706
7d12e780 707static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 708{
709 struct uart_port *port = ptr;
fd78a76a 710 unsigned long flags;
1da177e4 711
fd78a76a 712 spin_lock_irqsave(&port->lock, flags);
1da177e4 713 sci_transmit_chars(port);
fd78a76a 714 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 715
716 return IRQ_HANDLED;
717}
718
7d12e780 719static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 720{
721 struct uart_port *port = ptr;
722
723 /* Handle errors */
724 if (port->type == PORT_SCI) {
725 if (sci_handle_errors(port)) {
726 /* discard character in rx buffer */
727 sci_in(port, SCxSR);
728 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
729 }
730 } else {
d830fa45 731 sci_handle_fifo_overrun(port);
7d12e780 732 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 733 }
734
735 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
736
737 /* Kick the transmission */
7d12e780 738 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 739
740 return IRQ_HANDLED;
741}
742
7d12e780 743static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 744{
745 struct uart_port *port = ptr;
746
747 /* Handle BREAKs */
748 sci_handle_breaks(port);
749 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
750
751 return IRQ_HANDLED;
752}
753
7d12e780 754static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 755{
44e18e9e 756 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 757 struct uart_port *port = ptr;
73a19e4c 758 struct sci_port *s = to_sci_port(port);
a8884e34 759 irqreturn_t ret = IRQ_NONE;
1da177e4 760
e7c98dc7
MT		 761 ssr_status = sci_in(port, SCxSR);
762 scr_status = sci_in(port, SCSCR);
44e18e9e 763 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
1da177e4
LT		 764
765 /* Tx Interrupt */
73a19e4c
GL		 766 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) &&
767 !s->chan_tx)
a8884e34 768 ret = sci_tx_interrupt(irq, ptr);
73a19e4c
GL		 769 /*
770 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
771 * DR flags
772 */
773 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
774 (scr_status & SCI_CTRL_FLAGS_RIE))
a8884e34 775 ret = sci_rx_interrupt(irq, ptr);
1da177e4 776 /* Error Interrupt */
dd4da3a5 777 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 778 ret = sci_er_interrupt(irq, ptr);
1da177e4 779 /* Break Interrupt */
dd4da3a5 780 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 781 ret = sci_br_interrupt(irq, ptr);
1da177e4 782
73a19e4c
GL		 783 WARN_ONCE(ret == IRQ_NONE,
784 "%s: %d IRQ %d, status %x, control %x\n", __func__,
785 irq, port->line, ssr_status, scr_status);
786
a8884e34 787 return ret;
1da177e4
LT		 788}
789
1da177e4
LT		 790/*
791 * Here we define a transistion notifier so that we can update all of our
792 * ports' baud rate when the peripheral clock changes.
793 */
e108b2ca
PM		 794static int sci_notifier(struct notifier_block *self,
795 unsigned long phase, void *p)
1da177e4 796{
e552de24
MD		 797 struct sh_sci_priv *priv = container_of(self,
798 struct sh_sci_priv, clk_nb);
799 struct sci_port *sci_port;
800 unsigned long flags;
1da177e4
LT		 801
802 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24
MD		 803 (phase == CPUFREQ_RESUMECHANGE)) {
804 spin_lock_irqsave(&priv->lock, flags);
805 list_for_each_entry(sci_port, &priv->ports, node)
501b825d 806 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
e552de24
MD		 807 spin_unlock_irqrestore(&priv->lock, flags);
808 }
1da177e4 809
1da177e4
LT		 810 return NOTIFY_OK;
811}
501b825d
MD		 812
813static void sci_clk_enable(struct uart_port *port)
814{
815 struct sci_port *sci_port = to_sci_port(port);
816
817 clk_enable(sci_port->dclk);
818 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
819
820 if (sci_port->iclk)
821 clk_enable(sci_port->iclk);
822}
823
824static void sci_clk_disable(struct uart_port *port)
825{
826 struct sci_port *sci_port = to_sci_port(port);
827
828 if (sci_port->iclk)
829 clk_disable(sci_port->iclk);
830
831 clk_disable(sci_port->dclk);
832}
1da177e4
LT		 833
834static int sci_request_irq(struct sci_port *port)
835{
836 int i;
7d12e780 837 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
1da177e4
LT		 838 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
839 sci_br_interrupt,
840 };
841 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
842 "SCI Transmit Data Empty", "SCI Break" };
843
844 if (port->irqs[0] == port->irqs[1]) {
762c69e3 845 if (unlikely(!port->irqs[0]))
1da177e4 846 return -ENODEV;
e108b2ca
PM		 847
848 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
35f3c518 849 IRQF_DISABLED, "sci", port)) {
762c69e3 850 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 851 return -ENODEV;
852 }
853 } else {
854 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
762c69e3 855 if (unlikely(!port->irqs[i]))
1da177e4 856 continue;
762c69e3 857
e108b2ca 858 if (request_irq(port->irqs[i], handlers[i],
35f3c518 859 IRQF_DISABLED, desc[i], port)) {
762c69e3 860 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 861 return -ENODEV;
862 }
863 }
864 }
865
866 return 0;
867}
868
869static void sci_free_irq(struct sci_port *port)
870{
871 int i;
872
762c69e3
PM		 873 if (port->irqs[0] == port->irqs[1])
874 free_irq(port->irqs[0], port);
875 else {
1da177e4
LT		 876 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
877 if (!port->irqs[i])
878 continue;
879
880 free_irq(port->irqs[i], port);
881 }
882 }
883}
884
885static unsigned int sci_tx_empty(struct uart_port *port)
886{
b1516803 887 unsigned short status = sci_in(port, SCxSR);
73a19e4c
GL		 888 unsigned short in_tx_fifo = scif_txfill(port);
889
890 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 891}
892
893static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
894{
895 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
896 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
897 /* If you have signals for DTR and DCD, please implement here. */
898}
899
900static unsigned int sci_get_mctrl(struct uart_port *port)
901{
73a19e4c 902 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1da177e4
LT		 903 and CTS/RTS */
904
905 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
906}
907
73a19e4c
GL		 908#ifdef CONFIG_SERIAL_SH_SCI_DMA
909static void sci_dma_tx_complete(void *arg)
910{
911 struct sci_port *s = arg;
912 struct uart_port *port = &s->port;
913 struct circ_buf *xmit = &port->state->xmit;
914 unsigned long flags;
915
916 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
917
918 spin_lock_irqsave(&port->lock, flags);
919
920 xmit->tail += s->sg_tx.length;
921 xmit->tail &= UART_XMIT_SIZE - 1;
922
923 port->icount.tx += s->sg_tx.length;
924
925 async_tx_ack(s->desc_tx);
926 s->cookie_tx = -EINVAL;
927 s->desc_tx = NULL;
928
929 spin_unlock_irqrestore(&port->lock, flags);
930
931 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
932 uart_write_wakeup(port);
933
934 if (uart_circ_chars_pending(xmit))
935 schedule_work(&s->work_tx);
936}
937
938/* Locking: called with port lock held */
939static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
940 size_t count)
941{
942 struct uart_port *port = &s->port;
943 int i, active, room;
944
945 room = tty_buffer_request_room(tty, count);
946
947 if (s->active_rx == s->cookie_rx[0]) {
948 active = 0;
949 } else if (s->active_rx == s->cookie_rx[1]) {
950 active = 1;
951 } else {
952 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
953 return 0;
954 }
955
956 if (room < count)
957 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
958 count - room);
959 if (!room)
960 return room;
961
962 for (i = 0; i < room; i++)
963 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
964 TTY_NORMAL);
965
966 port->icount.rx += room;
967
968 return room;
969}
970
971static void sci_dma_rx_complete(void *arg)
972{
973 struct sci_port *s = arg;
974 struct uart_port *port = &s->port;
975 struct tty_struct *tty = port->state->port.tty;
976 unsigned long flags;
977 int count;
978
979 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
980
981 spin_lock_irqsave(&port->lock, flags);
982
983 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
984
985 mod_timer(&s->rx_timer, jiffies + msecs_to_jiffies(5));
986
987 spin_unlock_irqrestore(&port->lock, flags);
988
989 if (count)
990 tty_flip_buffer_push(tty);
991
992 schedule_work(&s->work_rx);
993}
994
995static void sci_start_rx(struct uart_port *port);
996static void sci_start_tx(struct uart_port *port);
997
998static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
999{
1000 struct dma_chan *chan = s->chan_rx;
1001 struct uart_port *port = &s->port;
73a19e4c
GL		 1002
1003 s->chan_rx = NULL;
1004 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1005 dma_release_channel(chan);
1006 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1007 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1008 if (enable_pio)
1009 sci_start_rx(port);
1010}
1011
1012static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1013{
1014 struct dma_chan *chan = s->chan_tx;
1015 struct uart_port *port = &s->port;
73a19e4c
GL		 1016
1017 s->chan_tx = NULL;
1018 s->cookie_tx = -EINVAL;
1019 dma_release_channel(chan);
1020 if (enable_pio)
1021 sci_start_tx(port);
1022}
1023
1024static void sci_submit_rx(struct sci_port *s)
1025{
1026 struct dma_chan *chan = s->chan_rx;
1027 int i;
1028
1029 for (i = 0; i < 2; i++) {
1030 struct scatterlist *sg = &s->sg_rx[i];
1031 struct dma_async_tx_descriptor *desc;
1032
1033 desc = chan->device->device_prep_slave_sg(chan,
1034 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1035
1036 if (desc) {
1037 s->desc_rx[i] = desc;
1038 desc->callback = sci_dma_rx_complete;
1039 desc->callback_param = s;
1040 s->cookie_rx[i] = desc->tx_submit(desc);
1041 }
1042
1043 if (!desc || s->cookie_rx[i] < 0) {
1044 if (i) {
1045 async_tx_ack(s->desc_rx[0]);
1046 s->cookie_rx[0] = -EINVAL;
1047 }
1048 if (desc) {
1049 async_tx_ack(desc);
1050 s->cookie_rx[i] = -EINVAL;
1051 }
1052 dev_warn(s->port.dev,
1053 "failed to re-start DMA, using PIO\n");
1054 sci_rx_dma_release(s, true);
1055 return;
1056 }
1057 }
1058
1059 s->active_rx = s->cookie_rx[0];
1060
1061 dma_async_issue_pending(chan);
1062}
1063
1064static void work_fn_rx(struct work_struct *work)
1065{
1066 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1067 struct uart_port *port = &s->port;
1068 struct dma_async_tx_descriptor *desc;
1069 int new;
1070
1071 if (s->active_rx == s->cookie_rx[0]) {
1072 new = 0;
1073 } else if (s->active_rx == s->cookie_rx[1]) {
1074 new = 1;
1075 } else {
1076 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1077 return;
1078 }
1079 desc = s->desc_rx[new];
1080
1081 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1082 DMA_SUCCESS) {
1083 /* Handle incomplete DMA receive */
1084 struct tty_struct *tty = port->state->port.tty;
1085 struct dma_chan *chan = s->chan_rx;
1086 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1087 async_tx);
1088 unsigned long flags;
1089 int count;
1090
1091 chan->device->device_terminate_all(chan);
1092 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1093 sh_desc->partial, sh_desc->cookie);
1094
1095 spin_lock_irqsave(&port->lock, flags);
1096 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1097 spin_unlock_irqrestore(&port->lock, flags);
1098
1099 if (count)
1100 tty_flip_buffer_push(tty);
1101
1102 sci_submit_rx(s);
1103
1104 return;
1105 }
1106
1107 s->cookie_rx[new] = desc->tx_submit(desc);
1108 if (s->cookie_rx[new] < 0) {
1109 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1110 sci_rx_dma_release(s, true);
1111 return;
1112 }
1113
1114 dev_dbg(port->dev, "%s: cookie %d #%d\n", __func__,
1115 s->cookie_rx[new], new);
1116
1117 s->active_rx = s->cookie_rx[!new];
1118}
1119
1120static void work_fn_tx(struct work_struct *work)
1121{
1122 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1123 struct dma_async_tx_descriptor *desc;
1124 struct dma_chan *chan = s->chan_tx;
1125 struct uart_port *port = &s->port;
1126 struct circ_buf *xmit = &port->state->xmit;
1127 struct scatterlist *sg = &s->sg_tx;
1128
1129 /*
1130 * DMA is idle now.
1131 * Port xmit buffer is already mapped, and it is one page... Just adjust
1132 * offsets and lengths. Since it is a circular buffer, we have to
1133 * transmit till the end, and then the rest. Take the port lock to get a
1134 * consistent xmit buffer state.
1135 */
1136 spin_lock_irq(&port->lock);
1137 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1138 sg->dma_address = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1139 sg->offset;
1140 sg->length = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1141 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1142 sg->dma_length = sg->length;
1143 spin_unlock_irq(&port->lock);
1144
1145 BUG_ON(!sg->length);
1146
1147 desc = chan->device->device_prep_slave_sg(chan,
1148 sg, s->sg_len_tx, DMA_TO_DEVICE,
1149 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1150 if (!desc) {
1151 /* switch to PIO */
1152 sci_tx_dma_release(s, true);
1153 return;
1154 }
1155
1156 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1157
1158 spin_lock_irq(&port->lock);
1159 s->desc_tx = desc;
1160 desc->callback = sci_dma_tx_complete;
1161 desc->callback_param = s;
1162 spin_unlock_irq(&port->lock);
1163 s->cookie_tx = desc->tx_submit(desc);
1164 if (s->cookie_tx < 0) {
1165 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1166 /* switch to PIO */
1167 sci_tx_dma_release(s, true);
1168 return;
1169 }
1170
1171 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1172 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1173
1174 dma_async_issue_pending(chan);
1175}
1176#endif
1177
b129a8cc 1178static void sci_start_tx(struct uart_port *port)
1da177e4 1179{
e108b2ca 1180 unsigned short ctrl;
1da177e4 1181
73a19e4c
GL		 1182#ifdef CONFIG_SERIAL_SH_SCI_DMA
1183 struct sci_port *s = to_sci_port(port);
1184
1185 if (s->chan_tx) {
1186 if (!uart_circ_empty(&s->port.state->xmit) && s->cookie_tx < 0)
1187 schedule_work(&s->work_tx);
1188
1189 return;
1190 }
1191#endif
1192
e108b2ca
PM		 1193 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1194 ctrl = sci_in(port, SCSCR);
1195 ctrl |= SCI_CTRL_FLAGS_TIE;
1196 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1197}
1198
b129a8cc 1199static void sci_stop_tx(struct uart_port *port)
1da177e4 1200{
1da177e4
LT		 1201 unsigned short ctrl;
1202
1203 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4
LT		 1204 ctrl = sci_in(port, SCSCR);
1205 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1206 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1207}
1208
73a19e4c 1209static void sci_start_rx(struct uart_port *port)
1da177e4 1210{
73a19e4c 1211 unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
1da177e4
LT		 1212
1213 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
73a19e4c 1214 ctrl |= sci_in(port, SCSCR);
1da177e4 1215 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1216}
1217
1218static void sci_stop_rx(struct uart_port *port)
1219{
1da177e4
LT		 1220 unsigned short ctrl;
1221
1222 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1da177e4
LT		 1223 ctrl = sci_in(port, SCSCR);
1224 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1225 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1226}
1227
1228static void sci_enable_ms(struct uart_port *port)
1229{
1230 /* Nothing here yet .. */
1231}
1232
1233static void sci_break_ctl(struct uart_port *port, int break_state)
1234{
1235 /* Nothing here yet .. */
1236}
1237
73a19e4c
GL		 1238#ifdef CONFIG_SERIAL_SH_SCI_DMA
1239static bool filter(struct dma_chan *chan, void *slave)
1240{
1241 struct sh_dmae_slave *param = slave;
1242
1243 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1244 param->slave_id);
1245
1246 if (param->dma_dev == chan->device->dev) {
1247 chan->private = param;
1248 return true;
1249 } else {
1250 return false;
1251 }
1252}
1253
1254static void rx_timer_fn(unsigned long arg)
1255{
1256 struct sci_port *s = (struct sci_port *)arg;
1257 struct uart_port *port = &s->port;
1258
1259 u16 scr = sci_in(port, SCSCR);
1260 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
1261 dev_dbg(port->dev, "DMA Rx timed out\n");
1262 schedule_work(&s->work_rx);
1263}
1264
1265static void sci_request_dma(struct uart_port *port)
1266{
1267 struct sci_port *s = to_sci_port(port);
1268 struct sh_dmae_slave *param;
1269 struct dma_chan *chan;
1270 dma_cap_mask_t mask;
1271 int nent;
1272
1273 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1274 port->line, s->dma_dev);
1275
1276 if (!s->dma_dev)
1277 return;
1278
1279 dma_cap_zero(mask);
1280 dma_cap_set(DMA_SLAVE, mask);
1281
1282 param = &s->param_tx;
1283
1284 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1285 param->slave_id = s->slave_tx;
1286 param->dma_dev = s->dma_dev;
1287
1288 s->cookie_tx = -EINVAL;
1289 chan = dma_request_channel(mask, filter, param);
1290 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1291 if (chan) {
1292 s->chan_tx = chan;
1293 sg_init_table(&s->sg_tx, 1);
1294 /* UART circular tx buffer is an aligned page. */
1295 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1296 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1297 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1298 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1299 if (!nent)
1300 sci_tx_dma_release(s, false);
1301 else
1302 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1303 sg_dma_len(&s->sg_tx),
1304 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1305
1306 s->sg_len_tx = nent;
1307
1308 INIT_WORK(&s->work_tx, work_fn_tx);
1309 }
1310
1311 param = &s->param_rx;
1312
1313 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1314 param->slave_id = s->slave_rx;
1315 param->dma_dev = s->dma_dev;
1316
1317 chan = dma_request_channel(mask, filter, param);
1318 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1319 if (chan) {
1320 dma_addr_t dma[2];
1321 void *buf[2];
1322 int i;
1323
1324 s->chan_rx = chan;
1325
1326 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1327 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1328 &dma[0], GFP_KERNEL);
1329
1330 if (!buf[0]) {
1331 dev_warn(port->dev,
1332 "failed to allocate dma buffer, using PIO\n");
1333 sci_rx_dma_release(s, true);
1334 return;
1335 }
1336
1337 buf[1] = buf[0] + s->buf_len_rx;
1338 dma[1] = dma[0] + s->buf_len_rx;
1339
1340 for (i = 0; i < 2; i++) {
1341 struct scatterlist *sg = &s->sg_rx[i];
1342
1343 sg_init_table(sg, 1);
1344 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1345 (int)buf[i] & ~PAGE_MASK);
1346 sg->dma_address = dma[i];
1347 sg->dma_length = sg->length;
1348 }
1349
1350 INIT_WORK(&s->work_rx, work_fn_rx);
1351 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1352
1353 sci_submit_rx(s);
1354 }
1355}
1356
1357static void sci_free_dma(struct uart_port *port)
1358{
1359 struct sci_port *s = to_sci_port(port);
1360
1361 if (!s->dma_dev)
1362 return;
1363
1364 if (s->chan_tx)
1365 sci_tx_dma_release(s, false);
1366 if (s->chan_rx)
1367 sci_rx_dma_release(s, false);
1368}
1369#endif
1370
1da177e4
LT		 1371static int sci_startup(struct uart_port *port)
1372{
a5660ada 1373 struct sci_port *s = to_sci_port(port);
1da177e4 1374
73a19e4c
GL		 1375 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1376
e108b2ca
PM		 1377 if (s->enable)
1378 s->enable(port);
1da177e4
LT		 1379
1380 sci_request_irq(s);
73a19e4c
GL		 1381#ifdef CONFIG_SERIAL_SH_SCI_DMA
1382 sci_request_dma(port);
1383#endif
d656901b 1384 sci_start_tx(port);
73a19e4c 1385 sci_start_rx(port);
1da177e4
LT		 1386
1387 return 0;
1388}
1389
1390static void sci_shutdown(struct uart_port *port)
1391{
a5660ada 1392 struct sci_port *s = to_sci_port(port);
1da177e4 1393
73a19e4c
GL		 1394 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1395
1da177e4 1396 sci_stop_rx(port);
b129a8cc 1397 sci_stop_tx(port);
73a19e4c
GL		 1398#ifdef CONFIG_SERIAL_SH_SCI_DMA
1399 sci_free_dma(port);
1400#endif
1da177e4
LT		 1401 sci_free_irq(s);
1402
e108b2ca
PM		 1403 if (s->disable)
1404 s->disable(port);
1da177e4
LT		 1405}
1406
606d099c
AC		 1407static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1408 struct ktermios *old)
1da177e4 1409{
154280fd 1410 unsigned int status, baud, smr_val, max_baud;
a2159b52 1411 int t = -1;
1da177e4 1412
154280fd
MD		 1413 /*
1414 * earlyprintk comes here early on with port->uartclk set to zero.
1415 * the clock framework is not up and running at this point so here
1416 * we assume that 115200 is the maximum baud rate. please note that
1417 * the baud rate is not programmed during earlyprintk - it is assumed
1418 * that the previous boot loader has enabled required clocks and
1419 * setup the baud rate generator hardware for us already.
1420 */
1421 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1422
1423 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1424 if (likely(baud && port->uartclk))
a2159b52 1425 t = SCBRR_VALUE(baud, port->uartclk);
e108b2ca 1426
1da177e4
LT		 1427 do {
1428 status = sci_in(port, SCxSR);
1429 } while (!(status & SCxSR_TEND(port)));
1430
1431 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1432
1a22f08d 1433 if (port->type != PORT_SCI)
1da177e4 1434 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 1435
1436 smr_val = sci_in(port, SCSMR) & 3;
1437 if ((termios->c_cflag & CSIZE) == CS7)
1438 smr_val |= 0x40;
1439 if (termios->c_cflag & PARENB)
1440 smr_val |= 0x20;
1441 if (termios->c_cflag & PARODD)
1442 smr_val |= 0x30;
1443 if (termios->c_cflag & CSTOPB)
1444 smr_val |= 0x08;
1445
1446 uart_update_timeout(port, termios->c_cflag, baud);
1447
1448 sci_out(port, SCSMR, smr_val);
1449
73a19e4c
GL		 1450 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1451 SCSCR_INIT(port));
1452
1da177e4 1453 if (t > 0) {
e7c98dc7 1454 if (t >= 256) {
1da177e4
LT		 1455 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1456 t >>= 2;
e7c98dc7 1457 } else
1da177e4 1458 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1459
1da177e4
LT		 1460 sci_out(port, SCBRR, t);
1461 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1462 }
1463
d5701647
PM		 1464 sci_init_pins(port, termios->c_cflag);
1465 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
b7a76e4b 1466
1da177e4
LT		 1467 sci_out(port, SCSCR, SCSCR_INIT(port));
1468
1469 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1470 sci_start_rx(port);
1da177e4
LT		 1471}
1472
1473static const char *sci_type(struct uart_port *port)
1474{
1475 switch (port->type) {
e7c98dc7
MT		 1476 case PORT_IRDA:
1477 return "irda";
1478 case PORT_SCI:
1479 return "sci";
1480 case PORT_SCIF:
1481 return "scif";
1482 case PORT_SCIFA:
1483 return "scifa";
1da177e4
LT		 1484 }
1485
fa43972f 1486 return NULL;
1da177e4
LT		 1487}
1488
1489static void sci_release_port(struct uart_port *port)
1490{
1491 /* Nothing here yet .. */
1492}
1493
1494static int sci_request_port(struct uart_port *port)
1495{
1496 /* Nothing here yet .. */
1497 return 0;
1498}
1499
1500static void sci_config_port(struct uart_port *port, int flags)
1501{
a5660ada 1502 struct sci_port *s = to_sci_port(port);
1da177e4
LT		 1503
1504 port->type = s->type;
1505
08f8cb31
MD		 1506 if (port->membase)
1507 return;
1508
1509 if (port->flags & UPF_IOREMAP) {
7ff731ae 1510 port->membase = ioremap_nocache(port->mapbase, 0x40);
08f8cb31
MD		 1511
1512 if (IS_ERR(port->membase))
1513 dev_err(port->dev, "can't remap port#%d\n", port->line);
1514 } else {
1515 /*
1516 * For the simple (and majority of) cases where we don't
1517 * need to do any remapping, just cast the cookie
1518 * directly.
1519 */
1520 port->membase = (void __iomem *)port->mapbase;
7ff731ae 1521 }
1da177e4
LT		 1522}
1523
1524static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1525{
a5660ada 1526 struct sci_port *s = to_sci_port(port);
1da177e4 1527
a62c4133 1528 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1529 return -EINVAL;
1530 if (ser->baud_base < 2400)
1531 /* No paper tape reader for Mitch.. */
1532 return -EINVAL;
1533
1534 return 0;
1535}
1536
1537static struct uart_ops sci_uart_ops = {
1538 .tx_empty = sci_tx_empty,
1539 .set_mctrl = sci_set_mctrl,
1540 .get_mctrl = sci_get_mctrl,
1541 .start_tx = sci_start_tx,
1542 .stop_tx = sci_stop_tx,
1543 .stop_rx = sci_stop_rx,
1544 .enable_ms = sci_enable_ms,
1545 .break_ctl = sci_break_ctl,
1546 .startup = sci_startup,
1547 .shutdown = sci_shutdown,
1548 .set_termios = sci_set_termios,
1549 .type = sci_type,
1550 .release_port = sci_release_port,
1551 .request_port = sci_request_port,
1552 .config_port = sci_config_port,
1553 .verify_port = sci_verify_port,
07d2a1a1
PM		 1554#ifdef CONFIG_CONSOLE_POLL
1555 .poll_get_char = sci_poll_get_char,
1556 .poll_put_char = sci_poll_put_char,
1557#endif
1da177e4
LT		 1558};
1559
501b825d
MD		 1560static void __devinit sci_init_single(struct platform_device *dev,
1561 struct sci_port *sci_port,
08f8cb31
MD		 1562 unsigned int index,
1563 struct plat_sci_port *p)
e108b2ca 1564{
73a19e4c
GL		 1565 struct uart_port *port = &sci_port->port;
1566
1567 port->ops = &sci_uart_ops;
1568 port->iotype = UPIO_MEM;
1569 port->line = index;
75136d48
MP		 1570
1571 switch (p->type) {
1572 case PORT_SCIFA:
73a19e4c 1573 port->fifosize = 64;
75136d48
MP		 1574 break;
1575 case PORT_SCIF:
73a19e4c 1576 port->fifosize = 16;
75136d48
MP		 1577 break;
1578 default:
73a19e4c 1579 port->fifosize = 1;
75136d48
MP		 1580 break;
1581 }
7b6fd3bf
MD		 1582
1583 if (dev) {
1584 sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
1585 sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
1586 sci_port->enable = sci_clk_enable;
1587 sci_port->disable = sci_clk_disable;
73a19e4c 1588 port->dev = &dev->dev;
7b6fd3bf 1589 }
e108b2ca 1590
7ed7e071
MD		 1591 sci_port->break_timer.data = (unsigned long)sci_port;
1592 sci_port->break_timer.function = sci_break_timer;
1593 init_timer(&sci_port->break_timer);
1594
73a19e4c
GL		 1595 port->mapbase = p->mapbase;
1596 port->membase = p->membase;
7ed7e071 1597
73a19e4c
GL		 1598 port->irq = p->irqs[SCIx_TXI_IRQ];
1599 port->flags = p->flags;
1600 sci_port->type = port->type = p->type;
1601
1602#ifdef CONFIG_SERIAL_SH_SCI_DMA
1603 sci_port->dma_dev = p->dma_dev;
1604 sci_port->slave_tx = p->dma_slave_tx;
1605 sci_port->slave_rx = p->dma_slave_rx;
1606
1607 dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__,
1608 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1609#endif
7ed7e071
MD		 1610
1611 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
e108b2ca
PM		 1612}
1613
1da177e4 1614#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 1615static struct tty_driver *serial_console_device(struct console *co, int *index)
1616{
1617 struct uart_driver *p = &sci_uart_driver;
1618 *index = co->index;
1619 return p->tty_driver;
1620}
1621
1622static void serial_console_putchar(struct uart_port *port, int ch)
1623{
1624 sci_poll_put_char(port, ch);
1625}
1626
1da177e4
LT		 1627/*
1628 * Print a string to the serial port trying not to disturb
1629 * any possible real use of the port...
1630 */
1631static void serial_console_write(struct console *co, const char *s,
1632 unsigned count)
1633{
dc8e6f5b 1634 struct uart_port *port = co->data;
501b825d 1635 struct sci_port *sci_port = to_sci_port(port);
973e5d52 1636 unsigned short bits;
07d2a1a1 1637
501b825d
MD		 1638 if (sci_port->enable)
1639 sci_port->enable(port);
1640
1641 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 1642
1643 /* wait until fifo is empty and last bit has been transmitted */
1644 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1645 while ((sci_in(port, SCxSR) & bits) != bits)
1646 cpu_relax();
501b825d 1647
345e5a76 1648 if (sci_port->disable)
501b825d 1649 sci_port->disable(port);
1da177e4
LT		 1650}
1651
7b6fd3bf 1652static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 1653{
dc8e6f5b 1654 struct sci_port *sci_port;
1da177e4
LT		 1655 struct uart_port *port;
1656 int baud = 115200;
1657 int bits = 8;
1658 int parity = 'n';
1659 int flow = 'n';
1660 int ret;
1661
e108b2ca
PM		 1662 /*
1663 * Check whether an invalid uart number has been specified, and
1664 * if so, search for the first available port that does have
1665 * console support.
1666 */
1667 if (co->index >= SCI_NPORTS)
1668 co->index = 0;
1669
7b6fd3bf
MD		 1670 if (co->data) {
1671 port = co->data;
1672 sci_port = to_sci_port(port);
1673 } else {
1674 sci_port = &sci_ports[co->index];
1675 port = &sci_port->port;
1676 co->data = port;
1677 }
1da177e4
LT		 1678
1679 /*
e108b2ca
PM		 1680 * Also need to check port->type, we don't actually have any
1681 * UPIO_PORT ports, but uart_report_port() handily misreports
1682 * it anyways if we don't have a port available by the time this is
1683 * called.
1da177e4 1684 */
e108b2ca
PM		 1685 if (!port->type)
1686 return -ENODEV;
e108b2ca 1687
08f8cb31 1688 sci_config_port(port, 0);
e108b2ca 1689
dc8e6f5b
MD		 1690 if (sci_port->enable)
1691 sci_port->enable(port);
b7a76e4b 1692
1da177e4
LT		 1693 if (options)
1694 uart_parse_options(options, &baud, &parity, &bits, &flow);
1695
1696 ret = uart_set_options(port, co, baud, parity, bits, flow);
1697#if defined(__H8300H__) || defined(__H8300S__)
1698 /* disable rx interrupt */
1699 if (ret == 0)
1700 sci_stop_rx(port);
1701#endif
501b825d 1702 /* TODO: disable clock */
1da177e4
LT		 1703 return ret;
1704}
1705
1706static struct console serial_console = {
1707 .name = "ttySC",
dc8e6f5b 1708 .device = serial_console_device,
1da177e4
LT		 1709 .write = serial_console_write,
1710 .setup = serial_console_setup,
fa5da2f7 1711 .flags = CON_PRINTBUFFER,
1da177e4 1712 .index = -1,
1da177e4
LT		 1713};
1714
1715static int __init sci_console_init(void)
1716{
1717 register_console(&serial_console);
1718 return 0;
1719}
1da177e4 1720console_initcall(sci_console_init);
7b6fd3bf
MD		 1721
1722static struct sci_port early_serial_port;
1723static struct console early_serial_console = {
1724 .name = "early_ttySC",
1725 .write = serial_console_write,
1726 .flags = CON_PRINTBUFFER,
1727};
1728static char early_serial_buf[32];
1729
1da177e4
LT		 1730#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1731
07d2a1a1 1732#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
e7c98dc7 1733#define SCI_CONSOLE (&serial_console)
1da177e4 1734#else
b7a76e4b 1735#define SCI_CONSOLE 0
1da177e4
LT		 1736#endif
1737
1738static char banner[] __initdata =
1739 KERN_INFO "SuperH SCI(F) driver initialized\n";
1740
1741static struct uart_driver sci_uart_driver = {
1742 .owner = THIS_MODULE,
1743 .driver_name = "sci",
1da177e4
LT		 1744 .dev_name = "ttySC",
1745 .major = SCI_MAJOR,
1746 .minor = SCI_MINOR_START,
e108b2ca 1747 .nr = SCI_NPORTS,
1da177e4
LT		 1748 .cons = SCI_CONSOLE,
1749};
1750
e552de24 1751
54507f6e 1752static int sci_remove(struct platform_device *dev)
e552de24
MD		 1753{
1754 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1755 struct sci_port *p;
1756 unsigned long flags;
1757
e552de24 1758 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
e552de24
MD		 1759
1760 spin_lock_irqsave(&priv->lock, flags);
1761 list_for_each_entry(p, &priv->ports, node)
1762 uart_remove_one_port(&sci_uart_driver, &p->port);
e552de24
MD		 1763 spin_unlock_irqrestore(&priv->lock, flags);
1764
1765 kfree(priv);
1766 return 0;
1767}
1768
0ee70712
MD		 1769static int __devinit sci_probe_single(struct platform_device *dev,
1770 unsigned int index,
1771 struct plat_sci_port *p,
1772 struct sci_port *sciport)
1773{
1774 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1775 unsigned long flags;
1776 int ret;
1777
1778 /* Sanity check */
1779 if (unlikely(index >= SCI_NPORTS)) {
1780 dev_notice(&dev->dev, "Attempting to register port "
1781 "%d when only %d are available.\n",
1782 index+1, SCI_NPORTS);
1783 dev_notice(&dev->dev, "Consider bumping "
1784 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1785 return 0;
1786 }
1787
501b825d 1788 sci_init_single(dev, sciport, index, p);
0ee70712
MD		 1789
1790 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
08f8cb31 1791 if (ret)
0ee70712 1792 return ret;
0ee70712
MD		 1793
1794 INIT_LIST_HEAD(&sciport->node);
1795
1796 spin_lock_irqsave(&priv->lock, flags);
1797 list_add(&sciport->node, &priv->ports);
1798 spin_unlock_irqrestore(&priv->lock, flags);
1799
1800 return 0;
1801}
1802
e108b2ca
PM		 1803/*
1804 * Register a set of serial devices attached to a platform device. The
1805 * list is terminated with a zero flags entry, which means we expect
1806 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1807 * remapping (such as sh64) should also set UPF_IOREMAP.
1808 */
1809static int __devinit sci_probe(struct platform_device *dev)
1da177e4 1810{
e108b2ca 1811 struct plat_sci_port *p = dev->dev.platform_data;
e552de24 1812 struct sh_sci_priv *priv;
7ff731ae 1813 int i, ret = -EINVAL;
e552de24 1814
7b6fd3bf
MD		 1815#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1816 if (is_early_platform_device(dev)) {
1817 if (dev->id == -1)
1818 return -ENOTSUPP;
1819 early_serial_console.index = dev->id;
1820 early_serial_console.data = &early_serial_port.port;
1821 sci_init_single(NULL, &early_serial_port, dev->id, p);
1822 serial_console_setup(&early_serial_console, early_serial_buf);
1823 if (!strstr(early_serial_buf, "keep"))
1824 early_serial_console.flags |= CON_BOOT;
1825 register_console(&early_serial_console);
1826 return 0;
1827 }
1828#endif
1829
e552de24
MD		 1830 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1831 if (!priv)
1832 return -ENOMEM;
1833
1834 INIT_LIST_HEAD(&priv->ports);
1835 spin_lock_init(&priv->lock);
1836 platform_set_drvdata(dev, priv);
1837
e552de24
MD		 1838 priv->clk_nb.notifier_call = sci_notifier;
1839 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1da177e4 1840
0ee70712
MD		 1841 if (dev->id != -1) {
1842 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1843 if (ret)
e552de24 1844 goto err_unreg;
0ee70712
MD		 1845 } else {
1846 for (i = 0; p && p->flags != 0; p++, i++) {
1847 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1848 if (ret)
1849 goto err_unreg;
e552de24 1850 }
e552de24 1851 }
1da177e4
LT		 1852
1853#ifdef CONFIG_SH_STANDARD_BIOS
1854 sh_bios_gdb_detach();
1855#endif
1856
e108b2ca 1857 return 0;
7ff731ae
PM		 1858
1859err_unreg:
e552de24 1860 sci_remove(dev);
7ff731ae 1861 return ret;
1da177e4
LT		 1862}
1863
6daa79b3 1864static int sci_suspend(struct device *dev)
1da177e4 1865{
6daa79b3 1866 struct sh_sci_priv *priv = dev_get_drvdata(dev);
e552de24
MD		 1867 struct sci_port *p;
1868 unsigned long flags;
e108b2ca 1869
e552de24
MD		 1870 spin_lock_irqsave(&priv->lock, flags);
1871 list_for_each_entry(p, &priv->ports, node)
1872 uart_suspend_port(&sci_uart_driver, &p->port);
e552de24 1873 spin_unlock_irqrestore(&priv->lock, flags);
1da177e4 1874
e108b2ca
PM		 1875 return 0;
1876}
1da177e4 1877
6daa79b3 1878static int sci_resume(struct device *dev)
e108b2ca 1879{
6daa79b3 1880 struct sh_sci_priv *priv = dev_get_drvdata(dev);
e552de24
MD		 1881 struct sci_port *p;
1882 unsigned long flags;
e108b2ca 1883
e552de24
MD		 1884 spin_lock_irqsave(&priv->lock, flags);
1885 list_for_each_entry(p, &priv->ports, node)
1886 uart_resume_port(&sci_uart_driver, &p->port);
e552de24 1887 spin_unlock_irqrestore(&priv->lock, flags);
e108b2ca
PM		 1888
1889 return 0;
1890}
1891
47145210 1892static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 1893 .suspend = sci_suspend,
1894 .resume = sci_resume,
1895};
1896
e108b2ca
PM		 1897static struct platform_driver sci_driver = {
1898 .probe = sci_probe,
b9e39c89 1899 .remove = sci_remove,
e108b2ca
PM		 1900 .driver = {
1901 .name = "sh-sci",
1902 .owner = THIS_MODULE,
6daa79b3 1903 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 1904 },
1905};
1906
1907static int __init sci_init(void)
1908{
1909 int ret;
1910
1911 printk(banner);
1912
e108b2ca
PM		 1913 ret = uart_register_driver(&sci_uart_driver);
1914 if (likely(ret == 0)) {
1915 ret = platform_driver_register(&sci_driver);
1916 if (unlikely(ret))
1917 uart_unregister_driver(&sci_uart_driver);
1918 }
1919
1920 return ret;
1921}
1922
1923static void __exit sci_exit(void)
1924{
1925 platform_driver_unregister(&sci_driver);
1da177e4
LT		 1926 uart_unregister_driver(&sci_uart_driver);
1927}
1928
7b6fd3bf
MD		 1929#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1930early_platform_init_buffer("earlyprintk", &sci_driver,
1931 early_serial_buf, ARRAY_SIZE(early_serial_buf));
1932#endif
1da177e4
LT		 1933module_init(sci_init);
1934module_exit(sci_exit);
1935
e108b2ca 1936MODULE_LICENSE("GPL");
e169c139 1937MODULE_ALIAS("platform:sh-sci");
Linux kernel - Deliverables
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