Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/serial/sh-sci.c | |
3 | * | |
4 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
5 | * | |
f43dc23d | 6 | * Copyright (C) 2002 - 2011 Paul Mundt |
3ea6bc3d | 7 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
8 | * |
9 | * based off of the old drivers/char/sh-sci.c by: | |
10 | * | |
11 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
12 | * Copyright (C) 2000 Sugioka Toshinobu | |
13 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
14 | * Modified to support SecureEdge. David McCullough (2002) | |
15 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 16 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
17 | * |
18 | * This file is subject to the terms and conditions of the GNU General Public | |
19 | * License. See the file "COPYING" in the main directory of this archive | |
20 | * for more details. | |
21 | */ | |
0b3d4ef6 PM |
22 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
23 | #define SUPPORT_SYSRQ | |
24 | #endif | |
1da177e4 LT |
25 | |
26 | #undef DEBUG | |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/errno.h> | |
1da177e4 LT |
30 | #include <linux/timer.h> |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/tty_flip.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/major.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/sysrq.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/mm.h> | |
1da177e4 LT |
40 | #include <linux/init.h> |
41 | #include <linux/delay.h> | |
42 | #include <linux/console.h> | |
e108b2ca | 43 | #include <linux/platform_device.h> |
96de1a8f | 44 | #include <linux/serial_sci.h> |
1da177e4 LT |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpufreq.h> | |
85f094ec | 47 | #include <linux/clk.h> |
fa5da2f7 | 48 | #include <linux/ctype.h> |
7ff731ae | 49 | #include <linux/err.h> |
73a19e4c GL |
50 | #include <linux/dmaengine.h> |
51 | #include <linux/scatterlist.h> | |
5a0e3ad6 | 52 | #include <linux/slab.h> |
85f094ec PM |
53 | |
54 | #ifdef CONFIG_SUPERH | |
1da177e4 LT |
55 | #include <asm/sh_bios.h> |
56 | #endif | |
57 | ||
168f3623 YS |
58 | #ifdef CONFIG_H8300 |
59 | #include <asm/gpio.h> | |
60 | #endif | |
61 | ||
1da177e4 LT |
62 | #include "sh-sci.h" |
63 | ||
e108b2ca PM |
64 | struct sci_port { |
65 | struct uart_port port; | |
66 | ||
ce6738b6 PM |
67 | /* Platform configuration */ |
68 | struct plat_sci_port *cfg; | |
e108b2ca | 69 | |
e108b2ca PM |
70 | /* Port enable callback */ |
71 | void (*enable)(struct uart_port *port); | |
72 | ||
73 | /* Port disable callback */ | |
74 | void (*disable)(struct uart_port *port); | |
75 | ||
76 | /* Break timer */ | |
77 | struct timer_list break_timer; | |
78 | int break_flag; | |
1534a3b3 | 79 | |
501b825d MD |
80 | /* Interface clock */ |
81 | struct clk *iclk; | |
c7ed1ab3 PM |
82 | /* Function clock */ |
83 | struct clk *fclk; | |
edad1f20 | 84 | |
73a19e4c GL |
85 | struct dma_chan *chan_tx; |
86 | struct dma_chan *chan_rx; | |
f43dc23d | 87 | |
73a19e4c | 88 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
73a19e4c GL |
89 | struct dma_async_tx_descriptor *desc_tx; |
90 | struct dma_async_tx_descriptor *desc_rx[2]; | |
91 | dma_cookie_t cookie_tx; | |
92 | dma_cookie_t cookie_rx[2]; | |
93 | dma_cookie_t active_rx; | |
94 | struct scatterlist sg_tx; | |
95 | unsigned int sg_len_tx; | |
96 | struct scatterlist sg_rx[2]; | |
97 | size_t buf_len_rx; | |
98 | struct sh_dmae_slave param_tx; | |
99 | struct sh_dmae_slave param_rx; | |
100 | struct work_struct work_tx; | |
101 | struct work_struct work_rx; | |
102 | struct timer_list rx_timer; | |
3089f381 | 103 | unsigned int rx_timeout; |
73a19e4c | 104 | #endif |
e552de24 | 105 | |
d535a230 | 106 | struct notifier_block freq_transition; |
e108b2ca PM |
107 | }; |
108 | ||
1da177e4 | 109 | /* Function prototypes */ |
d535a230 | 110 | static void sci_start_tx(struct uart_port *port); |
b129a8cc | 111 | static void sci_stop_tx(struct uart_port *port); |
d535a230 | 112 | static void sci_start_rx(struct uart_port *port); |
1da177e4 | 113 | |
e108b2ca | 114 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 115 | |
e108b2ca PM |
116 | static struct sci_port sci_ports[SCI_NPORTS]; |
117 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 118 | |
e7c98dc7 MT |
119 | static inline struct sci_port * |
120 | to_sci_port(struct uart_port *uart) | |
121 | { | |
122 | return container_of(uart, struct sci_port, port); | |
123 | } | |
124 | ||
07d2a1a1 | 125 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
1f6fd5c9 PM |
126 | |
127 | #ifdef CONFIG_CONSOLE_POLL | |
e108b2ca PM |
128 | static inline void handle_error(struct uart_port *port) |
129 | { | |
130 | /* Clear error flags */ | |
1da177e4 LT |
131 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
132 | } | |
133 | ||
07d2a1a1 | 134 | static int sci_poll_get_char(struct uart_port *port) |
1da177e4 | 135 | { |
1da177e4 LT |
136 | unsigned short status; |
137 | int c; | |
138 | ||
e108b2ca | 139 | do { |
1da177e4 LT |
140 | status = sci_in(port, SCxSR); |
141 | if (status & SCxSR_ERRORS(port)) { | |
142 | handle_error(port); | |
143 | continue; | |
144 | } | |
3f255eb3 JW |
145 | break; |
146 | } while (1); | |
147 | ||
148 | if (!(status & SCxSR_RDxF(port))) | |
149 | return NO_POLL_CHAR; | |
07d2a1a1 | 150 | |
1da177e4 | 151 | c = sci_in(port, SCxRDR); |
07d2a1a1 | 152 | |
e7c98dc7 MT |
153 | /* Dummy read */ |
154 | sci_in(port, SCxSR); | |
1da177e4 | 155 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
156 | |
157 | return c; | |
158 | } | |
1f6fd5c9 | 159 | #endif |
1da177e4 | 160 | |
07d2a1a1 | 161 | static void sci_poll_put_char(struct uart_port *port, unsigned char c) |
1da177e4 | 162 | { |
1da177e4 LT |
163 | unsigned short status; |
164 | ||
1da177e4 LT |
165 | do { |
166 | status = sci_in(port, SCxSR); | |
167 | } while (!(status & SCxSR_TDxE(port))); | |
168 | ||
272966c0 | 169 | sci_out(port, SCxTDR, c); |
dd0a3e77 | 170 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); |
1da177e4 | 171 | } |
07d2a1a1 | 172 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1da177e4 | 173 | |
15c73aaa | 174 | #if defined(__H8300H__) || defined(__H8300S__) |
d5701647 | 175 | static void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 LT |
176 | { |
177 | int ch = (port->mapbase - SMR0) >> 3; | |
178 | ||
179 | /* set DDR regs */ | |
e108b2ca PM |
180 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, |
181 | h8300_sci_pins[ch].rx, | |
182 | H8300_GPIO_INPUT); | |
183 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, | |
184 | h8300_sci_pins[ch].tx, | |
185 | H8300_GPIO_OUTPUT); | |
186 | ||
1da177e4 LT |
187 | /* tx mark output*/ |
188 | H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; | |
189 | } | |
d5701647 PM |
190 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
191 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) | |
e108b2ca | 192 | { |
d5701647 PM |
193 | if (port->mapbase == 0xA4400000) { |
194 | __raw_writew(__raw_readw(PACR) & 0xffc0, PACR); | |
195 | __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); | |
196 | } else if (port->mapbase == 0xA4410000) | |
197 | __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); | |
9465a54f | 198 | } |
31a49c4b | 199 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) |
d5701647 | 200 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
3ea6bc3d | 201 | { |
3ea6bc3d MB |
202 | unsigned short data; |
203 | ||
204 | if (cflag & CRTSCTS) { | |
205 | /* enable RTS/CTS */ | |
206 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
207 | /* Clear PTCR bit 9-2; enable all scif pins but sck */ | |
d5701647 PM |
208 | data = __raw_readw(PORT_PTCR); |
209 | __raw_writew((data & 0xfc03), PORT_PTCR); | |
3ea6bc3d MB |
210 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
211 | /* Clear PVCR bit 9-2 */ | |
d5701647 PM |
212 | data = __raw_readw(PORT_PVCR); |
213 | __raw_writew((data & 0xfc03), PORT_PVCR); | |
3ea6bc3d | 214 | } |
3ea6bc3d MB |
215 | } else { |
216 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
217 | /* Clear PTCR bit 5-2; enable only tx and rx */ | |
d5701647 PM |
218 | data = __raw_readw(PORT_PTCR); |
219 | __raw_writew((data & 0xffc3), PORT_PTCR); | |
3ea6bc3d MB |
220 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
221 | /* Clear PVCR bit 5-2 */ | |
d5701647 PM |
222 | data = __raw_readw(PORT_PVCR); |
223 | __raw_writew((data & 0xffc3), PORT_PVCR); | |
3ea6bc3d MB |
224 | } |
225 | } | |
3ea6bc3d | 226 | } |
b7a76e4b | 227 | #elif defined(CONFIG_CPU_SH3) |
e108b2ca | 228 | /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ |
d5701647 | 229 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 | 230 | { |
b7a76e4b PM |
231 | unsigned short data; |
232 | ||
233 | /* We need to set SCPCR to enable RTS/CTS */ | |
d5701647 | 234 | data = __raw_readw(SCPCR); |
b7a76e4b | 235 | /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ |
d5701647 | 236 | __raw_writew(data & 0x0fcf, SCPCR); |
1da177e4 | 237 | |
d5701647 | 238 | if (!(cflag & CRTSCTS)) { |
1da177e4 | 239 | /* We need to set SCPCR to enable RTS/CTS */ |
d5701647 | 240 | data = __raw_readw(SCPCR); |
1da177e4 LT |
241 | /* Clear out SCP7MD1,0, SCP4MD1,0, |
242 | Set SCP6MD1,0 = {01} (output) */ | |
d5701647 | 243 | __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); |
1da177e4 | 244 | |
32b53076 | 245 | data = __raw_readb(SCPDR); |
1da177e4 | 246 | /* Set /RTS2 (bit6) = 0 */ |
32b53076 | 247 | __raw_writeb(data & 0xbf, SCPDR); |
1da177e4 | 248 | } |
1da177e4 | 249 | } |
41504c39 | 250 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
d5701647 | 251 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
41504c39 | 252 | { |
346b7463 | 253 | unsigned short data; |
41504c39 | 254 | |
346b7463 | 255 | if (port->mapbase == 0xffe00000) { |
d5701647 | 256 | data = __raw_readw(PSCR); |
346b7463 | 257 | data &= ~0x03cf; |
d5701647 | 258 | if (!(cflag & CRTSCTS)) |
346b7463 | 259 | data |= 0x0340; |
41504c39 | 260 | |
d5701647 | 261 | __raw_writew(data, PSCR); |
41504c39 | 262 | } |
178dd0cd | 263 | } |
c01f0f1a YS |
264 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \ |
265 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ | |
7d740a06 | 266 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
2b1bd1ac | 267 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
55ba99eb | 268 | defined(CONFIG_CPU_SUBTYPE_SH7786) || \ |
2b1bd1ac | 269 | defined(CONFIG_CPU_SUBTYPE_SHX3) |
d5701647 PM |
270 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
271 | { | |
272 | if (!(cflag & CRTSCTS)) | |
273 | __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */ | |
274 | } | |
b0c50ad7 | 275 | #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A) |
d5701647 PM |
276 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
277 | { | |
278 | if (!(cflag & CRTSCTS)) | |
279 | __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */ | |
280 | } | |
b7a76e4b | 281 | #else |
d5701647 PM |
282 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
283 | { | |
284 | /* Nothing to do */ | |
1da177e4 | 285 | } |
e108b2ca PM |
286 | #endif |
287 | ||
32351a28 PM |
288 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
289 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
55ba99eb KM |
290 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
291 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
73a19e4c | 292 | static int scif_txfill(struct uart_port *port) |
e108b2ca | 293 | { |
73a19e4c | 294 | return sci_in(port, SCTFDR) & 0xff; |
e108b2ca PM |
295 | } |
296 | ||
73a19e4c | 297 | static int scif_txroom(struct uart_port *port) |
e108b2ca | 298 | { |
73a19e4c | 299 | return SCIF_TXROOM_MAX - scif_txfill(port); |
e108b2ca PM |
300 | } |
301 | ||
73a19e4c | 302 | static int scif_rxfill(struct uart_port *port) |
e108b2ca | 303 | { |
cae167d3 | 304 | return sci_in(port, SCRFDR) & 0xff; |
e108b2ca | 305 | } |
c63847a3 | 306 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
73a19e4c | 307 | static int scif_txfill(struct uart_port *port) |
c63847a3 | 308 | { |
73a19e4c GL |
309 | if (port->mapbase == 0xffe00000 || |
310 | port->mapbase == 0xffe08000) | |
e7c98dc7 | 311 | /* SCIF0/1*/ |
73a19e4c GL |
312 | return sci_in(port, SCTFDR) & 0xff; |
313 | else | |
e7c98dc7 | 314 | /* SCIF2 */ |
73a19e4c | 315 | return sci_in(port, SCFDR) >> 8; |
c63847a3 NI |
316 | } |
317 | ||
73a19e4c GL |
318 | static int scif_txroom(struct uart_port *port) |
319 | { | |
320 | if (port->mapbase == 0xffe00000 || | |
321 | port->mapbase == 0xffe08000) | |
322 | /* SCIF0/1*/ | |
323 | return SCIF_TXROOM_MAX - scif_txfill(port); | |
324 | else | |
325 | /* SCIF2 */ | |
326 | return SCIF2_TXROOM_MAX - scif_txfill(port); | |
c63847a3 NI |
327 | } |
328 | ||
73a19e4c | 329 | static int scif_rxfill(struct uart_port *port) |
c63847a3 | 330 | { |
e7c98dc7 MT |
331 | if ((port->mapbase == 0xffe00000) || |
332 | (port->mapbase == 0xffe08000)) { | |
333 | /* SCIF0/1*/ | |
c63847a3 | 334 | return sci_in(port, SCRFDR) & 0xff; |
e7c98dc7 MT |
335 | } else { |
336 | /* SCIF2 */ | |
c63847a3 | 337 | return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; |
e7c98dc7 | 338 | } |
c63847a3 | 339 | } |
d1d4b10c GL |
340 | #elif defined(CONFIG_ARCH_SH7372) |
341 | static int scif_txfill(struct uart_port *port) | |
342 | { | |
343 | if (port->type == PORT_SCIFA) | |
344 | return sci_in(port, SCFDR) >> 8; | |
345 | else | |
346 | return sci_in(port, SCTFDR); | |
347 | } | |
348 | ||
349 | static int scif_txroom(struct uart_port *port) | |
350 | { | |
351 | return port->fifosize - scif_txfill(port); | |
352 | } | |
353 | ||
354 | static int scif_rxfill(struct uart_port *port) | |
355 | { | |
356 | if (port->type == PORT_SCIFA) | |
357 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
358 | else | |
359 | return sci_in(port, SCRFDR); | |
360 | } | |
e108b2ca | 361 | #else |
73a19e4c | 362 | static int scif_txfill(struct uart_port *port) |
e108b2ca | 363 | { |
73a19e4c | 364 | return sci_in(port, SCFDR) >> 8; |
e108b2ca | 365 | } |
1da177e4 | 366 | |
73a19e4c | 367 | static int scif_txroom(struct uart_port *port) |
e108b2ca | 368 | { |
73a19e4c | 369 | return SCIF_TXROOM_MAX - scif_txfill(port); |
e108b2ca | 370 | } |
1da177e4 | 371 | |
73a19e4c | 372 | static int scif_rxfill(struct uart_port *port) |
e108b2ca PM |
373 | { |
374 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
375 | } | |
1da177e4 | 376 | #endif |
1da177e4 | 377 | |
73a19e4c | 378 | static int sci_txfill(struct uart_port *port) |
e108b2ca | 379 | { |
73a19e4c | 380 | return !(sci_in(port, SCxSR) & SCI_TDRE); |
e108b2ca PM |
381 | } |
382 | ||
73a19e4c GL |
383 | static int sci_txroom(struct uart_port *port) |
384 | { | |
385 | return !sci_txfill(port); | |
386 | } | |
387 | ||
388 | static int sci_rxfill(struct uart_port *port) | |
e108b2ca | 389 | { |
e7c98dc7 | 390 | return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
391 | } |
392 | ||
1da177e4 LT |
393 | /* ********************************************************************** * |
394 | * the interrupt related routines * | |
395 | * ********************************************************************** */ | |
396 | ||
397 | static void sci_transmit_chars(struct uart_port *port) | |
398 | { | |
ebd2c8f6 | 399 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 | 400 | unsigned int stopped = uart_tx_stopped(port); |
1da177e4 LT |
401 | unsigned short status; |
402 | unsigned short ctrl; | |
e108b2ca | 403 | int count; |
1da177e4 LT |
404 | |
405 | status = sci_in(port, SCxSR); | |
406 | if (!(status & SCxSR_TDxE(port))) { | |
1da177e4 | 407 | ctrl = sci_in(port, SCSCR); |
e7c98dc7 | 408 | if (uart_circ_empty(xmit)) |
8e698614 | 409 | ctrl &= ~SCSCR_TIE; |
e7c98dc7 | 410 | else |
8e698614 | 411 | ctrl |= SCSCR_TIE; |
1da177e4 | 412 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
413 | return; |
414 | } | |
415 | ||
1a22f08d | 416 | if (port->type == PORT_SCI) |
e108b2ca | 417 | count = sci_txroom(port); |
1a22f08d YS |
418 | else |
419 | count = scif_txroom(port); | |
1da177e4 LT |
420 | |
421 | do { | |
422 | unsigned char c; | |
423 | ||
424 | if (port->x_char) { | |
425 | c = port->x_char; | |
426 | port->x_char = 0; | |
427 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
428 | c = xmit->buf[xmit->tail]; | |
429 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
430 | } else { | |
431 | break; | |
432 | } | |
433 | ||
434 | sci_out(port, SCxTDR, c); | |
435 | ||
436 | port->icount.tx++; | |
437 | } while (--count > 0); | |
438 | ||
439 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
440 | ||
441 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
442 | uart_write_wakeup(port); | |
443 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 444 | sci_stop_tx(port); |
1da177e4 | 445 | } else { |
1da177e4 LT |
446 | ctrl = sci_in(port, SCSCR); |
447 | ||
1a22f08d | 448 | if (port->type != PORT_SCI) { |
1da177e4 LT |
449 | sci_in(port, SCxSR); /* Dummy read */ |
450 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
451 | } | |
1da177e4 | 452 | |
8e698614 | 453 | ctrl |= SCSCR_TIE; |
1da177e4 | 454 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
455 | } |
456 | } | |
457 | ||
458 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 459 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 460 | |
7d12e780 | 461 | static inline void sci_receive_chars(struct uart_port *port) |
1da177e4 | 462 | { |
e7c98dc7 | 463 | struct sci_port *sci_port = to_sci_port(port); |
ebd2c8f6 | 464 | struct tty_struct *tty = port->state->port.tty; |
1da177e4 LT |
465 | int i, count, copied = 0; |
466 | unsigned short status; | |
33f0f88f | 467 | unsigned char flag; |
1da177e4 LT |
468 | |
469 | status = sci_in(port, SCxSR); | |
470 | if (!(status & SCxSR_RDxF(port))) | |
471 | return; | |
472 | ||
473 | while (1) { | |
1a22f08d | 474 | if (port->type == PORT_SCI) |
73a19e4c | 475 | count = sci_rxfill(port); |
1a22f08d | 476 | else |
73a19e4c | 477 | count = scif_rxfill(port); |
1da177e4 LT |
478 | |
479 | /* Don't copy more bytes than there is room for in the buffer */ | |
33f0f88f | 480 | count = tty_buffer_request_room(tty, count); |
1da177e4 LT |
481 | |
482 | /* If for any reason we can't copy more data, we're done! */ | |
483 | if (count == 0) | |
484 | break; | |
485 | ||
486 | if (port->type == PORT_SCI) { | |
487 | char c = sci_in(port, SCxRDR); | |
e7c98dc7 MT |
488 | if (uart_handle_sysrq_char(port, c) || |
489 | sci_port->break_flag) | |
1da177e4 | 490 | count = 0; |
e7c98dc7 | 491 | else |
e108b2ca | 492 | tty_insert_flip_char(tty, c, TTY_NORMAL); |
1da177e4 | 493 | } else { |
e7c98dc7 | 494 | for (i = 0; i < count; i++) { |
1da177e4 LT |
495 | char c = sci_in(port, SCxRDR); |
496 | status = sci_in(port, SCxSR); | |
497 | #if defined(CONFIG_CPU_SH3) | |
498 | /* Skip "chars" during break */ | |
e108b2ca | 499 | if (sci_port->break_flag) { |
1da177e4 LT |
500 | if ((c == 0) && |
501 | (status & SCxSR_FER(port))) { | |
502 | count--; i--; | |
503 | continue; | |
504 | } | |
e108b2ca | 505 | |
1da177e4 | 506 | /* Nonzero => end-of-break */ |
762c69e3 | 507 | dev_dbg(port->dev, "debounce<%02x>\n", c); |
e108b2ca PM |
508 | sci_port->break_flag = 0; |
509 | ||
1da177e4 LT |
510 | if (STEPFN(c)) { |
511 | count--; i--; | |
512 | continue; | |
513 | } | |
514 | } | |
515 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 516 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
517 | count--; i--; |
518 | continue; | |
519 | } | |
520 | ||
521 | /* Store data and status */ | |
73a19e4c | 522 | if (status & SCxSR_FER(port)) { |
33f0f88f | 523 | flag = TTY_FRAME; |
762c69e3 | 524 | dev_notice(port->dev, "frame error\n"); |
73a19e4c | 525 | } else if (status & SCxSR_PER(port)) { |
33f0f88f | 526 | flag = TTY_PARITY; |
762c69e3 | 527 | dev_notice(port->dev, "parity error\n"); |
33f0f88f AC |
528 | } else |
529 | flag = TTY_NORMAL; | |
762c69e3 | 530 | |
33f0f88f | 531 | tty_insert_flip_char(tty, c, flag); |
1da177e4 LT |
532 | } |
533 | } | |
534 | ||
535 | sci_in(port, SCxSR); /* dummy read */ | |
536 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
537 | ||
1da177e4 LT |
538 | copied += count; |
539 | port->icount.rx += count; | |
540 | } | |
541 | ||
542 | if (copied) { | |
543 | /* Tell the rest of the system the news. New characters! */ | |
544 | tty_flip_buffer_push(tty); | |
545 | } else { | |
546 | sci_in(port, SCxSR); /* dummy read */ | |
547 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
548 | } | |
549 | } | |
550 | ||
551 | #define SCI_BREAK_JIFFIES (HZ/20) | |
552 | /* The sci generates interrupts during the break, | |
553 | * 1 per millisecond or so during the break period, for 9600 baud. | |
554 | * So dont bother disabling interrupts. | |
555 | * But dont want more than 1 break event. | |
556 | * Use a kernel timer to periodically poll the rx line until | |
557 | * the break is finished. | |
558 | */ | |
559 | static void sci_schedule_break_timer(struct sci_port *port) | |
560 | { | |
561 | port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES; | |
562 | add_timer(&port->break_timer); | |
563 | } | |
564 | /* Ensure that two consecutive samples find the break over. */ | |
565 | static void sci_break_timer(unsigned long data) | |
566 | { | |
e108b2ca PM |
567 | struct sci_port *port = (struct sci_port *)data; |
568 | ||
569 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 570 | port->break_flag = 1; |
e108b2ca PM |
571 | sci_schedule_break_timer(port); |
572 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
573 | /* break is over. */ |
574 | port->break_flag = 2; | |
e108b2ca PM |
575 | sci_schedule_break_timer(port); |
576 | } else | |
577 | port->break_flag = 0; | |
1da177e4 LT |
578 | } |
579 | ||
580 | static inline int sci_handle_errors(struct uart_port *port) | |
581 | { | |
582 | int copied = 0; | |
583 | unsigned short status = sci_in(port, SCxSR); | |
ebd2c8f6 | 584 | struct tty_struct *tty = port->state->port.tty; |
1da177e4 | 585 | |
e108b2ca | 586 | if (status & SCxSR_ORER(port)) { |
1da177e4 | 587 | /* overrun error */ |
e108b2ca | 588 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) |
33f0f88f | 589 | copied++; |
762c69e3 PM |
590 | |
591 | dev_notice(port->dev, "overrun error"); | |
1da177e4 LT |
592 | } |
593 | ||
e108b2ca | 594 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
595 | if (sci_rxd_in(port) == 0) { |
596 | /* Notify of BREAK */ | |
e7c98dc7 | 597 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
598 | |
599 | if (!sci_port->break_flag) { | |
600 | sci_port->break_flag = 1; | |
601 | sci_schedule_break_timer(sci_port); | |
602 | ||
1da177e4 | 603 | /* Do sysrq handling. */ |
e108b2ca | 604 | if (uart_handle_break(port)) |
1da177e4 | 605 | return 0; |
762c69e3 PM |
606 | |
607 | dev_dbg(port->dev, "BREAK detected\n"); | |
608 | ||
e108b2ca | 609 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
e7c98dc7 MT |
610 | copied++; |
611 | } | |
612 | ||
e108b2ca | 613 | } else { |
1da177e4 | 614 | /* frame error */ |
e108b2ca | 615 | if (tty_insert_flip_char(tty, 0, TTY_FRAME)) |
33f0f88f | 616 | copied++; |
762c69e3 PM |
617 | |
618 | dev_notice(port->dev, "frame error\n"); | |
1da177e4 LT |
619 | } |
620 | } | |
621 | ||
e108b2ca | 622 | if (status & SCxSR_PER(port)) { |
1da177e4 | 623 | /* parity error */ |
e108b2ca PM |
624 | if (tty_insert_flip_char(tty, 0, TTY_PARITY)) |
625 | copied++; | |
762c69e3 PM |
626 | |
627 | dev_notice(port->dev, "parity error"); | |
1da177e4 LT |
628 | } |
629 | ||
33f0f88f | 630 | if (copied) |
1da177e4 | 631 | tty_flip_buffer_push(tty); |
1da177e4 LT |
632 | |
633 | return copied; | |
634 | } | |
635 | ||
d830fa45 PM |
636 | static inline int sci_handle_fifo_overrun(struct uart_port *port) |
637 | { | |
ebd2c8f6 | 638 | struct tty_struct *tty = port->state->port.tty; |
d830fa45 PM |
639 | int copied = 0; |
640 | ||
641 | if (port->type != PORT_SCIF) | |
642 | return 0; | |
643 | ||
644 | if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { | |
645 | sci_out(port, SCLSR, 0); | |
646 | ||
647 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
648 | tty_flip_buffer_push(tty); | |
649 | ||
650 | dev_notice(port->dev, "overrun error\n"); | |
651 | copied++; | |
652 | } | |
653 | ||
654 | return copied; | |
655 | } | |
656 | ||
1da177e4 LT |
657 | static inline int sci_handle_breaks(struct uart_port *port) |
658 | { | |
659 | int copied = 0; | |
660 | unsigned short status = sci_in(port, SCxSR); | |
ebd2c8f6 | 661 | struct tty_struct *tty = port->state->port.tty; |
a5660ada | 662 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 663 | |
0b3d4ef6 PM |
664 | if (uart_handle_break(port)) |
665 | return 0; | |
666 | ||
b7a76e4b | 667 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
668 | #if defined(CONFIG_CPU_SH3) |
669 | /* Debounce break */ | |
670 | s->break_flag = 1; | |
671 | #endif | |
672 | /* Notify of BREAK */ | |
e108b2ca | 673 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
33f0f88f | 674 | copied++; |
762c69e3 PM |
675 | |
676 | dev_dbg(port->dev, "BREAK detected\n"); | |
1da177e4 LT |
677 | } |
678 | ||
33f0f88f | 679 | if (copied) |
1da177e4 | 680 | tty_flip_buffer_push(tty); |
e108b2ca | 681 | |
d830fa45 PM |
682 | copied += sci_handle_fifo_overrun(port); |
683 | ||
1da177e4 LT |
684 | return copied; |
685 | } | |
686 | ||
73a19e4c | 687 | static irqreturn_t sci_rx_interrupt(int irq, void *ptr) |
1da177e4 | 688 | { |
73a19e4c GL |
689 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
690 | struct uart_port *port = ptr; | |
691 | struct sci_port *s = to_sci_port(port); | |
692 | ||
693 | if (s->chan_rx) { | |
73a19e4c GL |
694 | u16 scr = sci_in(port, SCSCR); |
695 | u16 ssr = sci_in(port, SCxSR); | |
696 | ||
697 | /* Disable future Rx interrupts */ | |
d1d4b10c | 698 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 GL |
699 | disable_irq_nosync(irq); |
700 | scr |= 0x4000; | |
701 | } else { | |
f43dc23d | 702 | scr &= ~SCSCR_RIE; |
3089f381 GL |
703 | } |
704 | sci_out(port, SCSCR, scr); | |
73a19e4c GL |
705 | /* Clear current interrupt */ |
706 | sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); | |
3089f381 GL |
707 | dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", |
708 | jiffies, s->rx_timeout); | |
709 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); | |
73a19e4c GL |
710 | |
711 | return IRQ_HANDLED; | |
712 | } | |
713 | #endif | |
714 | ||
1da177e4 LT |
715 | /* I think sci_receive_chars has to be called irrespective |
716 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
717 | * to be disabled? | |
718 | */ | |
73a19e4c | 719 | sci_receive_chars(ptr); |
1da177e4 LT |
720 | |
721 | return IRQ_HANDLED; | |
722 | } | |
723 | ||
7d12e780 | 724 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
725 | { |
726 | struct uart_port *port = ptr; | |
fd78a76a | 727 | unsigned long flags; |
1da177e4 | 728 | |
fd78a76a | 729 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 730 | sci_transmit_chars(port); |
fd78a76a | 731 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
732 | |
733 | return IRQ_HANDLED; | |
734 | } | |
735 | ||
7d12e780 | 736 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
737 | { |
738 | struct uart_port *port = ptr; | |
739 | ||
740 | /* Handle errors */ | |
741 | if (port->type == PORT_SCI) { | |
742 | if (sci_handle_errors(port)) { | |
743 | /* discard character in rx buffer */ | |
744 | sci_in(port, SCxSR); | |
745 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
746 | } | |
747 | } else { | |
d830fa45 | 748 | sci_handle_fifo_overrun(port); |
7d12e780 | 749 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
750 | } |
751 | ||
752 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); | |
753 | ||
754 | /* Kick the transmission */ | |
7d12e780 | 755 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
756 | |
757 | return IRQ_HANDLED; | |
758 | } | |
759 | ||
7d12e780 | 760 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
761 | { |
762 | struct uart_port *port = ptr; | |
763 | ||
764 | /* Handle BREAKs */ | |
765 | sci_handle_breaks(port); | |
766 | sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); | |
767 | ||
768 | return IRQ_HANDLED; | |
769 | } | |
770 | ||
f43dc23d PM |
771 | static inline unsigned long port_rx_irq_mask(struct uart_port *port) |
772 | { | |
773 | /* | |
774 | * Not all ports (such as SCIFA) will support REIE. Rather than | |
775 | * special-casing the port type, we check the port initialization | |
776 | * IRQ enable mask to see whether the IRQ is desired at all. If | |
777 | * it's unset, it's logically inferred that there's no point in | |
778 | * testing for it. | |
779 | */ | |
ce6738b6 | 780 | return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); |
f43dc23d PM |
781 | } |
782 | ||
7d12e780 | 783 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 | 784 | { |
44e18e9e | 785 | unsigned short ssr_status, scr_status, err_enabled; |
a8884e34 | 786 | struct uart_port *port = ptr; |
73a19e4c | 787 | struct sci_port *s = to_sci_port(port); |
a8884e34 | 788 | irqreturn_t ret = IRQ_NONE; |
1da177e4 | 789 | |
e7c98dc7 MT |
790 | ssr_status = sci_in(port, SCxSR); |
791 | scr_status = sci_in(port, SCSCR); | |
f43dc23d | 792 | err_enabled = scr_status & port_rx_irq_mask(port); |
1da177e4 LT |
793 | |
794 | /* Tx Interrupt */ | |
f43dc23d | 795 | if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && |
73a19e4c | 796 | !s->chan_tx) |
a8884e34 | 797 | ret = sci_tx_interrupt(irq, ptr); |
f43dc23d | 798 | |
73a19e4c GL |
799 | /* |
800 | * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / | |
801 | * DR flags | |
802 | */ | |
803 | if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && | |
f43dc23d | 804 | (scr_status & SCSCR_RIE)) |
a8884e34 | 805 | ret = sci_rx_interrupt(irq, ptr); |
f43dc23d | 806 | |
1da177e4 | 807 | /* Error Interrupt */ |
dd4da3a5 | 808 | if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) |
a8884e34 | 809 | ret = sci_er_interrupt(irq, ptr); |
f43dc23d | 810 | |
1da177e4 | 811 | /* Break Interrupt */ |
dd4da3a5 | 812 | if ((ssr_status & SCxSR_BRK(port)) && err_enabled) |
a8884e34 | 813 | ret = sci_br_interrupt(irq, ptr); |
1da177e4 | 814 | |
a8884e34 | 815 | return ret; |
1da177e4 LT |
816 | } |
817 | ||
1da177e4 LT |
818 | /* |
819 | * Here we define a transistion notifier so that we can update all of our | |
820 | * ports' baud rate when the peripheral clock changes. | |
821 | */ | |
e108b2ca PM |
822 | static int sci_notifier(struct notifier_block *self, |
823 | unsigned long phase, void *p) | |
1da177e4 | 824 | { |
e552de24 MD |
825 | struct sci_port *sci_port; |
826 | unsigned long flags; | |
1da177e4 | 827 | |
d535a230 PM |
828 | sci_port = container_of(self, struct sci_port, freq_transition); |
829 | ||
1da177e4 | 830 | if ((phase == CPUFREQ_POSTCHANGE) || |
e552de24 | 831 | (phase == CPUFREQ_RESUMECHANGE)) { |
d535a230 PM |
832 | struct uart_port *port = &sci_port->port; |
833 | spin_lock_irqsave(&port->lock, flags); | |
834 | port->uartclk = clk_get_rate(sci_port->iclk); | |
835 | spin_unlock_irqrestore(&port->lock, flags); | |
e552de24 | 836 | } |
1da177e4 | 837 | |
1da177e4 LT |
838 | return NOTIFY_OK; |
839 | } | |
501b825d MD |
840 | |
841 | static void sci_clk_enable(struct uart_port *port) | |
842 | { | |
843 | struct sci_port *sci_port = to_sci_port(port); | |
844 | ||
c7ed1ab3 PM |
845 | clk_enable(sci_port->iclk); |
846 | sci_port->port.uartclk = clk_get_rate(sci_port->iclk); | |
847 | clk_enable(sci_port->fclk); | |
501b825d MD |
848 | } |
849 | ||
850 | static void sci_clk_disable(struct uart_port *port) | |
851 | { | |
852 | struct sci_port *sci_port = to_sci_port(port); | |
853 | ||
c7ed1ab3 PM |
854 | clk_disable(sci_port->fclk); |
855 | clk_disable(sci_port->iclk); | |
501b825d | 856 | } |
1da177e4 LT |
857 | |
858 | static int sci_request_irq(struct sci_port *port) | |
859 | { | |
860 | int i; | |
7d12e780 | 861 | irqreturn_t (*handlers[4])(int irq, void *ptr) = { |
1da177e4 LT |
862 | sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, |
863 | sci_br_interrupt, | |
864 | }; | |
865 | const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", | |
866 | "SCI Transmit Data Empty", "SCI Break" }; | |
867 | ||
ce6738b6 PM |
868 | if (port->cfg->irqs[0] == port->cfg->irqs[1]) { |
869 | if (unlikely(!port->cfg->irqs[0])) | |
1da177e4 | 870 | return -ENODEV; |
e108b2ca | 871 | |
ce6738b6 | 872 | if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt, |
35f3c518 | 873 | IRQF_DISABLED, "sci", port)) { |
762c69e3 | 874 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
875 | return -ENODEV; |
876 | } | |
877 | } else { | |
878 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { | |
ce6738b6 | 879 | if (unlikely(!port->cfg->irqs[i])) |
1da177e4 | 880 | continue; |
762c69e3 | 881 | |
ce6738b6 | 882 | if (request_irq(port->cfg->irqs[i], handlers[i], |
35f3c518 | 883 | IRQF_DISABLED, desc[i], port)) { |
762c69e3 | 884 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
885 | return -ENODEV; |
886 | } | |
887 | } | |
888 | } | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
893 | static void sci_free_irq(struct sci_port *port) | |
894 | { | |
895 | int i; | |
896 | ||
ce6738b6 PM |
897 | if (port->cfg->irqs[0] == port->cfg->irqs[1]) |
898 | free_irq(port->cfg->irqs[0], port); | |
762c69e3 | 899 | else { |
ce6738b6 PM |
900 | for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) { |
901 | if (!port->cfg->irqs[i]) | |
1da177e4 LT |
902 | continue; |
903 | ||
ce6738b6 | 904 | free_irq(port->cfg->irqs[i], port); |
1da177e4 LT |
905 | } |
906 | } | |
907 | } | |
908 | ||
909 | static unsigned int sci_tx_empty(struct uart_port *port) | |
910 | { | |
b1516803 | 911 | unsigned short status = sci_in(port, SCxSR); |
73a19e4c GL |
912 | unsigned short in_tx_fifo = scif_txfill(port); |
913 | ||
914 | return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; | |
1da177e4 LT |
915 | } |
916 | ||
917 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
918 | { | |
919 | /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ | |
920 | /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ | |
921 | /* If you have signals for DTR and DCD, please implement here. */ | |
922 | } | |
923 | ||
924 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
925 | { | |
73a19e4c | 926 | /* This routine is used for getting signals of: DTR, DCD, DSR, RI, |
1da177e4 LT |
927 | and CTS/RTS */ |
928 | ||
929 | return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; | |
930 | } | |
931 | ||
73a19e4c GL |
932 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
933 | static void sci_dma_tx_complete(void *arg) | |
934 | { | |
935 | struct sci_port *s = arg; | |
936 | struct uart_port *port = &s->port; | |
937 | struct circ_buf *xmit = &port->state->xmit; | |
938 | unsigned long flags; | |
939 | ||
940 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); | |
941 | ||
942 | spin_lock_irqsave(&port->lock, flags); | |
943 | ||
f354a381 | 944 | xmit->tail += sg_dma_len(&s->sg_tx); |
73a19e4c GL |
945 | xmit->tail &= UART_XMIT_SIZE - 1; |
946 | ||
f354a381 | 947 | port->icount.tx += sg_dma_len(&s->sg_tx); |
73a19e4c GL |
948 | |
949 | async_tx_ack(s->desc_tx); | |
950 | s->cookie_tx = -EINVAL; | |
951 | s->desc_tx = NULL; | |
952 | ||
73a19e4c GL |
953 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
954 | uart_write_wakeup(port); | |
955 | ||
3089f381 | 956 | if (!uart_circ_empty(xmit)) { |
73a19e4c | 957 | schedule_work(&s->work_tx); |
d1d4b10c | 958 | } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 | 959 | u16 ctrl = sci_in(port, SCSCR); |
f43dc23d | 960 | sci_out(port, SCSCR, ctrl & ~SCSCR_TIE); |
3089f381 GL |
961 | } |
962 | ||
963 | spin_unlock_irqrestore(&port->lock, flags); | |
73a19e4c GL |
964 | } |
965 | ||
966 | /* Locking: called with port lock held */ | |
967 | static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty, | |
968 | size_t count) | |
969 | { | |
970 | struct uart_port *port = &s->port; | |
971 | int i, active, room; | |
972 | ||
973 | room = tty_buffer_request_room(tty, count); | |
974 | ||
975 | if (s->active_rx == s->cookie_rx[0]) { | |
976 | active = 0; | |
977 | } else if (s->active_rx == s->cookie_rx[1]) { | |
978 | active = 1; | |
979 | } else { | |
980 | dev_err(port->dev, "cookie %d not found!\n", s->active_rx); | |
981 | return 0; | |
982 | } | |
983 | ||
984 | if (room < count) | |
985 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", | |
986 | count - room); | |
987 | if (!room) | |
988 | return room; | |
989 | ||
990 | for (i = 0; i < room; i++) | |
991 | tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i], | |
992 | TTY_NORMAL); | |
993 | ||
994 | port->icount.rx += room; | |
995 | ||
996 | return room; | |
997 | } | |
998 | ||
999 | static void sci_dma_rx_complete(void *arg) | |
1000 | { | |
1001 | struct sci_port *s = arg; | |
1002 | struct uart_port *port = &s->port; | |
1003 | struct tty_struct *tty = port->state->port.tty; | |
1004 | unsigned long flags; | |
1005 | int count; | |
1006 | ||
3089f381 | 1007 | dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); |
73a19e4c GL |
1008 | |
1009 | spin_lock_irqsave(&port->lock, flags); | |
1010 | ||
1011 | count = sci_dma_rx_push(s, tty, s->buf_len_rx); | |
1012 | ||
3089f381 | 1013 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); |
73a19e4c GL |
1014 | |
1015 | spin_unlock_irqrestore(&port->lock, flags); | |
1016 | ||
1017 | if (count) | |
1018 | tty_flip_buffer_push(tty); | |
1019 | ||
1020 | schedule_work(&s->work_rx); | |
1021 | } | |
1022 | ||
73a19e4c GL |
1023 | static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) |
1024 | { | |
1025 | struct dma_chan *chan = s->chan_rx; | |
1026 | struct uart_port *port = &s->port; | |
73a19e4c GL |
1027 | |
1028 | s->chan_rx = NULL; | |
1029 | s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; | |
1030 | dma_release_channel(chan); | |
85b8e3ff GL |
1031 | if (sg_dma_address(&s->sg_rx[0])) |
1032 | dma_free_coherent(port->dev, s->buf_len_rx * 2, | |
1033 | sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); | |
73a19e4c GL |
1034 | if (enable_pio) |
1035 | sci_start_rx(port); | |
1036 | } | |
1037 | ||
1038 | static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) | |
1039 | { | |
1040 | struct dma_chan *chan = s->chan_tx; | |
1041 | struct uart_port *port = &s->port; | |
73a19e4c GL |
1042 | |
1043 | s->chan_tx = NULL; | |
1044 | s->cookie_tx = -EINVAL; | |
1045 | dma_release_channel(chan); | |
1046 | if (enable_pio) | |
1047 | sci_start_tx(port); | |
1048 | } | |
1049 | ||
1050 | static void sci_submit_rx(struct sci_port *s) | |
1051 | { | |
1052 | struct dma_chan *chan = s->chan_rx; | |
1053 | int i; | |
1054 | ||
1055 | for (i = 0; i < 2; i++) { | |
1056 | struct scatterlist *sg = &s->sg_rx[i]; | |
1057 | struct dma_async_tx_descriptor *desc; | |
1058 | ||
1059 | desc = chan->device->device_prep_slave_sg(chan, | |
1060 | sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT); | |
1061 | ||
1062 | if (desc) { | |
1063 | s->desc_rx[i] = desc; | |
1064 | desc->callback = sci_dma_rx_complete; | |
1065 | desc->callback_param = s; | |
1066 | s->cookie_rx[i] = desc->tx_submit(desc); | |
1067 | } | |
1068 | ||
1069 | if (!desc || s->cookie_rx[i] < 0) { | |
1070 | if (i) { | |
1071 | async_tx_ack(s->desc_rx[0]); | |
1072 | s->cookie_rx[0] = -EINVAL; | |
1073 | } | |
1074 | if (desc) { | |
1075 | async_tx_ack(desc); | |
1076 | s->cookie_rx[i] = -EINVAL; | |
1077 | } | |
1078 | dev_warn(s->port.dev, | |
1079 | "failed to re-start DMA, using PIO\n"); | |
1080 | sci_rx_dma_release(s, true); | |
1081 | return; | |
1082 | } | |
3089f381 GL |
1083 | dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, |
1084 | s->cookie_rx[i], i); | |
73a19e4c GL |
1085 | } |
1086 | ||
1087 | s->active_rx = s->cookie_rx[0]; | |
1088 | ||
1089 | dma_async_issue_pending(chan); | |
1090 | } | |
1091 | ||
1092 | static void work_fn_rx(struct work_struct *work) | |
1093 | { | |
1094 | struct sci_port *s = container_of(work, struct sci_port, work_rx); | |
1095 | struct uart_port *port = &s->port; | |
1096 | struct dma_async_tx_descriptor *desc; | |
1097 | int new; | |
1098 | ||
1099 | if (s->active_rx == s->cookie_rx[0]) { | |
1100 | new = 0; | |
1101 | } else if (s->active_rx == s->cookie_rx[1]) { | |
1102 | new = 1; | |
1103 | } else { | |
1104 | dev_err(port->dev, "cookie %d not found!\n", s->active_rx); | |
1105 | return; | |
1106 | } | |
1107 | desc = s->desc_rx[new]; | |
1108 | ||
1109 | if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != | |
1110 | DMA_SUCCESS) { | |
1111 | /* Handle incomplete DMA receive */ | |
1112 | struct tty_struct *tty = port->state->port.tty; | |
1113 | struct dma_chan *chan = s->chan_rx; | |
1114 | struct sh_desc *sh_desc = container_of(desc, struct sh_desc, | |
1115 | async_tx); | |
1116 | unsigned long flags; | |
1117 | int count; | |
1118 | ||
05827630 | 1119 | chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); |
73a19e4c GL |
1120 | dev_dbg(port->dev, "Read %u bytes with cookie %d\n", |
1121 | sh_desc->partial, sh_desc->cookie); | |
1122 | ||
1123 | spin_lock_irqsave(&port->lock, flags); | |
1124 | count = sci_dma_rx_push(s, tty, sh_desc->partial); | |
1125 | spin_unlock_irqrestore(&port->lock, flags); | |
1126 | ||
1127 | if (count) | |
1128 | tty_flip_buffer_push(tty); | |
1129 | ||
1130 | sci_submit_rx(s); | |
1131 | ||
1132 | return; | |
1133 | } | |
1134 | ||
1135 | s->cookie_rx[new] = desc->tx_submit(desc); | |
1136 | if (s->cookie_rx[new] < 0) { | |
1137 | dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); | |
1138 | sci_rx_dma_release(s, true); | |
1139 | return; | |
1140 | } | |
1141 | ||
73a19e4c | 1142 | s->active_rx = s->cookie_rx[!new]; |
3089f381 GL |
1143 | |
1144 | dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, | |
1145 | s->cookie_rx[new], new, s->active_rx); | |
73a19e4c GL |
1146 | } |
1147 | ||
1148 | static void work_fn_tx(struct work_struct *work) | |
1149 | { | |
1150 | struct sci_port *s = container_of(work, struct sci_port, work_tx); | |
1151 | struct dma_async_tx_descriptor *desc; | |
1152 | struct dma_chan *chan = s->chan_tx; | |
1153 | struct uart_port *port = &s->port; | |
1154 | struct circ_buf *xmit = &port->state->xmit; | |
1155 | struct scatterlist *sg = &s->sg_tx; | |
1156 | ||
1157 | /* | |
1158 | * DMA is idle now. | |
1159 | * Port xmit buffer is already mapped, and it is one page... Just adjust | |
1160 | * offsets and lengths. Since it is a circular buffer, we have to | |
1161 | * transmit till the end, and then the rest. Take the port lock to get a | |
1162 | * consistent xmit buffer state. | |
1163 | */ | |
1164 | spin_lock_irq(&port->lock); | |
1165 | sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); | |
f354a381 | 1166 | sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + |
73a19e4c | 1167 | sg->offset; |
f354a381 | 1168 | sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), |
73a19e4c | 1169 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); |
73a19e4c GL |
1170 | spin_unlock_irq(&port->lock); |
1171 | ||
f354a381 | 1172 | BUG_ON(!sg_dma_len(sg)); |
73a19e4c GL |
1173 | |
1174 | desc = chan->device->device_prep_slave_sg(chan, | |
1175 | sg, s->sg_len_tx, DMA_TO_DEVICE, | |
1176 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1177 | if (!desc) { | |
1178 | /* switch to PIO */ | |
1179 | sci_tx_dma_release(s, true); | |
1180 | return; | |
1181 | } | |
1182 | ||
1183 | dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); | |
1184 | ||
1185 | spin_lock_irq(&port->lock); | |
1186 | s->desc_tx = desc; | |
1187 | desc->callback = sci_dma_tx_complete; | |
1188 | desc->callback_param = s; | |
1189 | spin_unlock_irq(&port->lock); | |
1190 | s->cookie_tx = desc->tx_submit(desc); | |
1191 | if (s->cookie_tx < 0) { | |
1192 | dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); | |
1193 | /* switch to PIO */ | |
1194 | sci_tx_dma_release(s, true); | |
1195 | return; | |
1196 | } | |
1197 | ||
1198 | dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, | |
1199 | xmit->buf, xmit->tail, xmit->head, s->cookie_tx); | |
1200 | ||
1201 | dma_async_issue_pending(chan); | |
1202 | } | |
1203 | #endif | |
1204 | ||
b129a8cc | 1205 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 1206 | { |
3089f381 | 1207 | struct sci_port *s = to_sci_port(port); |
e108b2ca | 1208 | unsigned short ctrl; |
1da177e4 | 1209 | |
73a19e4c | 1210 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
d1d4b10c | 1211 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 GL |
1212 | u16 new, scr = sci_in(port, SCSCR); |
1213 | if (s->chan_tx) | |
1214 | new = scr | 0x8000; | |
1215 | else | |
1216 | new = scr & ~0x8000; | |
1217 | if (new != scr) | |
1218 | sci_out(port, SCSCR, new); | |
73a19e4c | 1219 | } |
f43dc23d | 1220 | |
3089f381 GL |
1221 | if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && |
1222 | s->cookie_tx < 0) | |
1223 | schedule_work(&s->work_tx); | |
73a19e4c | 1224 | #endif |
f43dc23d | 1225 | |
d1d4b10c | 1226 | if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 GL |
1227 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
1228 | ctrl = sci_in(port, SCSCR); | |
f43dc23d | 1229 | sci_out(port, SCSCR, ctrl | SCSCR_TIE); |
3089f381 | 1230 | } |
1da177e4 LT |
1231 | } |
1232 | ||
b129a8cc | 1233 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 1234 | { |
1da177e4 LT |
1235 | unsigned short ctrl; |
1236 | ||
1237 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
1da177e4 | 1238 | ctrl = sci_in(port, SCSCR); |
f43dc23d | 1239 | |
d1d4b10c | 1240 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1241 | ctrl &= ~0x8000; |
f43dc23d | 1242 | |
8e698614 | 1243 | ctrl &= ~SCSCR_TIE; |
f43dc23d | 1244 | |
1da177e4 | 1245 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
1246 | } |
1247 | ||
73a19e4c | 1248 | static void sci_start_rx(struct uart_port *port) |
1da177e4 | 1249 | { |
1da177e4 LT |
1250 | unsigned short ctrl; |
1251 | ||
f43dc23d | 1252 | ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port); |
1da177e4 | 1253 | |
d1d4b10c | 1254 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1255 | ctrl &= ~0x4000; |
f43dc23d | 1256 | |
1da177e4 | 1257 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
1258 | } |
1259 | ||
1260 | static void sci_stop_rx(struct uart_port *port) | |
1261 | { | |
1da177e4 LT |
1262 | unsigned short ctrl; |
1263 | ||
1da177e4 | 1264 | ctrl = sci_in(port, SCSCR); |
f43dc23d | 1265 | |
d1d4b10c | 1266 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1267 | ctrl &= ~0x4000; |
f43dc23d PM |
1268 | |
1269 | ctrl &= ~port_rx_irq_mask(port); | |
1270 | ||
1da177e4 | 1271 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
1272 | } |
1273 | ||
1274 | static void sci_enable_ms(struct uart_port *port) | |
1275 | { | |
1276 | /* Nothing here yet .. */ | |
1277 | } | |
1278 | ||
1279 | static void sci_break_ctl(struct uart_port *port, int break_state) | |
1280 | { | |
1281 | /* Nothing here yet .. */ | |
1282 | } | |
1283 | ||
73a19e4c GL |
1284 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1285 | static bool filter(struct dma_chan *chan, void *slave) | |
1286 | { | |
1287 | struct sh_dmae_slave *param = slave; | |
1288 | ||
1289 | dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, | |
1290 | param->slave_id); | |
1291 | ||
1292 | if (param->dma_dev == chan->device->dev) { | |
1293 | chan->private = param; | |
1294 | return true; | |
1295 | } else { | |
1296 | return false; | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | static void rx_timer_fn(unsigned long arg) | |
1301 | { | |
1302 | struct sci_port *s = (struct sci_port *)arg; | |
1303 | struct uart_port *port = &s->port; | |
73a19e4c | 1304 | u16 scr = sci_in(port, SCSCR); |
3089f381 | 1305 | |
d1d4b10c | 1306 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 | 1307 | scr &= ~0x4000; |
ce6738b6 | 1308 | enable_irq(s->cfg->irqs[1]); |
3089f381 | 1309 | } |
f43dc23d | 1310 | sci_out(port, SCSCR, scr | SCSCR_RIE); |
73a19e4c GL |
1311 | dev_dbg(port->dev, "DMA Rx timed out\n"); |
1312 | schedule_work(&s->work_rx); | |
1313 | } | |
1314 | ||
1315 | static void sci_request_dma(struct uart_port *port) | |
1316 | { | |
1317 | struct sci_port *s = to_sci_port(port); | |
1318 | struct sh_dmae_slave *param; | |
1319 | struct dma_chan *chan; | |
1320 | dma_cap_mask_t mask; | |
1321 | int nent; | |
1322 | ||
1323 | dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__, | |
ce6738b6 | 1324 | port->line, s->cfg->dma_dev); |
73a19e4c | 1325 | |
ce6738b6 | 1326 | if (!s->cfg->dma_dev) |
73a19e4c GL |
1327 | return; |
1328 | ||
1329 | dma_cap_zero(mask); | |
1330 | dma_cap_set(DMA_SLAVE, mask); | |
1331 | ||
1332 | param = &s->param_tx; | |
1333 | ||
1334 | /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ | |
ce6738b6 PM |
1335 | param->slave_id = s->cfg->dma_slave_tx; |
1336 | param->dma_dev = s->cfg->dma_dev; | |
73a19e4c GL |
1337 | |
1338 | s->cookie_tx = -EINVAL; | |
1339 | chan = dma_request_channel(mask, filter, param); | |
1340 | dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); | |
1341 | if (chan) { | |
1342 | s->chan_tx = chan; | |
1343 | sg_init_table(&s->sg_tx, 1); | |
1344 | /* UART circular tx buffer is an aligned page. */ | |
1345 | BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); | |
1346 | sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), | |
1347 | UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); | |
1348 | nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); | |
1349 | if (!nent) | |
1350 | sci_tx_dma_release(s, false); | |
1351 | else | |
1352 | dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, | |
1353 | sg_dma_len(&s->sg_tx), | |
1354 | port->state->xmit.buf, sg_dma_address(&s->sg_tx)); | |
1355 | ||
1356 | s->sg_len_tx = nent; | |
1357 | ||
1358 | INIT_WORK(&s->work_tx, work_fn_tx); | |
1359 | } | |
1360 | ||
1361 | param = &s->param_rx; | |
1362 | ||
1363 | /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ | |
ce6738b6 PM |
1364 | param->slave_id = s->cfg->dma_slave_rx; |
1365 | param->dma_dev = s->cfg->dma_dev; | |
73a19e4c GL |
1366 | |
1367 | chan = dma_request_channel(mask, filter, param); | |
1368 | dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); | |
1369 | if (chan) { | |
1370 | dma_addr_t dma[2]; | |
1371 | void *buf[2]; | |
1372 | int i; | |
1373 | ||
1374 | s->chan_rx = chan; | |
1375 | ||
1376 | s->buf_len_rx = 2 * max(16, (int)port->fifosize); | |
1377 | buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, | |
1378 | &dma[0], GFP_KERNEL); | |
1379 | ||
1380 | if (!buf[0]) { | |
1381 | dev_warn(port->dev, | |
1382 | "failed to allocate dma buffer, using PIO\n"); | |
1383 | sci_rx_dma_release(s, true); | |
1384 | return; | |
1385 | } | |
1386 | ||
1387 | buf[1] = buf[0] + s->buf_len_rx; | |
1388 | dma[1] = dma[0] + s->buf_len_rx; | |
1389 | ||
1390 | for (i = 0; i < 2; i++) { | |
1391 | struct scatterlist *sg = &s->sg_rx[i]; | |
1392 | ||
1393 | sg_init_table(sg, 1); | |
1394 | sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, | |
1395 | (int)buf[i] & ~PAGE_MASK); | |
f354a381 | 1396 | sg_dma_address(sg) = dma[i]; |
73a19e4c GL |
1397 | } |
1398 | ||
1399 | INIT_WORK(&s->work_rx, work_fn_rx); | |
1400 | setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); | |
1401 | ||
1402 | sci_submit_rx(s); | |
1403 | } | |
1404 | } | |
1405 | ||
1406 | static void sci_free_dma(struct uart_port *port) | |
1407 | { | |
1408 | struct sci_port *s = to_sci_port(port); | |
1409 | ||
ce6738b6 | 1410 | if (!s->cfg->dma_dev) |
73a19e4c GL |
1411 | return; |
1412 | ||
1413 | if (s->chan_tx) | |
1414 | sci_tx_dma_release(s, false); | |
1415 | if (s->chan_rx) | |
1416 | sci_rx_dma_release(s, false); | |
1417 | } | |
27bd1075 PM |
1418 | #else |
1419 | static inline void sci_request_dma(struct uart_port *port) | |
1420 | { | |
1421 | } | |
1422 | ||
1423 | static inline void sci_free_dma(struct uart_port *port) | |
1424 | { | |
1425 | } | |
73a19e4c GL |
1426 | #endif |
1427 | ||
1da177e4 LT |
1428 | static int sci_startup(struct uart_port *port) |
1429 | { | |
a5660ada | 1430 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1431 | |
73a19e4c GL |
1432 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1433 | ||
e108b2ca PM |
1434 | if (s->enable) |
1435 | s->enable(port); | |
1da177e4 LT |
1436 | |
1437 | sci_request_irq(s); | |
73a19e4c | 1438 | sci_request_dma(port); |
d656901b | 1439 | sci_start_tx(port); |
73a19e4c | 1440 | sci_start_rx(port); |
1da177e4 LT |
1441 | |
1442 | return 0; | |
1443 | } | |
1444 | ||
1445 | static void sci_shutdown(struct uart_port *port) | |
1446 | { | |
a5660ada | 1447 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1448 | |
73a19e4c GL |
1449 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1450 | ||
1da177e4 | 1451 | sci_stop_rx(port); |
b129a8cc | 1452 | sci_stop_tx(port); |
73a19e4c | 1453 | sci_free_dma(port); |
1da177e4 LT |
1454 | sci_free_irq(s); |
1455 | ||
e108b2ca PM |
1456 | if (s->disable) |
1457 | s->disable(port); | |
1da177e4 LT |
1458 | } |
1459 | ||
26c92f37 PM |
1460 | static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, |
1461 | unsigned long freq) | |
1462 | { | |
1463 | switch (algo_id) { | |
1464 | case SCBRR_ALGO_1: | |
1465 | return ((freq + 16 * bps) / (16 * bps) - 1); | |
1466 | case SCBRR_ALGO_2: | |
1467 | return ((freq + 16 * bps) / (32 * bps) - 1); | |
1468 | case SCBRR_ALGO_3: | |
1469 | return (((freq * 2) + 16 * bps) / (16 * bps) - 1); | |
1470 | case SCBRR_ALGO_4: | |
1471 | return (((freq * 2) + 16 * bps) / (32 * bps) - 1); | |
1472 | case SCBRR_ALGO_5: | |
1473 | return (((freq * 1000 / 32) / bps) - 1); | |
1474 | } | |
1475 | ||
1476 | /* Warn, but use a safe default */ | |
1477 | WARN_ON(1); | |
1478 | return ((freq + 16 * bps) / (32 * bps) - 1); | |
1479 | } | |
1480 | ||
606d099c AC |
1481 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
1482 | struct ktermios *old) | |
1da177e4 | 1483 | { |
00b9de9c | 1484 | struct sci_port *s = to_sci_port(port); |
154280fd | 1485 | unsigned int status, baud, smr_val, max_baud; |
a2159b52 | 1486 | int t = -1; |
3089f381 | 1487 | u16 scfcr = 0; |
1da177e4 | 1488 | |
154280fd MD |
1489 | /* |
1490 | * earlyprintk comes here early on with port->uartclk set to zero. | |
1491 | * the clock framework is not up and running at this point so here | |
1492 | * we assume that 115200 is the maximum baud rate. please note that | |
1493 | * the baud rate is not programmed during earlyprintk - it is assumed | |
1494 | * that the previous boot loader has enabled required clocks and | |
1495 | * setup the baud rate generator hardware for us already. | |
1496 | */ | |
1497 | max_baud = port->uartclk ? port->uartclk / 16 : 115200; | |
1da177e4 | 1498 | |
154280fd MD |
1499 | baud = uart_get_baud_rate(port, termios, old, 0, max_baud); |
1500 | if (likely(baud && port->uartclk)) | |
ce6738b6 | 1501 | t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk); |
e108b2ca | 1502 | |
1da177e4 LT |
1503 | do { |
1504 | status = sci_in(port, SCxSR); | |
1505 | } while (!(status & SCxSR_TEND(port))); | |
1506 | ||
1507 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ | |
1508 | ||
1a22f08d | 1509 | if (port->type != PORT_SCI) |
3089f381 | 1510 | sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST); |
1da177e4 LT |
1511 | |
1512 | smr_val = sci_in(port, SCSMR) & 3; | |
1513 | if ((termios->c_cflag & CSIZE) == CS7) | |
1514 | smr_val |= 0x40; | |
1515 | if (termios->c_cflag & PARENB) | |
1516 | smr_val |= 0x20; | |
1517 | if (termios->c_cflag & PARODD) | |
1518 | smr_val |= 0x30; | |
1519 | if (termios->c_cflag & CSTOPB) | |
1520 | smr_val |= 0x08; | |
1521 | ||
1522 | uart_update_timeout(port, termios->c_cflag, baud); | |
1523 | ||
1524 | sci_out(port, SCSMR, smr_val); | |
1525 | ||
73a19e4c | 1526 | dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t, |
ce6738b6 | 1527 | s->cfg->scscr); |
73a19e4c | 1528 | |
1da177e4 | 1529 | if (t > 0) { |
e7c98dc7 | 1530 | if (t >= 256) { |
1da177e4 LT |
1531 | sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); |
1532 | t >>= 2; | |
e7c98dc7 | 1533 | } else |
1da177e4 | 1534 | sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); |
e7c98dc7 | 1535 | |
1da177e4 LT |
1536 | sci_out(port, SCBRR, t); |
1537 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ | |
1538 | } | |
1539 | ||
d5701647 | 1540 | sci_init_pins(port, termios->c_cflag); |
3089f381 | 1541 | sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0)); |
b7a76e4b | 1542 | |
ce6738b6 | 1543 | sci_out(port, SCSCR, s->cfg->scscr); |
1da177e4 | 1544 | |
3089f381 GL |
1545 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1546 | /* | |
1547 | * Calculate delay for 1.5 DMA buffers: see | |
1548 | * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits | |
1549 | * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function | |
1550 | * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." | |
1551 | * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO | |
1552 | * sizes), but it has been found out experimentally, that this is not | |
1553 | * enough: the driver too often needlessly runs on a DMA timeout. 20ms | |
1554 | * as a minimum seem to work perfectly. | |
1555 | */ | |
1556 | if (s->chan_rx) { | |
1557 | s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / | |
1558 | port->fifosize / 2; | |
1559 | dev_dbg(port->dev, | |
1560 | "DMA Rx t-out %ums, tty t-out %u jiffies\n", | |
1561 | s->rx_timeout * 1000 / HZ, port->timeout); | |
1562 | if (s->rx_timeout < msecs_to_jiffies(20)) | |
1563 | s->rx_timeout = msecs_to_jiffies(20); | |
1564 | } | |
1565 | #endif | |
1566 | ||
1da177e4 | 1567 | if ((termios->c_cflag & CREAD) != 0) |
73a19e4c | 1568 | sci_start_rx(port); |
1da177e4 LT |
1569 | } |
1570 | ||
1571 | static const char *sci_type(struct uart_port *port) | |
1572 | { | |
1573 | switch (port->type) { | |
e7c98dc7 MT |
1574 | case PORT_IRDA: |
1575 | return "irda"; | |
1576 | case PORT_SCI: | |
1577 | return "sci"; | |
1578 | case PORT_SCIF: | |
1579 | return "scif"; | |
1580 | case PORT_SCIFA: | |
1581 | return "scifa"; | |
d1d4b10c GL |
1582 | case PORT_SCIFB: |
1583 | return "scifb"; | |
1da177e4 LT |
1584 | } |
1585 | ||
fa43972f | 1586 | return NULL; |
1da177e4 LT |
1587 | } |
1588 | ||
1589 | static void sci_release_port(struct uart_port *port) | |
1590 | { | |
1591 | /* Nothing here yet .. */ | |
1592 | } | |
1593 | ||
1594 | static int sci_request_port(struct uart_port *port) | |
1595 | { | |
1596 | /* Nothing here yet .. */ | |
1597 | return 0; | |
1598 | } | |
1599 | ||
1600 | static void sci_config_port(struct uart_port *port, int flags) | |
1601 | { | |
a5660ada | 1602 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1603 | |
ce6738b6 | 1604 | port->type = s->cfg->type; |
1da177e4 | 1605 | |
08f8cb31 | 1606 | if (port->flags & UPF_IOREMAP) { |
7ff731ae | 1607 | port->membase = ioremap_nocache(port->mapbase, 0x40); |
08f8cb31 MD |
1608 | |
1609 | if (IS_ERR(port->membase)) | |
1610 | dev_err(port->dev, "can't remap port#%d\n", port->line); | |
1611 | } else { | |
1612 | /* | |
1613 | * For the simple (and majority of) cases where we don't | |
1614 | * need to do any remapping, just cast the cookie | |
1615 | * directly. | |
1616 | */ | |
1617 | port->membase = (void __iomem *)port->mapbase; | |
7ff731ae | 1618 | } |
1da177e4 LT |
1619 | } |
1620 | ||
1621 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1622 | { | |
a5660ada | 1623 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1624 | |
ce6738b6 | 1625 | if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) |
1da177e4 LT |
1626 | return -EINVAL; |
1627 | if (ser->baud_base < 2400) | |
1628 | /* No paper tape reader for Mitch.. */ | |
1629 | return -EINVAL; | |
1630 | ||
1631 | return 0; | |
1632 | } | |
1633 | ||
1634 | static struct uart_ops sci_uart_ops = { | |
1635 | .tx_empty = sci_tx_empty, | |
1636 | .set_mctrl = sci_set_mctrl, | |
1637 | .get_mctrl = sci_get_mctrl, | |
1638 | .start_tx = sci_start_tx, | |
1639 | .stop_tx = sci_stop_tx, | |
1640 | .stop_rx = sci_stop_rx, | |
1641 | .enable_ms = sci_enable_ms, | |
1642 | .break_ctl = sci_break_ctl, | |
1643 | .startup = sci_startup, | |
1644 | .shutdown = sci_shutdown, | |
1645 | .set_termios = sci_set_termios, | |
1646 | .type = sci_type, | |
1647 | .release_port = sci_release_port, | |
1648 | .request_port = sci_request_port, | |
1649 | .config_port = sci_config_port, | |
1650 | .verify_port = sci_verify_port, | |
07d2a1a1 PM |
1651 | #ifdef CONFIG_CONSOLE_POLL |
1652 | .poll_get_char = sci_poll_get_char, | |
1653 | .poll_put_char = sci_poll_put_char, | |
1654 | #endif | |
1da177e4 LT |
1655 | }; |
1656 | ||
c7ed1ab3 PM |
1657 | static int __devinit sci_init_single(struct platform_device *dev, |
1658 | struct sci_port *sci_port, | |
1659 | unsigned int index, | |
1660 | struct plat_sci_port *p) | |
e108b2ca | 1661 | { |
73a19e4c | 1662 | struct uart_port *port = &sci_port->port; |
e108b2ca | 1663 | |
73a19e4c GL |
1664 | port->ops = &sci_uart_ops; |
1665 | port->iotype = UPIO_MEM; | |
1666 | port->line = index; | |
75136d48 MP |
1667 | |
1668 | switch (p->type) { | |
d1d4b10c GL |
1669 | case PORT_SCIFB: |
1670 | port->fifosize = 256; | |
1671 | break; | |
75136d48 | 1672 | case PORT_SCIFA: |
73a19e4c | 1673 | port->fifosize = 64; |
75136d48 MP |
1674 | break; |
1675 | case PORT_SCIF: | |
73a19e4c | 1676 | port->fifosize = 16; |
75136d48 MP |
1677 | break; |
1678 | default: | |
73a19e4c | 1679 | port->fifosize = 1; |
75136d48 MP |
1680 | break; |
1681 | } | |
7b6fd3bf MD |
1682 | |
1683 | if (dev) { | |
c7ed1ab3 PM |
1684 | sci_port->iclk = clk_get(&dev->dev, "sci_ick"); |
1685 | if (IS_ERR(sci_port->iclk)) { | |
1686 | sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); | |
1687 | if (IS_ERR(sci_port->iclk)) { | |
1688 | dev_err(&dev->dev, "can't get iclk\n"); | |
1689 | return PTR_ERR(sci_port->iclk); | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | /* | |
1694 | * The function clock is optional, ignore it if we can't | |
1695 | * find it. | |
1696 | */ | |
1697 | sci_port->fclk = clk_get(&dev->dev, "sci_fck"); | |
1698 | if (IS_ERR(sci_port->fclk)) | |
1699 | sci_port->fclk = NULL; | |
1700 | ||
7b6fd3bf MD |
1701 | sci_port->enable = sci_clk_enable; |
1702 | sci_port->disable = sci_clk_disable; | |
73a19e4c | 1703 | port->dev = &dev->dev; |
7b6fd3bf | 1704 | } |
e108b2ca | 1705 | |
7ed7e071 MD |
1706 | sci_port->break_timer.data = (unsigned long)sci_port; |
1707 | sci_port->break_timer.function = sci_break_timer; | |
1708 | init_timer(&sci_port->break_timer); | |
1709 | ||
ce6738b6 | 1710 | sci_port->cfg = p; |
7ed7e071 | 1711 | |
ce6738b6 PM |
1712 | port->mapbase = p->mapbase; |
1713 | port->type = p->type; | |
f43dc23d | 1714 | port->flags = p->flags; |
73a19e4c | 1715 | |
ce6738b6 PM |
1716 | /* |
1717 | * The UART port needs an IRQ value, so we peg this to the TX IRQ | |
1718 | * for the multi-IRQ ports, which is where we are primarily | |
1719 | * concerned with the shutdown path synchronization. | |
1720 | * | |
1721 | * For the muxed case there's nothing more to do. | |
1722 | */ | |
1723 | port->irq = p->irqs[SCIx_TXI_IRQ]; | |
73a19e4c | 1724 | |
ce6738b6 PM |
1725 | if (p->dma_dev) |
1726 | dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n", | |
1727 | p->dma_dev, p->dma_slave_tx, p->dma_slave_rx); | |
7ed7e071 | 1728 | |
c7ed1ab3 | 1729 | return 0; |
e108b2ca PM |
1730 | } |
1731 | ||
1da177e4 | 1732 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
dc8e6f5b MD |
1733 | static struct tty_driver *serial_console_device(struct console *co, int *index) |
1734 | { | |
1735 | struct uart_driver *p = &sci_uart_driver; | |
1736 | *index = co->index; | |
1737 | return p->tty_driver; | |
1738 | } | |
1739 | ||
1740 | static void serial_console_putchar(struct uart_port *port, int ch) | |
1741 | { | |
1742 | sci_poll_put_char(port, ch); | |
1743 | } | |
1744 | ||
1da177e4 LT |
1745 | /* |
1746 | * Print a string to the serial port trying not to disturb | |
1747 | * any possible real use of the port... | |
1748 | */ | |
1749 | static void serial_console_write(struct console *co, const char *s, | |
1750 | unsigned count) | |
1751 | { | |
dc8e6f5b | 1752 | struct uart_port *port = co->data; |
501b825d | 1753 | struct sci_port *sci_port = to_sci_port(port); |
973e5d52 | 1754 | unsigned short bits; |
07d2a1a1 | 1755 | |
501b825d MD |
1756 | if (sci_port->enable) |
1757 | sci_port->enable(port); | |
1758 | ||
1759 | uart_console_write(port, s, count, serial_console_putchar); | |
973e5d52 MD |
1760 | |
1761 | /* wait until fifo is empty and last bit has been transmitted */ | |
1762 | bits = SCxSR_TDxE(port) | SCxSR_TEND(port); | |
1763 | while ((sci_in(port, SCxSR) & bits) != bits) | |
1764 | cpu_relax(); | |
501b825d | 1765 | |
345e5a76 | 1766 | if (sci_port->disable) |
501b825d | 1767 | sci_port->disable(port); |
1da177e4 LT |
1768 | } |
1769 | ||
7b6fd3bf | 1770 | static int __devinit serial_console_setup(struct console *co, char *options) |
1da177e4 | 1771 | { |
dc8e6f5b | 1772 | struct sci_port *sci_port; |
1da177e4 LT |
1773 | struct uart_port *port; |
1774 | int baud = 115200; | |
1775 | int bits = 8; | |
1776 | int parity = 'n'; | |
1777 | int flow = 'n'; | |
1778 | int ret; | |
1779 | ||
e108b2ca PM |
1780 | /* |
1781 | * Check whether an invalid uart number has been specified, and | |
1782 | * if so, search for the first available port that does have | |
1783 | * console support. | |
1784 | */ | |
1785 | if (co->index >= SCI_NPORTS) | |
1786 | co->index = 0; | |
1787 | ||
7b6fd3bf MD |
1788 | if (co->data) { |
1789 | port = co->data; | |
1790 | sci_port = to_sci_port(port); | |
1791 | } else { | |
1792 | sci_port = &sci_ports[co->index]; | |
1793 | port = &sci_port->port; | |
1794 | co->data = port; | |
1795 | } | |
1da177e4 LT |
1796 | |
1797 | /* | |
e108b2ca PM |
1798 | * Also need to check port->type, we don't actually have any |
1799 | * UPIO_PORT ports, but uart_report_port() handily misreports | |
1800 | * it anyways if we don't have a port available by the time this is | |
1801 | * called. | |
1da177e4 | 1802 | */ |
e108b2ca PM |
1803 | if (!port->type) |
1804 | return -ENODEV; | |
e108b2ca | 1805 | |
08f8cb31 | 1806 | sci_config_port(port, 0); |
e108b2ca | 1807 | |
dc8e6f5b MD |
1808 | if (sci_port->enable) |
1809 | sci_port->enable(port); | |
b7a76e4b | 1810 | |
1da177e4 LT |
1811 | if (options) |
1812 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1813 | ||
1814 | ret = uart_set_options(port, co, baud, parity, bits, flow); | |
1815 | #if defined(__H8300H__) || defined(__H8300S__) | |
1816 | /* disable rx interrupt */ | |
1817 | if (ret == 0) | |
1818 | sci_stop_rx(port); | |
1819 | #endif | |
501b825d | 1820 | /* TODO: disable clock */ |
1da177e4 LT |
1821 | return ret; |
1822 | } | |
1823 | ||
1824 | static struct console serial_console = { | |
1825 | .name = "ttySC", | |
dc8e6f5b | 1826 | .device = serial_console_device, |
1da177e4 LT |
1827 | .write = serial_console_write, |
1828 | .setup = serial_console_setup, | |
fa5da2f7 | 1829 | .flags = CON_PRINTBUFFER, |
1da177e4 | 1830 | .index = -1, |
1da177e4 LT |
1831 | }; |
1832 | ||
1833 | static int __init sci_console_init(void) | |
1834 | { | |
1835 | register_console(&serial_console); | |
1836 | return 0; | |
1837 | } | |
1da177e4 | 1838 | console_initcall(sci_console_init); |
7b6fd3bf MD |
1839 | |
1840 | static struct sci_port early_serial_port; | |
1841 | static struct console early_serial_console = { | |
1842 | .name = "early_ttySC", | |
1843 | .write = serial_console_write, | |
1844 | .flags = CON_PRINTBUFFER, | |
1845 | }; | |
1846 | static char early_serial_buf[32]; | |
1847 | ||
1da177e4 LT |
1848 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1849 | ||
07d2a1a1 | 1850 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
e7c98dc7 | 1851 | #define SCI_CONSOLE (&serial_console) |
1da177e4 | 1852 | #else |
b7a76e4b | 1853 | #define SCI_CONSOLE 0 |
1da177e4 LT |
1854 | #endif |
1855 | ||
1856 | static char banner[] __initdata = | |
1857 | KERN_INFO "SuperH SCI(F) driver initialized\n"; | |
1858 | ||
1859 | static struct uart_driver sci_uart_driver = { | |
1860 | .owner = THIS_MODULE, | |
1861 | .driver_name = "sci", | |
1da177e4 LT |
1862 | .dev_name = "ttySC", |
1863 | .major = SCI_MAJOR, | |
1864 | .minor = SCI_MINOR_START, | |
e108b2ca | 1865 | .nr = SCI_NPORTS, |
1da177e4 LT |
1866 | .cons = SCI_CONSOLE, |
1867 | }; | |
1868 | ||
54507f6e | 1869 | static int sci_remove(struct platform_device *dev) |
e552de24 | 1870 | { |
d535a230 | 1871 | struct sci_port *port = platform_get_drvdata(dev); |
e552de24 | 1872 | |
d535a230 PM |
1873 | cpufreq_unregister_notifier(&port->freq_transition, |
1874 | CPUFREQ_TRANSITION_NOTIFIER); | |
e552de24 | 1875 | |
d535a230 PM |
1876 | uart_remove_one_port(&sci_uart_driver, &port->port); |
1877 | ||
1878 | clk_put(port->iclk); | |
1879 | clk_put(port->fclk); | |
e552de24 | 1880 | |
e552de24 MD |
1881 | return 0; |
1882 | } | |
1883 | ||
0ee70712 MD |
1884 | static int __devinit sci_probe_single(struct platform_device *dev, |
1885 | unsigned int index, | |
1886 | struct plat_sci_port *p, | |
1887 | struct sci_port *sciport) | |
1888 | { | |
0ee70712 MD |
1889 | int ret; |
1890 | ||
1891 | /* Sanity check */ | |
1892 | if (unlikely(index >= SCI_NPORTS)) { | |
1893 | dev_notice(&dev->dev, "Attempting to register port " | |
1894 | "%d when only %d are available.\n", | |
1895 | index+1, SCI_NPORTS); | |
1896 | dev_notice(&dev->dev, "Consider bumping " | |
1897 | "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); | |
1898 | return 0; | |
1899 | } | |
1900 | ||
c7ed1ab3 PM |
1901 | ret = sci_init_single(dev, sciport, index, p); |
1902 | if (ret) | |
1903 | return ret; | |
0ee70712 | 1904 | |
d535a230 | 1905 | return uart_add_one_port(&sci_uart_driver, &sciport->port); |
0ee70712 MD |
1906 | } |
1907 | ||
e108b2ca PM |
1908 | /* |
1909 | * Register a set of serial devices attached to a platform device. The | |
1910 | * list is terminated with a zero flags entry, which means we expect | |
1911 | * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need | |
1912 | * remapping (such as sh64) should also set UPF_IOREMAP. | |
1913 | */ | |
1914 | static int __devinit sci_probe(struct platform_device *dev) | |
1da177e4 | 1915 | { |
e108b2ca | 1916 | struct plat_sci_port *p = dev->dev.platform_data; |
d535a230 PM |
1917 | struct sci_port *sp = &sci_ports[dev->id]; |
1918 | int ret = -EINVAL; | |
e552de24 | 1919 | |
7b6fd3bf MD |
1920 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
1921 | if (is_early_platform_device(dev)) { | |
7b6fd3bf MD |
1922 | early_serial_console.index = dev->id; |
1923 | early_serial_console.data = &early_serial_port.port; | |
d535a230 | 1924 | |
7b6fd3bf | 1925 | sci_init_single(NULL, &early_serial_port, dev->id, p); |
d535a230 | 1926 | |
7b6fd3bf | 1927 | serial_console_setup(&early_serial_console, early_serial_buf); |
d535a230 | 1928 | |
7b6fd3bf MD |
1929 | if (!strstr(early_serial_buf, "keep")) |
1930 | early_serial_console.flags |= CON_BOOT; | |
d535a230 | 1931 | |
7b6fd3bf MD |
1932 | register_console(&early_serial_console); |
1933 | return 0; | |
1934 | } | |
1935 | #endif | |
1936 | ||
d535a230 | 1937 | platform_set_drvdata(dev, sp); |
e552de24 | 1938 | |
d535a230 PM |
1939 | ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]); |
1940 | if (ret) | |
1941 | goto err_unreg; | |
e552de24 | 1942 | |
d535a230 | 1943 | sp->freq_transition.notifier_call = sci_notifier; |
1da177e4 | 1944 | |
d535a230 PM |
1945 | ret = cpufreq_register_notifier(&sp->freq_transition, |
1946 | CPUFREQ_TRANSITION_NOTIFIER); | |
1947 | if (unlikely(ret < 0)) | |
1948 | goto err_unreg; | |
1da177e4 LT |
1949 | |
1950 | #ifdef CONFIG_SH_STANDARD_BIOS | |
1951 | sh_bios_gdb_detach(); | |
1952 | #endif | |
1953 | ||
e108b2ca | 1954 | return 0; |
7ff731ae PM |
1955 | |
1956 | err_unreg: | |
e552de24 | 1957 | sci_remove(dev); |
7ff731ae | 1958 | return ret; |
1da177e4 LT |
1959 | } |
1960 | ||
6daa79b3 | 1961 | static int sci_suspend(struct device *dev) |
1da177e4 | 1962 | { |
d535a230 | 1963 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 1964 | |
d535a230 PM |
1965 | if (sport) |
1966 | uart_suspend_port(&sci_uart_driver, &sport->port); | |
1da177e4 | 1967 | |
e108b2ca PM |
1968 | return 0; |
1969 | } | |
1da177e4 | 1970 | |
6daa79b3 | 1971 | static int sci_resume(struct device *dev) |
e108b2ca | 1972 | { |
d535a230 | 1973 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 1974 | |
d535a230 PM |
1975 | if (sport) |
1976 | uart_resume_port(&sci_uart_driver, &sport->port); | |
e108b2ca PM |
1977 | |
1978 | return 0; | |
1979 | } | |
1980 | ||
47145210 | 1981 | static const struct dev_pm_ops sci_dev_pm_ops = { |
6daa79b3 PM |
1982 | .suspend = sci_suspend, |
1983 | .resume = sci_resume, | |
1984 | }; | |
1985 | ||
e108b2ca PM |
1986 | static struct platform_driver sci_driver = { |
1987 | .probe = sci_probe, | |
b9e39c89 | 1988 | .remove = sci_remove, |
e108b2ca PM |
1989 | .driver = { |
1990 | .name = "sh-sci", | |
1991 | .owner = THIS_MODULE, | |
6daa79b3 | 1992 | .pm = &sci_dev_pm_ops, |
e108b2ca PM |
1993 | }, |
1994 | }; | |
1995 | ||
1996 | static int __init sci_init(void) | |
1997 | { | |
1998 | int ret; | |
1999 | ||
2000 | printk(banner); | |
2001 | ||
e108b2ca PM |
2002 | ret = uart_register_driver(&sci_uart_driver); |
2003 | if (likely(ret == 0)) { | |
2004 | ret = platform_driver_register(&sci_driver); | |
2005 | if (unlikely(ret)) | |
2006 | uart_unregister_driver(&sci_uart_driver); | |
2007 | } | |
2008 | ||
2009 | return ret; | |
2010 | } | |
2011 | ||
2012 | static void __exit sci_exit(void) | |
2013 | { | |
2014 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
2015 | uart_unregister_driver(&sci_uart_driver); |
2016 | } | |
2017 | ||
7b6fd3bf MD |
2018 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
2019 | early_platform_init_buffer("earlyprintk", &sci_driver, | |
2020 | early_serial_buf, ARRAY_SIZE(early_serial_buf)); | |
2021 | #endif | |
1da177e4 LT |
2022 | module_init(sci_init); |
2023 | module_exit(sci_exit); | |
2024 | ||
e108b2ca | 2025 | MODULE_LICENSE("GPL"); |
e169c139 | 2026 | MODULE_ALIAS("platform:sh-sci"); |