Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/serial/sh-sci.c | |
3 | * | |
4 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
5 | * | |
7ff731ae | 6 | * Copyright (C) 2002 - 2008 Paul Mundt |
3ea6bc3d | 7 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
8 | * |
9 | * based off of the old drivers/char/sh-sci.c by: | |
10 | * | |
11 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
12 | * Copyright (C) 2000 Sugioka Toshinobu | |
13 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
14 | * Modified to support SecureEdge. David McCullough (2002) | |
15 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 16 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
17 | * |
18 | * This file is subject to the terms and conditions of the GNU General Public | |
19 | * License. See the file "COPYING" in the main directory of this archive | |
20 | * for more details. | |
21 | */ | |
0b3d4ef6 PM |
22 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
23 | #define SUPPORT_SYSRQ | |
24 | #endif | |
1da177e4 LT |
25 | |
26 | #undef DEBUG | |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/errno.h> | |
1da177e4 LT |
30 | #include <linux/timer.h> |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/tty_flip.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/major.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/sysrq.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/mm.h> | |
1da177e4 LT |
40 | #include <linux/init.h> |
41 | #include <linux/delay.h> | |
42 | #include <linux/console.h> | |
e108b2ca | 43 | #include <linux/platform_device.h> |
96de1a8f | 44 | #include <linux/serial_sci.h> |
1da177e4 LT |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpufreq.h> | |
85f094ec | 47 | #include <linux/clk.h> |
fa5da2f7 | 48 | #include <linux/ctype.h> |
7ff731ae | 49 | #include <linux/err.h> |
e552de24 | 50 | #include <linux/list.h> |
85f094ec PM |
51 | |
52 | #ifdef CONFIG_SUPERH | |
b7a76e4b | 53 | #include <asm/clock.h> |
1da177e4 LT |
54 | #include <asm/sh_bios.h> |
55 | #endif | |
56 | ||
1da177e4 LT |
57 | #include "sh-sci.h" |
58 | ||
e108b2ca PM |
59 | struct sci_port { |
60 | struct uart_port port; | |
61 | ||
62 | /* Port type */ | |
63 | unsigned int type; | |
64 | ||
65 | /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ | |
32351a28 | 66 | unsigned int irqs[SCIx_NR_IRQS]; |
e108b2ca | 67 | |
e108b2ca PM |
68 | /* Port enable callback */ |
69 | void (*enable)(struct uart_port *port); | |
70 | ||
71 | /* Port disable callback */ | |
72 | void (*disable)(struct uart_port *port); | |
73 | ||
74 | /* Break timer */ | |
75 | struct timer_list break_timer; | |
76 | int break_flag; | |
1534a3b3 | 77 | |
a2159b52 | 78 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 79 | /* Port clock */ |
80 | struct clk *clk; | |
e552de24 MD |
81 | #endif |
82 | struct list_head node; | |
83 | }; | |
84 | ||
85 | struct sh_sci_priv { | |
86 | spinlock_t lock; | |
87 | struct list_head ports; | |
88 | ||
89 | #ifdef CONFIG_HAVE_CLK | |
90 | struct notifier_block clk_nb; | |
005a336e | 91 | #endif |
e108b2ca PM |
92 | }; |
93 | ||
1da177e4 | 94 | /* Function prototypes */ |
b129a8cc | 95 | static void sci_stop_tx(struct uart_port *port); |
1da177e4 | 96 | |
e108b2ca | 97 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 98 | |
e108b2ca PM |
99 | static struct sci_port sci_ports[SCI_NPORTS]; |
100 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 101 | |
e7c98dc7 MT |
102 | static inline struct sci_port * |
103 | to_sci_port(struct uart_port *uart) | |
104 | { | |
105 | return container_of(uart, struct sci_port, port); | |
106 | } | |
107 | ||
07d2a1a1 | 108 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
1f6fd5c9 PM |
109 | |
110 | #ifdef CONFIG_CONSOLE_POLL | |
e108b2ca PM |
111 | static inline void handle_error(struct uart_port *port) |
112 | { | |
113 | /* Clear error flags */ | |
1da177e4 LT |
114 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
115 | } | |
116 | ||
07d2a1a1 | 117 | static int sci_poll_get_char(struct uart_port *port) |
1da177e4 | 118 | { |
1da177e4 LT |
119 | unsigned short status; |
120 | int c; | |
121 | ||
e108b2ca | 122 | do { |
1da177e4 LT |
123 | status = sci_in(port, SCxSR); |
124 | if (status & SCxSR_ERRORS(port)) { | |
125 | handle_error(port); | |
126 | continue; | |
127 | } | |
128 | } while (!(status & SCxSR_RDxF(port))); | |
07d2a1a1 | 129 | |
1da177e4 | 130 | c = sci_in(port, SCxRDR); |
07d2a1a1 | 131 | |
e7c98dc7 MT |
132 | /* Dummy read */ |
133 | sci_in(port, SCxSR); | |
1da177e4 | 134 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
135 | |
136 | return c; | |
137 | } | |
1f6fd5c9 | 138 | #endif |
1da177e4 | 139 | |
07d2a1a1 | 140 | static void sci_poll_put_char(struct uart_port *port, unsigned char c) |
1da177e4 | 141 | { |
1da177e4 LT |
142 | unsigned short status; |
143 | ||
1da177e4 LT |
144 | do { |
145 | status = sci_in(port, SCxSR); | |
146 | } while (!(status & SCxSR_TDxE(port))); | |
147 | ||
1da177e4 | 148 | sci_in(port, SCxSR); /* Dummy read */ |
973e5d52 | 149 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); |
272966c0 | 150 | sci_out(port, SCxTDR, c); |
1da177e4 | 151 | } |
07d2a1a1 | 152 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1da177e4 LT |
153 | |
154 | #if defined(__H8300S__) | |
155 | enum { sci_disable, sci_enable }; | |
156 | ||
e7c98dc7 | 157 | static void h8300_sci_config(struct uart_port *port, unsigned int ctrl) |
1da177e4 | 158 | { |
e7c98dc7 | 159 | volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL; |
1da177e4 LT |
160 | int ch = (port->mapbase - SMR0) >> 3; |
161 | unsigned char mask = 1 << (ch+1); | |
162 | ||
e7c98dc7 | 163 | if (ctrl == sci_disable) |
1da177e4 | 164 | *mstpcrl |= mask; |
e7c98dc7 | 165 | else |
1da177e4 | 166 | *mstpcrl &= ~mask; |
1da177e4 | 167 | } |
e108b2ca PM |
168 | |
169 | static inline void h8300_sci_enable(struct uart_port *port) | |
170 | { | |
171 | h8300_sci_config(port, sci_enable); | |
172 | } | |
173 | ||
174 | static inline void h8300_sci_disable(struct uart_port *port) | |
175 | { | |
176 | h8300_sci_config(port, sci_disable); | |
177 | } | |
1da177e4 LT |
178 | #endif |
179 | ||
15c73aaa | 180 | #if defined(__H8300H__) || defined(__H8300S__) |
d5701647 | 181 | static void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 LT |
182 | { |
183 | int ch = (port->mapbase - SMR0) >> 3; | |
184 | ||
185 | /* set DDR regs */ | |
e108b2ca PM |
186 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, |
187 | h8300_sci_pins[ch].rx, | |
188 | H8300_GPIO_INPUT); | |
189 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, | |
190 | h8300_sci_pins[ch].tx, | |
191 | H8300_GPIO_OUTPUT); | |
192 | ||
1da177e4 LT |
193 | /* tx mark output*/ |
194 | H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; | |
195 | } | |
d5701647 PM |
196 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
197 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) | |
e108b2ca | 198 | { |
d5701647 PM |
199 | if (port->mapbase == 0xA4400000) { |
200 | __raw_writew(__raw_readw(PACR) & 0xffc0, PACR); | |
201 | __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); | |
202 | } else if (port->mapbase == 0xA4410000) | |
203 | __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); | |
9465a54f | 204 | } |
31a49c4b | 205 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) |
d5701647 | 206 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
3ea6bc3d | 207 | { |
3ea6bc3d MB |
208 | unsigned short data; |
209 | ||
210 | if (cflag & CRTSCTS) { | |
211 | /* enable RTS/CTS */ | |
212 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
213 | /* Clear PTCR bit 9-2; enable all scif pins but sck */ | |
d5701647 PM |
214 | data = __raw_readw(PORT_PTCR); |
215 | __raw_writew((data & 0xfc03), PORT_PTCR); | |
3ea6bc3d MB |
216 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
217 | /* Clear PVCR bit 9-2 */ | |
d5701647 PM |
218 | data = __raw_readw(PORT_PVCR); |
219 | __raw_writew((data & 0xfc03), PORT_PVCR); | |
3ea6bc3d | 220 | } |
3ea6bc3d MB |
221 | } else { |
222 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
223 | /* Clear PTCR bit 5-2; enable only tx and rx */ | |
d5701647 PM |
224 | data = __raw_readw(PORT_PTCR); |
225 | __raw_writew((data & 0xffc3), PORT_PTCR); | |
3ea6bc3d MB |
226 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
227 | /* Clear PVCR bit 5-2 */ | |
d5701647 PM |
228 | data = __raw_readw(PORT_PVCR); |
229 | __raw_writew((data & 0xffc3), PORT_PVCR); | |
3ea6bc3d MB |
230 | } |
231 | } | |
3ea6bc3d | 232 | } |
b7a76e4b | 233 | #elif defined(CONFIG_CPU_SH3) |
e108b2ca | 234 | /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ |
d5701647 | 235 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 | 236 | { |
b7a76e4b PM |
237 | unsigned short data; |
238 | ||
239 | /* We need to set SCPCR to enable RTS/CTS */ | |
d5701647 | 240 | data = __raw_readw(SCPCR); |
b7a76e4b | 241 | /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ |
d5701647 | 242 | __raw_writew(data & 0x0fcf, SCPCR); |
1da177e4 | 243 | |
d5701647 | 244 | if (!(cflag & CRTSCTS)) { |
1da177e4 | 245 | /* We need to set SCPCR to enable RTS/CTS */ |
d5701647 | 246 | data = __raw_readw(SCPCR); |
1da177e4 LT |
247 | /* Clear out SCP7MD1,0, SCP4MD1,0, |
248 | Set SCP6MD1,0 = {01} (output) */ | |
d5701647 | 249 | __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); |
1da177e4 LT |
250 | |
251 | data = ctrl_inb(SCPDR); | |
252 | /* Set /RTS2 (bit6) = 0 */ | |
b7a76e4b | 253 | ctrl_outb(data & 0xbf, SCPDR); |
1da177e4 | 254 | } |
1da177e4 | 255 | } |
41504c39 | 256 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
d5701647 | 257 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
41504c39 | 258 | { |
346b7463 | 259 | unsigned short data; |
41504c39 | 260 | |
346b7463 | 261 | if (port->mapbase == 0xffe00000) { |
d5701647 | 262 | data = __raw_readw(PSCR); |
346b7463 | 263 | data &= ~0x03cf; |
d5701647 | 264 | if (!(cflag & CRTSCTS)) |
346b7463 | 265 | data |= 0x0340; |
41504c39 | 266 | |
d5701647 | 267 | __raw_writew(data, PSCR); |
41504c39 | 268 | } |
178dd0cd | 269 | } |
7d740a06 YS |
270 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
271 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
2b1bd1ac | 272 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
55ba99eb | 273 | defined(CONFIG_CPU_SUBTYPE_SH7786) || \ |
2b1bd1ac | 274 | defined(CONFIG_CPU_SUBTYPE_SHX3) |
d5701647 PM |
275 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
276 | { | |
277 | if (!(cflag & CRTSCTS)) | |
278 | __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */ | |
279 | } | |
b0c50ad7 | 280 | #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A) |
d5701647 PM |
281 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
282 | { | |
283 | if (!(cflag & CRTSCTS)) | |
284 | __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */ | |
285 | } | |
b7a76e4b | 286 | #else |
d5701647 PM |
287 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
288 | { | |
289 | /* Nothing to do */ | |
1da177e4 | 290 | } |
e108b2ca PM |
291 | #endif |
292 | ||
32351a28 PM |
293 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
294 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
55ba99eb KM |
295 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
296 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
e108b2ca PM |
297 | static inline int scif_txroom(struct uart_port *port) |
298 | { | |
cae167d3 | 299 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e108b2ca PM |
300 | } |
301 | ||
302 | static inline int scif_rxroom(struct uart_port *port) | |
303 | { | |
cae167d3 | 304 | return sci_in(port, SCRFDR) & 0xff; |
e108b2ca | 305 | } |
c63847a3 NI |
306 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
307 | static inline int scif_txroom(struct uart_port *port) | |
308 | { | |
e7c98dc7 MT |
309 | if ((port->mapbase == 0xffe00000) || |
310 | (port->mapbase == 0xffe08000)) { | |
311 | /* SCIF0/1*/ | |
c63847a3 | 312 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e7c98dc7 MT |
313 | } else { |
314 | /* SCIF2 */ | |
c63847a3 | 315 | return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); |
e7c98dc7 | 316 | } |
c63847a3 NI |
317 | } |
318 | ||
319 | static inline int scif_rxroom(struct uart_port *port) | |
320 | { | |
e7c98dc7 MT |
321 | if ((port->mapbase == 0xffe00000) || |
322 | (port->mapbase == 0xffe08000)) { | |
323 | /* SCIF0/1*/ | |
c63847a3 | 324 | return sci_in(port, SCRFDR) & 0xff; |
e7c98dc7 MT |
325 | } else { |
326 | /* SCIF2 */ | |
c63847a3 | 327 | return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; |
e7c98dc7 | 328 | } |
c63847a3 | 329 | } |
e108b2ca PM |
330 | #else |
331 | static inline int scif_txroom(struct uart_port *port) | |
332 | { | |
333 | return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); | |
334 | } | |
1da177e4 | 335 | |
e108b2ca PM |
336 | static inline int scif_rxroom(struct uart_port *port) |
337 | { | |
338 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
339 | } | |
1da177e4 | 340 | #endif |
1da177e4 | 341 | |
e108b2ca PM |
342 | static inline int sci_txroom(struct uart_port *port) |
343 | { | |
e7c98dc7 | 344 | return (sci_in(port, SCxSR) & SCI_TDRE) != 0; |
e108b2ca PM |
345 | } |
346 | ||
347 | static inline int sci_rxroom(struct uart_port *port) | |
348 | { | |
e7c98dc7 | 349 | return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
350 | } |
351 | ||
1da177e4 LT |
352 | /* ********************************************************************** * |
353 | * the interrupt related routines * | |
354 | * ********************************************************************** */ | |
355 | ||
356 | static void sci_transmit_chars(struct uart_port *port) | |
357 | { | |
358 | struct circ_buf *xmit = &port->info->xmit; | |
359 | unsigned int stopped = uart_tx_stopped(port); | |
1da177e4 LT |
360 | unsigned short status; |
361 | unsigned short ctrl; | |
e108b2ca | 362 | int count; |
1da177e4 LT |
363 | |
364 | status = sci_in(port, SCxSR); | |
365 | if (!(status & SCxSR_TDxE(port))) { | |
1da177e4 | 366 | ctrl = sci_in(port, SCSCR); |
e7c98dc7 | 367 | if (uart_circ_empty(xmit)) |
1da177e4 | 368 | ctrl &= ~SCI_CTRL_FLAGS_TIE; |
e7c98dc7 | 369 | else |
1da177e4 | 370 | ctrl |= SCI_CTRL_FLAGS_TIE; |
1da177e4 | 371 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
372 | return; |
373 | } | |
374 | ||
1a22f08d | 375 | if (port->type == PORT_SCI) |
e108b2ca | 376 | count = sci_txroom(port); |
1a22f08d YS |
377 | else |
378 | count = scif_txroom(port); | |
1da177e4 LT |
379 | |
380 | do { | |
381 | unsigned char c; | |
382 | ||
383 | if (port->x_char) { | |
384 | c = port->x_char; | |
385 | port->x_char = 0; | |
386 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
387 | c = xmit->buf[xmit->tail]; | |
388 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
389 | } else { | |
390 | break; | |
391 | } | |
392 | ||
393 | sci_out(port, SCxTDR, c); | |
394 | ||
395 | port->icount.tx++; | |
396 | } while (--count > 0); | |
397 | ||
398 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
399 | ||
400 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
401 | uart_write_wakeup(port); | |
402 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 403 | sci_stop_tx(port); |
1da177e4 | 404 | } else { |
1da177e4 LT |
405 | ctrl = sci_in(port, SCSCR); |
406 | ||
1a22f08d | 407 | if (port->type != PORT_SCI) { |
1da177e4 LT |
408 | sci_in(port, SCxSR); /* Dummy read */ |
409 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
410 | } | |
1da177e4 LT |
411 | |
412 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
413 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
414 | } |
415 | } | |
416 | ||
417 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 418 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 419 | |
7d12e780 | 420 | static inline void sci_receive_chars(struct uart_port *port) |
1da177e4 | 421 | { |
e7c98dc7 | 422 | struct sci_port *sci_port = to_sci_port(port); |
a88487c7 | 423 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
424 | int i, count, copied = 0; |
425 | unsigned short status; | |
33f0f88f | 426 | unsigned char flag; |
1da177e4 LT |
427 | |
428 | status = sci_in(port, SCxSR); | |
429 | if (!(status & SCxSR_RDxF(port))) | |
430 | return; | |
431 | ||
432 | while (1) { | |
1a22f08d | 433 | if (port->type == PORT_SCI) |
e108b2ca | 434 | count = sci_rxroom(port); |
1a22f08d YS |
435 | else |
436 | count = scif_rxroom(port); | |
1da177e4 LT |
437 | |
438 | /* Don't copy more bytes than there is room for in the buffer */ | |
33f0f88f | 439 | count = tty_buffer_request_room(tty, count); |
1da177e4 LT |
440 | |
441 | /* If for any reason we can't copy more data, we're done! */ | |
442 | if (count == 0) | |
443 | break; | |
444 | ||
445 | if (port->type == PORT_SCI) { | |
446 | char c = sci_in(port, SCxRDR); | |
e7c98dc7 MT |
447 | if (uart_handle_sysrq_char(port, c) || |
448 | sci_port->break_flag) | |
1da177e4 | 449 | count = 0; |
e7c98dc7 | 450 | else |
e108b2ca | 451 | tty_insert_flip_char(tty, c, TTY_NORMAL); |
1da177e4 | 452 | } else { |
e7c98dc7 | 453 | for (i = 0; i < count; i++) { |
1da177e4 LT |
454 | char c = sci_in(port, SCxRDR); |
455 | status = sci_in(port, SCxSR); | |
456 | #if defined(CONFIG_CPU_SH3) | |
457 | /* Skip "chars" during break */ | |
e108b2ca | 458 | if (sci_port->break_flag) { |
1da177e4 LT |
459 | if ((c == 0) && |
460 | (status & SCxSR_FER(port))) { | |
461 | count--; i--; | |
462 | continue; | |
463 | } | |
e108b2ca | 464 | |
1da177e4 | 465 | /* Nonzero => end-of-break */ |
762c69e3 | 466 | dev_dbg(port->dev, "debounce<%02x>\n", c); |
e108b2ca PM |
467 | sci_port->break_flag = 0; |
468 | ||
1da177e4 LT |
469 | if (STEPFN(c)) { |
470 | count--; i--; | |
471 | continue; | |
472 | } | |
473 | } | |
474 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 475 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
476 | count--; i--; |
477 | continue; | |
478 | } | |
479 | ||
480 | /* Store data and status */ | |
1da177e4 | 481 | if (status&SCxSR_FER(port)) { |
33f0f88f | 482 | flag = TTY_FRAME; |
762c69e3 | 483 | dev_notice(port->dev, "frame error\n"); |
1da177e4 | 484 | } else if (status&SCxSR_PER(port)) { |
33f0f88f | 485 | flag = TTY_PARITY; |
762c69e3 | 486 | dev_notice(port->dev, "parity error\n"); |
33f0f88f AC |
487 | } else |
488 | flag = TTY_NORMAL; | |
762c69e3 | 489 | |
33f0f88f | 490 | tty_insert_flip_char(tty, c, flag); |
1da177e4 LT |
491 | } |
492 | } | |
493 | ||
494 | sci_in(port, SCxSR); /* dummy read */ | |
495 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
496 | ||
1da177e4 LT |
497 | copied += count; |
498 | port->icount.rx += count; | |
499 | } | |
500 | ||
501 | if (copied) { | |
502 | /* Tell the rest of the system the news. New characters! */ | |
503 | tty_flip_buffer_push(tty); | |
504 | } else { | |
505 | sci_in(port, SCxSR); /* dummy read */ | |
506 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
507 | } | |
508 | } | |
509 | ||
510 | #define SCI_BREAK_JIFFIES (HZ/20) | |
511 | /* The sci generates interrupts during the break, | |
512 | * 1 per millisecond or so during the break period, for 9600 baud. | |
513 | * So dont bother disabling interrupts. | |
514 | * But dont want more than 1 break event. | |
515 | * Use a kernel timer to periodically poll the rx line until | |
516 | * the break is finished. | |
517 | */ | |
518 | static void sci_schedule_break_timer(struct sci_port *port) | |
519 | { | |
520 | port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES; | |
521 | add_timer(&port->break_timer); | |
522 | } | |
523 | /* Ensure that two consecutive samples find the break over. */ | |
524 | static void sci_break_timer(unsigned long data) | |
525 | { | |
e108b2ca PM |
526 | struct sci_port *port = (struct sci_port *)data; |
527 | ||
528 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 529 | port->break_flag = 1; |
e108b2ca PM |
530 | sci_schedule_break_timer(port); |
531 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
532 | /* break is over. */ |
533 | port->break_flag = 2; | |
e108b2ca PM |
534 | sci_schedule_break_timer(port); |
535 | } else | |
536 | port->break_flag = 0; | |
1da177e4 LT |
537 | } |
538 | ||
539 | static inline int sci_handle_errors(struct uart_port *port) | |
540 | { | |
541 | int copied = 0; | |
542 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 543 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 | 544 | |
e108b2ca | 545 | if (status & SCxSR_ORER(port)) { |
1da177e4 | 546 | /* overrun error */ |
e108b2ca | 547 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) |
33f0f88f | 548 | copied++; |
762c69e3 PM |
549 | |
550 | dev_notice(port->dev, "overrun error"); | |
1da177e4 LT |
551 | } |
552 | ||
e108b2ca | 553 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
554 | if (sci_rxd_in(port) == 0) { |
555 | /* Notify of BREAK */ | |
e7c98dc7 | 556 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
557 | |
558 | if (!sci_port->break_flag) { | |
559 | sci_port->break_flag = 1; | |
560 | sci_schedule_break_timer(sci_port); | |
561 | ||
1da177e4 | 562 | /* Do sysrq handling. */ |
e108b2ca | 563 | if (uart_handle_break(port)) |
1da177e4 | 564 | return 0; |
762c69e3 PM |
565 | |
566 | dev_dbg(port->dev, "BREAK detected\n"); | |
567 | ||
e108b2ca | 568 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
e7c98dc7 MT |
569 | copied++; |
570 | } | |
571 | ||
e108b2ca | 572 | } else { |
1da177e4 | 573 | /* frame error */ |
e108b2ca | 574 | if (tty_insert_flip_char(tty, 0, TTY_FRAME)) |
33f0f88f | 575 | copied++; |
762c69e3 PM |
576 | |
577 | dev_notice(port->dev, "frame error\n"); | |
1da177e4 LT |
578 | } |
579 | } | |
580 | ||
e108b2ca | 581 | if (status & SCxSR_PER(port)) { |
1da177e4 | 582 | /* parity error */ |
e108b2ca PM |
583 | if (tty_insert_flip_char(tty, 0, TTY_PARITY)) |
584 | copied++; | |
762c69e3 PM |
585 | |
586 | dev_notice(port->dev, "parity error"); | |
1da177e4 LT |
587 | } |
588 | ||
33f0f88f | 589 | if (copied) |
1da177e4 | 590 | tty_flip_buffer_push(tty); |
1da177e4 LT |
591 | |
592 | return copied; | |
593 | } | |
594 | ||
d830fa45 PM |
595 | static inline int sci_handle_fifo_overrun(struct uart_port *port) |
596 | { | |
597 | struct tty_struct *tty = port->info->port.tty; | |
598 | int copied = 0; | |
599 | ||
600 | if (port->type != PORT_SCIF) | |
601 | return 0; | |
602 | ||
603 | if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { | |
604 | sci_out(port, SCLSR, 0); | |
605 | ||
606 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
607 | tty_flip_buffer_push(tty); | |
608 | ||
609 | dev_notice(port->dev, "overrun error\n"); | |
610 | copied++; | |
611 | } | |
612 | ||
613 | return copied; | |
614 | } | |
615 | ||
1da177e4 LT |
616 | static inline int sci_handle_breaks(struct uart_port *port) |
617 | { | |
618 | int copied = 0; | |
619 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 620 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
621 | struct sci_port *s = &sci_ports[port->line]; |
622 | ||
0b3d4ef6 PM |
623 | if (uart_handle_break(port)) |
624 | return 0; | |
625 | ||
b7a76e4b | 626 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
627 | #if defined(CONFIG_CPU_SH3) |
628 | /* Debounce break */ | |
629 | s->break_flag = 1; | |
630 | #endif | |
631 | /* Notify of BREAK */ | |
e108b2ca | 632 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
33f0f88f | 633 | copied++; |
762c69e3 PM |
634 | |
635 | dev_dbg(port->dev, "BREAK detected\n"); | |
1da177e4 LT |
636 | } |
637 | ||
33f0f88f | 638 | if (copied) |
1da177e4 | 639 | tty_flip_buffer_push(tty); |
e108b2ca | 640 | |
d830fa45 PM |
641 | copied += sci_handle_fifo_overrun(port); |
642 | ||
1da177e4 LT |
643 | return copied; |
644 | } | |
645 | ||
7d12e780 | 646 | static irqreturn_t sci_rx_interrupt(int irq, void *port) |
1da177e4 | 647 | { |
1da177e4 LT |
648 | /* I think sci_receive_chars has to be called irrespective |
649 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
650 | * to be disabled? | |
651 | */ | |
7d12e780 | 652 | sci_receive_chars(port); |
1da177e4 LT |
653 | |
654 | return IRQ_HANDLED; | |
655 | } | |
656 | ||
7d12e780 | 657 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
658 | { |
659 | struct uart_port *port = ptr; | |
660 | ||
e108b2ca | 661 | spin_lock_irq(&port->lock); |
1da177e4 | 662 | sci_transmit_chars(port); |
e108b2ca | 663 | spin_unlock_irq(&port->lock); |
1da177e4 LT |
664 | |
665 | return IRQ_HANDLED; | |
666 | } | |
667 | ||
7d12e780 | 668 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
669 | { |
670 | struct uart_port *port = ptr; | |
671 | ||
672 | /* Handle errors */ | |
673 | if (port->type == PORT_SCI) { | |
674 | if (sci_handle_errors(port)) { | |
675 | /* discard character in rx buffer */ | |
676 | sci_in(port, SCxSR); | |
677 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
678 | } | |
679 | } else { | |
d830fa45 | 680 | sci_handle_fifo_overrun(port); |
7d12e780 | 681 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
682 | } |
683 | ||
684 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); | |
685 | ||
686 | /* Kick the transmission */ | |
7d12e780 | 687 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
688 | |
689 | return IRQ_HANDLED; | |
690 | } | |
691 | ||
7d12e780 | 692 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
693 | { |
694 | struct uart_port *port = ptr; | |
695 | ||
696 | /* Handle BREAKs */ | |
697 | sci_handle_breaks(port); | |
698 | sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); | |
699 | ||
700 | return IRQ_HANDLED; | |
701 | } | |
702 | ||
7d12e780 | 703 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 | 704 | { |
a8884e34 MT |
705 | unsigned short ssr_status, scr_status; |
706 | struct uart_port *port = ptr; | |
707 | irqreturn_t ret = IRQ_NONE; | |
1da177e4 | 708 | |
e7c98dc7 MT |
709 | ssr_status = sci_in(port, SCxSR); |
710 | scr_status = sci_in(port, SCSCR); | |
1da177e4 LT |
711 | |
712 | /* Tx Interrupt */ | |
a8884e34 MT |
713 | if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE)) |
714 | ret = sci_tx_interrupt(irq, ptr); | |
1da177e4 | 715 | /* Rx Interrupt */ |
a8884e34 MT |
716 | if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE)) |
717 | ret = sci_rx_interrupt(irq, ptr); | |
1da177e4 | 718 | /* Error Interrupt */ |
a8884e34 MT |
719 | if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE)) |
720 | ret = sci_er_interrupt(irq, ptr); | |
1da177e4 | 721 | /* Break Interrupt */ |
a8884e34 MT |
722 | if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE)) |
723 | ret = sci_br_interrupt(irq, ptr); | |
1da177e4 | 724 | |
a8884e34 | 725 | return ret; |
1da177e4 LT |
726 | } |
727 | ||
027e6872 | 728 | #ifdef CONFIG_HAVE_CLK |
1da177e4 LT |
729 | /* |
730 | * Here we define a transistion notifier so that we can update all of our | |
731 | * ports' baud rate when the peripheral clock changes. | |
732 | */ | |
e108b2ca PM |
733 | static int sci_notifier(struct notifier_block *self, |
734 | unsigned long phase, void *p) | |
1da177e4 | 735 | { |
e552de24 MD |
736 | struct sh_sci_priv *priv = container_of(self, |
737 | struct sh_sci_priv, clk_nb); | |
738 | struct sci_port *sci_port; | |
739 | unsigned long flags; | |
1da177e4 LT |
740 | |
741 | if ((phase == CPUFREQ_POSTCHANGE) || | |
e552de24 MD |
742 | (phase == CPUFREQ_RESUMECHANGE)) { |
743 | spin_lock_irqsave(&priv->lock, flags); | |
744 | list_for_each_entry(sci_port, &priv->ports, node) | |
745 | sci_port->port.uartclk = clk_get_rate(sci_port->clk); | |
746 | ||
747 | spin_unlock_irqrestore(&priv->lock, flags); | |
748 | } | |
1da177e4 | 749 | |
1da177e4 LT |
750 | return NOTIFY_OK; |
751 | } | |
027e6872 | 752 | #endif |
1da177e4 LT |
753 | |
754 | static int sci_request_irq(struct sci_port *port) | |
755 | { | |
756 | int i; | |
7d12e780 | 757 | irqreturn_t (*handlers[4])(int irq, void *ptr) = { |
1da177e4 LT |
758 | sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, |
759 | sci_br_interrupt, | |
760 | }; | |
761 | const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", | |
762 | "SCI Transmit Data Empty", "SCI Break" }; | |
763 | ||
764 | if (port->irqs[0] == port->irqs[1]) { | |
762c69e3 | 765 | if (unlikely(!port->irqs[0])) |
1da177e4 | 766 | return -ENODEV; |
e108b2ca PM |
767 | |
768 | if (request_irq(port->irqs[0], sci_mpxed_interrupt, | |
35f3c518 | 769 | IRQF_DISABLED, "sci", port)) { |
762c69e3 | 770 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
771 | return -ENODEV; |
772 | } | |
773 | } else { | |
774 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { | |
762c69e3 | 775 | if (unlikely(!port->irqs[i])) |
1da177e4 | 776 | continue; |
762c69e3 | 777 | |
e108b2ca | 778 | if (request_irq(port->irqs[i], handlers[i], |
35f3c518 | 779 | IRQF_DISABLED, desc[i], port)) { |
762c69e3 | 780 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
781 | return -ENODEV; |
782 | } | |
783 | } | |
784 | } | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | static void sci_free_irq(struct sci_port *port) | |
790 | { | |
791 | int i; | |
792 | ||
762c69e3 PM |
793 | if (port->irqs[0] == port->irqs[1]) |
794 | free_irq(port->irqs[0], port); | |
795 | else { | |
1da177e4 LT |
796 | for (i = 0; i < ARRAY_SIZE(port->irqs); i++) { |
797 | if (!port->irqs[i]) | |
798 | continue; | |
799 | ||
800 | free_irq(port->irqs[i], port); | |
801 | } | |
802 | } | |
803 | } | |
804 | ||
805 | static unsigned int sci_tx_empty(struct uart_port *port) | |
806 | { | |
807 | /* Can't detect */ | |
808 | return TIOCSER_TEMT; | |
809 | } | |
810 | ||
811 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
812 | { | |
813 | /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ | |
814 | /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ | |
815 | /* If you have signals for DTR and DCD, please implement here. */ | |
816 | } | |
817 | ||
818 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
819 | { | |
820 | /* This routine is used for geting signals of: DTR, DCD, DSR, RI, | |
821 | and CTS/RTS */ | |
822 | ||
823 | return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; | |
824 | } | |
825 | ||
b129a8cc | 826 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 827 | { |
e108b2ca | 828 | unsigned short ctrl; |
1da177e4 | 829 | |
e108b2ca PM |
830 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
831 | ctrl = sci_in(port, SCSCR); | |
832 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
833 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
834 | } |
835 | ||
b129a8cc | 836 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 837 | { |
1da177e4 LT |
838 | unsigned short ctrl; |
839 | ||
840 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
841 | ctrl = sci_in(port, SCSCR); |
842 | ctrl &= ~SCI_CTRL_FLAGS_TIE; | |
843 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
844 | } |
845 | ||
846 | static void sci_start_rx(struct uart_port *port, unsigned int tty_start) | |
847 | { | |
1da177e4 LT |
848 | unsigned short ctrl; |
849 | ||
850 | /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
851 | ctrl = sci_in(port, SCSCR); |
852 | ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; | |
853 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
854 | } |
855 | ||
856 | static void sci_stop_rx(struct uart_port *port) | |
857 | { | |
1da177e4 LT |
858 | unsigned short ctrl; |
859 | ||
860 | /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
861 | ctrl = sci_in(port, SCSCR); |
862 | ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); | |
863 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
864 | } |
865 | ||
866 | static void sci_enable_ms(struct uart_port *port) | |
867 | { | |
868 | /* Nothing here yet .. */ | |
869 | } | |
870 | ||
871 | static void sci_break_ctl(struct uart_port *port, int break_state) | |
872 | { | |
873 | /* Nothing here yet .. */ | |
874 | } | |
875 | ||
876 | static int sci_startup(struct uart_port *port) | |
877 | { | |
878 | struct sci_port *s = &sci_ports[port->line]; | |
879 | ||
e108b2ca PM |
880 | if (s->enable) |
881 | s->enable(port); | |
1da177e4 | 882 | |
a2159b52 | 883 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 884 | s->clk = clk_get(NULL, "module_clk"); |
005a336e | 885 | #endif |
1534a3b3 | 886 | |
1da177e4 | 887 | sci_request_irq(s); |
d656901b | 888 | sci_start_tx(port); |
1da177e4 LT |
889 | sci_start_rx(port, 1); |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
894 | static void sci_shutdown(struct uart_port *port) | |
895 | { | |
896 | struct sci_port *s = &sci_ports[port->line]; | |
897 | ||
898 | sci_stop_rx(port); | |
b129a8cc | 899 | sci_stop_tx(port); |
1da177e4 LT |
900 | sci_free_irq(s); |
901 | ||
e108b2ca PM |
902 | if (s->disable) |
903 | s->disable(port); | |
1534a3b3 | 904 | |
a2159b52 | 905 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 906 | clk_put(s->clk); |
907 | s->clk = NULL; | |
005a336e | 908 | #endif |
1da177e4 LT |
909 | } |
910 | ||
606d099c AC |
911 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
912 | struct ktermios *old) | |
1da177e4 | 913 | { |
1da177e4 | 914 | unsigned int status, baud, smr_val; |
a2159b52 | 915 | int t = -1; |
1da177e4 LT |
916 | |
917 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
a2159b52 PM |
918 | if (likely(baud)) |
919 | t = SCBRR_VALUE(baud, port->uartclk); | |
e108b2ca | 920 | |
1da177e4 LT |
921 | do { |
922 | status = sci_in(port, SCxSR); | |
923 | } while (!(status & SCxSR_TEND(port))); | |
924 | ||
925 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ | |
926 | ||
1a22f08d | 927 | if (port->type != PORT_SCI) |
1da177e4 | 928 | sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); |
1da177e4 LT |
929 | |
930 | smr_val = sci_in(port, SCSMR) & 3; | |
931 | if ((termios->c_cflag & CSIZE) == CS7) | |
932 | smr_val |= 0x40; | |
933 | if (termios->c_cflag & PARENB) | |
934 | smr_val |= 0x20; | |
935 | if (termios->c_cflag & PARODD) | |
936 | smr_val |= 0x30; | |
937 | if (termios->c_cflag & CSTOPB) | |
938 | smr_val |= 0x08; | |
939 | ||
940 | uart_update_timeout(port, termios->c_cflag, baud); | |
941 | ||
942 | sci_out(port, SCSMR, smr_val); | |
943 | ||
1da177e4 | 944 | if (t > 0) { |
e7c98dc7 | 945 | if (t >= 256) { |
1da177e4 LT |
946 | sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); |
947 | t >>= 2; | |
e7c98dc7 | 948 | } else |
1da177e4 | 949 | sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); |
e7c98dc7 | 950 | |
1da177e4 LT |
951 | sci_out(port, SCBRR, t); |
952 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ | |
953 | } | |
954 | ||
d5701647 PM |
955 | sci_init_pins(port, termios->c_cflag); |
956 | sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0); | |
b7a76e4b | 957 | |
1da177e4 LT |
958 | sci_out(port, SCSCR, SCSCR_INIT(port)); |
959 | ||
960 | if ((termios->c_cflag & CREAD) != 0) | |
e7c98dc7 | 961 | sci_start_rx(port, 0); |
1da177e4 LT |
962 | } |
963 | ||
964 | static const char *sci_type(struct uart_port *port) | |
965 | { | |
966 | switch (port->type) { | |
e7c98dc7 MT |
967 | case PORT_IRDA: |
968 | return "irda"; | |
969 | case PORT_SCI: | |
970 | return "sci"; | |
971 | case PORT_SCIF: | |
972 | return "scif"; | |
973 | case PORT_SCIFA: | |
974 | return "scifa"; | |
1da177e4 LT |
975 | } |
976 | ||
fa43972f | 977 | return NULL; |
1da177e4 LT |
978 | } |
979 | ||
980 | static void sci_release_port(struct uart_port *port) | |
981 | { | |
982 | /* Nothing here yet .. */ | |
983 | } | |
984 | ||
985 | static int sci_request_port(struct uart_port *port) | |
986 | { | |
987 | /* Nothing here yet .. */ | |
988 | return 0; | |
989 | } | |
990 | ||
991 | static void sci_config_port(struct uart_port *port, int flags) | |
992 | { | |
993 | struct sci_port *s = &sci_ports[port->line]; | |
994 | ||
995 | port->type = s->type; | |
996 | ||
7ff731ae | 997 | if (port->flags & UPF_IOREMAP && !port->membase) { |
7ff731ae | 998 | port->membase = ioremap_nocache(port->mapbase, 0x40); |
762c69e3 | 999 | dev_err(port->dev, "can't remap port#%d\n", port->line); |
7ff731ae | 1000 | } |
1da177e4 LT |
1001 | } |
1002 | ||
1003 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1004 | { | |
1005 | struct sci_port *s = &sci_ports[port->line]; | |
1006 | ||
a62c4133 | 1007 | if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) |
1da177e4 LT |
1008 | return -EINVAL; |
1009 | if (ser->baud_base < 2400) | |
1010 | /* No paper tape reader for Mitch.. */ | |
1011 | return -EINVAL; | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | static struct uart_ops sci_uart_ops = { | |
1017 | .tx_empty = sci_tx_empty, | |
1018 | .set_mctrl = sci_set_mctrl, | |
1019 | .get_mctrl = sci_get_mctrl, | |
1020 | .start_tx = sci_start_tx, | |
1021 | .stop_tx = sci_stop_tx, | |
1022 | .stop_rx = sci_stop_rx, | |
1023 | .enable_ms = sci_enable_ms, | |
1024 | .break_ctl = sci_break_ctl, | |
1025 | .startup = sci_startup, | |
1026 | .shutdown = sci_shutdown, | |
1027 | .set_termios = sci_set_termios, | |
1028 | .type = sci_type, | |
1029 | .release_port = sci_release_port, | |
1030 | .request_port = sci_request_port, | |
1031 | .config_port = sci_config_port, | |
1032 | .verify_port = sci_verify_port, | |
07d2a1a1 PM |
1033 | #ifdef CONFIG_CONSOLE_POLL |
1034 | .poll_get_char = sci_poll_get_char, | |
1035 | .poll_put_char = sci_poll_put_char, | |
1036 | #endif | |
1da177e4 LT |
1037 | }; |
1038 | ||
e108b2ca PM |
1039 | static void __init sci_init_ports(void) |
1040 | { | |
1041 | static int first = 1; | |
1042 | int i; | |
1043 | ||
1044 | if (!first) | |
1045 | return; | |
1046 | ||
1047 | first = 0; | |
1048 | ||
1049 | for (i = 0; i < SCI_NPORTS; i++) { | |
1050 | sci_ports[i].port.ops = &sci_uart_ops; | |
1051 | sci_ports[i].port.iotype = UPIO_MEM; | |
1052 | sci_ports[i].port.line = i; | |
1053 | sci_ports[i].port.fifosize = 1; | |
1054 | ||
1055 | #if defined(__H8300H__) || defined(__H8300S__) | |
1056 | #ifdef __H8300S__ | |
1057 | sci_ports[i].enable = h8300_sci_enable; | |
1058 | sci_ports[i].disable = h8300_sci_disable; | |
1059 | #endif | |
1060 | sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK; | |
a2159b52 | 1061 | #elif defined(CONFIG_HAVE_CLK) |
e108b2ca PM |
1062 | /* |
1063 | * XXX: We should use a proper SCI/SCIF clock | |
1064 | */ | |
1065 | { | |
1d118562 | 1066 | struct clk *clk = clk_get(NULL, "module_clk"); |
a2159b52 | 1067 | sci_ports[i].port.uartclk = clk_get_rate(clk); |
e108b2ca PM |
1068 | clk_put(clk); |
1069 | } | |
a2159b52 PM |
1070 | #else |
1071 | #error "Need a valid uartclk" | |
1da177e4 | 1072 | #endif |
e108b2ca PM |
1073 | |
1074 | sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i]; | |
1075 | sci_ports[i].break_timer.function = sci_break_timer; | |
1076 | ||
1077 | init_timer(&sci_ports[i].break_timer); | |
1078 | } | |
1079 | } | |
1080 | ||
1da177e4 | 1081 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
dc8e6f5b MD |
1082 | static struct tty_driver *serial_console_device(struct console *co, int *index) |
1083 | { | |
1084 | struct uart_driver *p = &sci_uart_driver; | |
1085 | *index = co->index; | |
1086 | return p->tty_driver; | |
1087 | } | |
1088 | ||
1089 | static void serial_console_putchar(struct uart_port *port, int ch) | |
1090 | { | |
1091 | sci_poll_put_char(port, ch); | |
1092 | } | |
1093 | ||
1da177e4 LT |
1094 | /* |
1095 | * Print a string to the serial port trying not to disturb | |
1096 | * any possible real use of the port... | |
1097 | */ | |
1098 | static void serial_console_write(struct console *co, const char *s, | |
1099 | unsigned count) | |
1100 | { | |
dc8e6f5b | 1101 | struct uart_port *port = co->data; |
973e5d52 | 1102 | unsigned short bits; |
07d2a1a1 | 1103 | |
dc8e6f5b | 1104 | uart_console_write(co->data, s, count, serial_console_putchar); |
973e5d52 MD |
1105 | |
1106 | /* wait until fifo is empty and last bit has been transmitted */ | |
1107 | bits = SCxSR_TDxE(port) | SCxSR_TEND(port); | |
1108 | while ((sci_in(port, SCxSR) & bits) != bits) | |
1109 | cpu_relax(); | |
1da177e4 LT |
1110 | } |
1111 | ||
1112 | static int __init serial_console_setup(struct console *co, char *options) | |
1113 | { | |
dc8e6f5b | 1114 | struct sci_port *sci_port; |
1da177e4 LT |
1115 | struct uart_port *port; |
1116 | int baud = 115200; | |
1117 | int bits = 8; | |
1118 | int parity = 'n'; | |
1119 | int flow = 'n'; | |
1120 | int ret; | |
1121 | ||
e108b2ca PM |
1122 | /* |
1123 | * Check whether an invalid uart number has been specified, and | |
1124 | * if so, search for the first available port that does have | |
1125 | * console support. | |
1126 | */ | |
1127 | if (co->index >= SCI_NPORTS) | |
1128 | co->index = 0; | |
1129 | ||
dc8e6f5b MD |
1130 | sci_port = &sci_ports[co->index]; |
1131 | port = &sci_port->port; | |
1132 | co->data = port; | |
1da177e4 LT |
1133 | |
1134 | /* | |
e108b2ca PM |
1135 | * Also need to check port->type, we don't actually have any |
1136 | * UPIO_PORT ports, but uart_report_port() handily misreports | |
1137 | * it anyways if we don't have a port available by the time this is | |
1138 | * called. | |
1da177e4 | 1139 | */ |
e108b2ca PM |
1140 | if (!port->type) |
1141 | return -ENODEV; | |
e108b2ca | 1142 | |
a2159b52 | 1143 | #ifdef CONFIG_HAVE_CLK |
dc8e6f5b MD |
1144 | if (!sci_port->clk) |
1145 | sci_port->clk = clk_get(NULL, "module_clk"); | |
005a336e PM |
1146 | #endif |
1147 | ||
e108b2ca PM |
1148 | if (port->flags & UPF_IOREMAP) |
1149 | sci_config_port(port, 0); | |
1150 | ||
dc8e6f5b MD |
1151 | if (sci_port->enable) |
1152 | sci_port->enable(port); | |
b7a76e4b | 1153 | |
1da177e4 LT |
1154 | if (options) |
1155 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1156 | ||
1157 | ret = uart_set_options(port, co, baud, parity, bits, flow); | |
1158 | #if defined(__H8300H__) || defined(__H8300S__) | |
1159 | /* disable rx interrupt */ | |
1160 | if (ret == 0) | |
1161 | sci_stop_rx(port); | |
1162 | #endif | |
1163 | return ret; | |
1164 | } | |
1165 | ||
1166 | static struct console serial_console = { | |
1167 | .name = "ttySC", | |
dc8e6f5b | 1168 | .device = serial_console_device, |
1da177e4 LT |
1169 | .write = serial_console_write, |
1170 | .setup = serial_console_setup, | |
fa5da2f7 | 1171 | .flags = CON_PRINTBUFFER, |
1da177e4 | 1172 | .index = -1, |
1da177e4 LT |
1173 | }; |
1174 | ||
1175 | static int __init sci_console_init(void) | |
1176 | { | |
e108b2ca | 1177 | sci_init_ports(); |
1da177e4 LT |
1178 | register_console(&serial_console); |
1179 | return 0; | |
1180 | } | |
1da177e4 LT |
1181 | console_initcall(sci_console_init); |
1182 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
1183 | ||
07d2a1a1 | 1184 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
e7c98dc7 | 1185 | #define SCI_CONSOLE (&serial_console) |
1da177e4 | 1186 | #else |
b7a76e4b | 1187 | #define SCI_CONSOLE 0 |
1da177e4 LT |
1188 | #endif |
1189 | ||
1190 | static char banner[] __initdata = | |
1191 | KERN_INFO "SuperH SCI(F) driver initialized\n"; | |
1192 | ||
1193 | static struct uart_driver sci_uart_driver = { | |
1194 | .owner = THIS_MODULE, | |
1195 | .driver_name = "sci", | |
1da177e4 LT |
1196 | .dev_name = "ttySC", |
1197 | .major = SCI_MAJOR, | |
1198 | .minor = SCI_MINOR_START, | |
e108b2ca | 1199 | .nr = SCI_NPORTS, |
1da177e4 LT |
1200 | .cons = SCI_CONSOLE, |
1201 | }; | |
1202 | ||
e552de24 MD |
1203 | |
1204 | static int __devexit sci_remove(struct platform_device *dev) | |
1205 | { | |
1206 | struct sh_sci_priv *priv = platform_get_drvdata(dev); | |
1207 | struct sci_port *p; | |
1208 | unsigned long flags; | |
1209 | ||
1210 | #ifdef CONFIG_HAVE_CLK | |
1211 | cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); | |
1212 | #endif | |
1213 | ||
1214 | spin_lock_irqsave(&priv->lock, flags); | |
1215 | list_for_each_entry(p, &priv->ports, node) | |
1216 | uart_remove_one_port(&sci_uart_driver, &p->port); | |
1217 | ||
1218 | spin_unlock_irqrestore(&priv->lock, flags); | |
1219 | ||
1220 | kfree(priv); | |
1221 | return 0; | |
1222 | } | |
1223 | ||
e108b2ca PM |
1224 | /* |
1225 | * Register a set of serial devices attached to a platform device. The | |
1226 | * list is terminated with a zero flags entry, which means we expect | |
1227 | * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need | |
1228 | * remapping (such as sh64) should also set UPF_IOREMAP. | |
1229 | */ | |
1230 | static int __devinit sci_probe(struct platform_device *dev) | |
1da177e4 | 1231 | { |
e108b2ca | 1232 | struct plat_sci_port *p = dev->dev.platform_data; |
e552de24 | 1233 | struct sh_sci_priv *priv; |
7ff731ae | 1234 | int i, ret = -EINVAL; |
e552de24 MD |
1235 | unsigned long flags; |
1236 | ||
1237 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1238 | if (!priv) | |
1239 | return -ENOMEM; | |
1240 | ||
1241 | INIT_LIST_HEAD(&priv->ports); | |
1242 | spin_lock_init(&priv->lock); | |
1243 | platform_set_drvdata(dev, priv); | |
1244 | ||
1245 | #ifdef CONFIG_HAVE_CLK | |
1246 | priv->clk_nb.notifier_call = sci_notifier; | |
1247 | cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); | |
1248 | #endif | |
1da177e4 | 1249 | |
32351a28 | 1250 | for (i = 0; p && p->flags != 0; p++, i++) { |
e108b2ca | 1251 | struct sci_port *sciport = &sci_ports[i]; |
1da177e4 | 1252 | |
32351a28 PM |
1253 | /* Sanity check */ |
1254 | if (unlikely(i == SCI_NPORTS)) { | |
1255 | dev_notice(&dev->dev, "Attempting to register port " | |
1256 | "%d when only %d are available.\n", | |
1257 | i+1, SCI_NPORTS); | |
1258 | dev_notice(&dev->dev, "Consider bumping " | |
1259 | "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); | |
1260 | break; | |
1261 | } | |
1262 | ||
e108b2ca | 1263 | sciport->port.mapbase = p->mapbase; |
b7a76e4b | 1264 | |
7ff731ae PM |
1265 | if (p->mapbase && !p->membase) { |
1266 | if (p->flags & UPF_IOREMAP) { | |
1267 | p->membase = ioremap_nocache(p->mapbase, 0x40); | |
1268 | if (IS_ERR(p->membase)) { | |
1269 | ret = PTR_ERR(p->membase); | |
1270 | goto err_unreg; | |
1271 | } | |
1272 | } else { | |
1273 | /* | |
1274 | * For the simple (and majority of) cases | |
1275 | * where we don't need to do any remapping, | |
1276 | * just cast the cookie directly. | |
1277 | */ | |
1278 | p->membase = (void __iomem *)p->mapbase; | |
1279 | } | |
1280 | } | |
1da177e4 | 1281 | |
e108b2ca PM |
1282 | sciport->port.membase = p->membase; |
1283 | ||
1284 | sciport->port.irq = p->irqs[SCIx_TXI_IRQ]; | |
1285 | sciport->port.flags = p->flags; | |
1286 | sciport->port.dev = &dev->dev; | |
1287 | ||
1288 | sciport->type = sciport->port.type = p->type; | |
1289 | ||
1290 | memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs)); | |
1291 | ||
e552de24 | 1292 | ret = uart_add_one_port(&sci_uart_driver, &sciport->port); |
1da177e4 | 1293 | |
e552de24 MD |
1294 | if (ret && (p->flags & UPF_IOREMAP)) { |
1295 | iounmap(p->membase); | |
1296 | goto err_unreg; | |
1297 | } | |
1298 | ||
1299 | INIT_LIST_HEAD(&sciport->node); | |
1300 | ||
1301 | spin_lock_irqsave(&priv->lock, flags); | |
1302 | list_add(&sciport->node, &priv->ports); | |
1303 | spin_unlock_irqrestore(&priv->lock, flags); | |
1304 | } | |
1da177e4 LT |
1305 | |
1306 | #ifdef CONFIG_SH_STANDARD_BIOS | |
1307 | sh_bios_gdb_detach(); | |
1308 | #endif | |
1309 | ||
e108b2ca | 1310 | return 0; |
7ff731ae PM |
1311 | |
1312 | err_unreg: | |
e552de24 | 1313 | sci_remove(dev); |
7ff731ae | 1314 | return ret; |
1da177e4 LT |
1315 | } |
1316 | ||
e108b2ca | 1317 | static int sci_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 1318 | { |
e552de24 MD |
1319 | struct sh_sci_priv *priv = platform_get_drvdata(dev); |
1320 | struct sci_port *p; | |
1321 | unsigned long flags; | |
e108b2ca | 1322 | |
e552de24 MD |
1323 | spin_lock_irqsave(&priv->lock, flags); |
1324 | list_for_each_entry(p, &priv->ports, node) | |
1325 | uart_suspend_port(&sci_uart_driver, &p->port); | |
e108b2ca | 1326 | |
e552de24 | 1327 | spin_unlock_irqrestore(&priv->lock, flags); |
1da177e4 | 1328 | |
e108b2ca PM |
1329 | return 0; |
1330 | } | |
1da177e4 | 1331 | |
e108b2ca PM |
1332 | static int sci_resume(struct platform_device *dev) |
1333 | { | |
e552de24 MD |
1334 | struct sh_sci_priv *priv = platform_get_drvdata(dev); |
1335 | struct sci_port *p; | |
1336 | unsigned long flags; | |
e108b2ca | 1337 | |
e552de24 MD |
1338 | spin_lock_irqsave(&priv->lock, flags); |
1339 | list_for_each_entry(p, &priv->ports, node) | |
1340 | uart_resume_port(&sci_uart_driver, &p->port); | |
e108b2ca | 1341 | |
e552de24 | 1342 | spin_unlock_irqrestore(&priv->lock, flags); |
e108b2ca PM |
1343 | |
1344 | return 0; | |
1345 | } | |
1346 | ||
1347 | static struct platform_driver sci_driver = { | |
1348 | .probe = sci_probe, | |
1349 | .remove = __devexit_p(sci_remove), | |
1350 | .suspend = sci_suspend, | |
1351 | .resume = sci_resume, | |
1352 | .driver = { | |
1353 | .name = "sh-sci", | |
1354 | .owner = THIS_MODULE, | |
1355 | }, | |
1356 | }; | |
1357 | ||
1358 | static int __init sci_init(void) | |
1359 | { | |
1360 | int ret; | |
1361 | ||
1362 | printk(banner); | |
1363 | ||
1364 | sci_init_ports(); | |
1365 | ||
1366 | ret = uart_register_driver(&sci_uart_driver); | |
1367 | if (likely(ret == 0)) { | |
1368 | ret = platform_driver_register(&sci_driver); | |
1369 | if (unlikely(ret)) | |
1370 | uart_unregister_driver(&sci_uart_driver); | |
1371 | } | |
1372 | ||
1373 | return ret; | |
1374 | } | |
1375 | ||
1376 | static void __exit sci_exit(void) | |
1377 | { | |
1378 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
1379 | uart_unregister_driver(&sci_uart_driver); |
1380 | } | |
1381 | ||
1382 | module_init(sci_init); | |
1383 | module_exit(sci_exit); | |
1384 | ||
e108b2ca | 1385 | MODULE_LICENSE("GPL"); |
e169c139 | 1386 | MODULE_ALIAS("platform:sh-sci"); |