projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
serial: sh-sci: Handle port memory region reservations.
[deliverable/linux.git] / drivers / serial / sh-sci.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
f43dc23d 6 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
0b3d4ef6
PM		 22#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
1da177e4
LT		 25
26#undef DEBUG
27
1da177e4
LT		 28#include <linux/module.h>
29#include <linux/errno.h>
1da177e4
LT		 30#include <linux/timer.h>
31#include <linux/interrupt.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial.h>
35#include <linux/major.h>
36#include <linux/string.h>
37#include <linux/sysrq.h>
1da177e4
LT		 38#include <linux/ioport.h>
39#include <linux/mm.h>
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/console.h>
e108b2ca 43#include <linux/platform_device.h>
96de1a8f 44#include <linux/serial_sci.h>
1da177e4
LT		 45#include <linux/notifier.h>
46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
73a19e4c
GL		 50#include <linux/dmaengine.h>
51#include <linux/scatterlist.h>
5a0e3ad6 52#include <linux/slab.h>
85f094ec
PM		 53
54#ifdef CONFIG_SUPERH
1da177e4
LT		 55#include <asm/sh_bios.h>
56#endif
57
168f3623
YS		 58#ifdef CONFIG_H8300
59#include <asm/gpio.h>
60#endif
61
1da177e4
LT		 62#include "sh-sci.h"
63
e108b2ca
PM		 64struct sci_port {
65 struct uart_port port;
66
ce6738b6
PM		 67 /* Platform configuration */
68 struct plat_sci_port *cfg;
e108b2ca 69
e108b2ca
PM		 70 /* Port enable callback */
71 void (*enable)(struct uart_port *port);
72
73 /* Port disable callback */
74 void (*disable)(struct uart_port *port);
75
76 /* Break timer */
77 struct timer_list break_timer;
78 int break_flag;
1534a3b3 79
501b825d
MD		 80 /* Interface clock */
81 struct clk *iclk;
c7ed1ab3
PM		 82 /* Function clock */
83 struct clk *fclk;
edad1f20 84
73a19e4c
GL		 85 struct dma_chan *chan_tx;
86 struct dma_chan *chan_rx;
f43dc23d 87
73a19e4c 88#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 89 struct dma_async_tx_descriptor *desc_tx;
90 struct dma_async_tx_descriptor *desc_rx[2];
91 dma_cookie_t cookie_tx;
92 dma_cookie_t cookie_rx[2];
93 dma_cookie_t active_rx;
94 struct scatterlist sg_tx;
95 unsigned int sg_len_tx;
96 struct scatterlist sg_rx[2];
97 size_t buf_len_rx;
98 struct sh_dmae_slave param_tx;
99 struct sh_dmae_slave param_rx;
100 struct work_struct work_tx;
101 struct work_struct work_rx;
102 struct timer_list rx_timer;
3089f381 103 unsigned int rx_timeout;
73a19e4c 104#endif
e552de24 105
d535a230 106 struct notifier_block freq_transition;
e108b2ca
PM		 107};
108
1da177e4 109/* Function prototypes */
d535a230 110static void sci_start_tx(struct uart_port *port);
b129a8cc 111static void sci_stop_tx(struct uart_port *port);
d535a230 112static void sci_start_rx(struct uart_port *port);
1da177e4 113
e108b2ca 114#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 115
e108b2ca
PM		 116static struct sci_port sci_ports[SCI_NPORTS];
117static struct uart_driver sci_uart_driver;
1da177e4 118
e7c98dc7
MT		 119static inline struct sci_port *
120to_sci_port(struct uart_port *uart)
121{
122 return container_of(uart, struct sci_port, port);
123}
124
07d2a1a1 125#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 126
127#ifdef CONFIG_CONSOLE_POLL
e108b2ca
PM		 128static inline void handle_error(struct uart_port *port)
129{
130 /* Clear error flags */
1da177e4
LT		 131 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
132}
133
07d2a1a1 134static int sci_poll_get_char(struct uart_port *port)
1da177e4 135{
1da177e4
LT		 136 unsigned short status;
137 int c;
138
e108b2ca 139 do {
1da177e4
LT		 140 status = sci_in(port, SCxSR);
141 if (status & SCxSR_ERRORS(port)) {
142 handle_error(port);
143 continue;
144 }
3f255eb3
JW		 145 break;
146 } while (1);
147
148 if (!(status & SCxSR_RDxF(port)))
149 return NO_POLL_CHAR;
07d2a1a1 150
1da177e4 151 c = sci_in(port, SCxRDR);
07d2a1a1 152
e7c98dc7
MT		 153 /* Dummy read */
154 sci_in(port, SCxSR);
1da177e4 155 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 156
157 return c;
158}
1f6fd5c9 159#endif
1da177e4 160
07d2a1a1 161static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 162{
1da177e4
LT		 163 unsigned short status;
164
1da177e4
LT		 165 do {
166 status = sci_in(port, SCxSR);
167 } while (!(status & SCxSR_TDxE(port)));
168
272966c0 169 sci_out(port, SCxTDR, c);
dd0a3e77 170 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 171}
07d2a1a1 172#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 173
15c73aaa 174#if defined(__H8300H__) || defined(__H8300S__)
d5701647 175static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4
LT		 176{
177 int ch = (port->mapbase - SMR0) >> 3;
178
179 /* set DDR regs */
e108b2ca
PM		 180 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
181 h8300_sci_pins[ch].rx,
182 H8300_GPIO_INPUT);
183 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
184 h8300_sci_pins[ch].tx,
185 H8300_GPIO_OUTPUT);
186
1da177e4
LT		 187 /* tx mark output*/
188 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
189}
d5701647
PM		 190#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
191static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
e108b2ca 192{
d5701647
PM		 193 if (port->mapbase == 0xA4400000) {
194 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
195 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
196 } else if (port->mapbase == 0xA4410000)
197 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
9465a54f 198}
31a49c4b 199#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
d5701647 200static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
3ea6bc3d 201{
3ea6bc3d
MB		 202 unsigned short data;
203
204 if (cflag & CRTSCTS) {
205 /* enable RTS/CTS */
206 if (port->mapbase == 0xa4430000) { /* SCIF0 */
207 /* Clear PTCR bit 9-2; enable all scif pins but sck */
d5701647
PM		 208 data = __raw_readw(PORT_PTCR);
209 __raw_writew((data & 0xfc03), PORT_PTCR);
3ea6bc3d
MB		 210 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
211 /* Clear PVCR bit 9-2 */
d5701647
PM		 212 data = __raw_readw(PORT_PVCR);
213 __raw_writew((data & 0xfc03), PORT_PVCR);
3ea6bc3d 214 }
3ea6bc3d
MB		 215 } else {
216 if (port->mapbase == 0xa4430000) { /* SCIF0 */
217 /* Clear PTCR bit 5-2; enable only tx and rx */
d5701647
PM		 218 data = __raw_readw(PORT_PTCR);
219 __raw_writew((data & 0xffc3), PORT_PTCR);
3ea6bc3d
MB		 220 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
221 /* Clear PVCR bit 5-2 */
d5701647
PM		 222 data = __raw_readw(PORT_PVCR);
223 __raw_writew((data & 0xffc3), PORT_PVCR);
3ea6bc3d
MB		 224 }
225 }
3ea6bc3d 226}
b7a76e4b 227#elif defined(CONFIG_CPU_SH3)
e108b2ca 228/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
d5701647 229static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 230{
b7a76e4b
PM		 231 unsigned short data;
232
233 /* We need to set SCPCR to enable RTS/CTS */
d5701647 234 data = __raw_readw(SCPCR);
b7a76e4b 235 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
d5701647 236 __raw_writew(data & 0x0fcf, SCPCR);
1da177e4 237
d5701647 238 if (!(cflag & CRTSCTS)) {
1da177e4 239 /* We need to set SCPCR to enable RTS/CTS */
d5701647 240 data = __raw_readw(SCPCR);
1da177e4
LT		 241 /* Clear out SCP7MD1,0, SCP4MD1,0,
242 Set SCP6MD1,0 = {01} (output) */
d5701647 243 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
1da177e4 244
32b53076 245 data = __raw_readb(SCPDR);
1da177e4 246 /* Set /RTS2 (bit6) = 0 */
32b53076 247 __raw_writeb(data & 0xbf, SCPDR);
1da177e4 248 }
1da177e4 249}
41504c39 250#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
d5701647 251static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
41504c39 252{
346b7463 253 unsigned short data;
41504c39 254
346b7463 255 if (port->mapbase == 0xffe00000) {
d5701647 256 data = __raw_readw(PSCR);
346b7463 257 data &= ~0x03cf;
d5701647 258 if (!(cflag & CRTSCTS))
346b7463 259 data |= 0x0340;
41504c39 260
d5701647 261 __raw_writew(data, PSCR);
41504c39 262 }
178dd0cd 263}
c01f0f1a
YS		 264#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
7d740a06 266 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac 267 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
55ba99eb 268 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
2b1bd1ac 269 defined(CONFIG_CPU_SUBTYPE_SHX3)
d5701647
PM		 270static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
271{
272 if (!(cflag & CRTSCTS))
273 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
274}
b0c50ad7 275#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
d5701647
PM		 276static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
277{
278 if (!(cflag & CRTSCTS))
279 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
280}
b7a76e4b 281#else
d5701647
PM		 282static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
283{
284 /* Nothing to do */
1da177e4 285}
e108b2ca
PM		 286#endif
287
32351a28
PM		 288#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
289 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 290 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
291 defined(CONFIG_CPU_SUBTYPE_SH7786)
73a19e4c 292static int scif_txfill(struct uart_port *port)
e108b2ca 293{
73a19e4c 294 return sci_in(port, SCTFDR) & 0xff;
e108b2ca
PM		 295}
296
73a19e4c 297static int scif_txroom(struct uart_port *port)
e108b2ca 298{
73a19e4c 299 return SCIF_TXROOM_MAX - scif_txfill(port);
e108b2ca
PM		 300}
301
73a19e4c 302static int scif_rxfill(struct uart_port *port)
e108b2ca 303{
cae167d3 304 return sci_in(port, SCRFDR) & 0xff;
e108b2ca 305}
c63847a3 306#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
73a19e4c 307static int scif_txfill(struct uart_port *port)
c63847a3 308{
73a19e4c
GL		 309 if (port->mapbase == 0xffe00000 ||
310 port->mapbase == 0xffe08000)
e7c98dc7 311 /* SCIF0/1*/
73a19e4c
GL		 312 return sci_in(port, SCTFDR) & 0xff;
313 else
e7c98dc7 314 /* SCIF2 */
73a19e4c 315 return sci_in(port, SCFDR) >> 8;
c63847a3
NI		 316}
317
73a19e4c
GL		 318static int scif_txroom(struct uart_port *port)
319{
320 if (port->mapbase == 0xffe00000 ||
321 port->mapbase == 0xffe08000)
322 /* SCIF0/1*/
323 return SCIF_TXROOM_MAX - scif_txfill(port);
324 else
325 /* SCIF2 */
326 return SCIF2_TXROOM_MAX - scif_txfill(port);
c63847a3
NI		 327}
328
73a19e4c 329static int scif_rxfill(struct uart_port *port)
c63847a3 330{
e7c98dc7
MT		 331 if ((port->mapbase == 0xffe00000) ||
332 (port->mapbase == 0xffe08000)) {
333 /* SCIF0/1*/
c63847a3 334 return sci_in(port, SCRFDR) & 0xff;
e7c98dc7
MT		 335 } else {
336 /* SCIF2 */
c63847a3 337 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
e7c98dc7 338 }
c63847a3 339}
d1d4b10c
GL		 340#elif defined(CONFIG_ARCH_SH7372)
341static int scif_txfill(struct uart_port *port)
342{
343 if (port->type == PORT_SCIFA)
344 return sci_in(port, SCFDR) >> 8;
345 else
346 return sci_in(port, SCTFDR);
347}
348
349static int scif_txroom(struct uart_port *port)
350{
351 return port->fifosize - scif_txfill(port);
352}
353
354static int scif_rxfill(struct uart_port *port)
355{
356 if (port->type == PORT_SCIFA)
357 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
358 else
359 return sci_in(port, SCRFDR);
360}
e108b2ca 361#else
73a19e4c 362static int scif_txfill(struct uart_port *port)
e108b2ca 363{
73a19e4c 364 return sci_in(port, SCFDR) >> 8;
e108b2ca 365}
1da177e4 366
73a19e4c 367static int scif_txroom(struct uart_port *port)
e108b2ca 368{
73a19e4c 369 return SCIF_TXROOM_MAX - scif_txfill(port);
e108b2ca 370}
1da177e4 371
73a19e4c 372static int scif_rxfill(struct uart_port *port)
e108b2ca
PM		 373{
374 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
375}
1da177e4 376#endif
1da177e4 377
73a19e4c 378static int sci_txfill(struct uart_port *port)
e108b2ca 379{
73a19e4c 380 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 381}
382
73a19e4c
GL		 383static int sci_txroom(struct uart_port *port)
384{
385 return !sci_txfill(port);
386}
387
388static int sci_rxfill(struct uart_port *port)
e108b2ca 389{
e7c98dc7 390 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 391}
392
1da177e4
LT		 393/* ********************************************************************** *
394 * the interrupt related routines *
395 * ********************************************************************** */
396
397static void sci_transmit_chars(struct uart_port *port)
398{
ebd2c8f6 399 struct circ_buf *xmit = &port->state->xmit;
1da177e4 400 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 401 unsigned short status;
402 unsigned short ctrl;
e108b2ca 403 int count;
1da177e4
LT		 404
405 status = sci_in(port, SCxSR);
406 if (!(status & SCxSR_TDxE(port))) {
1da177e4 407 ctrl = sci_in(port, SCSCR);
e7c98dc7 408 if (uart_circ_empty(xmit))
8e698614 409 ctrl &= ~SCSCR_TIE;
e7c98dc7 410 else
8e698614 411 ctrl |= SCSCR_TIE;
1da177e4 412 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 413 return;
414 }
415
1a22f08d 416 if (port->type == PORT_SCI)
e108b2ca 417 count = sci_txroom(port);
1a22f08d
YS		 418 else
419 count = scif_txroom(port);
1da177e4
LT		 420
421 do {
422 unsigned char c;
423
424 if (port->x_char) {
425 c = port->x_char;
426 port->x_char = 0;
427 } else if (!uart_circ_empty(xmit) && !stopped) {
428 c = xmit->buf[xmit->tail];
429 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
430 } else {
431 break;
432 }
433
434 sci_out(port, SCxTDR, c);
435
436 port->icount.tx++;
437 } while (--count > 0);
438
439 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
440
441 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
442 uart_write_wakeup(port);
443 if (uart_circ_empty(xmit)) {
b129a8cc 444 sci_stop_tx(port);
1da177e4 445 } else {
1da177e4
LT		 446 ctrl = sci_in(port, SCSCR);
447
1a22f08d 448 if (port->type != PORT_SCI) {
1da177e4
LT		 449 sci_in(port, SCxSR); /* Dummy read */
450 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
451 }
1da177e4 452
8e698614 453 ctrl |= SCSCR_TIE;
1da177e4 454 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 455 }
456}
457
458/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 459#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 460
7d12e780 461static inline void sci_receive_chars(struct uart_port *port)
1da177e4 462{
e7c98dc7 463 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 464 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 465 int i, count, copied = 0;
466 unsigned short status;
33f0f88f 467 unsigned char flag;
1da177e4
LT		 468
469 status = sci_in(port, SCxSR);
470 if (!(status & SCxSR_RDxF(port)))
471 return;
472
473 while (1) {
1a22f08d 474 if (port->type == PORT_SCI)
73a19e4c 475 count = sci_rxfill(port);
1a22f08d 476 else
73a19e4c 477 count = scif_rxfill(port);
1da177e4
LT		 478
479 /* Don't copy more bytes than there is room for in the buffer */
33f0f88f 480 count = tty_buffer_request_room(tty, count);
1da177e4
LT		 481
482 /* If for any reason we can't copy more data, we're done! */
483 if (count == 0)
484 break;
485
486 if (port->type == PORT_SCI) {
487 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 488 if (uart_handle_sysrq_char(port, c) ||
489 sci_port->break_flag)
1da177e4 490 count = 0;
e7c98dc7 491 else
e108b2ca 492 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 493 } else {
e7c98dc7 494 for (i = 0; i < count; i++) {
1da177e4
LT		 495 char c = sci_in(port, SCxRDR);
496 status = sci_in(port, SCxSR);
497#if defined(CONFIG_CPU_SH3)
498 /* Skip "chars" during break */
e108b2ca 499 if (sci_port->break_flag) {
1da177e4
LT		 500 if ((c == 0) &&
501 (status & SCxSR_FER(port))) {
502 count--; i--;
503 continue;
504 }
e108b2ca 505
1da177e4 506 /* Nonzero => end-of-break */
762c69e3 507 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 508 sci_port->break_flag = 0;
509
1da177e4
LT		 510 if (STEPFN(c)) {
511 count--; i--;
512 continue;
513 }
514 }
515#endif /* CONFIG_CPU_SH3 */
7d12e780 516 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 517 count--; i--;
518 continue;
519 }
520
521 /* Store data and status */
73a19e4c 522 if (status & SCxSR_FER(port)) {
33f0f88f 523 flag = TTY_FRAME;
762c69e3 524 dev_notice(port->dev, "frame error\n");
73a19e4c 525 } else if (status & SCxSR_PER(port)) {
33f0f88f 526 flag = TTY_PARITY;
762c69e3 527 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 528 } else
529 flag = TTY_NORMAL;
762c69e3 530
33f0f88f 531 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 532 }
533 }
534
535 sci_in(port, SCxSR); /* dummy read */
536 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
537
1da177e4
LT		 538 copied += count;
539 port->icount.rx += count;
540 }
541
542 if (copied) {
543 /* Tell the rest of the system the news. New characters! */
544 tty_flip_buffer_push(tty);
545 } else {
546 sci_in(port, SCxSR); /* dummy read */
547 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
548 }
549}
550
551#define SCI_BREAK_JIFFIES (HZ/20)
552/* The sci generates interrupts during the break,
553 * 1 per millisecond or so during the break period, for 9600 baud.
554 * So dont bother disabling interrupts.
555 * But dont want more than 1 break event.
556 * Use a kernel timer to periodically poll the rx line until
557 * the break is finished.
558 */
559static void sci_schedule_break_timer(struct sci_port *port)
560{
561 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
562 add_timer(&port->break_timer);
563}
564/* Ensure that two consecutive samples find the break over. */
565static void sci_break_timer(unsigned long data)
566{
e108b2ca
PM		 567 struct sci_port *port = (struct sci_port *)data;
568
569 if (sci_rxd_in(&port->port) == 0) {
1da177e4 570 port->break_flag = 1;
e108b2ca
PM		 571 sci_schedule_break_timer(port);
572 } else if (port->break_flag == 1) {
1da177e4
LT		 573 /* break is over. */
574 port->break_flag = 2;
e108b2ca
PM		 575 sci_schedule_break_timer(port);
576 } else
577 port->break_flag = 0;
1da177e4
LT		 578}
579
580static inline int sci_handle_errors(struct uart_port *port)
581{
582 int copied = 0;
583 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 584 struct tty_struct *tty = port->state->port.tty;
1da177e4 585
e108b2ca 586 if (status & SCxSR_ORER(port)) {
1da177e4 587 /* overrun error */
e108b2ca 588 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
33f0f88f 589 copied++;
762c69e3
PM		 590
591 dev_notice(port->dev, "overrun error");
1da177e4
LT		 592 }
593
e108b2ca 594 if (status & SCxSR_FER(port)) {
1da177e4
LT		 595 if (sci_rxd_in(port) == 0) {
596 /* Notify of BREAK */
e7c98dc7 597 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 598
599 if (!sci_port->break_flag) {
600 sci_port->break_flag = 1;
601 sci_schedule_break_timer(sci_port);
602
1da177e4 603 /* Do sysrq handling. */
e108b2ca 604 if (uart_handle_break(port))
1da177e4 605 return 0;
762c69e3
PM		 606
607 dev_dbg(port->dev, "BREAK detected\n");
608
e108b2ca 609 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 610 copied++;
611 }
612
e108b2ca 613 } else {
1da177e4 614 /* frame error */
e108b2ca 615 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 616 copied++;
762c69e3
PM		 617
618 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 619 }
620 }
621
e108b2ca 622 if (status & SCxSR_PER(port)) {
1da177e4 623 /* parity error */
e108b2ca
PM		 624 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
625 copied++;
762c69e3
PM		 626
627 dev_notice(port->dev, "parity error");
1da177e4
LT		 628 }
629
33f0f88f 630 if (copied)
1da177e4 631 tty_flip_buffer_push(tty);
1da177e4
LT		 632
633 return copied;
634}
635
d830fa45
PM		 636static inline int sci_handle_fifo_overrun(struct uart_port *port)
637{
ebd2c8f6 638 struct tty_struct *tty = port->state->port.tty;
d830fa45
PM		 639 int copied = 0;
640
641 if (port->type != PORT_SCIF)
642 return 0;
643
644 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
645 sci_out(port, SCLSR, 0);
646
647 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
648 tty_flip_buffer_push(tty);
649
650 dev_notice(port->dev, "overrun error\n");
651 copied++;
652 }
653
654 return copied;
655}
656
1da177e4
LT		 657static inline int sci_handle_breaks(struct uart_port *port)
658{
659 int copied = 0;
660 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 661 struct tty_struct *tty = port->state->port.tty;
a5660ada 662 struct sci_port *s = to_sci_port(port);
1da177e4 663
0b3d4ef6
PM		 664 if (uart_handle_break(port))
665 return 0;
666
b7a76e4b 667 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 668#if defined(CONFIG_CPU_SH3)
669 /* Debounce break */
670 s->break_flag = 1;
671#endif
672 /* Notify of BREAK */
e108b2ca 673 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 674 copied++;
762c69e3
PM		 675
676 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 677 }
678
33f0f88f 679 if (copied)
1da177e4 680 tty_flip_buffer_push(tty);
e108b2ca 681
d830fa45
PM		 682 copied += sci_handle_fifo_overrun(port);
683
1da177e4
LT		 684 return copied;
685}
686
73a19e4c 687static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 688{
73a19e4c
GL		 689#ifdef CONFIG_SERIAL_SH_SCI_DMA
690 struct uart_port *port = ptr;
691 struct sci_port *s = to_sci_port(port);
692
693 if (s->chan_rx) {
73a19e4c
GL		 694 u16 scr = sci_in(port, SCSCR);
695 u16 ssr = sci_in(port, SCxSR);
696
697 /* Disable future Rx interrupts */
d1d4b10c 698 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 699 disable_irq_nosync(irq);
700 scr |= 0x4000;
701 } else {
f43dc23d 702 scr &= ~SCSCR_RIE;
3089f381
GL		 703 }
704 sci_out(port, SCSCR, scr);
73a19e4c
GL		 705 /* Clear current interrupt */
706 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 707 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
708 jiffies, s->rx_timeout);
709 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 710
711 return IRQ_HANDLED;
712 }
713#endif
714
1da177e4
LT		 715 /* I think sci_receive_chars has to be called irrespective
716 * of whether the I_IXOFF is set, otherwise, how is the interrupt
717 * to be disabled?
718 */
73a19e4c 719 sci_receive_chars(ptr);
1da177e4
LT		 720
721 return IRQ_HANDLED;
722}
723
7d12e780 724static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 725{
726 struct uart_port *port = ptr;
fd78a76a 727 unsigned long flags;
1da177e4 728
fd78a76a 729 spin_lock_irqsave(&port->lock, flags);
1da177e4 730 sci_transmit_chars(port);
fd78a76a 731 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 732
733 return IRQ_HANDLED;
734}
735
7d12e780 736static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 737{
738 struct uart_port *port = ptr;
739
740 /* Handle errors */
741 if (port->type == PORT_SCI) {
742 if (sci_handle_errors(port)) {
743 /* discard character in rx buffer */
744 sci_in(port, SCxSR);
745 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
746 }
747 } else {
d830fa45 748 sci_handle_fifo_overrun(port);
7d12e780 749 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 750 }
751
752 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
753
754 /* Kick the transmission */
7d12e780 755 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 756
757 return IRQ_HANDLED;
758}
759
7d12e780 760static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 761{
762 struct uart_port *port = ptr;
763
764 /* Handle BREAKs */
765 sci_handle_breaks(port);
766 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
767
768 return IRQ_HANDLED;
769}
770
f43dc23d
PM		 771static inline unsigned long port_rx_irq_mask(struct uart_port *port)
772{
773 /*
774 * Not all ports (such as SCIFA) will support REIE. Rather than
775 * special-casing the port type, we check the port initialization
776 * IRQ enable mask to see whether the IRQ is desired at all. If
777 * it's unset, it's logically inferred that there's no point in
778 * testing for it.
779 */
ce6738b6 780 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 781}
782
7d12e780 783static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 784{
44e18e9e 785 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 786 struct uart_port *port = ptr;
73a19e4c 787 struct sci_port *s = to_sci_port(port);
a8884e34 788 irqreturn_t ret = IRQ_NONE;
1da177e4 789
e7c98dc7
MT		 790 ssr_status = sci_in(port, SCxSR);
791 scr_status = sci_in(port, SCSCR);
f43dc23d 792 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 793
794 /* Tx Interrupt */
f43dc23d 795 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 796 !s->chan_tx)
a8884e34 797 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 798
73a19e4c
GL		 799 /*
800 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
801 * DR flags
802 */
803 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 804 (scr_status & SCSCR_RIE))
a8884e34 805 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 806
1da177e4 807 /* Error Interrupt */
dd4da3a5 808 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 809 ret = sci_er_interrupt(irq, ptr);
f43dc23d 810
1da177e4 811 /* Break Interrupt */
dd4da3a5 812 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 813 ret = sci_br_interrupt(irq, ptr);
1da177e4 814
a8884e34 815 return ret;
1da177e4
LT		 816}
817
1da177e4
LT		 818/*
819 * Here we define a transistion notifier so that we can update all of our
820 * ports' baud rate when the peripheral clock changes.
821 */
e108b2ca
PM		 822static int sci_notifier(struct notifier_block *self,
823 unsigned long phase, void *p)
1da177e4 824{
e552de24
MD		 825 struct sci_port *sci_port;
826 unsigned long flags;
1da177e4 827
d535a230
PM		 828 sci_port = container_of(self, struct sci_port, freq_transition);
829
1da177e4 830 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 831 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 832 struct uart_port *port = &sci_port->port;
073e84c9 833
d535a230
PM		 834 spin_lock_irqsave(&port->lock, flags);
835 port->uartclk = clk_get_rate(sci_port->iclk);
836 spin_unlock_irqrestore(&port->lock, flags);
e552de24 837 }
1da177e4 838
1da177e4
LT		 839 return NOTIFY_OK;
840}
501b825d
MD		 841
842static void sci_clk_enable(struct uart_port *port)
843{
844 struct sci_port *sci_port = to_sci_port(port);
845
c7ed1ab3
PM		 846 clk_enable(sci_port->iclk);
847 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
848 clk_enable(sci_port->fclk);
501b825d
MD		 849}
850
851static void sci_clk_disable(struct uart_port *port)
852{
853 struct sci_port *sci_port = to_sci_port(port);
854
c7ed1ab3
PM		 855 clk_disable(sci_port->fclk);
856 clk_disable(sci_port->iclk);
501b825d 857}
1da177e4
LT		 858
859static int sci_request_irq(struct sci_port *port)
860{
861 int i;
7d12e780 862 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
1da177e4
LT		 863 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
864 sci_br_interrupt,
865 };
866 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
867 "SCI Transmit Data Empty", "SCI Break" };
868
ce6738b6
PM		 869 if (port->cfg->irqs[0] == port->cfg->irqs[1]) {
870 if (unlikely(!port->cfg->irqs[0]))
1da177e4 871 return -ENODEV;
e108b2ca 872
ce6738b6 873 if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt,
35f3c518 874 IRQF_DISABLED, "sci", port)) {
762c69e3 875 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 876 return -ENODEV;
877 }
878 } else {
879 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
ce6738b6 880 if (unlikely(!port->cfg->irqs[i]))
1da177e4 881 continue;
762c69e3 882
ce6738b6 883 if (request_irq(port->cfg->irqs[i], handlers[i],
35f3c518 884 IRQF_DISABLED, desc[i], port)) {
762c69e3 885 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 886 return -ENODEV;
887 }
888 }
889 }
890
891 return 0;
892}
893
894static void sci_free_irq(struct sci_port *port)
895{
896 int i;
897
ce6738b6
PM		 898 if (port->cfg->irqs[0] == port->cfg->irqs[1])
899 free_irq(port->cfg->irqs[0], port);
762c69e3 900 else {
ce6738b6
PM		 901 for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) {
902 if (!port->cfg->irqs[i])
1da177e4
LT		 903 continue;
904
ce6738b6 905 free_irq(port->cfg->irqs[i], port);
1da177e4
LT		 906 }
907 }
908}
909
910static unsigned int sci_tx_empty(struct uart_port *port)
911{
b1516803 912 unsigned short status = sci_in(port, SCxSR);
73a19e4c
GL		 913 unsigned short in_tx_fifo = scif_txfill(port);
914
915 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 916}
917
918static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
919{
920 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
921 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
922 /* If you have signals for DTR and DCD, please implement here. */
923}
924
925static unsigned int sci_get_mctrl(struct uart_port *port)
926{
73a19e4c 927 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1da177e4
LT		 928 and CTS/RTS */
929
930 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
931}
932
73a19e4c
GL		 933#ifdef CONFIG_SERIAL_SH_SCI_DMA
934static void sci_dma_tx_complete(void *arg)
935{
936 struct sci_port *s = arg;
937 struct uart_port *port = &s->port;
938 struct circ_buf *xmit = &port->state->xmit;
939 unsigned long flags;
940
941 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
942
943 spin_lock_irqsave(&port->lock, flags);
944
f354a381 945 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 946 xmit->tail &= UART_XMIT_SIZE - 1;
947
f354a381 948 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 949
950 async_tx_ack(s->desc_tx);
951 s->cookie_tx = -EINVAL;
952 s->desc_tx = NULL;
953
73a19e4c
GL		 954 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
955 uart_write_wakeup(port);
956
3089f381 957 if (!uart_circ_empty(xmit)) {
73a19e4c 958 schedule_work(&s->work_tx);
d1d4b10c 959 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 960 u16 ctrl = sci_in(port, SCSCR);
f43dc23d 961 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
3089f381
GL		 962 }
963
964 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 965}
966
967/* Locking: called with port lock held */
968static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
969 size_t count)
970{
971 struct uart_port *port = &s->port;
972 int i, active, room;
973
974 room = tty_buffer_request_room(tty, count);
975
976 if (s->active_rx == s->cookie_rx[0]) {
977 active = 0;
978 } else if (s->active_rx == s->cookie_rx[1]) {
979 active = 1;
980 } else {
981 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
982 return 0;
983 }
984
985 if (room < count)
986 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
987 count - room);
988 if (!room)
989 return room;
990
991 for (i = 0; i < room; i++)
992 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
993 TTY_NORMAL);
994
995 port->icount.rx += room;
996
997 return room;
998}
999
1000static void sci_dma_rx_complete(void *arg)
1001{
1002 struct sci_port *s = arg;
1003 struct uart_port *port = &s->port;
1004 struct tty_struct *tty = port->state->port.tty;
1005 unsigned long flags;
1006 int count;
1007
3089f381 1008 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1009
1010 spin_lock_irqsave(&port->lock, flags);
1011
1012 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1013
3089f381 1014 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1015
1016 spin_unlock_irqrestore(&port->lock, flags);
1017
1018 if (count)
1019 tty_flip_buffer_push(tty);
1020
1021 schedule_work(&s->work_rx);
1022}
1023
73a19e4c
GL		 1024static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1025{
1026 struct dma_chan *chan = s->chan_rx;
1027 struct uart_port *port = &s->port;
73a19e4c
GL		 1028
1029 s->chan_rx = NULL;
1030 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1031 dma_release_channel(chan);
85b8e3ff
GL		 1032 if (sg_dma_address(&s->sg_rx[0]))
1033 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1034 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1035 if (enable_pio)
1036 sci_start_rx(port);
1037}
1038
1039static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1040{
1041 struct dma_chan *chan = s->chan_tx;
1042 struct uart_port *port = &s->port;
73a19e4c
GL		 1043
1044 s->chan_tx = NULL;
1045 s->cookie_tx = -EINVAL;
1046 dma_release_channel(chan);
1047 if (enable_pio)
1048 sci_start_tx(port);
1049}
1050
1051static void sci_submit_rx(struct sci_port *s)
1052{
1053 struct dma_chan *chan = s->chan_rx;
1054 int i;
1055
1056 for (i = 0; i < 2; i++) {
1057 struct scatterlist *sg = &s->sg_rx[i];
1058 struct dma_async_tx_descriptor *desc;
1059
1060 desc = chan->device->device_prep_slave_sg(chan,
1061 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1062
1063 if (desc) {
1064 s->desc_rx[i] = desc;
1065 desc->callback = sci_dma_rx_complete;
1066 desc->callback_param = s;
1067 s->cookie_rx[i] = desc->tx_submit(desc);
1068 }
1069
1070 if (!desc || s->cookie_rx[i] < 0) {
1071 if (i) {
1072 async_tx_ack(s->desc_rx[0]);
1073 s->cookie_rx[0] = -EINVAL;
1074 }
1075 if (desc) {
1076 async_tx_ack(desc);
1077 s->cookie_rx[i] = -EINVAL;
1078 }
1079 dev_warn(s->port.dev,
1080 "failed to re-start DMA, using PIO\n");
1081 sci_rx_dma_release(s, true);
1082 return;
1083 }
3089f381
GL		 1084 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1085 s->cookie_rx[i], i);
73a19e4c
GL		 1086 }
1087
1088 s->active_rx = s->cookie_rx[0];
1089
1090 dma_async_issue_pending(chan);
1091}
1092
1093static void work_fn_rx(struct work_struct *work)
1094{
1095 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1096 struct uart_port *port = &s->port;
1097 struct dma_async_tx_descriptor *desc;
1098 int new;
1099
1100 if (s->active_rx == s->cookie_rx[0]) {
1101 new = 0;
1102 } else if (s->active_rx == s->cookie_rx[1]) {
1103 new = 1;
1104 } else {
1105 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1106 return;
1107 }
1108 desc = s->desc_rx[new];
1109
1110 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1111 DMA_SUCCESS) {
1112 /* Handle incomplete DMA receive */
1113 struct tty_struct *tty = port->state->port.tty;
1114 struct dma_chan *chan = s->chan_rx;
1115 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1116 async_tx);
1117 unsigned long flags;
1118 int count;
1119
05827630 1120 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1121 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1122 sh_desc->partial, sh_desc->cookie);
1123
1124 spin_lock_irqsave(&port->lock, flags);
1125 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1126 spin_unlock_irqrestore(&port->lock, flags);
1127
1128 if (count)
1129 tty_flip_buffer_push(tty);
1130
1131 sci_submit_rx(s);
1132
1133 return;
1134 }
1135
1136 s->cookie_rx[new] = desc->tx_submit(desc);
1137 if (s->cookie_rx[new] < 0) {
1138 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1139 sci_rx_dma_release(s, true);
1140 return;
1141 }
1142
73a19e4c 1143 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1144
1145 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1146 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1147}
1148
1149static void work_fn_tx(struct work_struct *work)
1150{
1151 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1152 struct dma_async_tx_descriptor *desc;
1153 struct dma_chan *chan = s->chan_tx;
1154 struct uart_port *port = &s->port;
1155 struct circ_buf *xmit = &port->state->xmit;
1156 struct scatterlist *sg = &s->sg_tx;
1157
1158 /*
1159 * DMA is idle now.
1160 * Port xmit buffer is already mapped, and it is one page... Just adjust
1161 * offsets and lengths. Since it is a circular buffer, we have to
1162 * transmit till the end, and then the rest. Take the port lock to get a
1163 * consistent xmit buffer state.
1164 */
1165 spin_lock_irq(&port->lock);
1166 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1167 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1168 sg->offset;
f354a381 1169 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1170 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1171 spin_unlock_irq(&port->lock);
1172
f354a381 1173 BUG_ON(!sg_dma_len(sg));
73a19e4c
GL		 1174
1175 desc = chan->device->device_prep_slave_sg(chan,
1176 sg, s->sg_len_tx, DMA_TO_DEVICE,
1177 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1178 if (!desc) {
1179 /* switch to PIO */
1180 sci_tx_dma_release(s, true);
1181 return;
1182 }
1183
1184 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1185
1186 spin_lock_irq(&port->lock);
1187 s->desc_tx = desc;
1188 desc->callback = sci_dma_tx_complete;
1189 desc->callback_param = s;
1190 spin_unlock_irq(&port->lock);
1191 s->cookie_tx = desc->tx_submit(desc);
1192 if (s->cookie_tx < 0) {
1193 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1194 /* switch to PIO */
1195 sci_tx_dma_release(s, true);
1196 return;
1197 }
1198
1199 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1200 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1201
1202 dma_async_issue_pending(chan);
1203}
1204#endif
1205
b129a8cc 1206static void sci_start_tx(struct uart_port *port)
1da177e4 1207{
3089f381 1208 struct sci_port *s = to_sci_port(port);
e108b2ca 1209 unsigned short ctrl;
1da177e4 1210
73a19e4c 1211#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1212 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1213 u16 new, scr = sci_in(port, SCSCR);
1214 if (s->chan_tx)
1215 new = scr | 0x8000;
1216 else
1217 new = scr & ~0x8000;
1218 if (new != scr)
1219 sci_out(port, SCSCR, new);
73a19e4c 1220 }
f43dc23d 1221
3089f381
GL		 1222 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1223 s->cookie_tx < 0)
1224 schedule_work(&s->work_tx);
73a19e4c 1225#endif
f43dc23d 1226
d1d4b10c 1227 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1228 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1229 ctrl = sci_in(port, SCSCR);
f43dc23d 1230 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1231 }
1da177e4
LT		 1232}
1233
b129a8cc 1234static void sci_stop_tx(struct uart_port *port)
1da177e4 1235{
1da177e4
LT		 1236 unsigned short ctrl;
1237
1238 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4 1239 ctrl = sci_in(port, SCSCR);
f43dc23d 1240
d1d4b10c 1241 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1242 ctrl &= ~0x8000;
f43dc23d 1243
8e698614 1244 ctrl &= ~SCSCR_TIE;
f43dc23d 1245
1da177e4 1246 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1247}
1248
73a19e4c 1249static void sci_start_rx(struct uart_port *port)
1da177e4 1250{
1da177e4
LT		 1251 unsigned short ctrl;
1252
f43dc23d 1253 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1254
d1d4b10c 1255 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1256 ctrl &= ~0x4000;
f43dc23d 1257
1da177e4 1258 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1259}
1260
1261static void sci_stop_rx(struct uart_port *port)
1262{
1da177e4
LT		 1263 unsigned short ctrl;
1264
1da177e4 1265 ctrl = sci_in(port, SCSCR);
f43dc23d 1266
d1d4b10c 1267 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1268 ctrl &= ~0x4000;
f43dc23d
PM		 1269
1270 ctrl &= ~port_rx_irq_mask(port);
1271
1da177e4 1272 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1273}
1274
1275static void sci_enable_ms(struct uart_port *port)
1276{
1277 /* Nothing here yet .. */
1278}
1279
1280static void sci_break_ctl(struct uart_port *port, int break_state)
1281{
1282 /* Nothing here yet .. */
1283}
1284
73a19e4c
GL		 1285#ifdef CONFIG_SERIAL_SH_SCI_DMA
1286static bool filter(struct dma_chan *chan, void *slave)
1287{
1288 struct sh_dmae_slave *param = slave;
1289
1290 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1291 param->slave_id);
1292
1293 if (param->dma_dev == chan->device->dev) {
1294 chan->private = param;
1295 return true;
1296 } else {
1297 return false;
1298 }
1299}
1300
1301static void rx_timer_fn(unsigned long arg)
1302{
1303 struct sci_port *s = (struct sci_port *)arg;
1304 struct uart_port *port = &s->port;
73a19e4c 1305 u16 scr = sci_in(port, SCSCR);
3089f381 1306
d1d4b10c 1307 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1308 scr &= ~0x4000;
ce6738b6 1309 enable_irq(s->cfg->irqs[1]);
3089f381 1310 }
f43dc23d 1311 sci_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1312 dev_dbg(port->dev, "DMA Rx timed out\n");
1313 schedule_work(&s->work_rx);
1314}
1315
1316static void sci_request_dma(struct uart_port *port)
1317{
1318 struct sci_port *s = to_sci_port(port);
1319 struct sh_dmae_slave *param;
1320 struct dma_chan *chan;
1321 dma_cap_mask_t mask;
1322 int nent;
1323
1324 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
ce6738b6 1325 port->line, s->cfg->dma_dev);
73a19e4c 1326
ce6738b6 1327 if (!s->cfg->dma_dev)
73a19e4c
GL		 1328 return;
1329
1330 dma_cap_zero(mask);
1331 dma_cap_set(DMA_SLAVE, mask);
1332
1333 param = &s->param_tx;
1334
1335 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
ce6738b6
PM		 1336 param->slave_id = s->cfg->dma_slave_tx;
1337 param->dma_dev = s->cfg->dma_dev;
73a19e4c
GL		 1338
1339 s->cookie_tx = -EINVAL;
1340 chan = dma_request_channel(mask, filter, param);
1341 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1342 if (chan) {
1343 s->chan_tx = chan;
1344 sg_init_table(&s->sg_tx, 1);
1345 /* UART circular tx buffer is an aligned page. */
1346 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1347 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1348 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1349 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1350 if (!nent)
1351 sci_tx_dma_release(s, false);
1352 else
1353 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1354 sg_dma_len(&s->sg_tx),
1355 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1356
1357 s->sg_len_tx = nent;
1358
1359 INIT_WORK(&s->work_tx, work_fn_tx);
1360 }
1361
1362 param = &s->param_rx;
1363
1364 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
ce6738b6
PM		 1365 param->slave_id = s->cfg->dma_slave_rx;
1366 param->dma_dev = s->cfg->dma_dev;
73a19e4c
GL		 1367
1368 chan = dma_request_channel(mask, filter, param);
1369 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1370 if (chan) {
1371 dma_addr_t dma[2];
1372 void *buf[2];
1373 int i;
1374
1375 s->chan_rx = chan;
1376
1377 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1378 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1379 &dma[0], GFP_KERNEL);
1380
1381 if (!buf[0]) {
1382 dev_warn(port->dev,
1383 "failed to allocate dma buffer, using PIO\n");
1384 sci_rx_dma_release(s, true);
1385 return;
1386 }
1387
1388 buf[1] = buf[0] + s->buf_len_rx;
1389 dma[1] = dma[0] + s->buf_len_rx;
1390
1391 for (i = 0; i < 2; i++) {
1392 struct scatterlist *sg = &s->sg_rx[i];
1393
1394 sg_init_table(sg, 1);
1395 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1396 (int)buf[i] & ~PAGE_MASK);
f354a381 1397 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1398 }
1399
1400 INIT_WORK(&s->work_rx, work_fn_rx);
1401 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1402
1403 sci_submit_rx(s);
1404 }
1405}
1406
1407static void sci_free_dma(struct uart_port *port)
1408{
1409 struct sci_port *s = to_sci_port(port);
1410
ce6738b6 1411 if (!s->cfg->dma_dev)
73a19e4c
GL		 1412 return;
1413
1414 if (s->chan_tx)
1415 sci_tx_dma_release(s, false);
1416 if (s->chan_rx)
1417 sci_rx_dma_release(s, false);
1418}
27bd1075
PM		 1419#else
1420static inline void sci_request_dma(struct uart_port *port)
1421{
1422}
1423
1424static inline void sci_free_dma(struct uart_port *port)
1425{
1426}
73a19e4c
GL		 1427#endif
1428
1da177e4
LT		 1429static int sci_startup(struct uart_port *port)
1430{
a5660ada 1431 struct sci_port *s = to_sci_port(port);
073e84c9 1432 int ret;
1da177e4 1433
73a19e4c
GL		 1434 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1435
e108b2ca
PM		 1436 if (s->enable)
1437 s->enable(port);
1da177e4 1438
073e84c9
PM		 1439 ret = sci_request_irq(s);
1440 if (unlikely(ret < 0))
1441 return ret;
1442
73a19e4c 1443 sci_request_dma(port);
073e84c9 1444
d656901b 1445 sci_start_tx(port);
73a19e4c 1446 sci_start_rx(port);
1da177e4
LT		 1447
1448 return 0;
1449}
1450
1451static void sci_shutdown(struct uart_port *port)
1452{
a5660ada 1453 struct sci_port *s = to_sci_port(port);
1da177e4 1454
73a19e4c
GL		 1455 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1456
1da177e4 1457 sci_stop_rx(port);
b129a8cc 1458 sci_stop_tx(port);
073e84c9 1459
73a19e4c 1460 sci_free_dma(port);
1da177e4
LT		 1461 sci_free_irq(s);
1462
e108b2ca
PM		 1463 if (s->disable)
1464 s->disable(port);
1da177e4
LT		 1465}
1466
26c92f37
PM		 1467static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1468 unsigned long freq)
1469{
1470 switch (algo_id) {
1471 case SCBRR_ALGO_1:
1472 return ((freq + 16 * bps) / (16 * bps) - 1);
1473 case SCBRR_ALGO_2:
1474 return ((freq + 16 * bps) / (32 * bps) - 1);
1475 case SCBRR_ALGO_3:
1476 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1477 case SCBRR_ALGO_4:
1478 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1479 case SCBRR_ALGO_5:
1480 return (((freq * 1000 / 32) / bps) - 1);
1481 }
1482
1483 /* Warn, but use a safe default */
1484 WARN_ON(1);
e8183a6c 1485
26c92f37
PM		 1486 return ((freq + 16 * bps) / (32 * bps) - 1);
1487}
1488
606d099c
AC		 1489static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1490 struct ktermios *old)
1da177e4 1491{
00b9de9c 1492 struct sci_port *s = to_sci_port(port);
154280fd 1493 unsigned int status, baud, smr_val, max_baud;
a2159b52 1494 int t = -1;
3089f381 1495 u16 scfcr = 0;
1da177e4 1496
154280fd
MD		 1497 /*
1498 * earlyprintk comes here early on with port->uartclk set to zero.
1499 * the clock framework is not up and running at this point so here
1500 * we assume that 115200 is the maximum baud rate. please note that
1501 * the baud rate is not programmed during earlyprintk - it is assumed
1502 * that the previous boot loader has enabled required clocks and
1503 * setup the baud rate generator hardware for us already.
1504 */
1505 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1506
154280fd
MD		 1507 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1508 if (likely(baud && port->uartclk))
ce6738b6 1509 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1510
1da177e4
LT		 1511 do {
1512 status = sci_in(port, SCxSR);
1513 } while (!(status & SCxSR_TEND(port)));
1514
1515 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1516
1a22f08d 1517 if (port->type != PORT_SCI)
3089f381 1518 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 1519
1520 smr_val = sci_in(port, SCSMR) & 3;
e8183a6c 1521
1da177e4
LT		 1522 if ((termios->c_cflag & CSIZE) == CS7)
1523 smr_val |= 0x40;
1524 if (termios->c_cflag & PARENB)
1525 smr_val |= 0x20;
1526 if (termios->c_cflag & PARODD)
1527 smr_val |= 0x30;
1528 if (termios->c_cflag & CSTOPB)
1529 smr_val |= 0x08;
1530
1531 uart_update_timeout(port, termios->c_cflag, baud);
1532
1533 sci_out(port, SCSMR, smr_val);
1534
73a19e4c 1535 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
ce6738b6 1536 s->cfg->scscr);
73a19e4c 1537
1da177e4 1538 if (t > 0) {
e7c98dc7 1539 if (t >= 256) {
1da177e4
LT		 1540 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1541 t >>= 2;
e7c98dc7 1542 } else
1da177e4 1543 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1544
1da177e4
LT		 1545 sci_out(port, SCBRR, t);
1546 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1547 }
1548
d5701647 1549 sci_init_pins(port, termios->c_cflag);
3089f381 1550 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
b7a76e4b 1551
ce6738b6 1552 sci_out(port, SCSCR, s->cfg->scscr);
1da177e4 1553
3089f381
GL		 1554#ifdef CONFIG_SERIAL_SH_SCI_DMA
1555 /*
1556 * Calculate delay for 1.5 DMA buffers: see
1557 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1558 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1559 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1560 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1561 * sizes), but it has been found out experimentally, that this is not
1562 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1563 * as a minimum seem to work perfectly.
1564 */
1565 if (s->chan_rx) {
1566 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1567 port->fifosize / 2;
1568 dev_dbg(port->dev,
1569 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1570 s->rx_timeout * 1000 / HZ, port->timeout);
1571 if (s->rx_timeout < msecs_to_jiffies(20))
1572 s->rx_timeout = msecs_to_jiffies(20);
1573 }
1574#endif
1575
1da177e4 1576 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1577 sci_start_rx(port);
1da177e4
LT		 1578}
1579
1580static const char *sci_type(struct uart_port *port)
1581{
1582 switch (port->type) {
e7c98dc7
MT		 1583 case PORT_IRDA:
1584 return "irda";
1585 case PORT_SCI:
1586 return "sci";
1587 case PORT_SCIF:
1588 return "scif";
1589 case PORT_SCIFA:
1590 return "scifa";
d1d4b10c
GL		 1591 case PORT_SCIFB:
1592 return "scifb";
1da177e4
LT		 1593 }
1594
fa43972f 1595 return NULL;
1da177e4
LT		 1596}
1597
e2651647 1598static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1599{
e2651647
PM		 1600 /*
1601 * Pick an arbitrary size that encapsulates all of the base
1602 * registers by default. This can be optimized later, or derived
1603 * from platform resource data at such a time that ports begin to
1604 * behave more erratically.
1605 */
1606 return 64;
1da177e4
LT		 1607}
1608
e2651647 1609static void sci_release_port(struct uart_port *port)
1da177e4 1610{
e2651647
PM		 1611 if (port->flags & UPF_IOREMAP) {
1612 iounmap(port->membase);
1613 port->membase = NULL;
1614 }
1615
1616 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 1617}
1618
e2651647 1619static int sci_request_port(struct uart_port *port)
1da177e4 1620{
e2651647
PM		 1621 unsigned long size = sci_port_size(port);
1622 struct resource *res;
1da177e4 1623
e2651647
PM		 1624 res = request_mem_region(port->mapbase, size, sci_type(port));
1625 if (unlikely(res == NULL))
1626 return -EBUSY;
1da177e4 1627
08f8cb31 1628 if (port->flags & UPF_IOREMAP) {
e2651647
PM		 1629 port->membase = ioremap_nocache(port->mapbase, size);
1630 if (unlikely(!port->membase)) {
08f8cb31 1631 dev_err(port->dev, "can't remap port#%d\n", port->line);
e2651647
PM		 1632 release_resource(res);
1633 return -ENXIO;
1634 }
08f8cb31
MD		 1635 } else {
1636 /*
1637 * For the simple (and majority of) cases where we don't
1638 * need to do any remapping, just cast the cookie
1639 * directly.
1640 */
1641 port->membase = (void __iomem *)port->mapbase;
7ff731ae 1642 }
e2651647
PM		 1643
1644 return 0;
1645}
1646
1647static void sci_config_port(struct uart_port *port, int flags)
1648{
1649 if (flags & UART_CONFIG_TYPE) {
1650 struct sci_port *sport = to_sci_port(port);
1651
1652 port->type = sport->cfg->type;
1653 sci_request_port(port);
1654 }
1da177e4
LT		 1655}
1656
1657static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1658{
a5660ada 1659 struct sci_port *s = to_sci_port(port);
1da177e4 1660
ce6738b6 1661 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1662 return -EINVAL;
1663 if (ser->baud_base < 2400)
1664 /* No paper tape reader for Mitch.. */
1665 return -EINVAL;
1666
1667 return 0;
1668}
1669
1670static struct uart_ops sci_uart_ops = {
1671 .tx_empty = sci_tx_empty,
1672 .set_mctrl = sci_set_mctrl,
1673 .get_mctrl = sci_get_mctrl,
1674 .start_tx = sci_start_tx,
1675 .stop_tx = sci_stop_tx,
1676 .stop_rx = sci_stop_rx,
1677 .enable_ms = sci_enable_ms,
1678 .break_ctl = sci_break_ctl,
1679 .startup = sci_startup,
1680 .shutdown = sci_shutdown,
1681 .set_termios = sci_set_termios,
1682 .type = sci_type,
1683 .release_port = sci_release_port,
1684 .request_port = sci_request_port,
1685 .config_port = sci_config_port,
1686 .verify_port = sci_verify_port,
07d2a1a1
PM		 1687#ifdef CONFIG_CONSOLE_POLL
1688 .poll_get_char = sci_poll_get_char,
1689 .poll_put_char = sci_poll_put_char,
1690#endif
1da177e4
LT		 1691};
1692
c7ed1ab3
PM		 1693static int __devinit sci_init_single(struct platform_device *dev,
1694 struct sci_port *sci_port,
1695 unsigned int index,
1696 struct plat_sci_port *p)
e108b2ca 1697{
73a19e4c 1698 struct uart_port *port = &sci_port->port;
e108b2ca 1699
73a19e4c
GL		 1700 port->ops = &sci_uart_ops;
1701 port->iotype = UPIO_MEM;
1702 port->line = index;
75136d48
MP		 1703
1704 switch (p->type) {
d1d4b10c
GL		 1705 case PORT_SCIFB:
1706 port->fifosize = 256;
1707 break;
75136d48 1708 case PORT_SCIFA:
73a19e4c 1709 port->fifosize = 64;
75136d48
MP		 1710 break;
1711 case PORT_SCIF:
73a19e4c 1712 port->fifosize = 16;
75136d48
MP		 1713 break;
1714 default:
73a19e4c 1715 port->fifosize = 1;
75136d48
MP		 1716 break;
1717 }
7b6fd3bf
MD		 1718
1719 if (dev) {
c7ed1ab3
PM		 1720 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1721 if (IS_ERR(sci_port->iclk)) {
1722 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1723 if (IS_ERR(sci_port->iclk)) {
1724 dev_err(&dev->dev, "can't get iclk\n");
1725 return PTR_ERR(sci_port->iclk);
1726 }
1727 }
1728
1729 /*
1730 * The function clock is optional, ignore it if we can't
1731 * find it.
1732 */
1733 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1734 if (IS_ERR(sci_port->fclk))
1735 sci_port->fclk = NULL;
1736
7b6fd3bf
MD		 1737 sci_port->enable = sci_clk_enable;
1738 sci_port->disable = sci_clk_disable;
73a19e4c 1739 port->dev = &dev->dev;
7b6fd3bf 1740 }
e108b2ca 1741
7ed7e071
MD		 1742 sci_port->break_timer.data = (unsigned long)sci_port;
1743 sci_port->break_timer.function = sci_break_timer;
1744 init_timer(&sci_port->break_timer);
1745
ce6738b6 1746 sci_port->cfg = p;
7ed7e071 1747
ce6738b6
PM		 1748 port->mapbase = p->mapbase;
1749 port->type = p->type;
f43dc23d 1750 port->flags = p->flags;
73a19e4c 1751
ce6738b6
PM		 1752 /*
1753 * The UART port needs an IRQ value, so we peg this to the TX IRQ
1754 * for the multi-IRQ ports, which is where we are primarily
1755 * concerned with the shutdown path synchronization.
1756 *
1757 * For the muxed case there's nothing more to do.
1758 */
1759 port->irq = p->irqs[SCIx_TXI_IRQ];
73a19e4c 1760
ce6738b6
PM		 1761 if (p->dma_dev)
1762 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
1763 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 1764
c7ed1ab3 1765 return 0;
e108b2ca
PM		 1766}
1767
1da177e4 1768#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 1769static struct tty_driver *serial_console_device(struct console *co, int *index)
1770{
1771 struct uart_driver *p = &sci_uart_driver;
1772 *index = co->index;
1773 return p->tty_driver;
1774}
1775
1776static void serial_console_putchar(struct uart_port *port, int ch)
1777{
1778 sci_poll_put_char(port, ch);
1779}
1780
1da177e4
LT		 1781/*
1782 * Print a string to the serial port trying not to disturb
1783 * any possible real use of the port...
1784 */
1785static void serial_console_write(struct console *co, const char *s,
1786 unsigned count)
1787{
dc8e6f5b 1788 struct uart_port *port = co->data;
501b825d 1789 struct sci_port *sci_port = to_sci_port(port);
973e5d52 1790 unsigned short bits;
07d2a1a1 1791
501b825d
MD		 1792 if (sci_port->enable)
1793 sci_port->enable(port);
1794
1795 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 1796
1797 /* wait until fifo is empty and last bit has been transmitted */
1798 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1799 while ((sci_in(port, SCxSR) & bits) != bits)
1800 cpu_relax();
501b825d 1801
345e5a76 1802 if (sci_port->disable)
501b825d 1803 sci_port->disable(port);
1da177e4
LT		 1804}
1805
7b6fd3bf 1806static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 1807{
dc8e6f5b 1808 struct sci_port *sci_port;
1da177e4
LT		 1809 struct uart_port *port;
1810 int baud = 115200;
1811 int bits = 8;
1812 int parity = 'n';
1813 int flow = 'n';
1814 int ret;
1815
e108b2ca
PM		 1816 /*
1817 * Check whether an invalid uart number has been specified, and
1818 * if so, search for the first available port that does have
1819 * console support.
1820 */
1821 if (co->index >= SCI_NPORTS)
1822 co->index = 0;
1823
7b6fd3bf
MD		 1824 if (co->data) {
1825 port = co->data;
1826 sci_port = to_sci_port(port);
1827 } else {
1828 sci_port = &sci_ports[co->index];
1829 port = &sci_port->port;
1830 co->data = port;
1831 }
1da177e4
LT		 1832
1833 /*
e108b2ca
PM		 1834 * Also need to check port->type, we don't actually have any
1835 * UPIO_PORT ports, but uart_report_port() handily misreports
1836 * it anyways if we don't have a port available by the time this is
1837 * called.
1da177e4 1838 */
e108b2ca
PM		 1839 if (!port->type)
1840 return -ENODEV;
e108b2ca 1841
08f8cb31 1842 sci_config_port(port, 0);
e108b2ca 1843
dc8e6f5b
MD		 1844 if (sci_port->enable)
1845 sci_port->enable(port);
b7a76e4b 1846
1da177e4
LT		 1847 if (options)
1848 uart_parse_options(options, &baud, &parity, &bits, &flow);
1849
1850 ret = uart_set_options(port, co, baud, parity, bits, flow);
1851#if defined(__H8300H__) || defined(__H8300S__)
1852 /* disable rx interrupt */
1853 if (ret == 0)
1854 sci_stop_rx(port);
1855#endif
501b825d 1856 /* TODO: disable clock */
1da177e4
LT		 1857 return ret;
1858}
1859
1860static struct console serial_console = {
1861 .name = "ttySC",
dc8e6f5b 1862 .device = serial_console_device,
1da177e4
LT		 1863 .write = serial_console_write,
1864 .setup = serial_console_setup,
fa5da2f7 1865 .flags = CON_PRINTBUFFER,
1da177e4 1866 .index = -1,
1da177e4
LT		 1867};
1868
1869static int __init sci_console_init(void)
1870{
1871 register_console(&serial_console);
1872 return 0;
1873}
1da177e4 1874console_initcall(sci_console_init);
7b6fd3bf
MD		 1875
1876static struct sci_port early_serial_port;
1877static struct console early_serial_console = {
1878 .name = "early_ttySC",
1879 .write = serial_console_write,
1880 .flags = CON_PRINTBUFFER,
1881};
1882static char early_serial_buf[32];
1883
1da177e4
LT		 1884#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1885
07d2a1a1 1886#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
e7c98dc7 1887#define SCI_CONSOLE (&serial_console)
1da177e4 1888#else
b7a76e4b 1889#define SCI_CONSOLE 0
1da177e4
LT		 1890#endif
1891
1892static char banner[] __initdata =
1893 KERN_INFO "SuperH SCI(F) driver initialized\n";
1894
1895static struct uart_driver sci_uart_driver = {
1896 .owner = THIS_MODULE,
1897 .driver_name = "sci",
1da177e4
LT		 1898 .dev_name = "ttySC",
1899 .major = SCI_MAJOR,
1900 .minor = SCI_MINOR_START,
e108b2ca 1901 .nr = SCI_NPORTS,
1da177e4
LT		 1902 .cons = SCI_CONSOLE,
1903};
1904
54507f6e 1905static int sci_remove(struct platform_device *dev)
e552de24 1906{
d535a230 1907 struct sci_port *port = platform_get_drvdata(dev);
e552de24 1908
d535a230
PM		 1909 cpufreq_unregister_notifier(&port->freq_transition,
1910 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 1911
d535a230
PM		 1912 uart_remove_one_port(&sci_uart_driver, &port->port);
1913
1914 clk_put(port->iclk);
1915 clk_put(port->fclk);
e552de24 1916
e552de24
MD		 1917 return 0;
1918}
1919
0ee70712
MD		 1920static int __devinit sci_probe_single(struct platform_device *dev,
1921 unsigned int index,
1922 struct plat_sci_port *p,
1923 struct sci_port *sciport)
1924{
0ee70712
MD		 1925 int ret;
1926
1927 /* Sanity check */
1928 if (unlikely(index >= SCI_NPORTS)) {
1929 dev_notice(&dev->dev, "Attempting to register port "
1930 "%d when only %d are available.\n",
1931 index+1, SCI_NPORTS);
1932 dev_notice(&dev->dev, "Consider bumping "
1933 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1934 return 0;
1935 }
1936
c7ed1ab3
PM		 1937 ret = sci_init_single(dev, sciport, index, p);
1938 if (ret)
1939 return ret;
0ee70712 1940
d535a230 1941 return uart_add_one_port(&sci_uart_driver, &sciport->port);
0ee70712
MD		 1942}
1943
e108b2ca
PM		 1944/*
1945 * Register a set of serial devices attached to a platform device. The
1946 * list is terminated with a zero flags entry, which means we expect
1947 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1948 * remapping (such as sh64) should also set UPF_IOREMAP.
1949 */
1950static int __devinit sci_probe(struct platform_device *dev)
1da177e4 1951{
e108b2ca 1952 struct plat_sci_port *p = dev->dev.platform_data;
d535a230
PM		 1953 struct sci_port *sp = &sci_ports[dev->id];
1954 int ret = -EINVAL;
e552de24 1955
7b6fd3bf
MD		 1956#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1957 if (is_early_platform_device(dev)) {
7b6fd3bf
MD		 1958 early_serial_console.index = dev->id;
1959 early_serial_console.data = &early_serial_port.port;
d535a230 1960
7b6fd3bf 1961 sci_init_single(NULL, &early_serial_port, dev->id, p);
d535a230 1962
7b6fd3bf 1963 serial_console_setup(&early_serial_console, early_serial_buf);
d535a230 1964
7b6fd3bf
MD		 1965 if (!strstr(early_serial_buf, "keep"))
1966 early_serial_console.flags |= CON_BOOT;
d535a230 1967
7b6fd3bf
MD		 1968 register_console(&early_serial_console);
1969 return 0;
1970 }
1971#endif
1972
d535a230 1973 platform_set_drvdata(dev, sp);
e552de24 1974
d535a230
PM		 1975 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1976 if (ret)
1977 goto err_unreg;
e552de24 1978
d535a230 1979 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 1980
d535a230
PM		 1981 ret = cpufreq_register_notifier(&sp->freq_transition,
1982 CPUFREQ_TRANSITION_NOTIFIER);
1983 if (unlikely(ret < 0))
1984 goto err_unreg;
1da177e4
LT		 1985
1986#ifdef CONFIG_SH_STANDARD_BIOS
1987 sh_bios_gdb_detach();
1988#endif
1989
e108b2ca 1990 return 0;
7ff731ae
PM		 1991
1992err_unreg:
e552de24 1993 sci_remove(dev);
7ff731ae 1994 return ret;
1da177e4
LT		 1995}
1996
6daa79b3 1997static int sci_suspend(struct device *dev)
1da177e4 1998{
d535a230 1999 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2000
d535a230
PM		 2001 if (sport)
2002 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2003
e108b2ca
PM		 2004 return 0;
2005}
1da177e4 2006
6daa79b3 2007static int sci_resume(struct device *dev)
e108b2ca 2008{
d535a230 2009 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2010
d535a230
PM		 2011 if (sport)
2012 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2013
2014 return 0;
2015}
2016
47145210 2017static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2018 .suspend = sci_suspend,
2019 .resume = sci_resume,
2020};
2021
e108b2ca
PM		 2022static struct platform_driver sci_driver = {
2023 .probe = sci_probe,
b9e39c89 2024 .remove = sci_remove,
e108b2ca
PM		 2025 .driver = {
2026 .name = "sh-sci",
2027 .owner = THIS_MODULE,
6daa79b3 2028 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2029 },
2030};
2031
2032static int __init sci_init(void)
2033{
2034 int ret;
2035
2036 printk(banner);
2037
e108b2ca
PM		 2038 ret = uart_register_driver(&sci_uart_driver);
2039 if (likely(ret == 0)) {
2040 ret = platform_driver_register(&sci_driver);
2041 if (unlikely(ret))
2042 uart_unregister_driver(&sci_uart_driver);
2043 }
2044
2045 return ret;
2046}
2047
2048static void __exit sci_exit(void)
2049{
2050 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2051 uart_unregister_driver(&sci_uart_driver);
2052}
2053
7b6fd3bf
MD		 2054#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2055early_platform_init_buffer("earlyprintk", &sci_driver,
2056 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2057#endif
1da177e4
LT		 2058module_init(sci_init);
2059module_exit(sci_exit);
2060
e108b2ca 2061MODULE_LICENSE("GPL");
e169c139 2062MODULE_ALIAS("platform:sh-sci");
Linux kernel - Deliverables
This page took 0.67358 seconds and 5 git commands to generate.