Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/serial/sh-sci.c | |
3 | * | |
4 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
5 | * | |
7ff731ae | 6 | * Copyright (C) 2002 - 2008 Paul Mundt |
3ea6bc3d | 7 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
8 | * |
9 | * based off of the old drivers/char/sh-sci.c by: | |
10 | * | |
11 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
12 | * Copyright (C) 2000 Sugioka Toshinobu | |
13 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
14 | * Modified to support SecureEdge. David McCullough (2002) | |
15 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 16 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
17 | * |
18 | * This file is subject to the terms and conditions of the GNU General Public | |
19 | * License. See the file "COPYING" in the main directory of this archive | |
20 | * for more details. | |
21 | */ | |
0b3d4ef6 PM |
22 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
23 | #define SUPPORT_SYSRQ | |
24 | #endif | |
1da177e4 LT |
25 | |
26 | #undef DEBUG | |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/errno.h> | |
1da177e4 LT |
30 | #include <linux/timer.h> |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/tty_flip.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/major.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/sysrq.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/mm.h> | |
1da177e4 LT |
40 | #include <linux/init.h> |
41 | #include <linux/delay.h> | |
42 | #include <linux/console.h> | |
e108b2ca | 43 | #include <linux/platform_device.h> |
96de1a8f | 44 | #include <linux/serial_sci.h> |
1da177e4 LT |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpufreq.h> | |
85f094ec | 47 | #include <linux/clk.h> |
fa5da2f7 | 48 | #include <linux/ctype.h> |
7ff731ae | 49 | #include <linux/err.h> |
e552de24 | 50 | #include <linux/list.h> |
85f094ec PM |
51 | |
52 | #ifdef CONFIG_SUPERH | |
b7a76e4b | 53 | #include <asm/clock.h> |
1da177e4 LT |
54 | #include <asm/sh_bios.h> |
55 | #endif | |
56 | ||
168f3623 YS |
57 | #ifdef CONFIG_H8300 |
58 | #include <asm/gpio.h> | |
59 | #endif | |
60 | ||
1da177e4 LT |
61 | #include "sh-sci.h" |
62 | ||
e108b2ca PM |
63 | struct sci_port { |
64 | struct uart_port port; | |
65 | ||
66 | /* Port type */ | |
67 | unsigned int type; | |
68 | ||
69 | /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ | |
32351a28 | 70 | unsigned int irqs[SCIx_NR_IRQS]; |
e108b2ca | 71 | |
e108b2ca PM |
72 | /* Port enable callback */ |
73 | void (*enable)(struct uart_port *port); | |
74 | ||
75 | /* Port disable callback */ | |
76 | void (*disable)(struct uart_port *port); | |
77 | ||
78 | /* Break timer */ | |
79 | struct timer_list break_timer; | |
80 | int break_flag; | |
1534a3b3 | 81 | |
00b9de9c PM |
82 | /* SCSCR initialization */ |
83 | unsigned int scscr; | |
84 | ||
26c92f37 PM |
85 | /* SCBRR calculation algo */ |
86 | unsigned int scbrr_algo_id; | |
87 | ||
a2159b52 | 88 | #ifdef CONFIG_HAVE_CLK |
501b825d MD |
89 | /* Interface clock */ |
90 | struct clk *iclk; | |
91 | /* Data clock */ | |
92 | struct clk *dclk; | |
e552de24 MD |
93 | #endif |
94 | struct list_head node; | |
95 | }; | |
96 | ||
97 | struct sh_sci_priv { | |
98 | spinlock_t lock; | |
99 | struct list_head ports; | |
100 | ||
101 | #ifdef CONFIG_HAVE_CLK | |
102 | struct notifier_block clk_nb; | |
005a336e | 103 | #endif |
e108b2ca PM |
104 | }; |
105 | ||
1da177e4 | 106 | /* Function prototypes */ |
b129a8cc | 107 | static void sci_stop_tx(struct uart_port *port); |
1da177e4 | 108 | |
e108b2ca | 109 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 110 | |
e108b2ca PM |
111 | static struct sci_port sci_ports[SCI_NPORTS]; |
112 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 113 | |
e7c98dc7 MT |
114 | static inline struct sci_port * |
115 | to_sci_port(struct uart_port *uart) | |
116 | { | |
117 | return container_of(uart, struct sci_port, port); | |
118 | } | |
119 | ||
07d2a1a1 | 120 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
1f6fd5c9 PM |
121 | |
122 | #ifdef CONFIG_CONSOLE_POLL | |
e108b2ca PM |
123 | static inline void handle_error(struct uart_port *port) |
124 | { | |
125 | /* Clear error flags */ | |
1da177e4 LT |
126 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
127 | } | |
128 | ||
07d2a1a1 | 129 | static int sci_poll_get_char(struct uart_port *port) |
1da177e4 | 130 | { |
1da177e4 LT |
131 | unsigned short status; |
132 | int c; | |
133 | ||
e108b2ca | 134 | do { |
1da177e4 LT |
135 | status = sci_in(port, SCxSR); |
136 | if (status & SCxSR_ERRORS(port)) { | |
137 | handle_error(port); | |
138 | continue; | |
139 | } | |
140 | } while (!(status & SCxSR_RDxF(port))); | |
07d2a1a1 | 141 | |
1da177e4 | 142 | c = sci_in(port, SCxRDR); |
07d2a1a1 | 143 | |
e7c98dc7 MT |
144 | /* Dummy read */ |
145 | sci_in(port, SCxSR); | |
1da177e4 | 146 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
147 | |
148 | return c; | |
149 | } | |
1f6fd5c9 | 150 | #endif |
1da177e4 | 151 | |
07d2a1a1 | 152 | static void sci_poll_put_char(struct uart_port *port, unsigned char c) |
1da177e4 | 153 | { |
1da177e4 LT |
154 | unsigned short status; |
155 | ||
1da177e4 LT |
156 | do { |
157 | status = sci_in(port, SCxSR); | |
158 | } while (!(status & SCxSR_TDxE(port))); | |
159 | ||
272966c0 | 160 | sci_out(port, SCxTDR, c); |
dd0a3e77 | 161 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); |
1da177e4 | 162 | } |
07d2a1a1 | 163 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1da177e4 LT |
164 | |
165 | #if defined(__H8300S__) | |
166 | enum { sci_disable, sci_enable }; | |
167 | ||
e7c98dc7 | 168 | static void h8300_sci_config(struct uart_port *port, unsigned int ctrl) |
1da177e4 | 169 | { |
e7c98dc7 | 170 | volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL; |
1da177e4 LT |
171 | int ch = (port->mapbase - SMR0) >> 3; |
172 | unsigned char mask = 1 << (ch+1); | |
173 | ||
e7c98dc7 | 174 | if (ctrl == sci_disable) |
1da177e4 | 175 | *mstpcrl |= mask; |
e7c98dc7 | 176 | else |
1da177e4 | 177 | *mstpcrl &= ~mask; |
1da177e4 | 178 | } |
e108b2ca | 179 | |
501b825d | 180 | static void h8300_sci_enable(struct uart_port *port) |
e108b2ca PM |
181 | { |
182 | h8300_sci_config(port, sci_enable); | |
183 | } | |
184 | ||
501b825d | 185 | static void h8300_sci_disable(struct uart_port *port) |
e108b2ca PM |
186 | { |
187 | h8300_sci_config(port, sci_disable); | |
188 | } | |
1da177e4 LT |
189 | #endif |
190 | ||
15c73aaa | 191 | #if defined(__H8300H__) || defined(__H8300S__) |
d5701647 | 192 | static void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 LT |
193 | { |
194 | int ch = (port->mapbase - SMR0) >> 3; | |
195 | ||
196 | /* set DDR regs */ | |
e108b2ca PM |
197 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, |
198 | h8300_sci_pins[ch].rx, | |
199 | H8300_GPIO_INPUT); | |
200 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, | |
201 | h8300_sci_pins[ch].tx, | |
202 | H8300_GPIO_OUTPUT); | |
203 | ||
1da177e4 LT |
204 | /* tx mark output*/ |
205 | H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; | |
206 | } | |
d5701647 PM |
207 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
208 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) | |
e108b2ca | 209 | { |
d5701647 PM |
210 | if (port->mapbase == 0xA4400000) { |
211 | __raw_writew(__raw_readw(PACR) & 0xffc0, PACR); | |
212 | __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); | |
213 | } else if (port->mapbase == 0xA4410000) | |
214 | __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); | |
9465a54f | 215 | } |
31a49c4b | 216 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) |
d5701647 | 217 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
3ea6bc3d | 218 | { |
3ea6bc3d MB |
219 | unsigned short data; |
220 | ||
221 | if (cflag & CRTSCTS) { | |
222 | /* enable RTS/CTS */ | |
223 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
224 | /* Clear PTCR bit 9-2; enable all scif pins but sck */ | |
d5701647 PM |
225 | data = __raw_readw(PORT_PTCR); |
226 | __raw_writew((data & 0xfc03), PORT_PTCR); | |
3ea6bc3d MB |
227 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
228 | /* Clear PVCR bit 9-2 */ | |
d5701647 PM |
229 | data = __raw_readw(PORT_PVCR); |
230 | __raw_writew((data & 0xfc03), PORT_PVCR); | |
3ea6bc3d | 231 | } |
3ea6bc3d MB |
232 | } else { |
233 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
234 | /* Clear PTCR bit 5-2; enable only tx and rx */ | |
d5701647 PM |
235 | data = __raw_readw(PORT_PTCR); |
236 | __raw_writew((data & 0xffc3), PORT_PTCR); | |
3ea6bc3d MB |
237 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ |
238 | /* Clear PVCR bit 5-2 */ | |
d5701647 PM |
239 | data = __raw_readw(PORT_PVCR); |
240 | __raw_writew((data & 0xffc3), PORT_PVCR); | |
3ea6bc3d MB |
241 | } |
242 | } | |
3ea6bc3d | 243 | } |
b7a76e4b | 244 | #elif defined(CONFIG_CPU_SH3) |
e108b2ca | 245 | /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ |
d5701647 | 246 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 | 247 | { |
b7a76e4b PM |
248 | unsigned short data; |
249 | ||
250 | /* We need to set SCPCR to enable RTS/CTS */ | |
d5701647 | 251 | data = __raw_readw(SCPCR); |
b7a76e4b | 252 | /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ |
d5701647 | 253 | __raw_writew(data & 0x0fcf, SCPCR); |
1da177e4 | 254 | |
d5701647 | 255 | if (!(cflag & CRTSCTS)) { |
1da177e4 | 256 | /* We need to set SCPCR to enable RTS/CTS */ |
d5701647 | 257 | data = __raw_readw(SCPCR); |
1da177e4 LT |
258 | /* Clear out SCP7MD1,0, SCP4MD1,0, |
259 | Set SCP6MD1,0 = {01} (output) */ | |
d5701647 | 260 | __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); |
1da177e4 LT |
261 | |
262 | data = ctrl_inb(SCPDR); | |
263 | /* Set /RTS2 (bit6) = 0 */ | |
b7a76e4b | 264 | ctrl_outb(data & 0xbf, SCPDR); |
1da177e4 | 265 | } |
1da177e4 | 266 | } |
41504c39 | 267 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
d5701647 | 268 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
41504c39 | 269 | { |
346b7463 | 270 | unsigned short data; |
41504c39 | 271 | |
346b7463 | 272 | if (port->mapbase == 0xffe00000) { |
d5701647 | 273 | data = __raw_readw(PSCR); |
346b7463 | 274 | data &= ~0x03cf; |
d5701647 | 275 | if (!(cflag & CRTSCTS)) |
346b7463 | 276 | data |= 0x0340; |
41504c39 | 277 | |
d5701647 | 278 | __raw_writew(data, PSCR); |
41504c39 | 279 | } |
178dd0cd | 280 | } |
7d740a06 YS |
281 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
282 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
2b1bd1ac | 283 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
55ba99eb | 284 | defined(CONFIG_CPU_SUBTYPE_SH7786) || \ |
2b1bd1ac | 285 | defined(CONFIG_CPU_SUBTYPE_SHX3) |
d5701647 PM |
286 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
287 | { | |
288 | if (!(cflag & CRTSCTS)) | |
289 | __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */ | |
290 | } | |
b0c50ad7 | 291 | #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A) |
d5701647 PM |
292 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
293 | { | |
294 | if (!(cflag & CRTSCTS)) | |
295 | __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */ | |
296 | } | |
b7a76e4b | 297 | #else |
d5701647 PM |
298 | static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) |
299 | { | |
300 | /* Nothing to do */ | |
1da177e4 | 301 | } |
e108b2ca PM |
302 | #endif |
303 | ||
32351a28 PM |
304 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
305 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
55ba99eb KM |
306 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
307 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
e108b2ca PM |
308 | static inline int scif_txroom(struct uart_port *port) |
309 | { | |
cae167d3 | 310 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e108b2ca PM |
311 | } |
312 | ||
313 | static inline int scif_rxroom(struct uart_port *port) | |
314 | { | |
cae167d3 | 315 | return sci_in(port, SCRFDR) & 0xff; |
e108b2ca | 316 | } |
c63847a3 NI |
317 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
318 | static inline int scif_txroom(struct uart_port *port) | |
319 | { | |
e7c98dc7 MT |
320 | if ((port->mapbase == 0xffe00000) || |
321 | (port->mapbase == 0xffe08000)) { | |
322 | /* SCIF0/1*/ | |
c63847a3 | 323 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e7c98dc7 MT |
324 | } else { |
325 | /* SCIF2 */ | |
c63847a3 | 326 | return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); |
e7c98dc7 | 327 | } |
c63847a3 NI |
328 | } |
329 | ||
330 | static inline int scif_rxroom(struct uart_port *port) | |
331 | { | |
e7c98dc7 MT |
332 | if ((port->mapbase == 0xffe00000) || |
333 | (port->mapbase == 0xffe08000)) { | |
334 | /* SCIF0/1*/ | |
c63847a3 | 335 | return sci_in(port, SCRFDR) & 0xff; |
e7c98dc7 MT |
336 | } else { |
337 | /* SCIF2 */ | |
c63847a3 | 338 | return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; |
e7c98dc7 | 339 | } |
c63847a3 | 340 | } |
e108b2ca PM |
341 | #else |
342 | static inline int scif_txroom(struct uart_port *port) | |
343 | { | |
344 | return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); | |
345 | } | |
1da177e4 | 346 | |
e108b2ca PM |
347 | static inline int scif_rxroom(struct uart_port *port) |
348 | { | |
349 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
350 | } | |
1da177e4 | 351 | #endif |
1da177e4 | 352 | |
e108b2ca PM |
353 | static inline int sci_txroom(struct uart_port *port) |
354 | { | |
e7c98dc7 | 355 | return (sci_in(port, SCxSR) & SCI_TDRE) != 0; |
e108b2ca PM |
356 | } |
357 | ||
358 | static inline int sci_rxroom(struct uart_port *port) | |
359 | { | |
e7c98dc7 | 360 | return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
361 | } |
362 | ||
1da177e4 LT |
363 | /* ********************************************************************** * |
364 | * the interrupt related routines * | |
365 | * ********************************************************************** */ | |
366 | ||
367 | static void sci_transmit_chars(struct uart_port *port) | |
368 | { | |
369 | struct circ_buf *xmit = &port->info->xmit; | |
370 | unsigned int stopped = uart_tx_stopped(port); | |
1da177e4 LT |
371 | unsigned short status; |
372 | unsigned short ctrl; | |
e108b2ca | 373 | int count; |
1da177e4 LT |
374 | |
375 | status = sci_in(port, SCxSR); | |
376 | if (!(status & SCxSR_TDxE(port))) { | |
1da177e4 | 377 | ctrl = sci_in(port, SCSCR); |
e7c98dc7 | 378 | if (uart_circ_empty(xmit)) |
8e698614 | 379 | ctrl &= ~SCSCR_TIE; |
e7c98dc7 | 380 | else |
8e698614 | 381 | ctrl |= SCSCR_TIE; |
1da177e4 | 382 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
383 | return; |
384 | } | |
385 | ||
1a22f08d | 386 | if (port->type == PORT_SCI) |
e108b2ca | 387 | count = sci_txroom(port); |
1a22f08d YS |
388 | else |
389 | count = scif_txroom(port); | |
1da177e4 LT |
390 | |
391 | do { | |
392 | unsigned char c; | |
393 | ||
394 | if (port->x_char) { | |
395 | c = port->x_char; | |
396 | port->x_char = 0; | |
397 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
398 | c = xmit->buf[xmit->tail]; | |
399 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
400 | } else { | |
401 | break; | |
402 | } | |
403 | ||
404 | sci_out(port, SCxTDR, c); | |
405 | ||
406 | port->icount.tx++; | |
407 | } while (--count > 0); | |
408 | ||
409 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
410 | ||
411 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
412 | uart_write_wakeup(port); | |
413 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 414 | sci_stop_tx(port); |
1da177e4 | 415 | } else { |
1da177e4 LT |
416 | ctrl = sci_in(port, SCSCR); |
417 | ||
1a22f08d | 418 | if (port->type != PORT_SCI) { |
1da177e4 LT |
419 | sci_in(port, SCxSR); /* Dummy read */ |
420 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
421 | } | |
1da177e4 | 422 | |
8e698614 | 423 | ctrl |= SCSCR_TIE; |
1da177e4 | 424 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
425 | } |
426 | } | |
427 | ||
428 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 429 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 430 | |
7d12e780 | 431 | static inline void sci_receive_chars(struct uart_port *port) |
1da177e4 | 432 | { |
e7c98dc7 | 433 | struct sci_port *sci_port = to_sci_port(port); |
a88487c7 | 434 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
435 | int i, count, copied = 0; |
436 | unsigned short status; | |
33f0f88f | 437 | unsigned char flag; |
1da177e4 LT |
438 | |
439 | status = sci_in(port, SCxSR); | |
440 | if (!(status & SCxSR_RDxF(port))) | |
441 | return; | |
442 | ||
443 | while (1) { | |
1a22f08d | 444 | if (port->type == PORT_SCI) |
e108b2ca | 445 | count = sci_rxroom(port); |
1a22f08d YS |
446 | else |
447 | count = scif_rxroom(port); | |
1da177e4 LT |
448 | |
449 | /* Don't copy more bytes than there is room for in the buffer */ | |
33f0f88f | 450 | count = tty_buffer_request_room(tty, count); |
1da177e4 LT |
451 | |
452 | /* If for any reason we can't copy more data, we're done! */ | |
453 | if (count == 0) | |
454 | break; | |
455 | ||
456 | if (port->type == PORT_SCI) { | |
457 | char c = sci_in(port, SCxRDR); | |
e7c98dc7 MT |
458 | if (uart_handle_sysrq_char(port, c) || |
459 | sci_port->break_flag) | |
1da177e4 | 460 | count = 0; |
e7c98dc7 | 461 | else |
e108b2ca | 462 | tty_insert_flip_char(tty, c, TTY_NORMAL); |
1da177e4 | 463 | } else { |
e7c98dc7 | 464 | for (i = 0; i < count; i++) { |
1da177e4 LT |
465 | char c = sci_in(port, SCxRDR); |
466 | status = sci_in(port, SCxSR); | |
467 | #if defined(CONFIG_CPU_SH3) | |
468 | /* Skip "chars" during break */ | |
e108b2ca | 469 | if (sci_port->break_flag) { |
1da177e4 LT |
470 | if ((c == 0) && |
471 | (status & SCxSR_FER(port))) { | |
472 | count--; i--; | |
473 | continue; | |
474 | } | |
e108b2ca | 475 | |
1da177e4 | 476 | /* Nonzero => end-of-break */ |
762c69e3 | 477 | dev_dbg(port->dev, "debounce<%02x>\n", c); |
e108b2ca PM |
478 | sci_port->break_flag = 0; |
479 | ||
1da177e4 LT |
480 | if (STEPFN(c)) { |
481 | count--; i--; | |
482 | continue; | |
483 | } | |
484 | } | |
485 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 486 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
487 | count--; i--; |
488 | continue; | |
489 | } | |
490 | ||
491 | /* Store data and status */ | |
1da177e4 | 492 | if (status&SCxSR_FER(port)) { |
33f0f88f | 493 | flag = TTY_FRAME; |
762c69e3 | 494 | dev_notice(port->dev, "frame error\n"); |
1da177e4 | 495 | } else if (status&SCxSR_PER(port)) { |
33f0f88f | 496 | flag = TTY_PARITY; |
762c69e3 | 497 | dev_notice(port->dev, "parity error\n"); |
33f0f88f AC |
498 | } else |
499 | flag = TTY_NORMAL; | |
762c69e3 | 500 | |
33f0f88f | 501 | tty_insert_flip_char(tty, c, flag); |
1da177e4 LT |
502 | } |
503 | } | |
504 | ||
505 | sci_in(port, SCxSR); /* dummy read */ | |
506 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
507 | ||
1da177e4 LT |
508 | copied += count; |
509 | port->icount.rx += count; | |
510 | } | |
511 | ||
512 | if (copied) { | |
513 | /* Tell the rest of the system the news. New characters! */ | |
514 | tty_flip_buffer_push(tty); | |
515 | } else { | |
516 | sci_in(port, SCxSR); /* dummy read */ | |
517 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
518 | } | |
519 | } | |
520 | ||
521 | #define SCI_BREAK_JIFFIES (HZ/20) | |
522 | /* The sci generates interrupts during the break, | |
523 | * 1 per millisecond or so during the break period, for 9600 baud. | |
524 | * So dont bother disabling interrupts. | |
525 | * But dont want more than 1 break event. | |
526 | * Use a kernel timer to periodically poll the rx line until | |
527 | * the break is finished. | |
528 | */ | |
529 | static void sci_schedule_break_timer(struct sci_port *port) | |
530 | { | |
531 | port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES; | |
532 | add_timer(&port->break_timer); | |
533 | } | |
534 | /* Ensure that two consecutive samples find the break over. */ | |
535 | static void sci_break_timer(unsigned long data) | |
536 | { | |
e108b2ca PM |
537 | struct sci_port *port = (struct sci_port *)data; |
538 | ||
539 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 540 | port->break_flag = 1; |
e108b2ca PM |
541 | sci_schedule_break_timer(port); |
542 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
543 | /* break is over. */ |
544 | port->break_flag = 2; | |
e108b2ca PM |
545 | sci_schedule_break_timer(port); |
546 | } else | |
547 | port->break_flag = 0; | |
1da177e4 LT |
548 | } |
549 | ||
550 | static inline int sci_handle_errors(struct uart_port *port) | |
551 | { | |
552 | int copied = 0; | |
553 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 554 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 | 555 | |
e108b2ca | 556 | if (status & SCxSR_ORER(port)) { |
1da177e4 | 557 | /* overrun error */ |
e108b2ca | 558 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) |
33f0f88f | 559 | copied++; |
762c69e3 PM |
560 | |
561 | dev_notice(port->dev, "overrun error"); | |
1da177e4 LT |
562 | } |
563 | ||
e108b2ca | 564 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
565 | if (sci_rxd_in(port) == 0) { |
566 | /* Notify of BREAK */ | |
e7c98dc7 | 567 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
568 | |
569 | if (!sci_port->break_flag) { | |
570 | sci_port->break_flag = 1; | |
571 | sci_schedule_break_timer(sci_port); | |
572 | ||
1da177e4 | 573 | /* Do sysrq handling. */ |
e108b2ca | 574 | if (uart_handle_break(port)) |
1da177e4 | 575 | return 0; |
762c69e3 PM |
576 | |
577 | dev_dbg(port->dev, "BREAK detected\n"); | |
578 | ||
e108b2ca | 579 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
e7c98dc7 MT |
580 | copied++; |
581 | } | |
582 | ||
e108b2ca | 583 | } else { |
1da177e4 | 584 | /* frame error */ |
e108b2ca | 585 | if (tty_insert_flip_char(tty, 0, TTY_FRAME)) |
33f0f88f | 586 | copied++; |
762c69e3 PM |
587 | |
588 | dev_notice(port->dev, "frame error\n"); | |
1da177e4 LT |
589 | } |
590 | } | |
591 | ||
e108b2ca | 592 | if (status & SCxSR_PER(port)) { |
1da177e4 | 593 | /* parity error */ |
e108b2ca PM |
594 | if (tty_insert_flip_char(tty, 0, TTY_PARITY)) |
595 | copied++; | |
762c69e3 PM |
596 | |
597 | dev_notice(port->dev, "parity error"); | |
1da177e4 LT |
598 | } |
599 | ||
33f0f88f | 600 | if (copied) |
1da177e4 | 601 | tty_flip_buffer_push(tty); |
1da177e4 LT |
602 | |
603 | return copied; | |
604 | } | |
605 | ||
d830fa45 PM |
606 | static inline int sci_handle_fifo_overrun(struct uart_port *port) |
607 | { | |
608 | struct tty_struct *tty = port->info->port.tty; | |
609 | int copied = 0; | |
610 | ||
611 | if (port->type != PORT_SCIF) | |
612 | return 0; | |
613 | ||
614 | if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { | |
615 | sci_out(port, SCLSR, 0); | |
616 | ||
617 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
618 | tty_flip_buffer_push(tty); | |
619 | ||
620 | dev_notice(port->dev, "overrun error\n"); | |
621 | copied++; | |
622 | } | |
623 | ||
624 | return copied; | |
625 | } | |
626 | ||
1da177e4 LT |
627 | static inline int sci_handle_breaks(struct uart_port *port) |
628 | { | |
629 | int copied = 0; | |
630 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 631 | struct tty_struct *tty = port->info->port.tty; |
a5660ada | 632 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 633 | |
0b3d4ef6 PM |
634 | if (uart_handle_break(port)) |
635 | return 0; | |
636 | ||
b7a76e4b | 637 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
638 | #if defined(CONFIG_CPU_SH3) |
639 | /* Debounce break */ | |
640 | s->break_flag = 1; | |
641 | #endif | |
642 | /* Notify of BREAK */ | |
e108b2ca | 643 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
33f0f88f | 644 | copied++; |
762c69e3 PM |
645 | |
646 | dev_dbg(port->dev, "BREAK detected\n"); | |
1da177e4 LT |
647 | } |
648 | ||
33f0f88f | 649 | if (copied) |
1da177e4 | 650 | tty_flip_buffer_push(tty); |
e108b2ca | 651 | |
d830fa45 PM |
652 | copied += sci_handle_fifo_overrun(port); |
653 | ||
1da177e4 LT |
654 | return copied; |
655 | } | |
656 | ||
7d12e780 | 657 | static irqreturn_t sci_rx_interrupt(int irq, void *port) |
1da177e4 | 658 | { |
1da177e4 LT |
659 | /* I think sci_receive_chars has to be called irrespective |
660 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
661 | * to be disabled? | |
662 | */ | |
7d12e780 | 663 | sci_receive_chars(port); |
1da177e4 LT |
664 | |
665 | return IRQ_HANDLED; | |
666 | } | |
667 | ||
7d12e780 | 668 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
669 | { |
670 | struct uart_port *port = ptr; | |
671 | ||
e108b2ca | 672 | spin_lock_irq(&port->lock); |
1da177e4 | 673 | sci_transmit_chars(port); |
e108b2ca | 674 | spin_unlock_irq(&port->lock); |
1da177e4 LT |
675 | |
676 | return IRQ_HANDLED; | |
677 | } | |
678 | ||
7d12e780 | 679 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
680 | { |
681 | struct uart_port *port = ptr; | |
682 | ||
683 | /* Handle errors */ | |
684 | if (port->type == PORT_SCI) { | |
685 | if (sci_handle_errors(port)) { | |
686 | /* discard character in rx buffer */ | |
687 | sci_in(port, SCxSR); | |
688 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
689 | } | |
690 | } else { | |
d830fa45 | 691 | sci_handle_fifo_overrun(port); |
7d12e780 | 692 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
693 | } |
694 | ||
695 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); | |
696 | ||
697 | /* Kick the transmission */ | |
7d12e780 | 698 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
699 | |
700 | return IRQ_HANDLED; | |
701 | } | |
702 | ||
7d12e780 | 703 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
704 | { |
705 | struct uart_port *port = ptr; | |
706 | ||
707 | /* Handle BREAKs */ | |
708 | sci_handle_breaks(port); | |
709 | sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); | |
710 | ||
711 | return IRQ_HANDLED; | |
712 | } | |
713 | ||
7d12e780 | 714 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 | 715 | { |
a8884e34 MT |
716 | unsigned short ssr_status, scr_status; |
717 | struct uart_port *port = ptr; | |
718 | irqreturn_t ret = IRQ_NONE; | |
1da177e4 | 719 | |
e7c98dc7 MT |
720 | ssr_status = sci_in(port, SCxSR); |
721 | scr_status = sci_in(port, SCSCR); | |
1da177e4 LT |
722 | |
723 | /* Tx Interrupt */ | |
8e698614 | 724 | if ((ssr_status & 0x0020) && (scr_status & SCSCR_TIE)) |
a8884e34 | 725 | ret = sci_tx_interrupt(irq, ptr); |
1da177e4 | 726 | /* Rx Interrupt */ |
8e698614 | 727 | if ((ssr_status & 0x0002) && (scr_status & SCSCR_RIE)) |
a8884e34 | 728 | ret = sci_rx_interrupt(irq, ptr); |
1da177e4 | 729 | /* Error Interrupt */ |
8e698614 | 730 | if ((ssr_status & 0x0080) && (scr_status & SCSCR_REIE)) |
a8884e34 | 731 | ret = sci_er_interrupt(irq, ptr); |
1da177e4 | 732 | /* Break Interrupt */ |
8e698614 | 733 | if ((ssr_status & 0x0010) && (scr_status & SCSCR_REIE)) |
a8884e34 | 734 | ret = sci_br_interrupt(irq, ptr); |
1da177e4 | 735 | |
a8884e34 | 736 | return ret; |
1da177e4 LT |
737 | } |
738 | ||
027e6872 | 739 | #ifdef CONFIG_HAVE_CLK |
1da177e4 LT |
740 | /* |
741 | * Here we define a transistion notifier so that we can update all of our | |
742 | * ports' baud rate when the peripheral clock changes. | |
743 | */ | |
e108b2ca PM |
744 | static int sci_notifier(struct notifier_block *self, |
745 | unsigned long phase, void *p) | |
1da177e4 | 746 | { |
e552de24 MD |
747 | struct sh_sci_priv *priv = container_of(self, |
748 | struct sh_sci_priv, clk_nb); | |
749 | struct sci_port *sci_port; | |
750 | unsigned long flags; | |
1da177e4 LT |
751 | |
752 | if ((phase == CPUFREQ_POSTCHANGE) || | |
e552de24 MD |
753 | (phase == CPUFREQ_RESUMECHANGE)) { |
754 | spin_lock_irqsave(&priv->lock, flags); | |
755 | list_for_each_entry(sci_port, &priv->ports, node) | |
501b825d | 756 | sci_port->port.uartclk = clk_get_rate(sci_port->dclk); |
e552de24 MD |
757 | |
758 | spin_unlock_irqrestore(&priv->lock, flags); | |
759 | } | |
1da177e4 | 760 | |
1da177e4 LT |
761 | return NOTIFY_OK; |
762 | } | |
501b825d MD |
763 | |
764 | static void sci_clk_enable(struct uart_port *port) | |
765 | { | |
766 | struct sci_port *sci_port = to_sci_port(port); | |
767 | ||
768 | clk_enable(sci_port->dclk); | |
769 | sci_port->port.uartclk = clk_get_rate(sci_port->dclk); | |
770 | ||
771 | if (sci_port->iclk) | |
772 | clk_enable(sci_port->iclk); | |
773 | } | |
774 | ||
775 | static void sci_clk_disable(struct uart_port *port) | |
776 | { | |
777 | struct sci_port *sci_port = to_sci_port(port); | |
778 | ||
779 | if (sci_port->iclk) | |
780 | clk_disable(sci_port->iclk); | |
781 | ||
782 | clk_disable(sci_port->dclk); | |
783 | } | |
027e6872 | 784 | #endif |
1da177e4 LT |
785 | |
786 | static int sci_request_irq(struct sci_port *port) | |
787 | { | |
788 | int i; | |
7d12e780 | 789 | irqreturn_t (*handlers[4])(int irq, void *ptr) = { |
1da177e4 LT |
790 | sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, |
791 | sci_br_interrupt, | |
792 | }; | |
793 | const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", | |
794 | "SCI Transmit Data Empty", "SCI Break" }; | |
795 | ||
796 | if (port->irqs[0] == port->irqs[1]) { | |
762c69e3 | 797 | if (unlikely(!port->irqs[0])) |
1da177e4 | 798 | return -ENODEV; |
e108b2ca PM |
799 | |
800 | if (request_irq(port->irqs[0], sci_mpxed_interrupt, | |
35f3c518 | 801 | IRQF_DISABLED, "sci", port)) { |
762c69e3 | 802 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
803 | return -ENODEV; |
804 | } | |
805 | } else { | |
806 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { | |
762c69e3 | 807 | if (unlikely(!port->irqs[i])) |
1da177e4 | 808 | continue; |
762c69e3 | 809 | |
e108b2ca | 810 | if (request_irq(port->irqs[i], handlers[i], |
35f3c518 | 811 | IRQF_DISABLED, desc[i], port)) { |
762c69e3 | 812 | dev_err(port->port.dev, "Can't allocate IRQ\n"); |
1da177e4 LT |
813 | return -ENODEV; |
814 | } | |
815 | } | |
816 | } | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
821 | static void sci_free_irq(struct sci_port *port) | |
822 | { | |
823 | int i; | |
824 | ||
762c69e3 PM |
825 | if (port->irqs[0] == port->irqs[1]) |
826 | free_irq(port->irqs[0], port); | |
827 | else { | |
1da177e4 LT |
828 | for (i = 0; i < ARRAY_SIZE(port->irqs); i++) { |
829 | if (!port->irqs[i]) | |
830 | continue; | |
831 | ||
832 | free_irq(port->irqs[i], port); | |
833 | } | |
834 | } | |
835 | } | |
836 | ||
837 | static unsigned int sci_tx_empty(struct uart_port *port) | |
838 | { | |
839 | /* Can't detect */ | |
840 | return TIOCSER_TEMT; | |
841 | } | |
842 | ||
843 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
844 | { | |
845 | /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ | |
846 | /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ | |
847 | /* If you have signals for DTR and DCD, please implement here. */ | |
848 | } | |
849 | ||
850 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
851 | { | |
852 | /* This routine is used for geting signals of: DTR, DCD, DSR, RI, | |
853 | and CTS/RTS */ | |
854 | ||
855 | return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; | |
856 | } | |
857 | ||
b129a8cc | 858 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 859 | { |
e108b2ca | 860 | unsigned short ctrl; |
1da177e4 | 861 | |
e108b2ca PM |
862 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
863 | ctrl = sci_in(port, SCSCR); | |
8e698614 | 864 | ctrl |= SCSCR_TIE; |
e108b2ca | 865 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
866 | } |
867 | ||
b129a8cc | 868 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 869 | { |
1da177e4 LT |
870 | unsigned short ctrl; |
871 | ||
872 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
1da177e4 | 873 | ctrl = sci_in(port, SCSCR); |
8e698614 | 874 | ctrl &= ~SCSCR_TIE; |
1da177e4 | 875 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
876 | } |
877 | ||
878 | static void sci_start_rx(struct uart_port *port, unsigned int tty_start) | |
879 | { | |
1da177e4 LT |
880 | unsigned short ctrl; |
881 | ||
882 | /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 | 883 | ctrl = sci_in(port, SCSCR); |
8e698614 | 884 | ctrl |= SCSCR_RIE | SCSCR_REIE; |
1da177e4 | 885 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
886 | } |
887 | ||
888 | static void sci_stop_rx(struct uart_port *port) | |
889 | { | |
1da177e4 LT |
890 | unsigned short ctrl; |
891 | ||
892 | /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 | 893 | ctrl = sci_in(port, SCSCR); |
8e698614 | 894 | ctrl &= ~(SCSCR_RIE | SCSCR_REIE); |
1da177e4 | 895 | sci_out(port, SCSCR, ctrl); |
1da177e4 LT |
896 | } |
897 | ||
898 | static void sci_enable_ms(struct uart_port *port) | |
899 | { | |
900 | /* Nothing here yet .. */ | |
901 | } | |
902 | ||
903 | static void sci_break_ctl(struct uart_port *port, int break_state) | |
904 | { | |
905 | /* Nothing here yet .. */ | |
906 | } | |
907 | ||
908 | static int sci_startup(struct uart_port *port) | |
909 | { | |
a5660ada | 910 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 911 | |
e108b2ca PM |
912 | if (s->enable) |
913 | s->enable(port); | |
1da177e4 LT |
914 | |
915 | sci_request_irq(s); | |
d656901b | 916 | sci_start_tx(port); |
1da177e4 LT |
917 | sci_start_rx(port, 1); |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
922 | static void sci_shutdown(struct uart_port *port) | |
923 | { | |
a5660ada | 924 | struct sci_port *s = to_sci_port(port); |
1da177e4 LT |
925 | |
926 | sci_stop_rx(port); | |
b129a8cc | 927 | sci_stop_tx(port); |
1da177e4 LT |
928 | sci_free_irq(s); |
929 | ||
e108b2ca PM |
930 | if (s->disable) |
931 | s->disable(port); | |
1da177e4 LT |
932 | } |
933 | ||
26c92f37 PM |
934 | static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, |
935 | unsigned long freq) | |
936 | { | |
937 | switch (algo_id) { | |
938 | case SCBRR_ALGO_1: | |
939 | return ((freq + 16 * bps) / (16 * bps) - 1); | |
940 | case SCBRR_ALGO_2: | |
941 | return ((freq + 16 * bps) / (32 * bps) - 1); | |
942 | case SCBRR_ALGO_3: | |
943 | return (((freq * 2) + 16 * bps) / (16 * bps) - 1); | |
944 | case SCBRR_ALGO_4: | |
945 | return (((freq * 2) + 16 * bps) / (32 * bps) - 1); | |
946 | case SCBRR_ALGO_5: | |
947 | return (((freq * 1000 / 32) / bps) - 1); | |
948 | } | |
949 | ||
950 | /* Warn, but use a safe default */ | |
951 | WARN_ON(1); | |
952 | return ((freq + 16 * bps) / (32 * bps) - 1); | |
953 | } | |
954 | ||
606d099c AC |
955 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
956 | struct ktermios *old) | |
1da177e4 | 957 | { |
00b9de9c | 958 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 959 | unsigned int status, baud, smr_val; |
a2159b52 | 960 | int t = -1; |
1da177e4 LT |
961 | |
962 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
a2159b52 | 963 | if (likely(baud)) |
26c92f37 | 964 | t = sci_scbrr_calc(s->scbrr_algo_id, baud, port->uartclk); |
e108b2ca | 965 | |
1da177e4 LT |
966 | do { |
967 | status = sci_in(port, SCxSR); | |
968 | } while (!(status & SCxSR_TEND(port))); | |
969 | ||
970 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ | |
971 | ||
1a22f08d | 972 | if (port->type != PORT_SCI) |
1da177e4 | 973 | sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); |
1da177e4 LT |
974 | |
975 | smr_val = sci_in(port, SCSMR) & 3; | |
976 | if ((termios->c_cflag & CSIZE) == CS7) | |
977 | smr_val |= 0x40; | |
978 | if (termios->c_cflag & PARENB) | |
979 | smr_val |= 0x20; | |
980 | if (termios->c_cflag & PARODD) | |
981 | smr_val |= 0x30; | |
982 | if (termios->c_cflag & CSTOPB) | |
983 | smr_val |= 0x08; | |
984 | ||
985 | uart_update_timeout(port, termios->c_cflag, baud); | |
986 | ||
987 | sci_out(port, SCSMR, smr_val); | |
988 | ||
1da177e4 | 989 | if (t > 0) { |
e7c98dc7 | 990 | if (t >= 256) { |
1da177e4 LT |
991 | sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); |
992 | t >>= 2; | |
e7c98dc7 | 993 | } else |
1da177e4 | 994 | sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); |
e7c98dc7 | 995 | |
1da177e4 LT |
996 | sci_out(port, SCBRR, t); |
997 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ | |
998 | } | |
999 | ||
d5701647 PM |
1000 | sci_init_pins(port, termios->c_cflag); |
1001 | sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0); | |
b7a76e4b | 1002 | |
00b9de9c | 1003 | sci_out(port, SCSCR, s->scscr); |
1da177e4 LT |
1004 | |
1005 | if ((termios->c_cflag & CREAD) != 0) | |
e7c98dc7 | 1006 | sci_start_rx(port, 0); |
1da177e4 LT |
1007 | } |
1008 | ||
1009 | static const char *sci_type(struct uart_port *port) | |
1010 | { | |
1011 | switch (port->type) { | |
e7c98dc7 MT |
1012 | case PORT_IRDA: |
1013 | return "irda"; | |
1014 | case PORT_SCI: | |
1015 | return "sci"; | |
1016 | case PORT_SCIF: | |
1017 | return "scif"; | |
1018 | case PORT_SCIFA: | |
1019 | return "scifa"; | |
1da177e4 LT |
1020 | } |
1021 | ||
fa43972f | 1022 | return NULL; |
1da177e4 LT |
1023 | } |
1024 | ||
1025 | static void sci_release_port(struct uart_port *port) | |
1026 | { | |
1027 | /* Nothing here yet .. */ | |
1028 | } | |
1029 | ||
1030 | static int sci_request_port(struct uart_port *port) | |
1031 | { | |
1032 | /* Nothing here yet .. */ | |
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | static void sci_config_port(struct uart_port *port, int flags) | |
1037 | { | |
a5660ada | 1038 | struct sci_port *s = to_sci_port(port); |
1da177e4 LT |
1039 | |
1040 | port->type = s->type; | |
1041 | ||
08f8cb31 MD |
1042 | if (port->membase) |
1043 | return; | |
1044 | ||
1045 | if (port->flags & UPF_IOREMAP) { | |
7ff731ae | 1046 | port->membase = ioremap_nocache(port->mapbase, 0x40); |
08f8cb31 MD |
1047 | |
1048 | if (IS_ERR(port->membase)) | |
1049 | dev_err(port->dev, "can't remap port#%d\n", port->line); | |
1050 | } else { | |
1051 | /* | |
1052 | * For the simple (and majority of) cases where we don't | |
1053 | * need to do any remapping, just cast the cookie | |
1054 | * directly. | |
1055 | */ | |
1056 | port->membase = (void __iomem *)port->mapbase; | |
7ff731ae | 1057 | } |
1da177e4 LT |
1058 | } |
1059 | ||
1060 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1061 | { | |
a5660ada | 1062 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1063 | |
a62c4133 | 1064 | if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) |
1da177e4 LT |
1065 | return -EINVAL; |
1066 | if (ser->baud_base < 2400) | |
1067 | /* No paper tape reader for Mitch.. */ | |
1068 | return -EINVAL; | |
1069 | ||
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | static struct uart_ops sci_uart_ops = { | |
1074 | .tx_empty = sci_tx_empty, | |
1075 | .set_mctrl = sci_set_mctrl, | |
1076 | .get_mctrl = sci_get_mctrl, | |
1077 | .start_tx = sci_start_tx, | |
1078 | .stop_tx = sci_stop_tx, | |
1079 | .stop_rx = sci_stop_rx, | |
1080 | .enable_ms = sci_enable_ms, | |
1081 | .break_ctl = sci_break_ctl, | |
1082 | .startup = sci_startup, | |
1083 | .shutdown = sci_shutdown, | |
1084 | .set_termios = sci_set_termios, | |
1085 | .type = sci_type, | |
1086 | .release_port = sci_release_port, | |
1087 | .request_port = sci_request_port, | |
1088 | .config_port = sci_config_port, | |
1089 | .verify_port = sci_verify_port, | |
07d2a1a1 PM |
1090 | #ifdef CONFIG_CONSOLE_POLL |
1091 | .poll_get_char = sci_poll_get_char, | |
1092 | .poll_put_char = sci_poll_put_char, | |
1093 | #endif | |
1da177e4 LT |
1094 | }; |
1095 | ||
501b825d MD |
1096 | static void __devinit sci_init_single(struct platform_device *dev, |
1097 | struct sci_port *sci_port, | |
08f8cb31 MD |
1098 | unsigned int index, |
1099 | struct plat_sci_port *p) | |
e108b2ca | 1100 | { |
7ed7e071 MD |
1101 | sci_port->port.ops = &sci_uart_ops; |
1102 | sci_port->port.iotype = UPIO_MEM; | |
1103 | sci_port->port.line = index; | |
1104 | sci_port->port.fifosize = 1; | |
e108b2ca PM |
1105 | |
1106 | #if defined(__H8300H__) || defined(__H8300S__) | |
1107 | #ifdef __H8300S__ | |
7ed7e071 MD |
1108 | sci_port->enable = h8300_sci_enable; |
1109 | sci_port->disable = h8300_sci_disable; | |
e108b2ca | 1110 | #endif |
7ed7e071 | 1111 | sci_port->port.uartclk = CONFIG_CPU_CLOCK; |
a2159b52 | 1112 | #elif defined(CONFIG_HAVE_CLK) |
501b825d | 1113 | sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL; |
af777ce4 | 1114 | sci_port->dclk = clk_get(&dev->dev, "peripheral_clk"); |
501b825d MD |
1115 | sci_port->enable = sci_clk_enable; |
1116 | sci_port->disable = sci_clk_disable; | |
a2159b52 PM |
1117 | #else |
1118 | #error "Need a valid uartclk" | |
1da177e4 | 1119 | #endif |
e108b2ca | 1120 | |
7ed7e071 MD |
1121 | sci_port->break_timer.data = (unsigned long)sci_port; |
1122 | sci_port->break_timer.function = sci_break_timer; | |
1123 | init_timer(&sci_port->break_timer); | |
1124 | ||
1125 | sci_port->port.mapbase = p->mapbase; | |
7ed7e071 MD |
1126 | sci_port->port.membase = p->membase; |
1127 | ||
00b9de9c | 1128 | sci_port->scscr = p->scscr; |
7ed7e071 MD |
1129 | sci_port->port.irq = p->irqs[SCIx_TXI_IRQ]; |
1130 | sci_port->port.flags = p->flags; | |
501b825d | 1131 | sci_port->port.dev = &dev->dev; |
7ed7e071 MD |
1132 | sci_port->type = sci_port->port.type = p->type; |
1133 | ||
1134 | memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs)); | |
e108b2ca PM |
1135 | } |
1136 | ||
1da177e4 | 1137 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
dc8e6f5b MD |
1138 | static struct tty_driver *serial_console_device(struct console *co, int *index) |
1139 | { | |
1140 | struct uart_driver *p = &sci_uart_driver; | |
1141 | *index = co->index; | |
1142 | return p->tty_driver; | |
1143 | } | |
1144 | ||
1145 | static void serial_console_putchar(struct uart_port *port, int ch) | |
1146 | { | |
1147 | sci_poll_put_char(port, ch); | |
1148 | } | |
1149 | ||
1da177e4 LT |
1150 | /* |
1151 | * Print a string to the serial port trying not to disturb | |
1152 | * any possible real use of the port... | |
1153 | */ | |
1154 | static void serial_console_write(struct console *co, const char *s, | |
1155 | unsigned count) | |
1156 | { | |
dc8e6f5b | 1157 | struct uart_port *port = co->data; |
501b825d | 1158 | struct sci_port *sci_port = to_sci_port(port); |
973e5d52 | 1159 | unsigned short bits; |
07d2a1a1 | 1160 | |
501b825d MD |
1161 | if (sci_port->enable) |
1162 | sci_port->enable(port); | |
1163 | ||
1164 | uart_console_write(port, s, count, serial_console_putchar); | |
973e5d52 MD |
1165 | |
1166 | /* wait until fifo is empty and last bit has been transmitted */ | |
1167 | bits = SCxSR_TDxE(port) | SCxSR_TEND(port); | |
1168 | while ((sci_in(port, SCxSR) & bits) != bits) | |
1169 | cpu_relax(); | |
501b825d MD |
1170 | |
1171 | if (sci_port->disable); | |
1172 | sci_port->disable(port); | |
1da177e4 LT |
1173 | } |
1174 | ||
1175 | static int __init serial_console_setup(struct console *co, char *options) | |
1176 | { | |
dc8e6f5b | 1177 | struct sci_port *sci_port; |
1da177e4 LT |
1178 | struct uart_port *port; |
1179 | int baud = 115200; | |
1180 | int bits = 8; | |
1181 | int parity = 'n'; | |
1182 | int flow = 'n'; | |
1183 | int ret; | |
1184 | ||
e108b2ca PM |
1185 | /* |
1186 | * Check whether an invalid uart number has been specified, and | |
1187 | * if so, search for the first available port that does have | |
1188 | * console support. | |
1189 | */ | |
1190 | if (co->index >= SCI_NPORTS) | |
1191 | co->index = 0; | |
1192 | ||
dc8e6f5b MD |
1193 | sci_port = &sci_ports[co->index]; |
1194 | port = &sci_port->port; | |
1195 | co->data = port; | |
1da177e4 LT |
1196 | |
1197 | /* | |
e108b2ca PM |
1198 | * Also need to check port->type, we don't actually have any |
1199 | * UPIO_PORT ports, but uart_report_port() handily misreports | |
1200 | * it anyways if we don't have a port available by the time this is | |
1201 | * called. | |
1da177e4 | 1202 | */ |
e108b2ca PM |
1203 | if (!port->type) |
1204 | return -ENODEV; | |
e108b2ca | 1205 | |
08f8cb31 | 1206 | sci_config_port(port, 0); |
e108b2ca | 1207 | |
dc8e6f5b MD |
1208 | if (sci_port->enable) |
1209 | sci_port->enable(port); | |
b7a76e4b | 1210 | |
1da177e4 LT |
1211 | if (options) |
1212 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1213 | ||
1214 | ret = uart_set_options(port, co, baud, parity, bits, flow); | |
1215 | #if defined(__H8300H__) || defined(__H8300S__) | |
1216 | /* disable rx interrupt */ | |
1217 | if (ret == 0) | |
1218 | sci_stop_rx(port); | |
1219 | #endif | |
501b825d | 1220 | /* TODO: disable clock */ |
1da177e4 LT |
1221 | return ret; |
1222 | } | |
1223 | ||
1224 | static struct console serial_console = { | |
1225 | .name = "ttySC", | |
dc8e6f5b | 1226 | .device = serial_console_device, |
1da177e4 LT |
1227 | .write = serial_console_write, |
1228 | .setup = serial_console_setup, | |
fa5da2f7 | 1229 | .flags = CON_PRINTBUFFER, |
1da177e4 | 1230 | .index = -1, |
1da177e4 LT |
1231 | }; |
1232 | ||
1233 | static int __init sci_console_init(void) | |
1234 | { | |
1235 | register_console(&serial_console); | |
1236 | return 0; | |
1237 | } | |
1da177e4 LT |
1238 | console_initcall(sci_console_init); |
1239 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
1240 | ||
07d2a1a1 | 1241 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
e7c98dc7 | 1242 | #define SCI_CONSOLE (&serial_console) |
1da177e4 | 1243 | #else |
b7a76e4b | 1244 | #define SCI_CONSOLE 0 |
1da177e4 LT |
1245 | #endif |
1246 | ||
1247 | static char banner[] __initdata = | |
1248 | KERN_INFO "SuperH SCI(F) driver initialized\n"; | |
1249 | ||
1250 | static struct uart_driver sci_uart_driver = { | |
1251 | .owner = THIS_MODULE, | |
1252 | .driver_name = "sci", | |
1da177e4 LT |
1253 | .dev_name = "ttySC", |
1254 | .major = SCI_MAJOR, | |
1255 | .minor = SCI_MINOR_START, | |
e108b2ca | 1256 | .nr = SCI_NPORTS, |
1da177e4 LT |
1257 | .cons = SCI_CONSOLE, |
1258 | }; | |
1259 | ||
e552de24 | 1260 | |
54507f6e | 1261 | static int sci_remove(struct platform_device *dev) |
e552de24 MD |
1262 | { |
1263 | struct sh_sci_priv *priv = platform_get_drvdata(dev); | |
1264 | struct sci_port *p; | |
1265 | unsigned long flags; | |
1266 | ||
1267 | #ifdef CONFIG_HAVE_CLK | |
1268 | cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); | |
1269 | #endif | |
1270 | ||
1271 | spin_lock_irqsave(&priv->lock, flags); | |
1272 | list_for_each_entry(p, &priv->ports, node) | |
1273 | uart_remove_one_port(&sci_uart_driver, &p->port); | |
1274 | ||
1275 | spin_unlock_irqrestore(&priv->lock, flags); | |
1276 | ||
1277 | kfree(priv); | |
1278 | return 0; | |
1279 | } | |
1280 | ||
0ee70712 MD |
1281 | static int __devinit sci_probe_single(struct platform_device *dev, |
1282 | unsigned int index, | |
1283 | struct plat_sci_port *p, | |
1284 | struct sci_port *sciport) | |
1285 | { | |
1286 | struct sh_sci_priv *priv = platform_get_drvdata(dev); | |
1287 | unsigned long flags; | |
1288 | int ret; | |
1289 | ||
1290 | /* Sanity check */ | |
1291 | if (unlikely(index >= SCI_NPORTS)) { | |
1292 | dev_notice(&dev->dev, "Attempting to register port " | |
1293 | "%d when only %d are available.\n", | |
1294 | index+1, SCI_NPORTS); | |
1295 | dev_notice(&dev->dev, "Consider bumping " | |
1296 | "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); | |
1297 | return 0; | |
1298 | } | |
1299 | ||
501b825d | 1300 | sci_init_single(dev, sciport, index, p); |
0ee70712 MD |
1301 | |
1302 | ret = uart_add_one_port(&sci_uart_driver, &sciport->port); | |
08f8cb31 | 1303 | if (ret) |
0ee70712 | 1304 | return ret; |
0ee70712 MD |
1305 | |
1306 | INIT_LIST_HEAD(&sciport->node); | |
1307 | ||
1308 | spin_lock_irqsave(&priv->lock, flags); | |
1309 | list_add(&sciport->node, &priv->ports); | |
1310 | spin_unlock_irqrestore(&priv->lock, flags); | |
1311 | ||
1312 | return 0; | |
1313 | } | |
1314 | ||
e108b2ca PM |
1315 | /* |
1316 | * Register a set of serial devices attached to a platform device. The | |
1317 | * list is terminated with a zero flags entry, which means we expect | |
1318 | * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need | |
1319 | * remapping (such as sh64) should also set UPF_IOREMAP. | |
1320 | */ | |
1321 | static int __devinit sci_probe(struct platform_device *dev) | |
1da177e4 | 1322 | { |
e108b2ca | 1323 | struct plat_sci_port *p = dev->dev.platform_data; |
e552de24 | 1324 | struct sh_sci_priv *priv; |
7ff731ae | 1325 | int i, ret = -EINVAL; |
e552de24 MD |
1326 | |
1327 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1328 | if (!priv) | |
1329 | return -ENOMEM; | |
1330 | ||
1331 | INIT_LIST_HEAD(&priv->ports); | |
1332 | spin_lock_init(&priv->lock); | |
1333 | platform_set_drvdata(dev, priv); | |
1334 | ||
1335 | #ifdef CONFIG_HAVE_CLK | |
1336 | priv->clk_nb.notifier_call = sci_notifier; | |
1337 | cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER); | |
1338 | #endif | |
1da177e4 | 1339 | |
0ee70712 MD |
1340 | if (dev->id != -1) { |
1341 | ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]); | |
1342 | if (ret) | |
e552de24 | 1343 | goto err_unreg; |
0ee70712 MD |
1344 | } else { |
1345 | for (i = 0; p && p->flags != 0; p++, i++) { | |
1346 | ret = sci_probe_single(dev, i, p, &sci_ports[i]); | |
1347 | if (ret) | |
1348 | goto err_unreg; | |
e552de24 | 1349 | } |
e552de24 | 1350 | } |
1da177e4 LT |
1351 | |
1352 | #ifdef CONFIG_SH_STANDARD_BIOS | |
1353 | sh_bios_gdb_detach(); | |
1354 | #endif | |
1355 | ||
e108b2ca | 1356 | return 0; |
7ff731ae PM |
1357 | |
1358 | err_unreg: | |
e552de24 | 1359 | sci_remove(dev); |
7ff731ae | 1360 | return ret; |
1da177e4 LT |
1361 | } |
1362 | ||
6daa79b3 | 1363 | static int sci_suspend(struct device *dev) |
1da177e4 | 1364 | { |
6daa79b3 | 1365 | struct sh_sci_priv *priv = dev_get_drvdata(dev); |
e552de24 MD |
1366 | struct sci_port *p; |
1367 | unsigned long flags; | |
e108b2ca | 1368 | |
e552de24 MD |
1369 | spin_lock_irqsave(&priv->lock, flags); |
1370 | list_for_each_entry(p, &priv->ports, node) | |
1371 | uart_suspend_port(&sci_uart_driver, &p->port); | |
e552de24 | 1372 | spin_unlock_irqrestore(&priv->lock, flags); |
1da177e4 | 1373 | |
e108b2ca PM |
1374 | return 0; |
1375 | } | |
1da177e4 | 1376 | |
6daa79b3 | 1377 | static int sci_resume(struct device *dev) |
e108b2ca | 1378 | { |
6daa79b3 | 1379 | struct sh_sci_priv *priv = dev_get_drvdata(dev); |
e552de24 MD |
1380 | struct sci_port *p; |
1381 | unsigned long flags; | |
e108b2ca | 1382 | |
e552de24 MD |
1383 | spin_lock_irqsave(&priv->lock, flags); |
1384 | list_for_each_entry(p, &priv->ports, node) | |
1385 | uart_resume_port(&sci_uart_driver, &p->port); | |
e552de24 | 1386 | spin_unlock_irqrestore(&priv->lock, flags); |
e108b2ca PM |
1387 | |
1388 | return 0; | |
1389 | } | |
1390 | ||
6daa79b3 PM |
1391 | static struct dev_pm_ops sci_dev_pm_ops = { |
1392 | .suspend = sci_suspend, | |
1393 | .resume = sci_resume, | |
1394 | }; | |
1395 | ||
e108b2ca PM |
1396 | static struct platform_driver sci_driver = { |
1397 | .probe = sci_probe, | |
1398 | .remove = __devexit_p(sci_remove), | |
e108b2ca PM |
1399 | .driver = { |
1400 | .name = "sh-sci", | |
1401 | .owner = THIS_MODULE, | |
6daa79b3 | 1402 | .pm = &sci_dev_pm_ops, |
e108b2ca PM |
1403 | }, |
1404 | }; | |
1405 | ||
1406 | static int __init sci_init(void) | |
1407 | { | |
1408 | int ret; | |
1409 | ||
1410 | printk(banner); | |
1411 | ||
e108b2ca PM |
1412 | ret = uart_register_driver(&sci_uart_driver); |
1413 | if (likely(ret == 0)) { | |
1414 | ret = platform_driver_register(&sci_driver); | |
1415 | if (unlikely(ret)) | |
1416 | uart_unregister_driver(&sci_uart_driver); | |
1417 | } | |
1418 | ||
1419 | return ret; | |
1420 | } | |
1421 | ||
1422 | static void __exit sci_exit(void) | |
1423 | { | |
1424 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
1425 | uart_unregister_driver(&sci_uart_driver); |
1426 | } | |
1427 | ||
1428 | module_init(sci_init); | |
1429 | module_exit(sci_exit); | |
1430 | ||
e108b2ca | 1431 | MODULE_LICENSE("GPL"); |
e169c139 | 1432 | MODULE_ALIAS("platform:sh-sci"); |