Commit | Line | Data |
---|---|---|
1da177e4 | 1 | #include <linux/serial_core.h> |
edad1f20 | 2 | #include <linux/io.h> |
69edbba0 | 3 | #include <linux/gpio.h> |
3ea6bc3d | 4 | |
1da177e4 LT |
5 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) |
6 | #include <asm/regs306x.h> | |
7 | #endif | |
8 | #if defined(CONFIG_H8S2678) | |
9 | #include <asm/regs267x.h> | |
10 | #endif | |
1da177e4 | 11 | |
0fbde950 MD |
12 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
13 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
14 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | |
15 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
1da177e4 LT |
16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | |
18 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
1da177e4 LT |
19 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
20 | # define SCIF0 0xA4400000 | |
21 | # define SCIF2 0xA4410000 | |
b7a76e4b PM |
22 | # define SCSMR_Ir 0xA44A0000 |
23 | # define IRDA_SCIF SCIF0 | |
1da177e4 LT |
24 | # define SCPCR 0xA4000116 |
25 | # define SCPDR 0xA4000136 | |
26 | ||
27 | /* Set the clock source, | |
28 | * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input | |
29 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | |
30 | */ | |
31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | |
31a49c4b | 32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
8a77b8d0 | 33 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
8d099d44 MD |
34 | defined(CONFIG_ARCH_SH7367) || \ |
35 | defined(CONFIG_ARCH_SH7377) || \ | |
36 | defined(CONFIG_ARCH_SH7372) | |
3ea6bc3d | 37 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
fd88cac9 PM |
38 | # define PORT_PTCR 0xA405011EUL |
39 | # define PORT_PVCR 0xA4050122UL | |
40 | # define SCIF_ORER 0x0200 /* overrun error bit */ | |
1da177e4 | 41 | #elif defined(CONFIG_SH_RTS7751R2D) |
7abc404a | 42 | # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ |
1da177e4 LT |
43 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
44 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
45 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
05627486 PM |
46 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
47 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
48 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
49 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | |
50 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
51 | defined(CONFIG_CPU_SUBTYPE_SH7751R) | |
1da177e4 LT |
52 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ |
53 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | |
54 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
55 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | |
56 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | |
57 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | |
1da177e4 | 58 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
b7a76e4b PM |
59 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
60 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | |
61 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | |
1da177e4 LT |
62 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
63 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
2b1bd1ac | 64 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
e108b2ca | 65 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ |
9465a54f NI |
66 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
67 | # define PACR 0xa4050100 | |
68 | # define PBCR 0xa4050102 | |
69 | # define SCSCR_INIT(port) 0x3B | |
e108b2ca PM |
70 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
71 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | |
72 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | |
73 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | |
74 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | |
75 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | |
41504c39 | 76 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
346b7463 MD |
77 | # define PADR 0xA4050120 |
78 | # define PSDR 0xA405013e | |
79 | # define PWDR 0xA4050166 | |
80 | # define PSCR 0xA405011E | |
41504c39 PM |
81 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
82 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
9109a30e MD |
83 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
84 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | |
85 | # define SCSPTR0 SCPDR0 | |
86 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
87 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
178dd0cd PM |
88 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
89 | # define SCSPTR0 0xa4050160 | |
90 | # define SCSPTR1 0xa405013e | |
91 | # define SCSPTR2 0xa4050160 | |
92 | # define SCSPTR3 0xa405013e | |
93 | # define SCSPTR4 0xa4050128 | |
94 | # define SCSPTR5 0xa4050128 | |
95 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
96 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
47948d2b KM |
97 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) |
98 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
d7bbf7f5 GL |
99 | # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ |
100 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | |
101 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | |
1da177e4 | 102 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
1da177e4 LT |
103 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
104 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
105 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
1da177e4 | 106 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
1da177e4 LT |
107 | # define SCIF_BASE_ADDR 0x01030000 |
108 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR | |
109 | # define SCIF_PTR2_OFFS 0x0000020 | |
110 | # define SCIF_LSR2_OFFS 0x0000024 | |
1da177e4 LT |
111 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
112 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | |
f9669187 | 113 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ |
1da177e4 | 114 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) |
1da177e4 | 115 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
1da177e4 LT |
116 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
117 | #elif defined(CONFIG_H8S2678) | |
1da177e4 | 118 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
1da177e4 | 119 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
c01f0f1a YS |
120 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) |
121 | # define SCSPTR0 0xfe4b0020 | |
122 | # define SCSPTR1 0xfe4b0020 | |
123 | # define SCSPTR2 0xfe4b0020 | |
124 | # define SCIF_ORER 0x0001 | |
125 | # define SCSCR_INIT(port) 0x38 | |
126 | # define SCIF_ONLY | |
7d740a06 YS |
127 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
128 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
129 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ | |
c63847a3 | 130 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ |
7d740a06 | 131 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
c63847a3 | 132 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
b7a76e4b PM |
133 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
134 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | |
135 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | |
136 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | |
137 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
138 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | |
b7a76e4b PM |
139 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
140 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
141 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | |
e108b2ca | 142 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
b7a76e4b | 143 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
55ba99eb KM |
144 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
145 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
32351a28 PM |
146 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ |
147 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | |
148 | # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ | |
149 | # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ | |
150 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ | |
151 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | |
34aeb43e | 152 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
32351a28 | 153 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
2825999e PG |
154 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ |
155 | defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | |
a8f67f4b PM |
156 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
157 | defined(CONFIG_CPU_SUBTYPE_SH7263) | |
9d4436a6 YS |
158 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ |
159 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ | |
160 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | |
161 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | |
2825999e PG |
162 | # if defined(CONFIG_CPU_SUBTYPE_SH7201) |
163 | # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ | |
164 | # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ | |
165 | # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ | |
166 | # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ | |
167 | # endif | |
9d4436a6 | 168 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
9d4436a6 YS |
169 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
170 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | |
171 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | |
172 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | |
173 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
174 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
2b1bd1ac PM |
175 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
176 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ | |
177 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ | |
178 | # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ | |
179 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ | |
180 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | |
181 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
1da177e4 LT |
182 | #else |
183 | # error CPU subtype not defined | |
184 | #endif | |
185 | ||
186 | /* SCSCR */ | |
187 | #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ | |
188 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ | |
189 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ | |
190 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ | |
05627486 PM |
191 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
192 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | |
193 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
a8884e34 | 194 | defined(CONFIG_CPU_SUBTYPE_SH7722) || \ |
05627486 PM |
195 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
196 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
197 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | |
c63847a3 | 198 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
05627486 | 199 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
2b1bd1ac | 200 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
55ba99eb | 201 | defined(CONFIG_CPU_SUBTYPE_SH7786) || \ |
2b1bd1ac | 202 | defined(CONFIG_CPU_SUBTYPE_SHX3) |
1da177e4 | 203 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ |
d7bbf7f5 GL |
204 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) |
205 | #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) | |
1da177e4 LT |
206 | #else |
207 | #define SCI_CTRL_FLAGS_REIE 0 | |
208 | #endif | |
209 | /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
210 | /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
211 | /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ | |
212 | /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ | |
213 | ||
214 | /* SCxSR SCI */ | |
215 | #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
216 | #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
217 | #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
218 | #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
219 | #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
220 | #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
221 | /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
222 | /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
223 | ||
224 | #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) | |
225 | ||
226 | /* SCxSR SCIF */ | |
227 | #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
228 | #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
229 | #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
230 | #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
231 | #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
232 | #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
233 | #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
234 | #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
235 | ||
3ea6bc3d | 236 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31a49c4b | 237 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
8a77b8d0 | 238 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
8d099d44 MD |
239 | defined(CONFIG_ARCH_SH7367) || \ |
240 | defined(CONFIG_ARCH_SH7377) || \ | |
241 | defined(CONFIG_ARCH_SH7372) | |
c63847a3 NI |
242 | # define SCIF_ORER 0x0200 |
243 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | |
244 | # define SCIF_RFDC_MASK 0x007f | |
245 | # define SCIF_TXROOM_MAX 64 | |
246 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | |
247 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK ) | |
248 | # define SCIF_RFDC_MASK 0x007f | |
249 | # define SCIF_TXROOM_MAX 64 | |
250 | /* SH7763 SCIF2 support */ | |
251 | # define SCIF2_RFDC_MASK 0x001f | |
252 | # define SCIF2_TXROOM_MAX 16 | |
1da177e4 | 253 | #else |
c63847a3 NI |
254 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
255 | # define SCIF_RFDC_MASK 0x001f | |
256 | # define SCIF_TXROOM_MAX 16 | |
1da177e4 LT |
257 | #endif |
258 | ||
d830fa45 PM |
259 | #ifndef SCIF_ORER |
260 | #define SCIF_ORER 0x0000 | |
261 | #endif | |
262 | ||
15c73aaa PM |
263 | #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) |
264 | #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | |
265 | #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | |
266 | #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | |
267 | #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | |
268 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | |
269 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | |
d830fa45 | 270 | #define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) |
15c73aaa | 271 | |
3ea6bc3d | 272 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31a49c4b | 273 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
8a77b8d0 | 274 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
8d099d44 MD |
275 | defined(CONFIG_ARCH_SH7367) || \ |
276 | defined(CONFIG_ARCH_SH7377) || \ | |
277 | defined(CONFIG_ARCH_SH7372) | |
15c73aaa PM |
278 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) |
279 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) | |
280 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) | |
281 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) | |
1da177e4 | 282 | #else |
1da177e4 LT |
283 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) |
284 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | |
285 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | |
286 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) | |
287 | #endif | |
288 | ||
289 | /* SCFCR */ | |
290 | #define SCFCR_RFRST 0x0002 | |
291 | #define SCFCR_TFRST 0x0004 | |
292 | #define SCFCR_TCRST 0x4000 | |
293 | #define SCFCR_MCE 0x0008 | |
294 | ||
295 | #define SCI_MAJOR 204 | |
296 | #define SCI_MINOR_START 8 | |
297 | ||
298 | /* Generic serial flags */ | |
299 | #define SCI_RX_THROTTLE 0x0000001 | |
300 | ||
301 | #define SCI_MAGIC 0xbabeface | |
302 | ||
303 | /* | |
304 | * Events are used to schedule things to happen at timer-interrupt | |
305 | * time, instead of at rs interrupt time. | |
306 | */ | |
307 | #define SCI_EVENT_WRITE_WAKEUP 0 | |
308 | ||
1da177e4 | 309 | #define SCI_IN(size, offset) \ |
b7a76e4b | 310 | if ((size) == 8) { \ |
7ff731ae | 311 | return ioread8(port->membase + (offset)); \ |
b7a76e4b | 312 | } else { \ |
7ff731ae | 313 | return ioread16(port->membase + (offset)); \ |
1da177e4 LT |
314 | } |
315 | #define SCI_OUT(size, offset, value) \ | |
b7a76e4b | 316 | if ((size) == 8) { \ |
7ff731ae | 317 | iowrite8(value, port->membase + (offset)); \ |
3d2c2f3e | 318 | } else if ((size) == 16) { \ |
7ff731ae | 319 | iowrite16(value, port->membase + (offset)); \ |
1da177e4 LT |
320 | } |
321 | ||
322 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ | |
323 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
324 | { \ | |
1a22f08d YS |
325 | if (port->type == PORT_SCIF) { \ |
326 | SCI_IN(scif_size, scif_offset) \ | |
327 | } else { /* PORT_SCI or PORT_SCIFA */ \ | |
328 | SCI_IN(sci_size, sci_offset); \ | |
1da177e4 LT |
329 | } \ |
330 | } \ | |
331 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
332 | { \ | |
1a22f08d YS |
333 | if (port->type == PORT_SCIF) { \ |
334 | SCI_OUT(scif_size, scif_offset, value) \ | |
335 | } else { /* PORT_SCI or PORT_SCIFA */ \ | |
336 | SCI_OUT(sci_size, sci_offset, value); \ | |
1da177e4 LT |
337 | } \ |
338 | } | |
339 | ||
168f3623 YS |
340 | #ifdef CONFIG_H8300 |
341 | /* h8300 don't have SCIF */ | |
342 | #define CPU_SCIF_FNS(name) \ | |
343 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
344 | { \ | |
345 | return 0; \ | |
346 | } \ | |
347 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
348 | { \ | |
349 | } | |
350 | #else | |
351 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | |
1da177e4 LT |
352 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ |
353 | { \ | |
b7a76e4b | 354 | SCI_IN(scif_size, scif_offset); \ |
1da177e4 LT |
355 | } \ |
356 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
357 | { \ | |
358 | SCI_OUT(scif_size, scif_offset, value); \ | |
359 | } | |
168f3623 | 360 | #endif |
1da177e4 LT |
361 | |
362 | #define CPU_SCI_FNS(name, sci_offset, sci_size) \ | |
363 | static inline unsigned int sci_##name##_in(struct uart_port* port) \ | |
364 | { \ | |
b7a76e4b | 365 | SCI_IN(sci_size, sci_offset); \ |
1da177e4 LT |
366 | } \ |
367 | static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ | |
368 | { \ | |
369 | SCI_OUT(sci_size, sci_offset, value); \ | |
370 | } | |
371 | ||
8d099d44 MD |
372 | #if defined(CONFIG_CPU_SH3) || \ |
373 | defined(CONFIG_ARCH_SH7367) || \ | |
374 | defined(CONFIG_ARCH_SH7377) || \ | |
375 | defined(CONFIG_ARCH_SH7372) | |
9465a54f NI |
376 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
377 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
378 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
379 | h8_sci_offset, h8_sci_size) \ | |
380 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
381 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
382 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
3ea6bc3d | 383 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31a49c4b | 384 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
8a77b8d0 | 385 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
8d099d44 MD |
386 | defined(CONFIG_ARCH_SH7367) || \ |
387 | defined(CONFIG_ARCH_SH7377) || \ | |
388 | defined(CONFIG_ARCH_SH7372) | |
1da177e4 LT |
389 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
390 | CPU_SCIF_FNS(name, scif_offset, scif_size) | |
391 | #else | |
392 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
393 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
394 | h8_sci_offset, h8_sci_size) \ | |
395 | CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) | |
396 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
397 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) | |
398 | #endif | |
399 | #elif defined(__H8300H__) || defined(__H8300S__) | |
400 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
401 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
402 | h8_sci_offset, h8_sci_size) \ | |
403 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) | |
168f3623 YS |
404 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ |
405 | CPU_SCIF_FNS(name) | |
47948d2b KM |
406 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
407 | defined(CONFIG_CPU_SUBTYPE_SH7724) | |
178dd0cd PM |
408 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ |
409 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) | |
410 | #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ | |
411 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
1da177e4 LT |
412 | #else |
413 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
414 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
415 | h8_sci_offset, h8_sci_size) \ | |
416 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
417 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
418 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
419 | #endif | |
420 | ||
3ea6bc3d | 421 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31a49c4b | 422 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
8a77b8d0 | 423 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
8d099d44 MD |
424 | defined(CONFIG_ARCH_SH7367) || \ |
425 | defined(CONFIG_ARCH_SH7377) || \ | |
426 | defined(CONFIG_ARCH_SH7372) | |
9465a54f | 427 | |
1da177e4 LT |
428 | SCIF_FNS(SCSMR, 0x00, 16) |
429 | SCIF_FNS(SCBRR, 0x04, 8) | |
430 | SCIF_FNS(SCSCR, 0x08, 16) | |
431 | SCIF_FNS(SCTDSR, 0x0c, 8) | |
432 | SCIF_FNS(SCFER, 0x10, 16) | |
433 | SCIF_FNS(SCxSR, 0x14, 16) | |
434 | SCIF_FNS(SCFCR, 0x18, 16) | |
435 | SCIF_FNS(SCFDR, 0x1c, 16) | |
436 | SCIF_FNS(SCxTDR, 0x20, 8) | |
437 | SCIF_FNS(SCxRDR, 0x24, 8) | |
8a77b8d0 | 438 | SCIF_FNS(SCLSR, 0x00, 0) |
47948d2b KM |
439 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
440 | defined(CONFIG_CPU_SUBTYPE_SH7724) | |
178dd0cd PM |
441 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) |
442 | SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) | |
443 | SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) | |
444 | SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) | |
445 | SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) | |
446 | SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) | |
f686359e | 447 | SCIx_FNS(SCSPTR, 0, 0, 0, 0) |
178dd0cd PM |
448 | SCIF_FNS(SCTDSR, 0x0c, 8) |
449 | SCIF_FNS(SCFER, 0x10, 16) | |
450 | SCIF_FNS(SCFCR, 0x18, 16) | |
451 | SCIF_FNS(SCFDR, 0x1c, 16) | |
452 | SCIF_FNS(SCLSR, 0x24, 16) | |
1da177e4 LT |
453 | #else |
454 | /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ | |
455 | /* name off sz off sz off sz off sz off sz*/ | |
456 | SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) | |
457 | SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) | |
458 | SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) | |
459 | SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) | |
460 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) | |
461 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) | |
462 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) | |
32351a28 PM |
463 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
464 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
55ba99eb KM |
465 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
466 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
c2697968 | 467 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
b7a76e4b PM |
468 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
469 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
470 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
471 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
c2697968 | 472 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
c63847a3 NI |
473 | SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) |
474 | SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) | |
c2697968 PM |
475 | SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) |
476 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) | |
477 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
478 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
479 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
b7a76e4b | 480 | #else |
1da177e4 | 481 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
9b4e466f MD |
482 | #if defined(CONFIG_CPU_SUBTYPE_SH7722) |
483 | SCIF_FNS(SCSPTR, 0, 0, 0, 0) | |
484 | #else | |
1da177e4 | 485 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) |
9b4e466f | 486 | #endif |
1da177e4 LT |
487 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) |
488 | #endif | |
b7a76e4b | 489 | #endif |
1da177e4 LT |
490 | #define sci_in(port, reg) sci_##reg##_in(port) |
491 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | |
492 | ||
493 | /* H8/300 series SCI pins assignment */ | |
494 | #if defined(__H8300H__) || defined(__H8300S__) | |
495 | static const struct __attribute__((packed)) { | |
496 | int port; /* GPIO port no */ | |
497 | unsigned short rx,tx; /* GPIO bit no */ | |
498 | } h8300_sci_pins[] = { | |
499 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
500 | { /* SCI0 */ | |
501 | .port = H8300_GPIO_P9, | |
502 | .rx = H8300_GPIO_B2, | |
503 | .tx = H8300_GPIO_B0, | |
504 | }, | |
505 | { /* SCI1 */ | |
506 | .port = H8300_GPIO_P9, | |
507 | .rx = H8300_GPIO_B3, | |
508 | .tx = H8300_GPIO_B1, | |
509 | }, | |
510 | { /* SCI2 */ | |
511 | .port = H8300_GPIO_PB, | |
512 | .rx = H8300_GPIO_B7, | |
513 | .tx = H8300_GPIO_B6, | |
514 | } | |
515 | #elif defined(CONFIG_H8S2678) | |
516 | { /* SCI0 */ | |
517 | .port = H8300_GPIO_P3, | |
518 | .rx = H8300_GPIO_B2, | |
519 | .tx = H8300_GPIO_B0, | |
520 | }, | |
521 | { /* SCI1 */ | |
522 | .port = H8300_GPIO_P3, | |
523 | .rx = H8300_GPIO_B3, | |
524 | .tx = H8300_GPIO_B1, | |
525 | }, | |
526 | { /* SCI2 */ | |
527 | .port = H8300_GPIO_P5, | |
528 | .rx = H8300_GPIO_B1, | |
529 | .tx = H8300_GPIO_B0, | |
530 | } | |
531 | #endif | |
532 | }; | |
533 | #endif | |
534 | ||
0fbde950 MD |
535 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
536 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
537 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | |
538 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
1da177e4 LT |
539 | static inline int sci_rxd_in(struct uart_port *port) |
540 | { | |
541 | if (port->mapbase == 0xfffffe80) | |
32b53076 | 542 | return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ |
3ea6bc3d MB |
543 | return 1; |
544 | } | |
05627486 PM |
545 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
546 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
547 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | |
548 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
549 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
961e9ff9 | 550 | defined(CONFIG_CPU_SUBTYPE_SH7091) |
1da177e4 LT |
551 | static inline int sci_rxd_in(struct uart_port *port) |
552 | { | |
1da177e4 | 553 | if (port->mapbase == 0xffe00000) |
32b53076 | 554 | return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ |
47948d2b KM |
555 | return 1; |
556 | } | |
1da177e4 LT |
557 | #elif defined(__H8300H__) || defined(__H8300S__) |
558 | static inline int sci_rxd_in(struct uart_port *port) | |
559 | { | |
560 | int ch = (port->mapbase - SMR0) >> 3; | |
561 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | |
562 | } | |
9e9622d1 | 563 | #else /* default case for non-SCI processors */ |
2b1bd1ac PM |
564 | static inline int sci_rxd_in(struct uart_port *port) |
565 | { | |
1760b7d7 | 566 | return 1; |
2b1bd1ac | 567 | } |
1da177e4 LT |
568 | #endif |
569 | ||
570 | /* | |
571 | * Values for the BitRate Register (SCBRR) | |
572 | * | |
573 | * The values are actually divisors for a frequency which can | |
574 | * be internal to the SH3 (14.7456MHz) or derived from an external | |
575 | * clock source. This driver assumes the internal clock is used; | |
576 | * to support using an external clock source, config options or | |
577 | * possibly command-line options would need to be added. | |
578 | * | |
579 | * Also, to support speeds below 2400 (why?) the lower 2 bits of | |
580 | * the SCSMR register would also need to be set to non-zero values. | |
581 | * | |
582 | * -- Greg Banks 27Feb2000 | |
583 | * | |
584 | * Answer: The SCBRR register is only eight bits, and the value in | |
585 | * it gets larger with lower baud rates. At around 2400 (depending on | |
586 | * the peripherial module clock) you run out of bits. However the | |
587 | * lower two bits of SCSMR allow the module clock to be divided down, | |
588 | * scaling the value which is needed in SCBRR. | |
589 | * | |
590 | * -- Stuart Menefy - 23 May 2000 | |
591 | * | |
592 | * I meant, why would anyone bother with bitrates below 2400. | |
593 | * | |
594 | * -- Greg Banks - 7Jul2000 | |
595 | * | |
596 | * You "speedist"! How will I use my 110bps ASR-33 teletype with paper | |
597 | * tape reader as a console! | |
598 | * | |
599 | * -- Mitch Davis - 15 Jul 2000 | |
600 | */ | |
601 | ||
c63847a3 | 602 | #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
55ba99eb KM |
603 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
604 | defined(CONFIG_CPU_SUBTYPE_SH7786) | |
b7a76e4b | 605 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) |
3ea6bc3d | 606 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
31a49c4b | 607 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
8a77b8d0 | 608 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ |
8d099d44 MD |
609 | defined(CONFIG_ARCH_SH7367) || \ |
610 | defined(CONFIG_ARCH_SH7377) || \ | |
611 | defined(CONFIG_ARCH_SH7372) | |
b7a76e4b | 612 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
47948d2b KM |
613 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
614 | defined(CONFIG_CPU_SUBTYPE_SH7724) | |
ba1d2818 NI |
615 | static inline int scbrr_calc(struct uart_port *port, int bps, int clk) |
616 | { | |
617 | if (port->type == PORT_SCIF) | |
618 | return (clk+16*bps)/(32*bps)-1; | |
619 | else | |
620 | return ((clk*2)+16*bps)/(16*bps)-1; | |
621 | } | |
622 | #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) | |
b7a76e4b | 623 | #elif defined(__H8300H__) || defined(__H8300S__) |
a2159b52 | 624 | #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) |
b7a76e4b PM |
625 | #else /* Generic SH */ |
626 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) | |
1da177e4 | 627 | #endif |