[deliverable/linux.git] / drivers / sh / intc / core.c

/*
 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
 *
 * Copyright (C) 2007, 2008 Magnus Damm
 * Copyright (C) 2009 - 2012 Paul Mundt
 *
 * Based on intc2.c and ipr.c
 *
 * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
 * Copyright (C) 2000  Kazumoto Kojima
 * Copyright (C) 2001  David J. Mckay (david.mckay@st.com)
 * Copyright (C) 2003  Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
 * Copyright (C) 2005, 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#define pr_fmt(fmt) "intc: " fmt

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/stat.h>
#include <linux/interrupt.h>
#include <linux/sh_intc.h>
#include <linux/irqdomain.h>
#include <linux/device.h>
#include <linux/syscore_ops.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/radix-tree.h>
#include <linux/export.h>
#include <linux/sort.h>
#include "internals.h"

LIST_HEAD(intc_list);
DEFINE_RAW_SPINLOCK(intc_big_lock);
static unsigned int nr_intc_controllers;

/*
 * Default priority level
 * - this needs to be at least 2 for 5-bit priorities on 7780
 */
static unsigned int default_prio_level = 2;	/* 2 - 16 */
static unsigned int intc_prio_level[INTC_NR_IRQS];	/* for now */

unsigned int intc_get_dfl_prio_level(void)
{
	return default_prio_level;
}

unsigned int intc_get_prio_level(unsigned int irq)
{
	return intc_prio_level[irq];
}

void intc_set_prio_level(unsigned int irq, unsigned int level)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&intc_big_lock, flags);
	intc_prio_level[irq] = level;
	raw_spin_unlock_irqrestore(&intc_big_lock, flags);
}

static void intc_redirect_irq(struct irq_desc *desc)
{
	generic_handle_irq((unsigned int)irq_desc_get_handler_data(desc));
}

static void __init intc_register_irq(struct intc_desc *desc,
				     struct intc_desc_int *d,
				     intc_enum enum_id,
				     unsigned int irq)
{
	struct intc_handle_int *hp;
	struct irq_data *irq_data;
	unsigned int data[2], primary;
	unsigned long flags;

	raw_spin_lock_irqsave(&intc_big_lock, flags);
	radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
	raw_spin_unlock_irqrestore(&intc_big_lock, flags);

	/*
	 * Prefer single interrupt source bitmap over other combinations:
	 *
	 * 1. bitmap, single interrupt source
	 * 2. priority, single interrupt source
	 * 3. bitmap, multiple interrupt sources (groups)
	 * 4. priority, multiple interrupt sources (groups)
	 */
	data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
	data[1] = intc_get_prio_handle(desc, d, enum_id, 0);

	primary = 0;
	if (!data[0] && data[1])
		primary = 1;

	if (!data[0] && !data[1])
		pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
			   irq, irq2evt(irq));

	data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
	data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);

	if (!data[primary])
		primary ^= 1;

	BUG_ON(!data[primary]); /* must have primary masking method */

	irq_data = irq_get_irq_data(irq);

	disable_irq_nosync(irq);
	irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq,
				      "level");
	irq_set_chip_data(irq, (void *)data[primary]);

	/*
	 * set priority level
	 */
	intc_set_prio_level(irq, intc_get_dfl_prio_level());

	/* enable secondary masking method if present */
	if (data[!primary])
		_intc_enable(irq_data, data[!primary]);

	/* add irq to d->prio list if priority is available */
	if (data[1]) {
		hp = d->prio + d->nr_prio;
		hp->irq = irq;
		hp->handle = data[1];

		if (primary) {
			/*
			 * only secondary priority should access registers, so
			 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
			 */
			hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
			hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
		}
		d->nr_prio++;
	}

	/* add irq to d->sense list if sense is available */
	data[0] = intc_get_sense_handle(desc, d, enum_id);
	if (data[0]) {
		(d->sense + d->nr_sense)->irq = irq;
		(d->sense + d->nr_sense)->handle = data[0];
		d->nr_sense++;
	}

	/* irq should be disabled by default */
	d->chip.irq_mask(irq_data);

	intc_set_ack_handle(irq, desc, d, enum_id);
	intc_set_dist_handle(irq, desc, d, enum_id);

	activate_irq(irq);
}

static unsigned int __init save_reg(struct intc_desc_int *d,
				    unsigned int cnt,
				    unsigned long value,
				    unsigned int smp)
{
	if (value) {
		value = intc_phys_to_virt(d, value);

		d->reg[cnt] = value;
#ifdef CONFIG_SMP
		d->smp[cnt] = smp;
#endif
		return 1;
	}

	return 0;
}

int __init register_intc_controller(struct intc_desc *desc)
{
	unsigned int i, k, smp;
	struct intc_hw_desc *hw = &desc->hw;
	struct intc_desc_int *d;
	struct resource *res;

	pr_info("Registered controller '%s' with %u IRQs\n",
		desc->name, hw->nr_vectors);

	d = kzalloc(sizeof(*d), GFP_NOWAIT);
	if (!d)
		goto err0;

	INIT_LIST_HEAD(&d->list);
	list_add_tail(&d->list, &intc_list);

	raw_spin_lock_init(&d->lock);
	INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);

	d->index = nr_intc_controllers;

	if (desc->num_resources) {
		d->nr_windows = desc->num_resources;
		d->window = kzalloc(d->nr_windows * sizeof(*d->window),
				    GFP_NOWAIT);
		if (!d->window)
			goto err1;

		for (k = 0; k < d->nr_windows; k++) {
			res = desc->resource + k;
			WARN_ON(resource_type(res) != IORESOURCE_MEM);
			d->window[k].phys = res->start;
			d->window[k].size = resource_size(res);
			d->window[k].virt = ioremap_nocache(res->start,
							 resource_size(res));
			if (!d->window[k].virt)
				goto err2;
		}
	}

	d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
#ifdef CONFIG_INTC_BALANCING
	if (d->nr_reg)
		d->nr_reg += hw->nr_mask_regs;
#endif
	d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
	d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
	d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
	d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;

	d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
	if (!d->reg)
		goto err2;

#ifdef CONFIG_SMP
	d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
	if (!d->smp)
		goto err3;
#endif
	k = 0;

	if (hw->mask_regs) {
		for (i = 0; i < hw->nr_mask_regs; i++) {
			smp = IS_SMP(hw->mask_regs[i]);
			k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
			k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
#ifdef CONFIG_INTC_BALANCING
			k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
#endif
		}
	}

	if (hw->prio_regs) {
		d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
				  GFP_NOWAIT);
		if (!d->prio)
			goto err4;

		for (i = 0; i < hw->nr_prio_regs; i++) {
			smp = IS_SMP(hw->prio_regs[i]);
			k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
			k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
		}

		sort(d->prio, hw->nr_prio_regs, sizeof(*d->prio),
		     intc_handle_int_cmp, NULL);
	}

	if (hw->sense_regs) {
		d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
				   GFP_NOWAIT);
		if (!d->sense)
			goto err5;

		for (i = 0; i < hw->nr_sense_regs; i++)
			k += save_reg(d, k, hw->sense_regs[i].reg, 0);

		sort(d->sense, hw->nr_sense_regs, sizeof(*d->sense),
		     intc_handle_int_cmp, NULL);
	}

	if (hw->subgroups)
		for (i = 0; i < hw->nr_subgroups; i++)
			if (hw->subgroups[i].reg)
				k+= save_reg(d, k, hw->subgroups[i].reg, 0);

	memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
	d->chip.name = desc->name;

	if (hw->ack_regs)
		for (i = 0; i < hw->nr_ack_regs; i++)
			k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
	else
		d->chip.irq_mask_ack = d->chip.irq_disable;

	/* disable bits matching force_disable before registering irqs */
	if (desc->force_disable)
		intc_enable_disable_enum(desc, d, desc->force_disable, 0);

	/* disable bits matching force_enable before registering irqs */
	if (desc->force_enable)
		intc_enable_disable_enum(desc, d, desc->force_enable, 0);

	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */

	intc_irq_domain_init(d, hw);

	/* register the vectors one by one */
	for (i = 0; i < hw->nr_vectors; i++) {
		struct intc_vect *vect = hw->vectors + i;
		unsigned int irq = evt2irq(vect->vect);
		int res;

		if (!vect->enum_id)
			continue;

		res = irq_create_identity_mapping(d->domain, irq);
		if (unlikely(res)) {
			if (res == -EEXIST) {
				res = irq_domain_associate(d->domain, irq, irq);
				if (unlikely(res)) {
					pr_err("domain association failure\n");
					continue;
				}
			} else {
				pr_err("can't identity map IRQ %d\n", irq);
				continue;
			}
		}

		intc_irq_xlate_set(irq, vect->enum_id, d);
		intc_register_irq(desc, d, vect->enum_id, irq);

		for (k = i + 1; k < hw->nr_vectors; k++) {
			struct intc_vect *vect2 = hw->vectors + k;
			unsigned int irq2 = evt2irq(vect2->vect);

			if (vect->enum_id != vect2->enum_id)
				continue;

			/*
			 * In the case of multi-evt handling and sparse
			 * IRQ support, each vector still needs to have
			 * its own backing irq_desc.
			 */
			res = irq_create_identity_mapping(d->domain, irq2);
			if (unlikely(res)) {
				if (res == -EEXIST) {
					res = irq_domain_associate(d->domain,
								   irq2, irq2);
					if (unlikely(res)) {
						pr_err("domain association "
						       "failure\n");
						continue;
					}
				} else {
					pr_err("can't identity map IRQ %d\n",
					       irq);
					continue;
				}
			}

			vect2->enum_id = 0;

			/* redirect this interrupts to the first one */
			irq_set_chip(irq2, &dummy_irq_chip);
			irq_set_chained_handler_and_data(irq2,
							 intc_redirect_irq,
							 (void *)irq);
		}
	}

	intc_subgroup_init(desc, d);

	/* enable bits matching force_enable after registering irqs */
	if (desc->force_enable)
		intc_enable_disable_enum(desc, d, desc->force_enable, 1);

	d->skip_suspend = desc->skip_syscore_suspend;

	nr_intc_controllers++;

	return 0;
err5:
	kfree(d->prio);
err4:
#ifdef CONFIG_SMP
	kfree(d->smp);
err3:
#endif
	kfree(d->reg);
err2:
	for (k = 0; k < d->nr_windows; k++)
		if (d->window[k].virt)
			iounmap(d->window[k].virt);

	kfree(d->window);
err1:
	kfree(d);
err0:
	pr_err("unable to allocate INTC memory\n");

	return -ENOMEM;
}

static int intc_suspend(void)
{
	struct intc_desc_int *d;

	list_for_each_entry(d, &intc_list, list) {
		int irq;

		if (d->skip_suspend)
			continue;

		/* enable wakeup irqs belonging to this intc controller */
		for_each_active_irq(irq) {
			struct irq_data *data;
			struct irq_chip *chip;

			data = irq_get_irq_data(irq);
			chip = irq_data_get_irq_chip(data);
			if (chip != &d->chip)
				continue;
			if (irqd_is_wakeup_set(data))
				chip->irq_enable(data);
		}
	}
	return 0;
}

static void intc_resume(void)
{
	struct intc_desc_int *d;

	list_for_each_entry(d, &intc_list, list) {
		int irq;

		if (d->skip_suspend)
			continue;

		for_each_active_irq(irq) {
			struct irq_data *data;
			struct irq_chip *chip;

			data = irq_get_irq_data(irq);
			chip = irq_data_get_irq_chip(data);
			/*
			 * This will catch the redirect and VIRQ cases
			 * due to the dummy_irq_chip being inserted.
			 */
			if (chip != &d->chip)
				continue;
			if (irqd_irq_disabled(data))
				chip->irq_disable(data);
			else
				chip->irq_enable(data);
		}
	}
}

struct syscore_ops intc_syscore_ops = {
	.suspend	= intc_suspend,
	.resume		= intc_resume,
};

struct bus_type intc_subsys = {
	.name		= "intc",
	.dev_name	= "intc",
};

static ssize_t
show_intc_name(struct device *dev, struct device_attribute *attr, char *buf)
{
	struct intc_desc_int *d;

	d = container_of(dev, struct intc_desc_int, dev);

	return sprintf(buf, "%s\n", d->chip.name);
}

static DEVICE_ATTR(name, S_IRUGO, show_intc_name, NULL);

static int __init register_intc_devs(void)
{
	struct intc_desc_int *d;
	int error;

	register_syscore_ops(&intc_syscore_ops);

	error = subsys_system_register(&intc_subsys, NULL);
	if (!error) {
		list_for_each_entry(d, &intc_list, list) {
			d->dev.id = d->index;
			d->dev.bus = &intc_subsys;
			error = device_register(&d->dev);
			if (error == 0)
				error = device_create_file(&d->dev,
							   &dev_attr_name);
			if (error)
				break;
		}
	}

	if (error)
		pr_err("device registration error\n");

	return error;
}
device_initcall(register_intc_devs);
Commit	Line	Data
2be6bb0c PM	1	/*
	2	* Shared interrupt handling code for IPR and INTC2 types of IRQs.
	3	*
	4	* Copyright (C) 2007, 2008 Magnus Damm
b59f9f97	5	* Copyright (C) 2009 - 2012 Paul Mundt
2be6bb0c PM	6	*
	7	* Based on intc2.c and ipr.c
	8	*
	9	* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
	10	* Copyright (C) 2000 Kazumoto Kojima
	11	* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
	12	* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
	13	* Copyright (C) 2005, 2006 Paul Mundt
	14	*
	15	* This file is subject to the terms and conditions of the GNU General Public
	16	* License. See the file "COPYING" in the main directory of this archive
	17	* for more details.
	18	*/
	19	#define pr_fmt(fmt) "intc: " fmt
	20
	21	#include <linux/init.h>
	22	#include <linux/irq.h>
	23	#include <linux/io.h>
	24	#include <linux/slab.h>
0c43871b	25	#include <linux/stat.h>
2be6bb0c PM	26	#include <linux/interrupt.h>
2be6bb0c PM	27	#include <linux/sh_intc.h>
1d6a21b0	28	#include <linux/irqdomain.h>
f4e73bfc	29	#include <linux/device.h>
a696b89c	30	#include <linux/syscore_ops.h>
2be6bb0c PM	31	#include <linux/list.h>
	32	#include <linux/spinlock.h>
	33	#include <linux/radix-tree.h>
f7be3455	34	#include <linux/export.h>
b59f9f97	35	#include <linux/sort.h>
2be6bb0c PM	36	#include "internals.h"
	37
	38	LIST_HEAD(intc_list);
	39	DEFINE_RAW_SPINLOCK(intc_big_lock);
5fbebcbd	40	static unsigned int nr_intc_controllers;
2be6bb0c PM	41
	42	/*
	43	* Default priority level
	44	* - this needs to be at least 2 for 5-bit priorities on 7780
	45	*/
	46	static unsigned int default_prio_level = 2; /* 2 - 16 */
0f552393	47	static unsigned int intc_prio_level[INTC_NR_IRQS]; /* for now */
2be6bb0c PM	48
	49	unsigned int intc_get_dfl_prio_level(void)
	50	{
	51	return default_prio_level;
	52	}
	53
	54	unsigned int intc_get_prio_level(unsigned int irq)
	55	{
	56	return intc_prio_level[irq];
	57	}
	58
	59	void intc_set_prio_level(unsigned int irq, unsigned int level)
	60	{
	61	unsigned long flags;
	62
	63	raw_spin_lock_irqsave(&intc_big_lock, flags);
	64	intc_prio_level[irq] = level;
	65	raw_spin_unlock_irqrestore(&intc_big_lock, flags);
	66	}
	67
bd0b9ac4	68	static void intc_redirect_irq(struct irq_desc *desc)
2be6bb0c	69	{
8228a048	70	generic_handle_irq((unsigned int)irq_desc_get_handler_data(desc));
2be6bb0c PM	71	}
	72
	73	static void __init intc_register_irq(struct intc_desc *desc,
	74	struct intc_desc_int *d,
	75	intc_enum enum_id,
	76	unsigned int irq)
	77	{
	78	struct intc_handle_int *hp;
26599a94	79	struct irq_data *irq_data;
2be6bb0c PM	80	unsigned int data[2], primary;
	81	unsigned long flags;
	82
2be6bb0c PM	83	raw_spin_lock_irqsave(&intc_big_lock, flags);
	84	radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
	85	raw_spin_unlock_irqrestore(&intc_big_lock, flags);
	86
	87	/*
	88	* Prefer single interrupt source bitmap over other combinations:
	89	*
	90	* 1. bitmap, single interrupt source
	91	* 2. priority, single interrupt source
	92	* 3. bitmap, multiple interrupt sources (groups)
	93	* 4. priority, multiple interrupt sources (groups)
	94	*/
	95	data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
	96	data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
	97
	98	primary = 0;
	99	if (!data[0] && data[1])
	100	primary = 1;
	101
	102	if (!data[0] && !data[1])
	103	pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
	104	irq, irq2evt(irq));
	105
	106	data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
	107	data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
	108
	109	if (!data[primary])
	110	primary ^= 1;
	111
	112	BUG_ON(!data[primary]); /* must have primary masking method */
	113
26599a94 PM	114	irq_data = irq_get_irq_data(irq);
26599a94 PM	115
2be6bb0c	116	disable_irq_nosync(irq);
fcb8918f TG	117	irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq,
	118	"level");
	119	irq_set_chip_data(irq, (void *)data[primary]);
2be6bb0c PM	120
	121	/*
	122	* set priority level
	123	*/
	124	intc_set_prio_level(irq, intc_get_dfl_prio_level());
	125
	126	/* enable secondary masking method if present */
	127	if (data[!primary])
26599a94	128	_intc_enable(irq_data, data[!primary]);
2be6bb0c PM	129
	130	/* add irq to d->prio list if priority is available */
	131	if (data[1]) {
	132	hp = d->prio + d->nr_prio;
	133	hp->irq = irq;
	134	hp->handle = data[1];
	135
	136	if (primary) {
	137	/*
	138	* only secondary priority should access registers, so
	139	* set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
	140	*/
	141	hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
	142	hp->handle \|= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
	143	}
	144	d->nr_prio++;
	145	}
	146
	147	/* add irq to d->sense list if sense is available */
	148	data[0] = intc_get_sense_handle(desc, d, enum_id);
	149	if (data[0]) {
	150	(d->sense + d->nr_sense)->irq = irq;
	151	(d->sense + d->nr_sense)->handle = data[0];
	152	d->nr_sense++;
	153	}
	154
	155	/* irq should be disabled by default */
26599a94	156	d->chip.irq_mask(irq_data);
2be6bb0c PM	157
	158	intc_set_ack_handle(irq, desc, d, enum_id);
	159	intc_set_dist_handle(irq, desc, d, enum_id);
	160
	161	activate_irq(irq);
	162	}
	163
	164	static unsigned int __init save_reg(struct intc_desc_int *d,
	165	unsigned int cnt,
	166	unsigned long value,
	167	unsigned int smp)
	168	{
	169	if (value) {
	170	value = intc_phys_to_virt(d, value);
	171
	172	d->reg[cnt] = value;
	173	#ifdef CONFIG_SMP
	174	d->smp[cnt] = smp;
	175	#endif
	176	return 1;
	177	}
	178
	179	return 0;
	180	}
	181
	182	int __init register_intc_controller(struct intc_desc *desc)
	183	{
	184	unsigned int i, k, smp;
	185	struct intc_hw_desc *hw = &desc->hw;
	186	struct intc_desc_int *d;
	187	struct resource *res;
	188
	189	pr_info("Registered controller '%s' with %u IRQs\n",
	190	desc->name, hw->nr_vectors);
	191
	192	d = kzalloc(sizeof(*d), GFP_NOWAIT);
	193	if (!d)
	194	goto err0;
	195
	196	INIT_LIST_HEAD(&d->list);
	197	list_add_tail(&d->list, &intc_list);
	198
	199	raw_spin_lock_init(&d->lock);
30f2ba38	200	INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);
2be6bb0c PM	201
	202	d->index = nr_intc_controllers;
	203
	204	if (desc->num_resources) {
	205	d->nr_windows = desc->num_resources;
	206	d->window = kzalloc(d->nr_windows * sizeof(*d->window),
	207	GFP_NOWAIT);
	208	if (!d->window)
	209	goto err1;
	210
	211	for (k = 0; k < d->nr_windows; k++) {
	212	res = desc->resource + k;
	213	WARN_ON(resource_type(res) != IORESOURCE_MEM);
	214	d->window[k].phys = res->start;
	215	d->window[k].size = resource_size(res);
	216	d->window[k].virt = ioremap_nocache(res->start,
	217	resource_size(res));
	218	if (!d->window[k].virt)
	219	goto err2;
	220	}
	221	}
	222
	223	d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
	224	#ifdef CONFIG_INTC_BALANCING
	225	if (d->nr_reg)
	226	d->nr_reg += hw->nr_mask_regs;
	227	#endif
	228	d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
	229	d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
	230	d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
	231	d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
	232
	233	d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
	234	if (!d->reg)
	235	goto err2;
	236
	237	#ifdef CONFIG_SMP
	238	d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
	239	if (!d->smp)
	240	goto err3;
	241	#endif
	242	k = 0;
	243
	244	if (hw->mask_regs) {
	245	for (i = 0; i < hw->nr_mask_regs; i++) {
	246	smp = IS_SMP(hw->mask_regs[i]);
	247	k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
	248	k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
	249	#ifdef CONFIG_INTC_BALANCING
	250	k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
	251	#endif
	252	}
	253	}
	254
	255	if (hw->prio_regs) {
	256	d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
	257	GFP_NOWAIT);
	258	if (!d->prio)
	259	goto err4;
	260
	261	for (i = 0; i < hw->nr_prio_regs; i++) {
	262	smp = IS_SMP(hw->prio_regs[i]);
	263	k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
	264	k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
265	}
b59f9f97 PM	266
	267	sort(d->prio, hw->nr_prio_regs, sizeof(*d->prio),
	268	intc_handle_int_cmp, NULL);
2be6bb0c PM	269	}
	270
	271	if (hw->sense_regs) {
	272	d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
	273	GFP_NOWAIT);
	274	if (!d->sense)
	275	goto err5;
	276
	277	for (i = 0; i < hw->nr_sense_regs; i++)
	278	k += save_reg(d, k, hw->sense_regs[i].reg, 0);
b59f9f97 PM	279
	280	sort(d->sense, hw->nr_sense_regs, sizeof(*d->sense),
	281	intc_handle_int_cmp, NULL);
2be6bb0c PM	282	}
	283
	284	if (hw->subgroups)
	285	for (i = 0; i < hw->nr_subgroups; i++)
	286	if (hw->subgroups[i].reg)
	287	k+= save_reg(d, k, hw->subgroups[i].reg, 0);
	288
	289	memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
	290	d->chip.name = desc->name;
	291
	292	if (hw->ack_regs)
	293	for (i = 0; i < hw->nr_ack_regs; i++)
	294	k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
	295	else
26599a94	296	d->chip.irq_mask_ack = d->chip.irq_disable;
2be6bb0c PM	297
	298	/* disable bits matching force_disable before registering irqs */
	299	if (desc->force_disable)
	300	intc_enable_disable_enum(desc, d, desc->force_disable, 0);
	301
	302	/* disable bits matching force_enable before registering irqs */
	303	if (desc->force_enable)
	304	intc_enable_disable_enum(desc, d, desc->force_enable, 0);
	305
	306	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
	307
1d6a21b0 PM	308	intc_irq_domain_init(d, hw);
1d6a21b0 PM	309
2be6bb0c PM	310	/* register the vectors one by one */
	311	for (i = 0; i < hw->nr_vectors; i++) {
	312	struct intc_vect *vect = hw->vectors + i;
	313	unsigned int irq = evt2irq(vect->vect);
c4318baf	314	int res;
2be6bb0c PM	315
	316	if (!vect->enum_id)
	317	continue;
	318
1d6a21b0 PM	319	res = irq_create_identity_mapping(d->domain, irq);
1d6a21b0 PM	320	if (unlikely(res)) {
10260237 PM	321	if (res == -EEXIST) {
	322	res = irq_domain_associate(d->domain, irq, irq);
	323	if (unlikely(res)) {
	324	pr_err("domain association failure\n");
	325	continue;
	326	}
	327	} else {
	328	pr_err("can't identity map IRQ %d\n", irq);
	329	continue;
	330	}
2be6bb0c PM	331	}
	332
	333	intc_irq_xlate_set(irq, vect->enum_id, d);
	334	intc_register_irq(desc, d, vect->enum_id, irq);
	335
	336	for (k = i + 1; k < hw->nr_vectors; k++) {
	337	struct intc_vect *vect2 = hw->vectors + k;
	338	unsigned int irq2 = evt2irq(vect2->vect);
	339
	340	if (vect->enum_id != vect2->enum_id)
	341	continue;
	342
	343	/*
	344	* In the case of multi-evt handling and sparse
	345	* IRQ support, each vector still needs to have
	346	* its own backing irq_desc.
	347	*/
1d6a21b0 PM	348	res = irq_create_identity_mapping(d->domain, irq2);
1d6a21b0 PM	349	if (unlikely(res)) {
10260237 PM	350	if (res == -EEXIST) {
10260237 PM	351	res = irq_domain_associate(d->domain,
d4b7c5db	352	irq2, irq2);
10260237 PM	353	if (unlikely(res)) {
	354	pr_err("domain association "
	355	"failure\n");
	356	continue;
	357	}
	358	} else {
	359	pr_err("can't identity map IRQ %d\n",
	360	irq);
	361	continue;
	362	}
2be6bb0c PM	363	}
	364
	365	vect2->enum_id = 0;
	366
	367	/* redirect this interrupts to the first one */
fcb8918f	368	irq_set_chip(irq2, &dummy_irq_chip);
51b971b1 TG	369	irq_set_chained_handler_and_data(irq2,
	370	intc_redirect_irq,
	371	(void *)irq);
2be6bb0c PM	372	}
	373	}
	374
	375	intc_subgroup_init(desc, d);
	376
	377	/* enable bits matching force_enable after registering irqs */
	378	if (desc->force_enable)
	379	intc_enable_disable_enum(desc, d, desc->force_enable, 1);
	380
0f966d74 RW	381	d->skip_suspend = desc->skip_syscore_suspend;
0f966d74 RW	382
2be6bb0c PM	383	nr_intc_controllers++;
	384
	385	return 0;
	386	err5:
	387	kfree(d->prio);
	388	err4:
	389	#ifdef CONFIG_SMP
	390	kfree(d->smp);
	391	err3:
	392	#endif
	393	kfree(d->reg);
	394	err2:
	395	for (k = 0; k < d->nr_windows; k++)
	396	if (d->window[k].virt)
	397	iounmap(d->window[k].virt);
	398
	399	kfree(d->window);
	400	err1:
	401	kfree(d);
	402	err0:
	403	pr_err("unable to allocate INTC memory\n");
	404
	405	return -ENOMEM;
	406	}
	407
a696b89c	408	static int intc_suspend(void)
2be6bb0c PM	409	{
	410	struct intc_desc_int *d;
	411
a696b89c RW	412	list_for_each_entry(d, &intc_list, list) {
a696b89c RW	413	int irq;
2be6bb0c	414
0f966d74 RW	415	if (d->skip_suspend)
	416	continue;
	417
a696b89c RW	418	/* enable wakeup irqs belonging to this intc controller */
	419	for_each_active_irq(irq) {
	420	struct irq_data *data;
a696b89c	421	struct irq_chip *chip;
2be6bb0c	422
a696b89c RW	423	data = irq_get_irq_data(irq);
	424	chip = irq_data_get_irq_chip(data);
	425	if (chip != &d->chip)
	426	continue;
a821b279	427	if (irqd_is_wakeup_set(data))
a696b89c RW	428	chip->irq_enable(data);
	429	}
	430	}
a696b89c RW	431	return 0;
a696b89c RW	432	}
2be6bb0c	433
a696b89c	434	static void intc_resume(void)
2be6bb0c PM	435	{
2be6bb0c PM	436	struct intc_desc_int *d;
2be6bb0c	437
a696b89c RW	438	list_for_each_entry(d, &intc_list, list) {
a696b89c RW	439	int irq;
2be6bb0c	440
0f966d74 RW	441	if (d->skip_suspend)
	442	continue;
	443
63111a3a	444	for_each_active_irq(irq) {
a696b89c	445	struct irq_data *data;
a696b89c RW	446	struct irq_chip *chip;
a696b89c RW	447
26599a94 PM	448	data = irq_get_irq_data(irq);
26599a94 PM	449	chip = irq_data_get_irq_chip(data);
2be6bb0c PM	450	/*
	451	* This will catch the redirect and VIRQ cases
	452	* due to the dummy_irq_chip being inserted.
	453	*/
26599a94	454	if (chip != &d->chip)
2be6bb0c	455	continue;
a821b279	456	if (irqd_irq_disabled(data))
26599a94	457	chip->irq_disable(data);
2be6bb0c	458	else
26599a94	459	chip->irq_enable(data);
2be6bb0c	460	}
2be6bb0c	461	}
2be6bb0c PM	462	}
2be6bb0c PM	463
a696b89c RW	464	struct syscore_ops intc_syscore_ops = {
	465	.suspend = intc_suspend,
	466	.resume = intc_resume,
	467	};
2be6bb0c	468
f4e73bfc	469	struct bus_type intc_subsys = {
2be6bb0c	470	.name = "intc",
f4e73bfc	471	.dev_name = "intc",
2be6bb0c PM	472	};
2be6bb0c PM	473
a696b89c	474	static ssize_t
f4e73bfc	475	show_intc_name(struct device dev, struct device_attribute attr, char *buf)
a696b89c RW	476	{
	477	struct intc_desc_int *d;
	478
f4e73bfc	479	d = container_of(dev, struct intc_desc_int, dev);
a696b89c RW	480
	481	return sprintf(buf, "%s\n", d->chip.name);
	482	}
	483
f4e73bfc	484	static DEVICE_ATTR(name, S_IRUGO, show_intc_name, NULL);
a696b89c	485
f4e73bfc	486	static int __init register_intc_devs(void)
2be6bb0c PM	487	{
	488	struct intc_desc_int *d;
	489	int error;
	490
a696b89c RW	491	register_syscore_ops(&intc_syscore_ops);
a696b89c RW	492
f4e73bfc	493	error = subsys_system_register(&intc_subsys, NULL);
2be6bb0c PM	494	if (!error) {
2be6bb0c PM	495	list_for_each_entry(d, &intc_list, list) {
f4e73bfc KS	496	d->dev.id = d->index;
	497	d->dev.bus = &intc_subsys;
	498	error = device_register(&d->dev);
2be6bb0c	499	if (error == 0)
f4e73bfc KS	500	error = device_create_file(&d->dev,
f4e73bfc KS	501	&dev_attr_name);
2be6bb0c PM	502	if (error)
	503	break;
	504	}
	505	}
	506
	507	if (error)
f4e73bfc	508	pr_err("device registration error\n");
2be6bb0c PM	509
	510	return error;
	511	}
f4e73bfc	512	device_initcall(register_intc_devs);