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sh: Add KFR2R09 specific memory pre/post R-standby code
[deliverable/linux.git] / drivers / sh / intc.c
CommitLineData
02ab3f70
MD		 1/*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
d58876e2 4 * Copyright (C) 2007, 2008 Magnus Damm
02ab3f70
MD		 5 *
6 * Based on intc2.c and ipr.c
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/module.h>
21#include <linux/io.h>
22#include <linux/interrupt.h>
bbfbd8b1 23#include <linux/sh_intc.h>
2dcec7a9
MD		 24#include <linux/sysdev.h>
25#include <linux/list.h>
54ff328b 26#include <linux/topology.h>
73505b44
MD		 27
28#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
29 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
30 ((addr_e) << 16) | ((addr_d << 24)))
31
32#define _INTC_SHIFT(h) (h & 0x1f)
33#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
34#define _INTC_FN(h) ((h >> 9) & 0xf)
35#define _INTC_MODE(h) ((h >> 13) & 0x7)
36#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
37#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
38
39struct intc_handle_int {
40 unsigned int irq;
41 unsigned long handle;
42};
02ab3f70 43
73505b44 44struct intc_desc_int {
2dcec7a9
MD		 45 struct list_head list;
46 struct sys_device sysdev;
7fd87b3f 47 pm_message_t state;
73505b44 48 unsigned long *reg;
f18d533e
MD		 49#ifdef CONFIG_SMP
50 unsigned long *smp;
51#endif
73505b44
MD		 52 unsigned int nr_reg;
53 struct intc_handle_int *prio;
54 unsigned int nr_prio;
55 struct intc_handle_int *sense;
56 unsigned int nr_sense;
57 struct irq_chip chip;
58};
02ab3f70 59
2dcec7a9
MD		 60static LIST_HEAD(intc_list);
61
f18d533e
MD		 62#ifdef CONFIG_SMP
63#define IS_SMP(x) x.smp
64#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
65#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
66#else
67#define IS_SMP(x) 0
68#define INTC_REG(d, x, c) (d->reg[(x)])
69#define SMP_NR(d, x) 1
70#endif
71
73505b44 72static unsigned int intc_prio_level[NR_IRQS]; /* for now */
d58876e2 73static unsigned long ack_handle[NR_IRQS];
02ab3f70 74
73505b44 75static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
02ab3f70
MD		 76{
77 struct irq_chip *chip = get_irq_chip(irq);
6000fc4d 78 return container_of(chip, struct intc_desc_int, chip);
02ab3f70
MD		 79}
80
81static inline unsigned int set_field(unsigned int value,
82 unsigned int field_value,
73505b44 83 unsigned int handle)
02ab3f70 84{
73505b44
MD		 85 unsigned int width = _INTC_WIDTH(handle);
86 unsigned int shift = _INTC_SHIFT(handle);
87
02ab3f70
MD		 88 value &= ~(((1 << width) - 1) << shift);
89 value |= field_value << shift;
90 return value;
91}
92
73505b44 93static void write_8(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70 94{
62429e03 95 __raw_writeb(set_field(0, data, h), addr);
6000fc4d 96 (void)__raw_readb(addr); /* Defeat write posting */
02ab3f70
MD		 97}
98
73505b44 99static void write_16(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70 100{
62429e03 101 __raw_writew(set_field(0, data, h), addr);
6000fc4d 102 (void)__raw_readw(addr); /* Defeat write posting */
02ab3f70
MD		 103}
104
73505b44 105static void write_32(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70 106{
62429e03 107 __raw_writel(set_field(0, data, h), addr);
6000fc4d 108 (void)__raw_readl(addr); /* Defeat write posting */
02ab3f70
MD		 109}
110
73505b44 111static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70 112{
4370fe1c
MD		 113 unsigned long flags;
114 local_irq_save(flags);
62429e03 115 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
6000fc4d 116 (void)__raw_readb(addr); /* Defeat write posting */
4370fe1c 117 local_irq_restore(flags);
02ab3f70
MD		 118}
119
73505b44 120static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70 121{
4370fe1c
MD		 122 unsigned long flags;
123 local_irq_save(flags);
62429e03 124 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
6000fc4d 125 (void)__raw_readw(addr); /* Defeat write posting */
4370fe1c 126 local_irq_restore(flags);
02ab3f70
MD		 127}
128
73505b44 129static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70 130{
4370fe1c
MD		 131 unsigned long flags;
132 local_irq_save(flags);
62429e03 133 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
6000fc4d 134 (void)__raw_readl(addr); /* Defeat write posting */
4370fe1c 135 local_irq_restore(flags);
02ab3f70
MD		 136}
137
73505b44
MD		 138enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
139
140static void (*intc_reg_fns[])(unsigned long addr,
141 unsigned long h,
142 unsigned long data) = {
143 [REG_FN_WRITE_BASE + 0] = write_8,
144 [REG_FN_WRITE_BASE + 1] = write_16,
145 [REG_FN_WRITE_BASE + 3] = write_32,
146 [REG_FN_MODIFY_BASE + 0] = modify_8,
147 [REG_FN_MODIFY_BASE + 1] = modify_16,
148 [REG_FN_MODIFY_BASE + 3] = modify_32,
149};
02ab3f70 150
73505b44
MD		 151enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
152 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
153 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
154 MODE_PRIO_REG, /* Priority value written to enable interrupt */
155 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
156};
02ab3f70 157
73505b44
MD		 158static void intc_mode_field(unsigned long addr,
159 unsigned long handle,
160 void (*fn)(unsigned long,
161 unsigned long,
162 unsigned long),
163 unsigned int irq)
02ab3f70 164{
73505b44 165 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
02ab3f70
MD		 166}
167
73505b44
MD		 168static void intc_mode_zero(unsigned long addr,
169 unsigned long handle,
170 void (*fn)(unsigned long,
171 unsigned long,
172 unsigned long),
173 unsigned int irq)
51da6426 174{
73505b44 175 fn(addr, handle, 0);
51da6426
MD		 176}
177
73505b44
MD		 178static void intc_mode_prio(unsigned long addr,
179 unsigned long handle,
180 void (*fn)(unsigned long,
181 unsigned long,
182 unsigned long),
183 unsigned int irq)
51da6426 184{
73505b44 185 fn(addr, handle, intc_prio_level[irq]);
51da6426
MD		 186}
187
73505b44
MD		 188static void (*intc_enable_fns[])(unsigned long addr,
189 unsigned long handle,
190 void (*fn)(unsigned long,
191 unsigned long,
192 unsigned long),
193 unsigned int irq) = {
194 [MODE_ENABLE_REG] = intc_mode_field,
195 [MODE_MASK_REG] = intc_mode_zero,
196 [MODE_DUAL_REG] = intc_mode_field,
197 [MODE_PRIO_REG] = intc_mode_prio,
198 [MODE_PCLR_REG] = intc_mode_prio,
199};
51da6426 200
73505b44
MD		 201static void (*intc_disable_fns[])(unsigned long addr,
202 unsigned long handle,
203 void (*fn)(unsigned long,
204 unsigned long,
205 unsigned long),
206 unsigned int irq) = {
207 [MODE_ENABLE_REG] = intc_mode_zero,
208 [MODE_MASK_REG] = intc_mode_field,
209 [MODE_DUAL_REG] = intc_mode_field,
210 [MODE_PRIO_REG] = intc_mode_zero,
211 [MODE_PCLR_REG] = intc_mode_field,
212};
51da6426 213
73505b44 214static inline void _intc_enable(unsigned int irq, unsigned long handle)
51da6426 215{
73505b44 216 struct intc_desc_int *d = get_intc_desc(irq);
f18d533e
MD		 217 unsigned long addr;
218 unsigned int cpu;
51da6426 219
f18d533e
MD		 220 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
221 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
222 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
223 [_INTC_FN(handle)], irq);
224 }
51da6426
MD		 225}
226
02ab3f70
MD		 227static void intc_enable(unsigned int irq)
228{
73505b44 229 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
02ab3f70
MD		 230}
231
232static void intc_disable(unsigned int irq)
233{
f18d533e 234 struct intc_desc_int *d = get_intc_desc(irq);
73505b44 235 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
f18d533e
MD		 236 unsigned long addr;
237 unsigned int cpu;
02ab3f70 238
f18d533e
MD		 239 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
240 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
241 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
242 [_INTC_FN(handle)], irq);
243 }
02ab3f70
MD		 244}
245
2dcec7a9
MD		 246static int intc_set_wake(unsigned int irq, unsigned int on)
247{
248 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
249}
250
d58876e2
MD		 251static void intc_mask_ack(unsigned int irq)
252{
253 struct intc_desc_int *d = get_intc_desc(irq);
254 unsigned long handle = ack_handle[irq];
255 unsigned long addr;
256
257 intc_disable(irq);
258
259 /* read register and write zero only to the assocaited bit */
260
261 if (handle) {
262 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
6bdfb22a
YS		 263 switch (_INTC_FN(handle)) {
264 case REG_FN_MODIFY_BASE + 0: /* 8bit */
62429e03
PM		 265 __raw_readb(addr);
266 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
6bdfb22a
YS		 267 break;
268 case REG_FN_MODIFY_BASE + 1: /* 16bit */
62429e03
PM		 269 __raw_readw(addr);
270 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
6bdfb22a
YS		 271 break;
272 case REG_FN_MODIFY_BASE + 3: /* 32bit */
62429e03
PM		 273 __raw_readl(addr);
274 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
6bdfb22a
YS		 275 break;
276 default:
277 BUG();
278 break;
279 }
d58876e2
MD		 280 }
281}
d58876e2 282
73505b44
MD		 283static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
284 unsigned int nr_hp,
285 unsigned int irq)
02ab3f70 286{
73505b44
MD		 287 int i;
288
3d37d94e
MD		 289 /* this doesn't scale well, but...
290 *
291 * this function should only be used for cerain uncommon
292 * operations such as intc_set_priority() and intc_set_sense()
293 * and in those rare cases performance doesn't matter that much.
294 * keeping the memory footprint low is more important.
295 *
296 * one rather simple way to speed this up and still keep the
297 * memory footprint down is to make sure the array is sorted
298 * and then perform a bisect to lookup the irq.
299 */
300
73505b44
MD		 301 for (i = 0; i < nr_hp; i++) {
302 if ((hp + i)->irq != irq)
303 continue;
304
305 return hp + i;
306 }
02ab3f70 307
73505b44 308 return NULL;
02ab3f70
MD		 309}
310
73505b44 311int intc_set_priority(unsigned int irq, unsigned int prio)
02ab3f70 312{
73505b44
MD		 313 struct intc_desc_int *d = get_intc_desc(irq);
314 struct intc_handle_int *ihp;
315
316 if (!intc_prio_level[irq] || prio <= 1)
317 return -EINVAL;
318
319 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
320 if (ihp) {
3d37d94e 321 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
73505b44 322 return -EINVAL;
02ab3f70 323
73505b44
MD		 324 intc_prio_level[irq] = prio;
325
326 /*
327 * only set secondary masking method directly
328 * primary masking method is using intc_prio_level[irq]
329 * priority level will be set during next enable()
330 */
331
3d37d94e 332 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
73505b44
MD		 333 _intc_enable(irq, ihp->handle);
334 }
335 return 0;
02ab3f70
MD		 336}
337
338#define VALID(x) (x | 0x80)
339
340static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
341 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
342 [IRQ_TYPE_EDGE_RISING] = VALID(1),
343 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
720be990
MD		 344 /* SH7706, SH7707 and SH7709 do not support high level triggered */
345#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
346 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
347 !defined(CONFIG_CPU_SUBTYPE_SH7709)
02ab3f70 348 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
720be990 349#endif
02ab3f70
MD		 350};
351
352static int intc_set_sense(unsigned int irq, unsigned int type)
353{
73505b44 354 struct intc_desc_int *d = get_intc_desc(irq);
02ab3f70 355 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
73505b44
MD		 356 struct intc_handle_int *ihp;
357 unsigned long addr;
02ab3f70 358
73505b44 359 if (!value)
02ab3f70
MD		 360 return -EINVAL;
361
73505b44
MD		 362 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
363 if (ihp) {
f18d533e 364 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
73505b44 365 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
02ab3f70 366 }
73505b44 367 return 0;
02ab3f70
MD		 368}
369
73505b44
MD		 370static unsigned int __init intc_get_reg(struct intc_desc_int *d,
371 unsigned long address)
02ab3f70 372{
73505b44 373 unsigned int k;
02ab3f70 374
73505b44
MD		 375 for (k = 0; k < d->nr_reg; k++) {
376 if (d->reg[k] == address)
377 return k;
51da6426
MD		 378 }
379
380 BUG();
73505b44 381 return 0;
51da6426
MD		 382}
383
73505b44
MD		 384static intc_enum __init intc_grp_id(struct intc_desc *desc,
385 intc_enum enum_id)
680c4598
MD		 386{
387 struct intc_group *g = desc->groups;
388 unsigned int i, j;
389
390 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
391 g = desc->groups + i;
392
393 for (j = 0; g->enum_ids[j]; j++) {
394 if (g->enum_ids[j] != enum_id)
395 continue;
396
397 return g->enum_id;
398 }
399 }
400
401 return 0;
402}
403
02ab3f70 404static unsigned int __init intc_mask_data(struct intc_desc *desc,
73505b44 405 struct intc_desc_int *d,
680c4598 406 intc_enum enum_id, int do_grps)
02ab3f70 407{
680c4598 408 struct intc_mask_reg *mr = desc->mask_regs;
73505b44
MD		 409 unsigned int i, j, fn, mode;
410 unsigned long reg_e, reg_d;
02ab3f70 411
680c4598
MD		 412 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
413 mr = desc->mask_regs + i;
02ab3f70
MD		 414
415 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
416 if (mr->enum_ids[j] != enum_id)
417 continue;
418
73505b44
MD		 419 if (mr->set_reg && mr->clr_reg) {
420 fn = REG_FN_WRITE_BASE;
421 mode = MODE_DUAL_REG;
422 reg_e = mr->clr_reg;
423 reg_d = mr->set_reg;
424 } else {
425 fn = REG_FN_MODIFY_BASE;
426 if (mr->set_reg) {
427 mode = MODE_ENABLE_REG;
428 reg_e = mr->set_reg;
429 reg_d = mr->set_reg;
430 } else {
431 mode = MODE_MASK_REG;
432 reg_e = mr->clr_reg;
433 reg_d = mr->clr_reg;
434 }
51da6426
MD		 435 }
436
73505b44
MD		 437 fn += (mr->reg_width >> 3) - 1;
438 return _INTC_MK(fn, mode,
439 intc_get_reg(d, reg_e),
440 intc_get_reg(d, reg_d),
441 1,
442 (mr->reg_width - 1) - j);
02ab3f70
MD		 443 }
444 }
445
680c4598 446 if (do_grps)
73505b44 447 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
680c4598 448
02ab3f70
MD		 449 return 0;
450}
451
452static unsigned int __init intc_prio_data(struct intc_desc *desc,
73505b44 453 struct intc_desc_int *d,
680c4598 454 intc_enum enum_id, int do_grps)
02ab3f70 455{
680c4598 456 struct intc_prio_reg *pr = desc->prio_regs;
73505b44
MD		 457 unsigned int i, j, fn, mode, bit;
458 unsigned long reg_e, reg_d;
02ab3f70 459
680c4598
MD		 460 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
461 pr = desc->prio_regs + i;
02ab3f70
MD		 462
463 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
464 if (pr->enum_ids[j] != enum_id)
465 continue;
466
73505b44
MD		 467 if (pr->set_reg && pr->clr_reg) {
468 fn = REG_FN_WRITE_BASE;
469 mode = MODE_PCLR_REG;
470 reg_e = pr->set_reg;
471 reg_d = pr->clr_reg;
472 } else {
473 fn = REG_FN_MODIFY_BASE;
474 mode = MODE_PRIO_REG;
475 if (!pr->set_reg)
476 BUG();
477 reg_e = pr->set_reg;
478 reg_d = pr->set_reg;
479 }
02ab3f70 480
73505b44 481 fn += (pr->reg_width >> 3) - 1;
02ab3f70 482
b21a9104 483 BUG_ON((j + 1) * pr->field_width > pr->reg_width);
484
485 bit = pr->reg_width - ((j + 1) * pr->field_width);
02ab3f70 486
73505b44
MD		 487 return _INTC_MK(fn, mode,
488 intc_get_reg(d, reg_e),
489 intc_get_reg(d, reg_d),
490 pr->field_width, bit);
02ab3f70
MD		 491 }
492 }
493
680c4598 494 if (do_grps)
73505b44
MD		 495 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
496
497 return 0;
498}
499
d58876e2
MD		 500static unsigned int __init intc_ack_data(struct intc_desc *desc,
501 struct intc_desc_int *d,
502 intc_enum enum_id)
503{
504 struct intc_mask_reg *mr = desc->ack_regs;
505 unsigned int i, j, fn, mode;
506 unsigned long reg_e, reg_d;
507
508 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
509 mr = desc->ack_regs + i;
510
511 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
512 if (mr->enum_ids[j] != enum_id)
513 continue;
514
515 fn = REG_FN_MODIFY_BASE;
516 mode = MODE_ENABLE_REG;
517 reg_e = mr->set_reg;
518 reg_d = mr->set_reg;
519
520 fn += (mr->reg_width >> 3) - 1;
521 return _INTC_MK(fn, mode,
522 intc_get_reg(d, reg_e),
523 intc_get_reg(d, reg_d),
524 1,
525 (mr->reg_width - 1) - j);
526 }
527 }
528
529 return 0;
530}
d58876e2 531
73505b44
MD		 532static unsigned int __init intc_sense_data(struct intc_desc *desc,
533 struct intc_desc_int *d,
534 intc_enum enum_id)
535{
536 struct intc_sense_reg *sr = desc->sense_regs;
537 unsigned int i, j, fn, bit;
538
539 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
540 sr = desc->sense_regs + i;
541
542 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
543 if (sr->enum_ids[j] != enum_id)
544 continue;
545
546 fn = REG_FN_MODIFY_BASE;
547 fn += (sr->reg_width >> 3) - 1;
73505b44 548
b21a9104 549 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
550
551 bit = sr->reg_width - ((j + 1) * sr->field_width);
73505b44
MD		 552
553 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
554 0, sr->field_width, bit);
555 }
556 }
680c4598 557
02ab3f70
MD		 558 return 0;
559}
560
73505b44
MD		 561static void __init intc_register_irq(struct intc_desc *desc,
562 struct intc_desc_int *d,
563 intc_enum enum_id,
02ab3f70
MD		 564 unsigned int irq)
565{
3d37d94e 566 struct intc_handle_int *hp;
680c4598
MD		 567 unsigned int data[2], primary;
568
569 /* Prefer single interrupt source bitmap over other combinations:
570 * 1. bitmap, single interrupt source
571 * 2. priority, single interrupt source
572 * 3. bitmap, multiple interrupt sources (groups)
573 * 4. priority, multiple interrupt sources (groups)
574 */
02ab3f70 575
73505b44
MD		 576 data[0] = intc_mask_data(desc, d, enum_id, 0);
577 data[1] = intc_prio_data(desc, d, enum_id, 0);
680c4598
MD		 578
579 primary = 0;
580 if (!data[0] && data[1])
581 primary = 1;
582
bdaa6e80 583 if (!data[0] && !data[1])
f033599a
PM		 584 pr_warning("intc: missing unique irq mask for "
585 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
bdaa6e80 586
73505b44
MD		 587 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
588 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
680c4598
MD		 589
590 if (!data[primary])
591 primary ^= 1;
592
593 BUG_ON(!data[primary]); /* must have primary masking method */
02ab3f70
MD		 594
595 disable_irq_nosync(irq);
73505b44 596 set_irq_chip_and_handler_name(irq, &d->chip,
02ab3f70 597 handle_level_irq, "level");
680c4598 598 set_irq_chip_data(irq, (void *)data[primary]);
02ab3f70 599
7f3edee8
MD		 600 /* set priority level
601 * - this needs to be at least 2 for 5-bit priorities on 7780
602 */
603 intc_prio_level[irq] = 2;
73505b44 604
680c4598
MD		 605 /* enable secondary masking method if present */
606 if (data[!primary])
73505b44
MD		 607 _intc_enable(irq, data[!primary]);
608
609 /* add irq to d->prio list if priority is available */
610 if (data[1]) {
3d37d94e
MD		 611 hp = d->prio + d->nr_prio;
612 hp->irq = irq;
613 hp->handle = data[1];
614
615 if (primary) {
616 /*
617 * only secondary priority should access registers, so
618 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
619 */
620
621 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
622 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
623 }
73505b44
MD		 624 d->nr_prio++;
625 }
626
627 /* add irq to d->sense list if sense is available */
628 data[0] = intc_sense_data(desc, d, enum_id);
629 if (data[0]) {
630 (d->sense + d->nr_sense)->irq = irq;
631 (d->sense + d->nr_sense)->handle = data[0];
632 d->nr_sense++;
633 }
02ab3f70
MD		 634
635 /* irq should be disabled by default */
73505b44 636 d->chip.mask(irq);
d58876e2 637
d58876e2
MD		 638 if (desc->ack_regs)
639 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
02ab3f70
MD		 640}
641
f18d533e
MD		 642static unsigned int __init save_reg(struct intc_desc_int *d,
643 unsigned int cnt,
644 unsigned long value,
645 unsigned int smp)
646{
647 if (value) {
648 d->reg[cnt] = value;
649#ifdef CONFIG_SMP
650 d->smp[cnt] = smp;
651#endif
652 return 1;
653 }
654
655 return 0;
656}
657
05ecd5a1 658static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
bdaa6e80 659{
05ecd5a1 660 generic_handle_irq((unsigned int)get_irq_data(irq));
bdaa6e80 661}
f18d533e 662
02ab3f70
MD		 663void __init register_intc_controller(struct intc_desc *desc)
664{
54ff328b 665 unsigned int i, k, smp;
73505b44
MD		 666 struct intc_desc_int *d;
667
11b6aa95 668 d = kzalloc(sizeof(*d), GFP_NOWAIT);
73505b44 669
2dcec7a9
MD		 670 INIT_LIST_HEAD(&d->list);
671 list_add(&d->list, &intc_list);
672
73505b44
MD		 673 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
674 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
675 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
d58876e2 676 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
9b798d50 677
11b6aa95 678 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
f18d533e 679#ifdef CONFIG_SMP
11b6aa95 680 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
f18d533e 681#endif
73505b44
MD		 682 k = 0;
683
684 if (desc->mask_regs) {
685 for (i = 0; i < desc->nr_mask_regs; i++) {
f18d533e
MD		 686 smp = IS_SMP(desc->mask_regs[i]);
687 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
688 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
73505b44
MD		 689 }
690 }
691
692 if (desc->prio_regs) {
11b6aa95 693 d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT);
73505b44
MD		 694
695 for (i = 0; i < desc->nr_prio_regs; i++) {
f18d533e
MD		 696 smp = IS_SMP(desc->prio_regs[i]);
697 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
698 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
73505b44
MD		 699 }
700 }
701
702 if (desc->sense_regs) {
11b6aa95 703 d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT);
73505b44
MD		 704
705 for (i = 0; i < desc->nr_sense_regs; i++) {
f18d533e 706 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
73505b44
MD		 707 }
708 }
709
73505b44
MD		 710 d->chip.name = desc->name;
711 d->chip.mask = intc_disable;
712 d->chip.unmask = intc_enable;
713 d->chip.mask_ack = intc_disable;
f7dd2548
MD		 714 d->chip.enable = intc_enable;
715 d->chip.disable = intc_disable;
716 d->chip.shutdown = intc_disable;
73505b44 717 d->chip.set_type = intc_set_sense;
2dcec7a9 718 d->chip.set_wake = intc_set_wake;
02ab3f70 719
d58876e2
MD		 720 if (desc->ack_regs) {
721 for (i = 0; i < desc->nr_ack_regs; i++)
722 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
723
724 d->chip.mask_ack = intc_mask_ack;
725 }
d58876e2
MD		 726
727 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
728
bdaa6e80 729 /* register the vectors one by one */
02ab3f70
MD		 730 for (i = 0; i < desc->nr_vectors; i++) {
731 struct intc_vect *vect = desc->vectors + i;
05ff3004
PM		 732 unsigned int irq = evt2irq(vect->vect);
733 struct irq_desc *irq_desc;
54ff328b 734
bdaa6e80
MD		 735 if (!vect->enum_id)
736 continue;
737
54ff328b 738 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
05ff3004 739 if (unlikely(!irq_desc)) {
1279b7f1 740 pr_info("can't get irq_desc for %d\n", irq);
05ff3004
PM		 741 continue;
742 }
743
744 intc_register_irq(desc, d, vect->enum_id, irq);
05ecd5a1
PM		 745
746 for (k = i + 1; k < desc->nr_vectors; k++) {
747 struct intc_vect *vect2 = desc->vectors + k;
748 unsigned int irq2 = evt2irq(vect2->vect);
749
750 if (vect->enum_id != vect2->enum_id)
751 continue;
752
1279b7f1
PM		 753 /*
754 * In the case of multi-evt handling and sparse
755 * IRQ support, each vector still needs to have
756 * its own backing irq_desc.
757 */
758 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
759 if (unlikely(!irq_desc)) {
760 pr_info("can't get irq_desc for %d\n", irq2);
761 continue;
762 }
763
05ecd5a1
PM		 764 vect2->enum_id = 0;
765
766 /* redirect this interrupts to the first one */
767 set_irq_chip_and_handler_name(irq2, &d->chip,
768 intc_redirect_irq, "redirect");
769 set_irq_data(irq2, (void *)irq);
770 }
02ab3f70
MD		 771 }
772}
2dcec7a9
MD		 773
774static int intc_suspend(struct sys_device *dev, pm_message_t state)
775{
776 struct intc_desc_int *d;
777 struct irq_desc *desc;
778 int irq;
779
780 /* get intc controller associated with this sysdev */
781 d = container_of(dev, struct intc_desc_int, sysdev);
782
7fd87b3f
FV		 783 switch (state.event) {
784 case PM_EVENT_ON:
785 if (d->state.event != PM_EVENT_FREEZE)
786 break;
787 for_each_irq_desc(irq, desc) {
788 if (desc->chip != &d->chip)
789 continue;
790 if (desc->status & IRQ_DISABLED)
791 intc_disable(irq);
792 else
793 intc_enable(irq);
794 }
795 break;
796 case PM_EVENT_FREEZE:
797 /* nothing has to be done */
798 break;
799 case PM_EVENT_SUSPEND:
800 /* enable wakeup irqs belonging to this intc controller */
801 for_each_irq_desc(irq, desc) {
802 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
803 intc_enable(irq);
804 }
805 break;
2dcec7a9 806 }
7fd87b3f 807 d->state = state;
2dcec7a9
MD		 808
809 return 0;
810}
811
7fd87b3f
FV		 812static int intc_resume(struct sys_device *dev)
813{
814 return intc_suspend(dev, PMSG_ON);
815}
816
2dcec7a9
MD		 817static struct sysdev_class intc_sysdev_class = {
818 .name = "intc",
819 .suspend = intc_suspend,
7fd87b3f 820 .resume = intc_resume,
2dcec7a9
MD		 821};
822
823/* register this intc as sysdev to allow suspend/resume */
824static int __init register_intc_sysdevs(void)
825{
826 struct intc_desc_int *d;
827 int error;
828 int id = 0;
829
830 error = sysdev_class_register(&intc_sysdev_class);
831 if (!error) {
832 list_for_each_entry(d, &intc_list, list) {
833 d->sysdev.id = id;
834 d->sysdev.cls = &intc_sysdev_class;
835 error = sysdev_register(&d->sysdev);
836 if (error)
837 break;
838 id++;
839 }
840 }
841
842 if (error)
843 pr_warning("intc: sysdev registration error\n");
844
845 return error;
846}
847
848device_initcall(register_intc_sysdevs);
Linux kernel - Deliverables
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