Commit | Line | Data |
---|---|---|
02ab3f70 MD |
1 | /* |
2 | * Shared interrupt handling code for IPR and INTC2 types of IRQs. | |
3 | * | |
d58876e2 | 4 | * Copyright (C) 2007, 2008 Magnus Damm |
1ce7b039 | 5 | * Copyright (C) 2009 Paul Mundt |
02ab3f70 MD |
6 | * |
7 | * Based on intc2.c and ipr.c | |
8 | * | |
9 | * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi | |
10 | * Copyright (C) 2000 Kazumoto Kojima | |
11 | * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) | |
12 | * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> | |
13 | * Copyright (C) 2005, 2006 Paul Mundt | |
14 | * | |
15 | * This file is subject to the terms and conditions of the GNU General Public | |
16 | * License. See the file "COPYING" in the main directory of this archive | |
17 | * for more details. | |
18 | */ | |
19 | #include <linux/init.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/interrupt.h> | |
bbfbd8b1 | 24 | #include <linux/sh_intc.h> |
2dcec7a9 MD |
25 | #include <linux/sysdev.h> |
26 | #include <linux/list.h> | |
54ff328b | 27 | #include <linux/topology.h> |
1ce7b039 | 28 | #include <linux/bitmap.h> |
73505b44 MD |
29 | |
30 | #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \ | |
31 | ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \ | |
32 | ((addr_e) << 16) | ((addr_d << 24))) | |
33 | ||
34 | #define _INTC_SHIFT(h) (h & 0x1f) | |
35 | #define _INTC_WIDTH(h) ((h >> 5) & 0xf) | |
36 | #define _INTC_FN(h) ((h >> 9) & 0xf) | |
37 | #define _INTC_MODE(h) ((h >> 13) & 0x7) | |
38 | #define _INTC_ADDR_E(h) ((h >> 16) & 0xff) | |
39 | #define _INTC_ADDR_D(h) ((h >> 24) & 0xff) | |
40 | ||
41 | struct intc_handle_int { | |
42 | unsigned int irq; | |
43 | unsigned long handle; | |
44 | }; | |
02ab3f70 | 45 | |
73505b44 | 46 | struct intc_desc_int { |
2dcec7a9 MD |
47 | struct list_head list; |
48 | struct sys_device sysdev; | |
7fd87b3f | 49 | pm_message_t state; |
73505b44 | 50 | unsigned long *reg; |
f18d533e MD |
51 | #ifdef CONFIG_SMP |
52 | unsigned long *smp; | |
53 | #endif | |
73505b44 MD |
54 | unsigned int nr_reg; |
55 | struct intc_handle_int *prio; | |
56 | unsigned int nr_prio; | |
57 | struct intc_handle_int *sense; | |
58 | unsigned int nr_sense; | |
59 | struct irq_chip chip; | |
60 | }; | |
02ab3f70 | 61 | |
2dcec7a9 MD |
62 | static LIST_HEAD(intc_list); |
63 | ||
1ce7b039 PM |
64 | /* |
65 | * The intc_irq_map provides a global map of bound IRQ vectors for a | |
66 | * given platform. Allocation of IRQs are either static through the CPU | |
67 | * vector map, or dynamic in the case of board mux vectors or MSI. | |
68 | * | |
69 | * As this is a central point for all IRQ controllers on the system, | |
70 | * each of the available sources are mapped out here. This combined with | |
71 | * sparseirq makes it quite trivial to keep the vector map tightly packed | |
72 | * when dynamically creating IRQs, as well as tying in to otherwise | |
73 | * unused irq_desc positions in the sparse array. | |
74 | */ | |
75 | static DECLARE_BITMAP(intc_irq_map, NR_IRQS); | |
76 | static DEFINE_SPINLOCK(vector_lock); | |
77 | ||
f18d533e MD |
78 | #ifdef CONFIG_SMP |
79 | #define IS_SMP(x) x.smp | |
80 | #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c)) | |
81 | #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1) | |
82 | #else | |
83 | #define IS_SMP(x) 0 | |
84 | #define INTC_REG(d, x, c) (d->reg[(x)]) | |
85 | #define SMP_NR(d, x) 1 | |
86 | #endif | |
87 | ||
73505b44 | 88 | static unsigned int intc_prio_level[NR_IRQS]; /* for now */ |
d58876e2 | 89 | static unsigned long ack_handle[NR_IRQS]; |
02ab3f70 | 90 | |
73505b44 | 91 | static inline struct intc_desc_int *get_intc_desc(unsigned int irq) |
02ab3f70 MD |
92 | { |
93 | struct irq_chip *chip = get_irq_chip(irq); | |
6000fc4d | 94 | return container_of(chip, struct intc_desc_int, chip); |
02ab3f70 MD |
95 | } |
96 | ||
97 | static inline unsigned int set_field(unsigned int value, | |
98 | unsigned int field_value, | |
73505b44 | 99 | unsigned int handle) |
02ab3f70 | 100 | { |
73505b44 MD |
101 | unsigned int width = _INTC_WIDTH(handle); |
102 | unsigned int shift = _INTC_SHIFT(handle); | |
103 | ||
02ab3f70 MD |
104 | value &= ~(((1 << width) - 1) << shift); |
105 | value |= field_value << shift; | |
106 | return value; | |
107 | } | |
108 | ||
73505b44 | 109 | static void write_8(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 110 | { |
62429e03 | 111 | __raw_writeb(set_field(0, data, h), addr); |
6000fc4d | 112 | (void)__raw_readb(addr); /* Defeat write posting */ |
02ab3f70 MD |
113 | } |
114 | ||
73505b44 | 115 | static void write_16(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 116 | { |
62429e03 | 117 | __raw_writew(set_field(0, data, h), addr); |
6000fc4d | 118 | (void)__raw_readw(addr); /* Defeat write posting */ |
02ab3f70 MD |
119 | } |
120 | ||
73505b44 | 121 | static void write_32(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 122 | { |
62429e03 | 123 | __raw_writel(set_field(0, data, h), addr); |
6000fc4d | 124 | (void)__raw_readl(addr); /* Defeat write posting */ |
02ab3f70 MD |
125 | } |
126 | ||
73505b44 | 127 | static void modify_8(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 128 | { |
4370fe1c MD |
129 | unsigned long flags; |
130 | local_irq_save(flags); | |
62429e03 | 131 | __raw_writeb(set_field(__raw_readb(addr), data, h), addr); |
6000fc4d | 132 | (void)__raw_readb(addr); /* Defeat write posting */ |
4370fe1c | 133 | local_irq_restore(flags); |
02ab3f70 MD |
134 | } |
135 | ||
73505b44 | 136 | static void modify_16(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 137 | { |
4370fe1c MD |
138 | unsigned long flags; |
139 | local_irq_save(flags); | |
62429e03 | 140 | __raw_writew(set_field(__raw_readw(addr), data, h), addr); |
6000fc4d | 141 | (void)__raw_readw(addr); /* Defeat write posting */ |
4370fe1c | 142 | local_irq_restore(flags); |
02ab3f70 MD |
143 | } |
144 | ||
73505b44 | 145 | static void modify_32(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 146 | { |
4370fe1c MD |
147 | unsigned long flags; |
148 | local_irq_save(flags); | |
62429e03 | 149 | __raw_writel(set_field(__raw_readl(addr), data, h), addr); |
6000fc4d | 150 | (void)__raw_readl(addr); /* Defeat write posting */ |
4370fe1c | 151 | local_irq_restore(flags); |
02ab3f70 MD |
152 | } |
153 | ||
73505b44 MD |
154 | enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 }; |
155 | ||
156 | static void (*intc_reg_fns[])(unsigned long addr, | |
157 | unsigned long h, | |
158 | unsigned long data) = { | |
159 | [REG_FN_WRITE_BASE + 0] = write_8, | |
160 | [REG_FN_WRITE_BASE + 1] = write_16, | |
161 | [REG_FN_WRITE_BASE + 3] = write_32, | |
162 | [REG_FN_MODIFY_BASE + 0] = modify_8, | |
163 | [REG_FN_MODIFY_BASE + 1] = modify_16, | |
164 | [REG_FN_MODIFY_BASE + 3] = modify_32, | |
165 | }; | |
02ab3f70 | 166 | |
73505b44 MD |
167 | enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */ |
168 | MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */ | |
169 | MODE_DUAL_REG, /* Two registers, set bit to enable / disable */ | |
170 | MODE_PRIO_REG, /* Priority value written to enable interrupt */ | |
171 | MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */ | |
172 | }; | |
02ab3f70 | 173 | |
73505b44 MD |
174 | static void intc_mode_field(unsigned long addr, |
175 | unsigned long handle, | |
176 | void (*fn)(unsigned long, | |
177 | unsigned long, | |
178 | unsigned long), | |
179 | unsigned int irq) | |
02ab3f70 | 180 | { |
73505b44 | 181 | fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1)); |
02ab3f70 MD |
182 | } |
183 | ||
73505b44 MD |
184 | static void intc_mode_zero(unsigned long addr, |
185 | unsigned long handle, | |
186 | void (*fn)(unsigned long, | |
187 | unsigned long, | |
188 | unsigned long), | |
189 | unsigned int irq) | |
51da6426 | 190 | { |
73505b44 | 191 | fn(addr, handle, 0); |
51da6426 MD |
192 | } |
193 | ||
73505b44 MD |
194 | static void intc_mode_prio(unsigned long addr, |
195 | unsigned long handle, | |
196 | void (*fn)(unsigned long, | |
197 | unsigned long, | |
198 | unsigned long), | |
199 | unsigned int irq) | |
51da6426 | 200 | { |
73505b44 | 201 | fn(addr, handle, intc_prio_level[irq]); |
51da6426 MD |
202 | } |
203 | ||
73505b44 MD |
204 | static void (*intc_enable_fns[])(unsigned long addr, |
205 | unsigned long handle, | |
206 | void (*fn)(unsigned long, | |
207 | unsigned long, | |
208 | unsigned long), | |
209 | unsigned int irq) = { | |
210 | [MODE_ENABLE_REG] = intc_mode_field, | |
211 | [MODE_MASK_REG] = intc_mode_zero, | |
212 | [MODE_DUAL_REG] = intc_mode_field, | |
213 | [MODE_PRIO_REG] = intc_mode_prio, | |
214 | [MODE_PCLR_REG] = intc_mode_prio, | |
215 | }; | |
51da6426 | 216 | |
73505b44 MD |
217 | static void (*intc_disable_fns[])(unsigned long addr, |
218 | unsigned long handle, | |
219 | void (*fn)(unsigned long, | |
220 | unsigned long, | |
221 | unsigned long), | |
222 | unsigned int irq) = { | |
223 | [MODE_ENABLE_REG] = intc_mode_zero, | |
224 | [MODE_MASK_REG] = intc_mode_field, | |
225 | [MODE_DUAL_REG] = intc_mode_field, | |
226 | [MODE_PRIO_REG] = intc_mode_zero, | |
227 | [MODE_PCLR_REG] = intc_mode_field, | |
228 | }; | |
51da6426 | 229 | |
73505b44 | 230 | static inline void _intc_enable(unsigned int irq, unsigned long handle) |
51da6426 | 231 | { |
73505b44 | 232 | struct intc_desc_int *d = get_intc_desc(irq); |
f18d533e MD |
233 | unsigned long addr; |
234 | unsigned int cpu; | |
51da6426 | 235 | |
f18d533e MD |
236 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { |
237 | addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); | |
238 | intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\ | |
239 | [_INTC_FN(handle)], irq); | |
240 | } | |
51da6426 MD |
241 | } |
242 | ||
02ab3f70 MD |
243 | static void intc_enable(unsigned int irq) |
244 | { | |
73505b44 | 245 | _intc_enable(irq, (unsigned long)get_irq_chip_data(irq)); |
02ab3f70 MD |
246 | } |
247 | ||
248 | static void intc_disable(unsigned int irq) | |
249 | { | |
f18d533e | 250 | struct intc_desc_int *d = get_intc_desc(irq); |
73505b44 | 251 | unsigned long handle = (unsigned long) get_irq_chip_data(irq); |
f18d533e MD |
252 | unsigned long addr; |
253 | unsigned int cpu; | |
02ab3f70 | 254 | |
f18d533e MD |
255 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { |
256 | addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); | |
257 | intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\ | |
258 | [_INTC_FN(handle)], irq); | |
259 | } | |
02ab3f70 MD |
260 | } |
261 | ||
2dcec7a9 MD |
262 | static int intc_set_wake(unsigned int irq, unsigned int on) |
263 | { | |
264 | return 0; /* allow wakeup, but setup hardware in intc_suspend() */ | |
265 | } | |
266 | ||
d58876e2 MD |
267 | static void intc_mask_ack(unsigned int irq) |
268 | { | |
269 | struct intc_desc_int *d = get_intc_desc(irq); | |
270 | unsigned long handle = ack_handle[irq]; | |
271 | unsigned long addr; | |
272 | ||
273 | intc_disable(irq); | |
274 | ||
275 | /* read register and write zero only to the assocaited bit */ | |
276 | ||
277 | if (handle) { | |
278 | addr = INTC_REG(d, _INTC_ADDR_D(handle), 0); | |
6bdfb22a YS |
279 | switch (_INTC_FN(handle)) { |
280 | case REG_FN_MODIFY_BASE + 0: /* 8bit */ | |
62429e03 PM |
281 | __raw_readb(addr); |
282 | __raw_writeb(0xff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
283 | break; |
284 | case REG_FN_MODIFY_BASE + 1: /* 16bit */ | |
62429e03 PM |
285 | __raw_readw(addr); |
286 | __raw_writew(0xffff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
287 | break; |
288 | case REG_FN_MODIFY_BASE + 3: /* 32bit */ | |
62429e03 PM |
289 | __raw_readl(addr); |
290 | __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
291 | break; |
292 | default: | |
293 | BUG(); | |
294 | break; | |
295 | } | |
d58876e2 MD |
296 | } |
297 | } | |
d58876e2 | 298 | |
73505b44 MD |
299 | static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp, |
300 | unsigned int nr_hp, | |
301 | unsigned int irq) | |
02ab3f70 | 302 | { |
73505b44 MD |
303 | int i; |
304 | ||
3d37d94e MD |
305 | /* this doesn't scale well, but... |
306 | * | |
307 | * this function should only be used for cerain uncommon | |
308 | * operations such as intc_set_priority() and intc_set_sense() | |
309 | * and in those rare cases performance doesn't matter that much. | |
310 | * keeping the memory footprint low is more important. | |
311 | * | |
312 | * one rather simple way to speed this up and still keep the | |
313 | * memory footprint down is to make sure the array is sorted | |
314 | * and then perform a bisect to lookup the irq. | |
315 | */ | |
316 | ||
73505b44 MD |
317 | for (i = 0; i < nr_hp; i++) { |
318 | if ((hp + i)->irq != irq) | |
319 | continue; | |
320 | ||
321 | return hp + i; | |
322 | } | |
02ab3f70 | 323 | |
73505b44 | 324 | return NULL; |
02ab3f70 MD |
325 | } |
326 | ||
73505b44 | 327 | int intc_set_priority(unsigned int irq, unsigned int prio) |
02ab3f70 | 328 | { |
73505b44 MD |
329 | struct intc_desc_int *d = get_intc_desc(irq); |
330 | struct intc_handle_int *ihp; | |
331 | ||
332 | if (!intc_prio_level[irq] || prio <= 1) | |
333 | return -EINVAL; | |
334 | ||
335 | ihp = intc_find_irq(d->prio, d->nr_prio, irq); | |
336 | if (ihp) { | |
3d37d94e | 337 | if (prio >= (1 << _INTC_WIDTH(ihp->handle))) |
73505b44 | 338 | return -EINVAL; |
02ab3f70 | 339 | |
73505b44 MD |
340 | intc_prio_level[irq] = prio; |
341 | ||
342 | /* | |
343 | * only set secondary masking method directly | |
344 | * primary masking method is using intc_prio_level[irq] | |
345 | * priority level will be set during next enable() | |
346 | */ | |
347 | ||
3d37d94e | 348 | if (_INTC_FN(ihp->handle) != REG_FN_ERR) |
73505b44 MD |
349 | _intc_enable(irq, ihp->handle); |
350 | } | |
351 | return 0; | |
02ab3f70 MD |
352 | } |
353 | ||
354 | #define VALID(x) (x | 0x80) | |
355 | ||
356 | static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { | |
357 | [IRQ_TYPE_EDGE_FALLING] = VALID(0), | |
358 | [IRQ_TYPE_EDGE_RISING] = VALID(1), | |
359 | [IRQ_TYPE_LEVEL_LOW] = VALID(2), | |
720be990 MD |
360 | /* SH7706, SH7707 and SH7709 do not support high level triggered */ |
361 | #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \ | |
362 | !defined(CONFIG_CPU_SUBTYPE_SH7707) && \ | |
363 | !defined(CONFIG_CPU_SUBTYPE_SH7709) | |
02ab3f70 | 364 | [IRQ_TYPE_LEVEL_HIGH] = VALID(3), |
720be990 | 365 | #endif |
02ab3f70 MD |
366 | }; |
367 | ||
368 | static int intc_set_sense(unsigned int irq, unsigned int type) | |
369 | { | |
73505b44 | 370 | struct intc_desc_int *d = get_intc_desc(irq); |
02ab3f70 | 371 | unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK]; |
73505b44 MD |
372 | struct intc_handle_int *ihp; |
373 | unsigned long addr; | |
02ab3f70 | 374 | |
73505b44 | 375 | if (!value) |
02ab3f70 MD |
376 | return -EINVAL; |
377 | ||
73505b44 MD |
378 | ihp = intc_find_irq(d->sense, d->nr_sense, irq); |
379 | if (ihp) { | |
f18d533e | 380 | addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0); |
73505b44 | 381 | intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value); |
02ab3f70 | 382 | } |
73505b44 | 383 | return 0; |
02ab3f70 MD |
384 | } |
385 | ||
73505b44 MD |
386 | static unsigned int __init intc_get_reg(struct intc_desc_int *d, |
387 | unsigned long address) | |
02ab3f70 | 388 | { |
73505b44 | 389 | unsigned int k; |
02ab3f70 | 390 | |
73505b44 MD |
391 | for (k = 0; k < d->nr_reg; k++) { |
392 | if (d->reg[k] == address) | |
393 | return k; | |
51da6426 MD |
394 | } |
395 | ||
396 | BUG(); | |
73505b44 | 397 | return 0; |
51da6426 MD |
398 | } |
399 | ||
73505b44 MD |
400 | static intc_enum __init intc_grp_id(struct intc_desc *desc, |
401 | intc_enum enum_id) | |
680c4598 MD |
402 | { |
403 | struct intc_group *g = desc->groups; | |
404 | unsigned int i, j; | |
405 | ||
406 | for (i = 0; g && enum_id && i < desc->nr_groups; i++) { | |
407 | g = desc->groups + i; | |
408 | ||
409 | for (j = 0; g->enum_ids[j]; j++) { | |
410 | if (g->enum_ids[j] != enum_id) | |
411 | continue; | |
412 | ||
413 | return g->enum_id; | |
414 | } | |
415 | } | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
02ab3f70 | 420 | static unsigned int __init intc_mask_data(struct intc_desc *desc, |
73505b44 | 421 | struct intc_desc_int *d, |
680c4598 | 422 | intc_enum enum_id, int do_grps) |
02ab3f70 | 423 | { |
680c4598 | 424 | struct intc_mask_reg *mr = desc->mask_regs; |
73505b44 MD |
425 | unsigned int i, j, fn, mode; |
426 | unsigned long reg_e, reg_d; | |
02ab3f70 | 427 | |
680c4598 MD |
428 | for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) { |
429 | mr = desc->mask_regs + i; | |
02ab3f70 MD |
430 | |
431 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | |
432 | if (mr->enum_ids[j] != enum_id) | |
433 | continue; | |
434 | ||
73505b44 MD |
435 | if (mr->set_reg && mr->clr_reg) { |
436 | fn = REG_FN_WRITE_BASE; | |
437 | mode = MODE_DUAL_REG; | |
438 | reg_e = mr->clr_reg; | |
439 | reg_d = mr->set_reg; | |
440 | } else { | |
441 | fn = REG_FN_MODIFY_BASE; | |
442 | if (mr->set_reg) { | |
443 | mode = MODE_ENABLE_REG; | |
444 | reg_e = mr->set_reg; | |
445 | reg_d = mr->set_reg; | |
446 | } else { | |
447 | mode = MODE_MASK_REG; | |
448 | reg_e = mr->clr_reg; | |
449 | reg_d = mr->clr_reg; | |
450 | } | |
51da6426 MD |
451 | } |
452 | ||
73505b44 MD |
453 | fn += (mr->reg_width >> 3) - 1; |
454 | return _INTC_MK(fn, mode, | |
455 | intc_get_reg(d, reg_e), | |
456 | intc_get_reg(d, reg_d), | |
457 | 1, | |
458 | (mr->reg_width - 1) - j); | |
02ab3f70 MD |
459 | } |
460 | } | |
461 | ||
680c4598 | 462 | if (do_grps) |
73505b44 | 463 | return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0); |
680c4598 | 464 | |
02ab3f70 MD |
465 | return 0; |
466 | } | |
467 | ||
468 | static unsigned int __init intc_prio_data(struct intc_desc *desc, | |
73505b44 | 469 | struct intc_desc_int *d, |
680c4598 | 470 | intc_enum enum_id, int do_grps) |
02ab3f70 | 471 | { |
680c4598 | 472 | struct intc_prio_reg *pr = desc->prio_regs; |
73505b44 MD |
473 | unsigned int i, j, fn, mode, bit; |
474 | unsigned long reg_e, reg_d; | |
02ab3f70 | 475 | |
680c4598 MD |
476 | for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) { |
477 | pr = desc->prio_regs + i; | |
02ab3f70 MD |
478 | |
479 | for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) { | |
480 | if (pr->enum_ids[j] != enum_id) | |
481 | continue; | |
482 | ||
73505b44 MD |
483 | if (pr->set_reg && pr->clr_reg) { |
484 | fn = REG_FN_WRITE_BASE; | |
485 | mode = MODE_PCLR_REG; | |
486 | reg_e = pr->set_reg; | |
487 | reg_d = pr->clr_reg; | |
488 | } else { | |
489 | fn = REG_FN_MODIFY_BASE; | |
490 | mode = MODE_PRIO_REG; | |
491 | if (!pr->set_reg) | |
492 | BUG(); | |
493 | reg_e = pr->set_reg; | |
494 | reg_d = pr->set_reg; | |
495 | } | |
02ab3f70 | 496 | |
73505b44 | 497 | fn += (pr->reg_width >> 3) - 1; |
02ab3f70 | 498 | |
b21a9104 | 499 | BUG_ON((j + 1) * pr->field_width > pr->reg_width); |
500 | ||
501 | bit = pr->reg_width - ((j + 1) * pr->field_width); | |
02ab3f70 | 502 | |
73505b44 MD |
503 | return _INTC_MK(fn, mode, |
504 | intc_get_reg(d, reg_e), | |
505 | intc_get_reg(d, reg_d), | |
506 | pr->field_width, bit); | |
02ab3f70 MD |
507 | } |
508 | } | |
509 | ||
680c4598 | 510 | if (do_grps) |
73505b44 MD |
511 | return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0); |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
d58876e2 MD |
516 | static unsigned int __init intc_ack_data(struct intc_desc *desc, |
517 | struct intc_desc_int *d, | |
518 | intc_enum enum_id) | |
519 | { | |
520 | struct intc_mask_reg *mr = desc->ack_regs; | |
521 | unsigned int i, j, fn, mode; | |
522 | unsigned long reg_e, reg_d; | |
523 | ||
524 | for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) { | |
525 | mr = desc->ack_regs + i; | |
526 | ||
527 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | |
528 | if (mr->enum_ids[j] != enum_id) | |
529 | continue; | |
530 | ||
531 | fn = REG_FN_MODIFY_BASE; | |
532 | mode = MODE_ENABLE_REG; | |
533 | reg_e = mr->set_reg; | |
534 | reg_d = mr->set_reg; | |
535 | ||
536 | fn += (mr->reg_width >> 3) - 1; | |
537 | return _INTC_MK(fn, mode, | |
538 | intc_get_reg(d, reg_e), | |
539 | intc_get_reg(d, reg_d), | |
540 | 1, | |
541 | (mr->reg_width - 1) - j); | |
542 | } | |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
d58876e2 | 547 | |
73505b44 MD |
548 | static unsigned int __init intc_sense_data(struct intc_desc *desc, |
549 | struct intc_desc_int *d, | |
550 | intc_enum enum_id) | |
551 | { | |
552 | struct intc_sense_reg *sr = desc->sense_regs; | |
553 | unsigned int i, j, fn, bit; | |
554 | ||
555 | for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) { | |
556 | sr = desc->sense_regs + i; | |
557 | ||
558 | for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { | |
559 | if (sr->enum_ids[j] != enum_id) | |
560 | continue; | |
561 | ||
562 | fn = REG_FN_MODIFY_BASE; | |
563 | fn += (sr->reg_width >> 3) - 1; | |
73505b44 | 564 | |
b21a9104 | 565 | BUG_ON((j + 1) * sr->field_width > sr->reg_width); |
566 | ||
567 | bit = sr->reg_width - ((j + 1) * sr->field_width); | |
73505b44 MD |
568 | |
569 | return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg), | |
570 | 0, sr->field_width, bit); | |
571 | } | |
572 | } | |
680c4598 | 573 | |
02ab3f70 MD |
574 | return 0; |
575 | } | |
576 | ||
73505b44 MD |
577 | static void __init intc_register_irq(struct intc_desc *desc, |
578 | struct intc_desc_int *d, | |
579 | intc_enum enum_id, | |
02ab3f70 MD |
580 | unsigned int irq) |
581 | { | |
3d37d94e | 582 | struct intc_handle_int *hp; |
680c4598 MD |
583 | unsigned int data[2], primary; |
584 | ||
1ce7b039 PM |
585 | /* |
586 | * Register the IRQ position with the global IRQ map | |
587 | */ | |
588 | set_bit(irq, intc_irq_map); | |
589 | ||
680c4598 MD |
590 | /* Prefer single interrupt source bitmap over other combinations: |
591 | * 1. bitmap, single interrupt source | |
592 | * 2. priority, single interrupt source | |
593 | * 3. bitmap, multiple interrupt sources (groups) | |
594 | * 4. priority, multiple interrupt sources (groups) | |
595 | */ | |
02ab3f70 | 596 | |
73505b44 MD |
597 | data[0] = intc_mask_data(desc, d, enum_id, 0); |
598 | data[1] = intc_prio_data(desc, d, enum_id, 0); | |
680c4598 MD |
599 | |
600 | primary = 0; | |
601 | if (!data[0] && data[1]) | |
602 | primary = 1; | |
603 | ||
bdaa6e80 | 604 | if (!data[0] && !data[1]) |
f033599a PM |
605 | pr_warning("intc: missing unique irq mask for " |
606 | "irq %d (vect 0x%04x)\n", irq, irq2evt(irq)); | |
bdaa6e80 | 607 | |
73505b44 MD |
608 | data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1); |
609 | data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1); | |
680c4598 MD |
610 | |
611 | if (!data[primary]) | |
612 | primary ^= 1; | |
613 | ||
614 | BUG_ON(!data[primary]); /* must have primary masking method */ | |
02ab3f70 MD |
615 | |
616 | disable_irq_nosync(irq); | |
73505b44 | 617 | set_irq_chip_and_handler_name(irq, &d->chip, |
02ab3f70 | 618 | handle_level_irq, "level"); |
680c4598 | 619 | set_irq_chip_data(irq, (void *)data[primary]); |
02ab3f70 | 620 | |
7f3edee8 MD |
621 | /* set priority level |
622 | * - this needs to be at least 2 for 5-bit priorities on 7780 | |
623 | */ | |
624 | intc_prio_level[irq] = 2; | |
73505b44 | 625 | |
680c4598 MD |
626 | /* enable secondary masking method if present */ |
627 | if (data[!primary]) | |
73505b44 MD |
628 | _intc_enable(irq, data[!primary]); |
629 | ||
630 | /* add irq to d->prio list if priority is available */ | |
631 | if (data[1]) { | |
3d37d94e MD |
632 | hp = d->prio + d->nr_prio; |
633 | hp->irq = irq; | |
634 | hp->handle = data[1]; | |
635 | ||
636 | if (primary) { | |
637 | /* | |
638 | * only secondary priority should access registers, so | |
639 | * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority() | |
640 | */ | |
641 | ||
642 | hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0); | |
643 | hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0); | |
644 | } | |
73505b44 MD |
645 | d->nr_prio++; |
646 | } | |
647 | ||
648 | /* add irq to d->sense list if sense is available */ | |
649 | data[0] = intc_sense_data(desc, d, enum_id); | |
650 | if (data[0]) { | |
651 | (d->sense + d->nr_sense)->irq = irq; | |
652 | (d->sense + d->nr_sense)->handle = data[0]; | |
653 | d->nr_sense++; | |
654 | } | |
02ab3f70 MD |
655 | |
656 | /* irq should be disabled by default */ | |
73505b44 | 657 | d->chip.mask(irq); |
d58876e2 | 658 | |
d58876e2 MD |
659 | if (desc->ack_regs) |
660 | ack_handle[irq] = intc_ack_data(desc, d, enum_id); | |
02ab3f70 MD |
661 | } |
662 | ||
f18d533e MD |
663 | static unsigned int __init save_reg(struct intc_desc_int *d, |
664 | unsigned int cnt, | |
665 | unsigned long value, | |
666 | unsigned int smp) | |
667 | { | |
668 | if (value) { | |
669 | d->reg[cnt] = value; | |
670 | #ifdef CONFIG_SMP | |
671 | d->smp[cnt] = smp; | |
672 | #endif | |
673 | return 1; | |
674 | } | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
05ecd5a1 | 679 | static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc) |
bdaa6e80 | 680 | { |
05ecd5a1 | 681 | generic_handle_irq((unsigned int)get_irq_data(irq)); |
bdaa6e80 | 682 | } |
f18d533e | 683 | |
02ab3f70 MD |
684 | void __init register_intc_controller(struct intc_desc *desc) |
685 | { | |
54ff328b | 686 | unsigned int i, k, smp; |
73505b44 MD |
687 | struct intc_desc_int *d; |
688 | ||
11b6aa95 | 689 | d = kzalloc(sizeof(*d), GFP_NOWAIT); |
73505b44 | 690 | |
2dcec7a9 MD |
691 | INIT_LIST_HEAD(&d->list); |
692 | list_add(&d->list, &intc_list); | |
693 | ||
73505b44 MD |
694 | d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0; |
695 | d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0; | |
696 | d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0; | |
d58876e2 | 697 | d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0; |
9b798d50 | 698 | |
11b6aa95 | 699 | d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); |
f18d533e | 700 | #ifdef CONFIG_SMP |
11b6aa95 | 701 | d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT); |
f18d533e | 702 | #endif |
73505b44 MD |
703 | k = 0; |
704 | ||
705 | if (desc->mask_regs) { | |
706 | for (i = 0; i < desc->nr_mask_regs; i++) { | |
f18d533e MD |
707 | smp = IS_SMP(desc->mask_regs[i]); |
708 | k += save_reg(d, k, desc->mask_regs[i].set_reg, smp); | |
709 | k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp); | |
73505b44 MD |
710 | } |
711 | } | |
712 | ||
713 | if (desc->prio_regs) { | |
11b6aa95 | 714 | d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT); |
73505b44 MD |
715 | |
716 | for (i = 0; i < desc->nr_prio_regs; i++) { | |
f18d533e MD |
717 | smp = IS_SMP(desc->prio_regs[i]); |
718 | k += save_reg(d, k, desc->prio_regs[i].set_reg, smp); | |
719 | k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp); | |
73505b44 MD |
720 | } |
721 | } | |
722 | ||
723 | if (desc->sense_regs) { | |
11b6aa95 | 724 | d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT); |
73505b44 MD |
725 | |
726 | for (i = 0; i < desc->nr_sense_regs; i++) { | |
f18d533e | 727 | k += save_reg(d, k, desc->sense_regs[i].reg, 0); |
73505b44 MD |
728 | } |
729 | } | |
730 | ||
73505b44 MD |
731 | d->chip.name = desc->name; |
732 | d->chip.mask = intc_disable; | |
733 | d->chip.unmask = intc_enable; | |
734 | d->chip.mask_ack = intc_disable; | |
f7dd2548 MD |
735 | d->chip.enable = intc_enable; |
736 | d->chip.disable = intc_disable; | |
737 | d->chip.shutdown = intc_disable; | |
73505b44 | 738 | d->chip.set_type = intc_set_sense; |
2dcec7a9 | 739 | d->chip.set_wake = intc_set_wake; |
02ab3f70 | 740 | |
d58876e2 MD |
741 | if (desc->ack_regs) { |
742 | for (i = 0; i < desc->nr_ack_regs; i++) | |
743 | k += save_reg(d, k, desc->ack_regs[i].set_reg, 0); | |
744 | ||
745 | d->chip.mask_ack = intc_mask_ack; | |
746 | } | |
d58876e2 MD |
747 | |
748 | BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ | |
749 | ||
bdaa6e80 | 750 | /* register the vectors one by one */ |
02ab3f70 MD |
751 | for (i = 0; i < desc->nr_vectors; i++) { |
752 | struct intc_vect *vect = desc->vectors + i; | |
05ff3004 PM |
753 | unsigned int irq = evt2irq(vect->vect); |
754 | struct irq_desc *irq_desc; | |
54ff328b | 755 | |
bdaa6e80 MD |
756 | if (!vect->enum_id) |
757 | continue; | |
758 | ||
54ff328b | 759 | irq_desc = irq_to_desc_alloc_node(irq, numa_node_id()); |
05ff3004 | 760 | if (unlikely(!irq_desc)) { |
1279b7f1 | 761 | pr_info("can't get irq_desc for %d\n", irq); |
05ff3004 PM |
762 | continue; |
763 | } | |
764 | ||
765 | intc_register_irq(desc, d, vect->enum_id, irq); | |
05ecd5a1 PM |
766 | |
767 | for (k = i + 1; k < desc->nr_vectors; k++) { | |
768 | struct intc_vect *vect2 = desc->vectors + k; | |
769 | unsigned int irq2 = evt2irq(vect2->vect); | |
770 | ||
771 | if (vect->enum_id != vect2->enum_id) | |
772 | continue; | |
773 | ||
1279b7f1 PM |
774 | /* |
775 | * In the case of multi-evt handling and sparse | |
776 | * IRQ support, each vector still needs to have | |
777 | * its own backing irq_desc. | |
778 | */ | |
779 | irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id()); | |
780 | if (unlikely(!irq_desc)) { | |
781 | pr_info("can't get irq_desc for %d\n", irq2); | |
782 | continue; | |
783 | } | |
784 | ||
05ecd5a1 PM |
785 | vect2->enum_id = 0; |
786 | ||
787 | /* redirect this interrupts to the first one */ | |
788 | set_irq_chip_and_handler_name(irq2, &d->chip, | |
789 | intc_redirect_irq, "redirect"); | |
790 | set_irq_data(irq2, (void *)irq); | |
791 | } | |
02ab3f70 MD |
792 | } |
793 | } | |
2dcec7a9 MD |
794 | |
795 | static int intc_suspend(struct sys_device *dev, pm_message_t state) | |
796 | { | |
797 | struct intc_desc_int *d; | |
798 | struct irq_desc *desc; | |
799 | int irq; | |
800 | ||
801 | /* get intc controller associated with this sysdev */ | |
802 | d = container_of(dev, struct intc_desc_int, sysdev); | |
803 | ||
7fd87b3f FV |
804 | switch (state.event) { |
805 | case PM_EVENT_ON: | |
806 | if (d->state.event != PM_EVENT_FREEZE) | |
807 | break; | |
808 | for_each_irq_desc(irq, desc) { | |
809 | if (desc->chip != &d->chip) | |
810 | continue; | |
811 | if (desc->status & IRQ_DISABLED) | |
812 | intc_disable(irq); | |
813 | else | |
814 | intc_enable(irq); | |
815 | } | |
816 | break; | |
817 | case PM_EVENT_FREEZE: | |
818 | /* nothing has to be done */ | |
819 | break; | |
820 | case PM_EVENT_SUSPEND: | |
821 | /* enable wakeup irqs belonging to this intc controller */ | |
822 | for_each_irq_desc(irq, desc) { | |
823 | if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip)) | |
824 | intc_enable(irq); | |
825 | } | |
826 | break; | |
2dcec7a9 | 827 | } |
7fd87b3f | 828 | d->state = state; |
2dcec7a9 MD |
829 | |
830 | return 0; | |
831 | } | |
832 | ||
7fd87b3f FV |
833 | static int intc_resume(struct sys_device *dev) |
834 | { | |
835 | return intc_suspend(dev, PMSG_ON); | |
836 | } | |
837 | ||
2dcec7a9 MD |
838 | static struct sysdev_class intc_sysdev_class = { |
839 | .name = "intc", | |
840 | .suspend = intc_suspend, | |
7fd87b3f | 841 | .resume = intc_resume, |
2dcec7a9 MD |
842 | }; |
843 | ||
844 | /* register this intc as sysdev to allow suspend/resume */ | |
845 | static int __init register_intc_sysdevs(void) | |
846 | { | |
847 | struct intc_desc_int *d; | |
848 | int error; | |
849 | int id = 0; | |
850 | ||
851 | error = sysdev_class_register(&intc_sysdev_class); | |
852 | if (!error) { | |
853 | list_for_each_entry(d, &intc_list, list) { | |
854 | d->sysdev.id = id; | |
855 | d->sysdev.cls = &intc_sysdev_class; | |
856 | error = sysdev_register(&d->sysdev); | |
857 | if (error) | |
858 | break; | |
859 | id++; | |
860 | } | |
861 | } | |
862 | ||
863 | if (error) | |
864 | pr_warning("intc: sysdev registration error\n"); | |
865 | ||
866 | return error; | |
867 | } | |
2dcec7a9 | 868 | device_initcall(register_intc_sysdevs); |
1ce7b039 PM |
869 | |
870 | /* | |
871 | * Dynamic IRQ allocation and deallocation | |
872 | */ | |
873 | static unsigned int create_irq_on_node(unsigned int irq_want, int node) | |
874 | { | |
875 | unsigned int irq = 0, new; | |
876 | unsigned long flags; | |
877 | struct irq_desc *desc; | |
878 | ||
879 | spin_lock_irqsave(&vector_lock, flags); | |
880 | ||
881 | /* | |
882 | * First try the wanted IRQ, then scan. | |
883 | */ | |
884 | if (test_and_set_bit(irq_want, intc_irq_map)) { | |
885 | new = find_first_zero_bit(intc_irq_map, nr_irqs); | |
886 | if (unlikely(new == nr_irqs)) | |
887 | goto out_unlock; | |
888 | ||
889 | desc = irq_to_desc_alloc_node(new, node); | |
890 | if (unlikely(!desc)) { | |
891 | pr_info("can't get irq_desc for %d\n", new); | |
892 | goto out_unlock; | |
893 | } | |
894 | ||
895 | desc = move_irq_desc(desc, node); | |
896 | __set_bit(new, intc_irq_map); | |
897 | irq = new; | |
898 | } | |
899 | ||
900 | out_unlock: | |
901 | spin_unlock_irqrestore(&vector_lock, flags); | |
902 | ||
903 | if (irq > 0) | |
904 | dynamic_irq_init(irq); | |
905 | ||
906 | return irq; | |
907 | } | |
908 | ||
909 | int create_irq(void) | |
910 | { | |
911 | int nid = cpu_to_node(smp_processor_id()); | |
912 | int irq; | |
913 | ||
914 | irq = create_irq_on_node(NR_IRQS_LEGACY, nid); | |
915 | if (irq == 0) | |
916 | irq = -1; | |
917 | ||
918 | return irq; | |
919 | } | |
920 | ||
921 | void destroy_irq(unsigned int irq) | |
922 | { | |
923 | unsigned long flags; | |
924 | ||
925 | dynamic_irq_cleanup(irq); | |
926 | ||
927 | spin_lock_irqsave(&vector_lock, flags); | |
928 | __clear_bit(irq, intc_irq_map); | |
929 | spin_unlock_irqrestore(&vector_lock, flags); | |
930 | } | |
45b9deaf PM |
931 | |
932 | int reserve_irq_vector(unsigned int irq) | |
933 | { | |
934 | unsigned long flags; | |
935 | int ret = 0; | |
936 | ||
937 | spin_lock_irqsave(&vector_lock, flags); | |
938 | if (test_and_set_bit(irq, intc_irq_map)) | |
939 | ret = -EBUSY; | |
940 | spin_unlock_irqrestore(&vector_lock, flags); | |
941 | ||
942 | return ret; | |
943 | } | |
944 | ||
945 | void reserve_irq_legacy(void) | |
946 | { | |
947 | unsigned long flags; | |
948 | int i, j; | |
949 | ||
950 | spin_lock_irqsave(&vector_lock, flags); | |
951 | j = find_first_bit(intc_irq_map, nr_irqs); | |
952 | for (i = 0; i < j; i++) | |
953 | __set_bit(i, intc_irq_map); | |
954 | spin_unlock_irqrestore(&vector_lock, flags); | |
955 | } |