Commit | Line | Data |
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ca5481c6 PM |
1 | /* |
2 | * SuperH Pin Function Controller pinmux support. | |
3 | * | |
4 | * Copyright (C) 2012 Paul Mundt | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
54407110 | 10 | |
c6193eac | 11 | #define DRV_NAME "sh-pfc" |
f9492fda | 12 | #define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt |
ca5481c6 | 13 | |
1724acfd | 14 | #include <linux/device.h> |
ca5481c6 PM |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/sh_pfc.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/slab.h> | |
d93a891f | 20 | #include <linux/spinlock.h> |
ca5481c6 PM |
21 | #include <linux/pinctrl/consumer.h> |
22 | #include <linux/pinctrl/pinctrl.h> | |
23 | #include <linux/pinctrl/pinconf.h> | |
24 | #include <linux/pinctrl/pinmux.h> | |
25 | #include <linux/pinctrl/pinconf-generic.h> | |
26 | ||
f9165132 LP |
27 | #include "core.h" |
28 | ||
ca5481c6 PM |
29 | struct sh_pfc_pinctrl { |
30 | struct pinctrl_dev *pctl; | |
31 | struct sh_pfc *pfc; | |
32 | ||
d93a891f PM |
33 | struct pinmux_gpio **functions; |
34 | unsigned int nr_functions; | |
35 | ||
ca5481c6 PM |
36 | struct pinctrl_pin_desc *pads; |
37 | unsigned int nr_pads; | |
d93a891f PM |
38 | |
39 | spinlock_t lock; | |
ca5481c6 PM |
40 | }; |
41 | ||
e3f805e8 | 42 | static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) |
ca5481c6 | 43 | { |
e3f805e8 PM |
44 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
45 | ||
46 | return pmx->nr_pads; | |
ca5481c6 PM |
47 | } |
48 | ||
e3f805e8 | 49 | static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, |
ca5481c6 PM |
50 | unsigned selector) |
51 | { | |
e3f805e8 PM |
52 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
53 | ||
54 | return pmx->pads[selector].name; | |
ca5481c6 PM |
55 | } |
56 | ||
57 | static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, | |
58 | const unsigned **pins, unsigned *num_pins) | |
59 | { | |
e3f805e8 PM |
60 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
61 | ||
62 | *pins = &pmx->pads[group].number; | |
63 | *num_pins = 1; | |
64 | ||
65 | return 0; | |
ca5481c6 PM |
66 | } |
67 | ||
fdd85ec3 PM |
68 | static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
69 | unsigned offset) | |
70 | { | |
71 | seq_printf(s, "%s", DRV_NAME); | |
72 | } | |
73 | ||
ca5481c6 | 74 | static struct pinctrl_ops sh_pfc_pinctrl_ops = { |
e3f805e8 PM |
75 | .get_groups_count = sh_pfc_get_groups_count, |
76 | .get_group_name = sh_pfc_get_group_name, | |
ca5481c6 | 77 | .get_group_pins = sh_pfc_get_group_pins, |
fdd85ec3 | 78 | .pin_dbg_show = sh_pfc_pin_dbg_show, |
ca5481c6 PM |
79 | }; |
80 | ||
d93a891f PM |
81 | static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) |
82 | { | |
83 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
84 | ||
85 | return pmx->nr_functions; | |
86 | } | |
87 | ||
88 | static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, | |
89 | unsigned selector) | |
90 | { | |
91 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
92 | ||
93 | return pmx->functions[selector]->name; | |
94 | } | |
ca5481c6 | 95 | |
ca5481c6 PM |
96 | static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func, |
97 | const char * const **groups, | |
98 | unsigned * const num_groups) | |
99 | { | |
d93a891f PM |
100 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
101 | ||
102 | *groups = &pmx->functions[func]->name; | |
103 | *num_groups = 1; | |
104 | ||
ca5481c6 PM |
105 | return 0; |
106 | } | |
107 | ||
108 | static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func, | |
109 | unsigned group) | |
110 | { | |
111 | return 0; | |
112 | } | |
113 | ||
114 | static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func, | |
115 | unsigned group) | |
116 | { | |
117 | } | |
118 | ||
4a2e0d18 | 119 | static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset) |
d93a891f PM |
120 | { |
121 | if (sh_pfc_config_gpio(pfc, offset, | |
122 | PINMUX_TYPE_FUNCTION, | |
123 | GPIO_CFG_DRYRUN) != 0) | |
124 | return -EINVAL; | |
125 | ||
126 | if (sh_pfc_config_gpio(pfc, offset, | |
127 | PINMUX_TYPE_FUNCTION, | |
128 | GPIO_CFG_REQ) != 0) | |
129 | return -EINVAL; | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
fdd85ec3 PM |
134 | static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, |
135 | int new_type) | |
136 | { | |
137 | unsigned long flags; | |
138 | int pinmux_type; | |
139 | int ret = -EINVAL; | |
140 | ||
141 | spin_lock_irqsave(&pfc->lock, flags); | |
142 | ||
d4e62d00 | 143 | pinmux_type = pfc->pdata->gpios[offset].flags & PINMUX_FLAG_TYPE; |
fdd85ec3 PM |
144 | |
145 | /* | |
146 | * See if the present config needs to first be de-configured. | |
147 | */ | |
148 | switch (pinmux_type) { | |
149 | case PINMUX_TYPE_GPIO: | |
150 | break; | |
151 | case PINMUX_TYPE_OUTPUT: | |
152 | case PINMUX_TYPE_INPUT: | |
153 | case PINMUX_TYPE_INPUT_PULLUP: | |
154 | case PINMUX_TYPE_INPUT_PULLDOWN: | |
155 | sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); | |
156 | break; | |
157 | default: | |
158 | goto err; | |
159 | } | |
160 | ||
161 | /* | |
162 | * Dry run | |
163 | */ | |
164 | if (sh_pfc_config_gpio(pfc, offset, new_type, | |
165 | GPIO_CFG_DRYRUN) != 0) | |
166 | goto err; | |
167 | ||
168 | /* | |
169 | * Request | |
170 | */ | |
171 | if (sh_pfc_config_gpio(pfc, offset, new_type, | |
172 | GPIO_CFG_REQ) != 0) | |
173 | goto err; | |
174 | ||
d4e62d00 LP |
175 | pfc->pdata->gpios[offset].flags &= ~PINMUX_FLAG_TYPE; |
176 | pfc->pdata->gpios[offset].flags |= new_type; | |
fdd85ec3 PM |
177 | |
178 | ret = 0; | |
179 | ||
180 | err: | |
181 | spin_unlock_irqrestore(&pfc->lock, flags); | |
182 | ||
183 | return ret; | |
184 | } | |
185 | ||
186 | ||
ca5481c6 PM |
187 | static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, |
188 | struct pinctrl_gpio_range *range, | |
189 | unsigned offset) | |
190 | { | |
191 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
192 | struct sh_pfc *pfc = pmx->pfc; | |
ca5481c6 | 193 | unsigned long flags; |
d93a891f | 194 | int ret, pinmux_type; |
ca5481c6 PM |
195 | |
196 | spin_lock_irqsave(&pfc->lock, flags); | |
197 | ||
d4e62d00 | 198 | pinmux_type = pfc->pdata->gpios[offset].flags & PINMUX_FLAG_TYPE; |
ca5481c6 | 199 | |
d93a891f PM |
200 | switch (pinmux_type) { |
201 | case PINMUX_TYPE_FUNCTION: | |
202 | pr_notice_once("Use of GPIO API for function requests is " | |
203 | "deprecated, convert to pinctrl\n"); | |
204 | /* handle for now */ | |
205 | ret = sh_pfc_config_function(pfc, offset); | |
206 | if (unlikely(ret < 0)) | |
ca5481c6 | 207 | goto err; |
ca5481c6 | 208 | |
d93a891f PM |
209 | break; |
210 | case PINMUX_TYPE_GPIO: | |
16d74ebe PM |
211 | case PINMUX_TYPE_INPUT: |
212 | case PINMUX_TYPE_OUTPUT: | |
d93a891f PM |
213 | break; |
214 | default: | |
215 | pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type); | |
077664a2 LP |
216 | ret = -ENOTSUPP; |
217 | goto err; | |
d93a891f | 218 | } |
ca5481c6 PM |
219 | |
220 | ret = 0; | |
221 | ||
222 | err: | |
223 | spin_unlock_irqrestore(&pfc->lock, flags); | |
224 | ||
225 | return ret; | |
226 | } | |
227 | ||
228 | static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, | |
229 | struct pinctrl_gpio_range *range, | |
230 | unsigned offset) | |
231 | { | |
232 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
233 | struct sh_pfc *pfc = pmx->pfc; | |
234 | unsigned long flags; | |
235 | int pinmux_type; | |
236 | ||
237 | spin_lock_irqsave(&pfc->lock, flags); | |
238 | ||
d4e62d00 | 239 | pinmux_type = pfc->pdata->gpios[offset].flags & PINMUX_FLAG_TYPE; |
ca5481c6 PM |
240 | |
241 | sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); | |
242 | ||
ca5481c6 PM |
243 | spin_unlock_irqrestore(&pfc->lock, flags); |
244 | } | |
245 | ||
246 | static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, | |
247 | struct pinctrl_gpio_range *range, | |
248 | unsigned offset, bool input) | |
249 | { | |
250 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
fdd85ec3 | 251 | int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; |
ca5481c6 | 252 | |
fdd85ec3 | 253 | return sh_pfc_reconfig_pin(pmx->pfc, offset, type); |
ca5481c6 PM |
254 | } |
255 | ||
256 | static struct pinmux_ops sh_pfc_pinmux_ops = { | |
d93a891f PM |
257 | .get_functions_count = sh_pfc_get_functions_count, |
258 | .get_function_name = sh_pfc_get_function_name, | |
ca5481c6 PM |
259 | .get_function_groups = sh_pfc_get_function_groups, |
260 | .enable = sh_pfc_noop_enable, | |
261 | .disable = sh_pfc_noop_disable, | |
262 | .gpio_request_enable = sh_pfc_gpio_request_enable, | |
263 | .gpio_disable_free = sh_pfc_gpio_disable_free, | |
264 | .gpio_set_direction = sh_pfc_gpio_set_direction, | |
265 | }; | |
266 | ||
267 | static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, | |
268 | unsigned long *config) | |
269 | { | |
fdd85ec3 PM |
270 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
271 | struct sh_pfc *pfc = pmx->pfc; | |
d93a891f | 272 | |
d4e62d00 | 273 | *config = pfc->pdata->gpios[pin].flags & PINMUX_FLAG_TYPE; |
d93a891f | 274 | |
fdd85ec3 | 275 | return 0; |
ca5481c6 PM |
276 | } |
277 | ||
278 | static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, | |
279 | unsigned long config) | |
280 | { | |
fdd85ec3 | 281 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
fdd85ec3 PM |
282 | |
283 | /* Validate the new type */ | |
284 | if (config >= PINMUX_FLAG_TYPE) | |
285 | return -EINVAL; | |
286 | ||
287 | return sh_pfc_reconfig_pin(pmx->pfc, pin, config); | |
288 | } | |
289 | ||
290 | static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
291 | struct seq_file *s, unsigned pin) | |
292 | { | |
293 | const char *pinmux_type_str[] = { | |
294 | [PINMUX_TYPE_NONE] = "none", | |
295 | [PINMUX_TYPE_FUNCTION] = "function", | |
296 | [PINMUX_TYPE_GPIO] = "gpio", | |
297 | [PINMUX_TYPE_OUTPUT] = "output", | |
298 | [PINMUX_TYPE_INPUT] = "input", | |
299 | [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up", | |
300 | [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down", | |
301 | }; | |
302 | unsigned long config; | |
303 | int rc; | |
304 | ||
305 | rc = sh_pfc_pinconf_get(pctldev, pin, &config); | |
306 | if (unlikely(rc != 0)) | |
307 | return; | |
308 | ||
309 | seq_printf(s, " %s", pinmux_type_str[config]); | |
ca5481c6 PM |
310 | } |
311 | ||
312 | static struct pinconf_ops sh_pfc_pinconf_ops = { | |
ca5481c6 PM |
313 | .pin_config_get = sh_pfc_pinconf_get, |
314 | .pin_config_set = sh_pfc_pinconf_set, | |
fdd85ec3 | 315 | .pin_config_dbg_show = sh_pfc_pinconf_dbg_show, |
ca5481c6 PM |
316 | }; |
317 | ||
318 | static struct pinctrl_gpio_range sh_pfc_gpio_range = { | |
54407110 | 319 | .name = DRV_NAME, |
ca5481c6 PM |
320 | .id = 0, |
321 | }; | |
322 | ||
323 | static struct pinctrl_desc sh_pfc_pinctrl_desc = { | |
54407110 | 324 | .name = DRV_NAME, |
ca5481c6 PM |
325 | .owner = THIS_MODULE, |
326 | .pctlops = &sh_pfc_pinctrl_ops, | |
327 | .pmxops = &sh_pfc_pinmux_ops, | |
328 | .confops = &sh_pfc_pinconf_ops, | |
329 | }; | |
330 | ||
4a2e0d18 LP |
331 | static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, |
332 | struct pinmux_gpio *gpio, unsigned offset) | |
d93a891f PM |
333 | { |
334 | struct pinmux_data_reg *dummy; | |
335 | unsigned long flags; | |
336 | int bit; | |
337 | ||
338 | gpio->flags &= ~PINMUX_FLAG_TYPE; | |
339 | ||
340 | if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0) | |
341 | gpio->flags |= PINMUX_TYPE_GPIO; | |
342 | else { | |
343 | gpio->flags |= PINMUX_TYPE_FUNCTION; | |
344 | ||
345 | spin_lock_irqsave(&pmx->lock, flags); | |
346 | pmx->nr_functions++; | |
347 | spin_unlock_irqrestore(&pmx->lock, flags); | |
348 | } | |
349 | } | |
350 | ||
ca5481c6 | 351 | /* pinmux ranges -> pinctrl pin descs */ |
0fe763c5 | 352 | static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) |
ca5481c6 | 353 | { |
d93a891f | 354 | unsigned long flags; |
ca5481c6 PM |
355 | int i; |
356 | ||
d4e62d00 | 357 | pmx->nr_pads = pfc->pdata->last_gpio - pfc->pdata->first_gpio + 1; |
ca5481c6 | 358 | |
1724acfd LP |
359 | pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads, |
360 | GFP_KERNEL); | |
ca5481c6 PM |
361 | if (unlikely(!pmx->pads)) { |
362 | pmx->nr_pads = 0; | |
363 | return -ENOMEM; | |
364 | } | |
365 | ||
d93a891f PM |
366 | spin_lock_irqsave(&pfc->lock, flags); |
367 | ||
ca5481c6 PM |
368 | /* |
369 | * We don't necessarily have a 1:1 mapping between pin and linux | |
370 | * GPIO number, as the latter maps to the associated enum_id. | |
371 | * Care needs to be taken to translate back to pin space when | |
372 | * dealing with any pin configurations. | |
373 | */ | |
374 | for (i = 0; i < pmx->nr_pads; i++) { | |
375 | struct pinctrl_pin_desc *pin = pmx->pads + i; | |
d4e62d00 | 376 | struct pinmux_gpio *gpio = pfc->pdata->gpios + i; |
ca5481c6 | 377 | |
d4e62d00 | 378 | pin->number = pfc->pdata->first_gpio + i; |
ca5481c6 | 379 | pin->name = gpio->name; |
d93a891f | 380 | |
e3e79454 PM |
381 | /* XXX */ |
382 | if (unlikely(!gpio->enum_id)) | |
383 | continue; | |
384 | ||
d93a891f | 385 | sh_pfc_map_one_gpio(pfc, pmx, gpio, i); |
ca5481c6 PM |
386 | } |
387 | ||
d93a891f PM |
388 | spin_unlock_irqrestore(&pfc->lock, flags); |
389 | ||
ca5481c6 PM |
390 | sh_pfc_pinctrl_desc.pins = pmx->pads; |
391 | sh_pfc_pinctrl_desc.npins = pmx->nr_pads; | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
0fe763c5 | 396 | static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) |
d93a891f PM |
397 | { |
398 | unsigned long flags; | |
399 | int i, fn; | |
400 | ||
1724acfd LP |
401 | pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions * |
402 | sizeof(*pmx->functions), GFP_KERNEL); | |
d93a891f PM |
403 | if (unlikely(!pmx->functions)) |
404 | return -ENOMEM; | |
405 | ||
406 | spin_lock_irqsave(&pmx->lock, flags); | |
407 | ||
408 | for (i = fn = 0; i < pmx->nr_pads; i++) { | |
d4e62d00 | 409 | struct pinmux_gpio *gpio = pfc->pdata->gpios + i; |
d93a891f PM |
410 | |
411 | if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION) | |
412 | pmx->functions[fn++] = gpio; | |
413 | } | |
414 | ||
415 | spin_unlock_irqrestore(&pmx->lock, flags); | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
c6193eac | 420 | int sh_pfc_register_pinctrl(struct sh_pfc *pfc) |
ca5481c6 | 421 | { |
c6193eac | 422 | struct sh_pfc_pinctrl *pmx; |
ca5481c6 PM |
423 | int ret; |
424 | ||
1724acfd | 425 | pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); |
c6193eac LP |
426 | if (unlikely(!pmx)) |
427 | return -ENOMEM; | |
428 | ||
429 | spin_lock_init(&pmx->lock); | |
ca5481c6 | 430 | |
c6193eac LP |
431 | pmx->pfc = pfc; |
432 | pfc->pinctrl = pmx; | |
ca5481c6 | 433 | |
c6193eac | 434 | ret = sh_pfc_map_gpios(pfc, pmx); |
ca5481c6 PM |
435 | if (unlikely(ret != 0)) |
436 | return ret; | |
437 | ||
c6193eac | 438 | ret = sh_pfc_map_functions(pfc, pmx); |
d93a891f | 439 | if (unlikely(ret != 0)) |
1724acfd | 440 | return ret; |
d93a891f | 441 | |
c6193eac | 442 | pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx); |
1724acfd LP |
443 | if (IS_ERR(pmx->pctl)) |
444 | return PTR_ERR(pmx->pctl); | |
ca5481c6 | 445 | |
d4e62d00 LP |
446 | sh_pfc_gpio_range.npins = pfc->pdata->last_gpio |
447 | - pfc->pdata->first_gpio + 1; | |
448 | sh_pfc_gpio_range.base = pfc->pdata->first_gpio; | |
449 | sh_pfc_gpio_range.pin_base = pfc->pdata->first_gpio; | |
ca5481c6 | 450 | |
c6193eac | 451 | pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range); |
ca5481c6 PM |
452 | |
453 | return 0; | |
ca5481c6 PM |
454 | } |
455 | ||
c6193eac | 456 | int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc) |
ca5481c6 | 457 | { |
c6193eac | 458 | struct sh_pfc_pinctrl *pmx = pfc->pinctrl; |
ca5481c6 | 459 | |
ca5481c6 PM |
460 | pinctrl_unregister(pmx->pctl); |
461 | ||
c6193eac | 462 | pfc->pinctrl = NULL; |
ca5481c6 PM |
463 | return 0; |
464 | } |