[deliverable/linux.git] / drivers / sh / pfc / pinctrl.c

/*
 * SuperH Pin Function Controller pinmux support.
 *
 * Copyright (C) 2012  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#define DRV_NAME "pinctrl-sh_pfc"

#define pr_fmt(fmt) DRV_NAME " " KBUILD_MODNAME ": " fmt

#include <linux/init.h>
#include <linux/module.h>
#include <linux/sh_pfc.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf-generic.h>

struct sh_pfc_pinctrl {
	struct pinctrl_dev *pctl;
	struct sh_pfc *pfc;

	struct pinmux_gpio **functions;
	unsigned int nr_functions;

	struct pinctrl_pin_desc *pads;
	unsigned int nr_pads;

	spinlock_t lock;
};

static struct sh_pfc_pinctrl *sh_pfc_pmx;

static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->nr_pads;
}

static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
					 unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pads[selector].name;
}

static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
				 const unsigned **pins, unsigned *num_pins)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*pins = &pmx->pads[group].number;
	*num_pins = 1;

	return 0;
}

static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
				unsigned offset)
{
	seq_printf(s, "%s", DRV_NAME);
}

static struct pinctrl_ops sh_pfc_pinctrl_ops = {
	.get_groups_count	= sh_pfc_get_groups_count,
	.get_group_name		= sh_pfc_get_group_name,
	.get_group_pins		= sh_pfc_get_group_pins,
	.pin_dbg_show		= sh_pfc_pin_dbg_show,
};

static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->nr_functions;
}

static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
					    unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->functions[selector]->name;
}

static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
				      const char * const **groups,
				      unsigned * const num_groups)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*groups = &pmx->functions[func]->name;
	*num_groups = 1;

	return 0;
}

static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
			      unsigned group)
{
	return 0;
}

static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
				unsigned group)
{
}

static inline int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
{
	if (sh_pfc_config_gpio(pfc, offset,
			       PINMUX_TYPE_FUNCTION,
			       GPIO_CFG_DRYRUN) != 0)
		return -EINVAL;

	if (sh_pfc_config_gpio(pfc, offset,
			       PINMUX_TYPE_FUNCTION,
			       GPIO_CFG_REQ) != 0)
		return -EINVAL;

	return 0;
}

static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
			       int new_type)
{
	unsigned long flags;
	int pinmux_type;
	int ret = -EINVAL;

	spin_lock_irqsave(&pfc->lock, flags);

	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;

	/*
	 * See if the present config needs to first be de-configured.
	 */
	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
		break;
	case PINMUX_TYPE_OUTPUT:
	case PINMUX_TYPE_INPUT:
	case PINMUX_TYPE_INPUT_PULLUP:
	case PINMUX_TYPE_INPUT_PULLDOWN:
		sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
		break;
	default:
		goto err;
	}

	/*
	 * Dry run
	 */
	if (sh_pfc_config_gpio(pfc, offset, new_type,
			       GPIO_CFG_DRYRUN) != 0)
		goto err;

	/*
	 * Request
	 */
	if (sh_pfc_config_gpio(pfc, offset, new_type,
			       GPIO_CFG_REQ) != 0)
		goto err;

	pfc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
	pfc->gpios[offset].flags |= new_type;

	ret = 0;

err:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}


static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
				      struct pinctrl_gpio_range *range,
				      unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	unsigned long flags;
	int ret, pinmux_type;

	spin_lock_irqsave(&pfc->lock, flags);

	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;

	switch (pinmux_type) {
	case PINMUX_TYPE_FUNCTION:
		pr_notice_once("Use of GPIO API for function requests is "
			       "deprecated, convert to pinctrl\n");
		/* handle for now */
		ret = sh_pfc_config_function(pfc, offset);
		if (unlikely(ret < 0))
			goto err;

		break;
	case PINMUX_TYPE_GPIO:
		break;
	default:
		pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
		ret = -ENOTSUPP;
		goto err;
	}

	ret = 0;

err:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	unsigned long flags;
	int pinmux_type;

	spin_lock_irqsave(&pfc->lock, flags);

	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;

	sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);

	spin_unlock_irqrestore(&pfc->lock, flags);
}

static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset, bool input)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;

	return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
}

static struct pinmux_ops sh_pfc_pinmux_ops = {
	.get_functions_count	= sh_pfc_get_functions_count,
	.get_function_name	= sh_pfc_get_function_name,
	.get_function_groups	= sh_pfc_get_function_groups,
	.enable			= sh_pfc_noop_enable,
	.disable		= sh_pfc_noop_disable,
	.gpio_request_enable	= sh_pfc_gpio_request_enable,
	.gpio_disable_free	= sh_pfc_gpio_disable_free,
	.gpio_set_direction	= sh_pfc_gpio_set_direction,
};

static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
			      unsigned long *config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;

	*config = pfc->gpios[pin].flags & PINMUX_FLAG_TYPE;

	return 0;
}

static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
			      unsigned long config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	/* Validate the new type */
	if (config >= PINMUX_FLAG_TYPE)
		return -EINVAL;

	return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
}

static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
				    struct seq_file *s, unsigned pin)
{
	const char *pinmux_type_str[] = {
		[PINMUX_TYPE_NONE]		= "none",
		[PINMUX_TYPE_FUNCTION]		= "function",
		[PINMUX_TYPE_GPIO]		= "gpio",
		[PINMUX_TYPE_OUTPUT]		= "output",
		[PINMUX_TYPE_INPUT]		= "input",
		[PINMUX_TYPE_INPUT_PULLUP]	= "input bias pull up",
		[PINMUX_TYPE_INPUT_PULLDOWN]	= "input bias pull down",
	};
	unsigned long config;
	int rc;

	rc = sh_pfc_pinconf_get(pctldev, pin, &config);
	if (unlikely(rc != 0))
		return;

	seq_printf(s, " %s", pinmux_type_str[config]);
}

static struct pinconf_ops sh_pfc_pinconf_ops = {
	.pin_config_get		= sh_pfc_pinconf_get,
	.pin_config_set		= sh_pfc_pinconf_set,
	.pin_config_dbg_show	= sh_pfc_pinconf_dbg_show,
};

static struct pinctrl_gpio_range sh_pfc_gpio_range = {
	.name		= DRV_NAME,
	.id		= 0,
};

static struct pinctrl_desc sh_pfc_pinctrl_desc = {
	.name		= DRV_NAME,
	.owner		= THIS_MODULE,
	.pctlops	= &sh_pfc_pinctrl_ops,
	.pmxops		= &sh_pfc_pinmux_ops,
	.confops	= &sh_pfc_pinconf_ops,
};

static inline void __devinit sh_pfc_map_one_gpio(struct sh_pfc *pfc,
						 struct sh_pfc_pinctrl *pmx,
						 struct pinmux_gpio *gpio,
						 unsigned offset)
{
	struct pinmux_data_reg *dummy;
	unsigned long flags;
	int bit;

	gpio->flags &= ~PINMUX_FLAG_TYPE;

	if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
		gpio->flags |= PINMUX_TYPE_GPIO;
	else {
		gpio->flags |= PINMUX_TYPE_FUNCTION;

		spin_lock_irqsave(&pmx->lock, flags);
		pmx->nr_functions++;
		spin_unlock_irqrestore(&pmx->lock, flags);
	}
}

/* pinmux ranges -> pinctrl pin descs */
static int __devinit sh_pfc_map_gpios(struct sh_pfc *pfc,
				      struct sh_pfc_pinctrl *pmx)
{
	unsigned long flags;
	int i;

	pmx->nr_pads = pfc->last_gpio - pfc->first_gpio + 1;

	pmx->pads = kmalloc(sizeof(struct pinctrl_pin_desc) * pmx->nr_pads,
			    GFP_KERNEL);
	if (unlikely(!pmx->pads)) {
		pmx->nr_pads = 0;
		return -ENOMEM;
	}

	spin_lock_irqsave(&pfc->lock, flags);

	/*
	 * We don't necessarily have a 1:1 mapping between pin and linux
	 * GPIO number, as the latter maps to the associated enum_id.
	 * Care needs to be taken to translate back to pin space when
	 * dealing with any pin configurations.
	 */
	for (i = 0; i < pmx->nr_pads; i++) {
		struct pinctrl_pin_desc *pin = pmx->pads + i;
		struct pinmux_gpio *gpio = pfc->gpios + i;

		pin->number = pfc->first_gpio + i;
		pin->name = gpio->name;

		/* XXX */
		if (unlikely(!gpio->enum_id))
			continue;

		sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
	}

	spin_unlock_irqrestore(&pfc->lock, flags);

	sh_pfc_pinctrl_desc.pins = pmx->pads;
	sh_pfc_pinctrl_desc.npins = pmx->nr_pads;

	return 0;
}

static int __devinit sh_pfc_map_functions(struct sh_pfc *pfc,
					  struct sh_pfc_pinctrl *pmx)
{
	unsigned long flags;
	int i, fn;

	pmx->functions = kzalloc(pmx->nr_functions * sizeof(void *),
				 GFP_KERNEL);
	if (unlikely(!pmx->functions))
		return -ENOMEM;

	spin_lock_irqsave(&pmx->lock, flags);

	for (i = fn = 0; i < pmx->nr_pads; i++) {
		struct pinmux_gpio *gpio = pfc->gpios + i;

		if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
			pmx->functions[fn++] = gpio;
	}

	spin_unlock_irqrestore(&pmx->lock, flags);

	return 0;
}

static int __devinit sh_pfc_pinctrl_probe(struct platform_device *pdev)
{
	struct sh_pfc *pfc;
	int ret;

	if (unlikely(!sh_pfc_pmx))
		return -ENODEV;

	pfc = sh_pfc_pmx->pfc;

	ret = sh_pfc_map_gpios(pfc, sh_pfc_pmx);
	if (unlikely(ret != 0))
		return ret;

	ret = sh_pfc_map_functions(pfc, sh_pfc_pmx);
	if (unlikely(ret != 0))
		goto free_pads;

	sh_pfc_pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, &pdev->dev,
					    sh_pfc_pmx);
	if (IS_ERR(sh_pfc_pmx->pctl)) {
		ret = PTR_ERR(sh_pfc_pmx->pctl);
		goto free_functions;
	}

	sh_pfc_gpio_range.npins = pfc->last_gpio - pfc->first_gpio + 1;
	sh_pfc_gpio_range.base = pfc->first_gpio;
	sh_pfc_gpio_range.pin_base = pfc->first_gpio;

	pinctrl_add_gpio_range(sh_pfc_pmx->pctl, &sh_pfc_gpio_range);

	platform_set_drvdata(pdev, sh_pfc_pmx);

	return 0;

free_functions:
	kfree(sh_pfc_pmx->functions);
free_pads:
	kfree(sh_pfc_pmx->pads);
	kfree(sh_pfc_pmx);

	return ret;
}

static int __devexit sh_pfc_pinctrl_remove(struct platform_device *pdev)
{
	struct sh_pfc_pinctrl *pmx = platform_get_drvdata(pdev);

	pinctrl_unregister(pmx->pctl);

	platform_set_drvdata(pdev, NULL);

	kfree(sh_pfc_pmx->functions);
	kfree(sh_pfc_pmx->pads);
	kfree(sh_pfc_pmx);

	return 0;
}

static struct platform_driver sh_pfc_pinctrl_driver = {
	.probe		= sh_pfc_pinctrl_probe,
	.remove		= __devexit_p(sh_pfc_pinctrl_remove),
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
	},
};

static struct platform_device sh_pfc_pinctrl_device = {
	.name		= DRV_NAME,
	.id		= -1,
};

static int sh_pfc_pinctrl_init(void)
{
	int rc;

	rc = platform_driver_register(&sh_pfc_pinctrl_driver);
	if (likely(!rc)) {
		rc = platform_device_register(&sh_pfc_pinctrl_device);
		if (unlikely(rc))
			platform_driver_unregister(&sh_pfc_pinctrl_driver);
	}

	return rc;
}

int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
	sh_pfc_pmx = kzalloc(sizeof(struct sh_pfc_pinctrl), GFP_KERNEL);
	if (unlikely(!sh_pfc_pmx))
		return -ENOMEM;

	spin_lock_init(&sh_pfc_pmx->lock);

	sh_pfc_pmx->pfc = pfc;

	return sh_pfc_pinctrl_init();
}
EXPORT_SYMBOL_GPL(sh_pfc_register_pinctrl);

static void __exit sh_pfc_pinctrl_exit(void)
{
	platform_driver_unregister(&sh_pfc_pinctrl_driver);
}
module_exit(sh_pfc_pinctrl_exit);
Commit	Line	Data
ca5481c6 PM	1	/*
	2	* SuperH Pin Function Controller pinmux support.
	3	*
	4	* Copyright (C) 2012 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
54407110 PM	10	#define DRV_NAME "pinctrl-sh_pfc"
	11
	12	#define pr_fmt(fmt) DRV_NAME " " KBUILD_MODNAME ": " fmt
ca5481c6 PM	13
	14	#include <linux/init.h>
	15	#include <linux/module.h>
	16	#include <linux/sh_pfc.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
d93a891f	19	#include <linux/spinlock.h>
ca5481c6 PM	20	#include <linux/platform_device.h>
	21	#include <linux/pinctrl/consumer.h>
	22	#include <linux/pinctrl/pinctrl.h>
	23	#include <linux/pinctrl/pinconf.h>
	24	#include <linux/pinctrl/pinmux.h>
	25	#include <linux/pinctrl/pinconf-generic.h>
	26
	27	struct sh_pfc_pinctrl {
	28	struct pinctrl_dev *pctl;
	29	struct sh_pfc *pfc;
	30
d93a891f PM	31	struct pinmux_gpio **functions;
	32	unsigned int nr_functions;
	33
ca5481c6 PM	34	struct pinctrl_pin_desc *pads;
ca5481c6 PM	35	unsigned int nr_pads;
d93a891f PM	36
d93a891f PM	37	spinlock_t lock;
ca5481c6 PM	38	};
	39
	40	static struct sh_pfc_pinctrl *sh_pfc_pmx;
	41
e3f805e8	42	static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
ca5481c6	43	{
e3f805e8 PM	44	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	45
	46	return pmx->nr_pads;
ca5481c6 PM	47	}
ca5481c6 PM	48
e3f805e8	49	static const char sh_pfc_get_group_name(struct pinctrl_dev pctldev,
ca5481c6 PM	50	unsigned selector)
ca5481c6 PM	51	{
e3f805e8 PM	52	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	53
	54	return pmx->pads[selector].name;
ca5481c6 PM	55	}
	56
	57	static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
	58	const unsigned *pins, unsigned num_pins)
	59	{
e3f805e8 PM	60	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	61
	62	*pins = &pmx->pads[group].number;
	63	*num_pins = 1;
	64
	65	return 0;
ca5481c6 PM	66	}
ca5481c6 PM	67
fdd85ec3 PM	68	static void sh_pfc_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
	69	unsigned offset)
	70	{
	71	seq_printf(s, "%s", DRV_NAME);
	72	}
	73
ca5481c6	74	static struct pinctrl_ops sh_pfc_pinctrl_ops = {
e3f805e8 PM	75	.get_groups_count = sh_pfc_get_groups_count,
e3f805e8 PM	76	.get_group_name = sh_pfc_get_group_name,
ca5481c6	77	.get_group_pins = sh_pfc_get_group_pins,
fdd85ec3	78	.pin_dbg_show = sh_pfc_pin_dbg_show,
ca5481c6 PM	79	};
ca5481c6 PM	80
d93a891f PM	81	static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
	82	{
	83	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	84
	85	return pmx->nr_functions;
	86	}
	87
	88	static const char sh_pfc_get_function_name(struct pinctrl_dev pctldev,
	89	unsigned selector)
	90	{
	91	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	92
	93	return pmx->functions[selector]->name;
	94	}
ca5481c6	95
ca5481c6 PM	96	static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
	97	const char * const **groups,
	98	unsigned * const num_groups)
	99	{
d93a891f PM	100	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	101
	102	*groups = &pmx->functions[func]->name;
	103	*num_groups = 1;
	104
ca5481c6 PM	105	return 0;
	106	}
	107
	108	static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
	109	unsigned group)
	110	{
	111	return 0;
	112	}
	113
	114	static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
	115	unsigned group)
	116	{
	117	}
	118
d93a891f PM	119	static inline int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
	120	{
	121	if (sh_pfc_config_gpio(pfc, offset,
	122	PINMUX_TYPE_FUNCTION,
	123	GPIO_CFG_DRYRUN) != 0)
	124	return -EINVAL;
	125
	126	if (sh_pfc_config_gpio(pfc, offset,
	127	PINMUX_TYPE_FUNCTION,
	128	GPIO_CFG_REQ) != 0)
	129	return -EINVAL;
	130
	131	return 0;
	132	}
	133
fdd85ec3 PM	134	static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
	135	int new_type)
	136	{
	137	unsigned long flags;
	138	int pinmux_type;
	139	int ret = -EINVAL;
	140
	141	spin_lock_irqsave(&pfc->lock, flags);
	142
	143	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
	144
	145	/*
	146	* See if the present config needs to first be de-configured.
	147	*/
	148	switch (pinmux_type) {
	149	case PINMUX_TYPE_GPIO:
	150	break;
	151	case PINMUX_TYPE_OUTPUT:
	152	case PINMUX_TYPE_INPUT:
	153	case PINMUX_TYPE_INPUT_PULLUP:
	154	case PINMUX_TYPE_INPUT_PULLDOWN:
	155	sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
	156	break;
	157	default:
	158	goto err;
	159	}
	160
	161	/*
	162	* Dry run
	163	*/
	164	if (sh_pfc_config_gpio(pfc, offset, new_type,
	165	GPIO_CFG_DRYRUN) != 0)
	166	goto err;
	167
	168	/*
	169	* Request
	170	*/
	171	if (sh_pfc_config_gpio(pfc, offset, new_type,
	172	GPIO_CFG_REQ) != 0)
	173	goto err;
	174
	175	pfc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
	176	pfc->gpios[offset].flags \|= new_type;
	177
	178	ret = 0;
	179
	180	err:
	181	spin_unlock_irqrestore(&pfc->lock, flags);
	182
	183	return ret;
	184	}
	185
	186
ca5481c6 PM	187	static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
	188	struct pinctrl_gpio_range *range,
	189	unsigned offset)
	190	{
	191	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	192	struct sh_pfc *pfc = pmx->pfc;
ca5481c6	193	unsigned long flags;
d93a891f	194	int ret, pinmux_type;
ca5481c6 PM	195
	196	spin_lock_irqsave(&pfc->lock, flags);
	197
d93a891f	198	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
ca5481c6	199
d93a891f PM	200	switch (pinmux_type) {
	201	case PINMUX_TYPE_FUNCTION:
	202	pr_notice_once("Use of GPIO API for function requests is "
	203	"deprecated, convert to pinctrl\n");
	204	/* handle for now */
	205	ret = sh_pfc_config_function(pfc, offset);
	206	if (unlikely(ret < 0))
ca5481c6	207	goto err;
ca5481c6	208
d93a891f PM	209	break;
	210	case PINMUX_TYPE_GPIO:
	211	break;
	212	default:
	213	pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
077664a2 LP	214	ret = -ENOTSUPP;
077664a2 LP	215	goto err;
d93a891f	216	}
ca5481c6 PM	217
	218	ret = 0;
	219
	220	err:
	221	spin_unlock_irqrestore(&pfc->lock, flags);
	222
	223	return ret;
	224	}
	225
	226	static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
	227	struct pinctrl_gpio_range *range,
	228	unsigned offset)
	229	{
	230	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	231	struct sh_pfc *pfc = pmx->pfc;
	232	unsigned long flags;
	233	int pinmux_type;
	234
	235	spin_lock_irqsave(&pfc->lock, flags);
	236
	237	pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
	238
	239	sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
	240
ca5481c6 PM	241	spin_unlock_irqrestore(&pfc->lock, flags);
	242	}
	243
	244	static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
	245	struct pinctrl_gpio_range *range,
	246	unsigned offset, bool input)
	247	{
	248	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
fdd85ec3	249	int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
ca5481c6	250
fdd85ec3	251	return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
ca5481c6 PM	252	}
	253
	254	static struct pinmux_ops sh_pfc_pinmux_ops = {
d93a891f PM	255	.get_functions_count = sh_pfc_get_functions_count,
d93a891f PM	256	.get_function_name = sh_pfc_get_function_name,
ca5481c6 PM	257	.get_function_groups = sh_pfc_get_function_groups,
	258	.enable = sh_pfc_noop_enable,
	259	.disable = sh_pfc_noop_disable,
	260	.gpio_request_enable = sh_pfc_gpio_request_enable,
	261	.gpio_disable_free = sh_pfc_gpio_disable_free,
	262	.gpio_set_direction = sh_pfc_gpio_set_direction,
	263	};
	264
	265	static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
	266	unsigned long *config)
	267	{
fdd85ec3 PM	268	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
fdd85ec3 PM	269	struct sh_pfc *pfc = pmx->pfc;
d93a891f	270
fdd85ec3	271	*config = pfc->gpios[pin].flags & PINMUX_FLAG_TYPE;
d93a891f	272
fdd85ec3	273	return 0;
ca5481c6 PM	274	}
	275
	276	static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
	277	unsigned long config)
	278	{
fdd85ec3	279	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
fdd85ec3 PM	280
	281	/* Validate the new type */
	282	if (config >= PINMUX_FLAG_TYPE)
	283	return -EINVAL;
	284
	285	return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
	286	}
	287
	288	static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
	289	struct seq_file *s, unsigned pin)
	290	{
	291	const char *pinmux_type_str[] = {
	292	[PINMUX_TYPE_NONE] = "none",
	293	[PINMUX_TYPE_FUNCTION] = "function",
	294	[PINMUX_TYPE_GPIO] = "gpio",
	295	[PINMUX_TYPE_OUTPUT] = "output",
	296	[PINMUX_TYPE_INPUT] = "input",
	297	[PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
	298	[PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
	299	};
	300	unsigned long config;
	301	int rc;
	302
	303	rc = sh_pfc_pinconf_get(pctldev, pin, &config);
	304	if (unlikely(rc != 0))
	305	return;
	306
	307	seq_printf(s, " %s", pinmux_type_str[config]);
ca5481c6 PM	308	}
	309
	310	static struct pinconf_ops sh_pfc_pinconf_ops = {
ca5481c6 PM	311	.pin_config_get = sh_pfc_pinconf_get,
ca5481c6 PM	312	.pin_config_set = sh_pfc_pinconf_set,
fdd85ec3	313	.pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
ca5481c6 PM	314	};
	315
	316	static struct pinctrl_gpio_range sh_pfc_gpio_range = {
54407110	317	.name = DRV_NAME,
ca5481c6 PM	318	.id = 0,
	319	};
	320
	321	static struct pinctrl_desc sh_pfc_pinctrl_desc = {
54407110	322	.name = DRV_NAME,
ca5481c6 PM	323	.owner = THIS_MODULE,
	324	.pctlops = &sh_pfc_pinctrl_ops,
	325	.pmxops = &sh_pfc_pinmux_ops,
	326	.confops = &sh_pfc_pinconf_ops,
	327	};
	328
d93a891f PM	329	static inline void __devinit sh_pfc_map_one_gpio(struct sh_pfc *pfc,
	330	struct sh_pfc_pinctrl *pmx,
	331	struct pinmux_gpio *gpio,
	332	unsigned offset)
	333	{
	334	struct pinmux_data_reg *dummy;
	335	unsigned long flags;
	336	int bit;
	337
	338	gpio->flags &= ~PINMUX_FLAG_TYPE;
	339
	340	if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
	341	gpio->flags \|= PINMUX_TYPE_GPIO;
	342	else {
	343	gpio->flags \|= PINMUX_TYPE_FUNCTION;
	344
	345	spin_lock_irqsave(&pmx->lock, flags);
	346	pmx->nr_functions++;
	347	spin_unlock_irqrestore(&pmx->lock, flags);
	348	}
	349	}
	350
ca5481c6 PM	351	/* pinmux ranges -> pinctrl pin descs */
	352	static int __devinit sh_pfc_map_gpios(struct sh_pfc *pfc,
	353	struct sh_pfc_pinctrl *pmx)
	354	{
d93a891f	355	unsigned long flags;
ca5481c6 PM	356	int i;
	357
	358	pmx->nr_pads = pfc->last_gpio - pfc->first_gpio + 1;
	359
	360	pmx->pads = kmalloc(sizeof(struct pinctrl_pin_desc) * pmx->nr_pads,
	361	GFP_KERNEL);
	362	if (unlikely(!pmx->pads)) {
	363	pmx->nr_pads = 0;
	364	return -ENOMEM;
	365	}
	366
d93a891f PM	367	spin_lock_irqsave(&pfc->lock, flags);
d93a891f PM	368
ca5481c6 PM	369	/*
	370	* We don't necessarily have a 1:1 mapping between pin and linux
	371	* GPIO number, as the latter maps to the associated enum_id.
	372	* Care needs to be taken to translate back to pin space when
	373	* dealing with any pin configurations.
	374	*/
	375	for (i = 0; i < pmx->nr_pads; i++) {
	376	struct pinctrl_pin_desc *pin = pmx->pads + i;
	377	struct pinmux_gpio *gpio = pfc->gpios + i;
	378
	379	pin->number = pfc->first_gpio + i;
	380	pin->name = gpio->name;
d93a891f	381
e3e79454 PM	382	/* XXX */
	383	if (unlikely(!gpio->enum_id))
	384	continue;
	385
d93a891f	386	sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
ca5481c6 PM	387	}
ca5481c6 PM	388
d93a891f PM	389	spin_unlock_irqrestore(&pfc->lock, flags);
d93a891f PM	390
ca5481c6 PM	391	sh_pfc_pinctrl_desc.pins = pmx->pads;
	392	sh_pfc_pinctrl_desc.npins = pmx->nr_pads;
	393
	394	return 0;
	395	}
	396
d93a891f PM	397	static int __devinit sh_pfc_map_functions(struct sh_pfc *pfc,
	398	struct sh_pfc_pinctrl *pmx)
	399	{
	400	unsigned long flags;
	401	int i, fn;
	402
	403	pmx->functions = kzalloc(pmx->nr_functions * sizeof(void *),
	404	GFP_KERNEL);
	405	if (unlikely(!pmx->functions))
	406	return -ENOMEM;
	407
	408	spin_lock_irqsave(&pmx->lock, flags);
	409
	410	for (i = fn = 0; i < pmx->nr_pads; i++) {
	411	struct pinmux_gpio *gpio = pfc->gpios + i;
	412
	413	if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
	414	pmx->functions[fn++] = gpio;
	415	}
	416
	417	spin_unlock_irqrestore(&pmx->lock, flags);
	418
	419	return 0;
	420	}
	421
ca5481c6 PM	422	static int __devinit sh_pfc_pinctrl_probe(struct platform_device *pdev)
	423	{
	424	struct sh_pfc *pfc;
	425	int ret;
	426
	427	if (unlikely(!sh_pfc_pmx))
	428	return -ENODEV;
	429
	430	pfc = sh_pfc_pmx->pfc;
	431
	432	ret = sh_pfc_map_gpios(pfc, sh_pfc_pmx);
	433	if (unlikely(ret != 0))
	434	return ret;
	435
d93a891f PM	436	ret = sh_pfc_map_functions(pfc, sh_pfc_pmx);
	437	if (unlikely(ret != 0))
	438	goto free_pads;
	439
ca5481c6 PM	440	sh_pfc_pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, &pdev->dev,
	441	sh_pfc_pmx);
	442	if (IS_ERR(sh_pfc_pmx->pctl)) {
	443	ret = PTR_ERR(sh_pfc_pmx->pctl);
d93a891f	444	goto free_functions;
ca5481c6 PM	445	}
	446
	447	sh_pfc_gpio_range.npins = pfc->last_gpio - pfc->first_gpio + 1;
	448	sh_pfc_gpio_range.base = pfc->first_gpio;
	449	sh_pfc_gpio_range.pin_base = pfc->first_gpio;
	450
	451	pinctrl_add_gpio_range(sh_pfc_pmx->pctl, &sh_pfc_gpio_range);
	452
	453	platform_set_drvdata(pdev, sh_pfc_pmx);
	454
	455	return 0;
	456
d93a891f PM	457	free_functions:
	458	kfree(sh_pfc_pmx->functions);
	459	free_pads:
ca5481c6 PM	460	kfree(sh_pfc_pmx->pads);
ca5481c6 PM	461	kfree(sh_pfc_pmx);
d93a891f	462
ca5481c6 PM	463	return ret;
	464	}
	465
	466	static int __devexit sh_pfc_pinctrl_remove(struct platform_device *pdev)
	467	{
	468	struct sh_pfc_pinctrl *pmx = platform_get_drvdata(pdev);
	469
ca5481c6 PM	470	pinctrl_unregister(pmx->pctl);
	471
	472	platform_set_drvdata(pdev, NULL);
	473
d93a891f	474	kfree(sh_pfc_pmx->functions);
ca5481c6 PM	475	kfree(sh_pfc_pmx->pads);
	476	kfree(sh_pfc_pmx);
	477
	478	return 0;
	479	}
	480
	481	static struct platform_driver sh_pfc_pinctrl_driver = {
	482	.probe = sh_pfc_pinctrl_probe,
	483	.remove = __devexit_p(sh_pfc_pinctrl_remove),
	484	.driver = {
54407110	485	.name = DRV_NAME,
ca5481c6 PM	486	.owner = THIS_MODULE,
	487	},
	488	};
	489
	490	static struct platform_device sh_pfc_pinctrl_device = {
54407110	491	.name = DRV_NAME,
ca5481c6 PM	492	.id = -1,
	493	};
	494
1e32dfe3	495	static int sh_pfc_pinctrl_init(void)
ca5481c6 PM	496	{
	497	int rc;
	498
	499	rc = platform_driver_register(&sh_pfc_pinctrl_driver);
	500	if (likely(!rc)) {
	501	rc = platform_device_register(&sh_pfc_pinctrl_device);
	502	if (unlikely(rc))
	503	platform_driver_unregister(&sh_pfc_pinctrl_driver);
	504	}
	505
	506	return rc;
	507	}
	508
1e32dfe3 PM	509	int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
	510	{
	511	sh_pfc_pmx = kzalloc(sizeof(struct sh_pfc_pinctrl), GFP_KERNEL);
	512	if (unlikely(!sh_pfc_pmx))
	513	return -ENOMEM;
	514
	515	spin_lock_init(&sh_pfc_pmx->lock);
	516
	517	sh_pfc_pmx->pfc = pfc;
	518
	519	return sh_pfc_pinctrl_init();
	520	}
	521	EXPORT_SYMBOL_GPL(sh_pfc_register_pinctrl);
	522
ca5481c6 PM	523	static void __exit sh_pfc_pinctrl_exit(void)
	524	{
	525	platform_driver_unregister(&sh_pfc_pinctrl_driver);
	526	}
ca5481c6	527	module_exit(sh_pfc_pinctrl_exit);