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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2005 Silicon Graphics, Inc. All Rights Reserved. | |
7 | */ | |
8 | ||
22329b51 BC |
9 | /* This file contains the master driver module for use by SGI IOC4 subdrivers. |
10 | * | |
11 | * It allocates any resources shared between multiple subdevices, and | |
12 | * provides accessor functions (where needed) and the like for those | |
13 | * resources. It also provides a mechanism for the subdevice modules | |
14 | * to support loading and unloading. | |
15 | * | |
16 | * Non-shared resources (e.g. external interrupt A_INT_OUT register page | |
17 | * alias, serial port and UART registers) are handled by the subdevice | |
18 | * modules themselves. | |
19 | * | |
20 | * This is all necessary because IOC4 is not implemented as a multi-function | |
21 | * PCI device, but an amalgamation of disparate registers for several | |
22 | * types of device (ATA, serial, external interrupts). The normal | |
23 | * resource management in the kernel doesn't have quite the right interfaces | |
24 | * to handle this situation (e.g. multiple modules can't claim the same | |
25 | * PCI ID), thus this IOC4 master module. | |
1da177e4 LT |
26 | */ |
27 | ||
28 | #include <linux/errno.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
22329b51 | 31 | #include <linux/ioc4.h> |
d4c477ca BC |
32 | #include <linux/mmtimer.h> |
33 | #include <linux/rtc.h> | |
6e586f32 | 34 | #include <linux/mutex.h> |
d4c477ca BC |
35 | #include <asm/sn/addrs.h> |
36 | #include <asm/sn/clksupport.h> | |
37 | #include <asm/sn/shub_mmr.h> | |
38 | ||
39 | /*************** | |
40 | * Definitions * | |
41 | ***************/ | |
42 | ||
43 | /* Tweakable values */ | |
44 | ||
45 | /* PCI bus speed detection/calibration */ | |
46 | #define IOC4_CALIBRATE_COUNT 63 /* Calibration cycle period */ | |
47 | #define IOC4_CALIBRATE_CYCLES 256 /* Average over this many cycles */ | |
48 | #define IOC4_CALIBRATE_DISCARD 2 /* Discard first few cycles */ | |
49 | #define IOC4_CALIBRATE_LOW_MHZ 25 /* Lower bound on bus speed sanity */ | |
50 | #define IOC4_CALIBRATE_HIGH_MHZ 75 /* Upper bound on bus speed sanity */ | |
51 | #define IOC4_CALIBRATE_DEFAULT_MHZ 66 /* Assumed if sanity check fails */ | |
1da177e4 | 52 | |
22329b51 BC |
53 | /************************ |
54 | * Submodule management * | |
55 | ************************/ | |
1da177e4 | 56 | |
6e586f32 | 57 | static DEFINE_MUTEX(ioc4_mutex); |
22329b51 | 58 | |
6e586f32 | 59 | static LIST_HEAD(ioc4_devices); |
22329b51 | 60 | static LIST_HEAD(ioc4_submodules); |
22329b51 BC |
61 | |
62 | /* Register an IOC4 submodule */ | |
63 | int | |
64 | ioc4_register_submodule(struct ioc4_submodule *is) | |
65 | { | |
66 | struct ioc4_driver_data *idd; | |
67 | ||
6e586f32 | 68 | mutex_lock(&ioc4_mutex); |
22329b51 | 69 | list_add(&is->is_list, &ioc4_submodules); |
22329b51 BC |
70 | |
71 | /* Initialize submodule for each IOC4 */ | |
72 | if (!is->is_probe) | |
6e586f32 | 73 | goto out; |
22329b51 | 74 | |
22329b51 BC |
75 | list_for_each_entry(idd, &ioc4_devices, idd_list) { |
76 | if (is->is_probe(idd)) { | |
77 | printk(KERN_WARNING | |
78 | "%s: IOC4 submodule %s probe failed " | |
79 | "for pci_dev %s", | |
80 | __FUNCTION__, module_name(is->is_owner), | |
81 | pci_name(idd->idd_pdev)); | |
82 | } | |
83 | } | |
6e586f32 JS |
84 | out: |
85 | mutex_unlock(&ioc4_mutex); | |
22329b51 BC |
86 | return 0; |
87 | } | |
88 | ||
89 | /* Unregister an IOC4 submodule */ | |
90 | void | |
91 | ioc4_unregister_submodule(struct ioc4_submodule *is) | |
1da177e4 | 92 | { |
22329b51 BC |
93 | struct ioc4_driver_data *idd; |
94 | ||
6e586f32 | 95 | mutex_lock(&ioc4_mutex); |
22329b51 | 96 | list_del(&is->is_list); |
22329b51 BC |
97 | |
98 | /* Remove submodule for each IOC4 */ | |
99 | if (!is->is_remove) | |
6e586f32 | 100 | goto out; |
22329b51 | 101 | |
22329b51 BC |
102 | list_for_each_entry(idd, &ioc4_devices, idd_list) { |
103 | if (is->is_remove(idd)) { | |
104 | printk(KERN_WARNING | |
105 | "%s: IOC4 submodule %s remove failed " | |
106 | "for pci_dev %s.\n", | |
107 | __FUNCTION__, module_name(is->is_owner), | |
108 | pci_name(idd->idd_pdev)); | |
109 | } | |
110 | } | |
6e586f32 JS |
111 | out: |
112 | mutex_unlock(&ioc4_mutex); | |
22329b51 BC |
113 | } |
114 | ||
115 | /********************* | |
116 | * Device management * | |
117 | *********************/ | |
118 | ||
d4c477ca BC |
119 | #define IOC4_CALIBRATE_LOW_LIMIT \ |
120 | (1000*IOC4_EXTINT_COUNT_DIVISOR/IOC4_CALIBRATE_LOW_MHZ) | |
121 | #define IOC4_CALIBRATE_HIGH_LIMIT \ | |
122 | (1000*IOC4_EXTINT_COUNT_DIVISOR/IOC4_CALIBRATE_HIGH_MHZ) | |
123 | #define IOC4_CALIBRATE_DEFAULT \ | |
124 | (1000*IOC4_EXTINT_COUNT_DIVISOR/IOC4_CALIBRATE_DEFAULT_MHZ) | |
125 | ||
126 | #define IOC4_CALIBRATE_END \ | |
127 | (IOC4_CALIBRATE_CYCLES + IOC4_CALIBRATE_DISCARD) | |
128 | ||
129 | #define IOC4_INT_OUT_MODE_TOGGLE 0x7 /* Toggle INT_OUT every COUNT+1 ticks */ | |
130 | ||
131 | /* Determines external interrupt output clock period of the PCI bus an | |
132 | * IOC4 is attached to. This value can be used to determine the PCI | |
133 | * bus speed. | |
134 | * | |
135 | * IOC4 has a design feature that various internal timers are derived from | |
136 | * the PCI bus clock. This causes IOC4 device drivers to need to take the | |
137 | * bus speed into account when setting various register values (e.g. INT_OUT | |
138 | * register COUNT field, UART divisors, etc). Since this information is | |
139 | * needed by several subdrivers, it is determined by the main IOC4 driver, | |
140 | * even though the following code utilizes external interrupt registers | |
141 | * to perform the speed calculation. | |
142 | */ | |
143 | static void | |
144 | ioc4_clock_calibrate(struct ioc4_driver_data *idd) | |
145 | { | |
146 | extern unsigned long sn_rtc_cycles_per_second; | |
147 | union ioc4_int_out int_out; | |
148 | union ioc4_gpcr gpcr; | |
149 | unsigned int state, last_state = 1; | |
150 | uint64_t start = 0, end, period; | |
151 | unsigned int count = 0; | |
152 | ||
153 | /* Enable output */ | |
154 | gpcr.raw = 0; | |
155 | gpcr.fields.dir = IOC4_GPCR_DIR_0; | |
156 | gpcr.fields.int_out_en = 1; | |
157 | writel(gpcr.raw, &idd->idd_misc_regs->gpcr_s.raw); | |
158 | ||
159 | /* Reset to power-on state */ | |
160 | writel(0, &idd->idd_misc_regs->int_out.raw); | |
161 | mmiowb(); | |
162 | ||
163 | printk(KERN_INFO | |
164 | "%s: Calibrating PCI bus speed " | |
165 | "for pci_dev %s ... ", __FUNCTION__, pci_name(idd->idd_pdev)); | |
166 | /* Set up square wave */ | |
167 | int_out.raw = 0; | |
168 | int_out.fields.count = IOC4_CALIBRATE_COUNT; | |
169 | int_out.fields.mode = IOC4_INT_OUT_MODE_TOGGLE; | |
170 | int_out.fields.diag = 0; | |
171 | writel(int_out.raw, &idd->idd_misc_regs->int_out.raw); | |
172 | mmiowb(); | |
173 | ||
174 | /* Check square wave period averaged over some number of cycles */ | |
175 | do { | |
176 | int_out.raw = readl(&idd->idd_misc_regs->int_out.raw); | |
177 | state = int_out.fields.int_out; | |
178 | if (!last_state && state) { | |
179 | count++; | |
180 | if (count == IOC4_CALIBRATE_END) { | |
181 | end = rtc_time(); | |
182 | break; | |
183 | } else if (count == IOC4_CALIBRATE_DISCARD) | |
184 | start = rtc_time(); | |
185 | } | |
186 | last_state = state; | |
187 | } while (1); | |
188 | ||
189 | /* Calculation rearranged to preserve intermediate precision. | |
190 | * Logically: | |
191 | * 1. "end - start" gives us number of RTC cycles over all the | |
192 | * square wave cycles measured. | |
193 | * 2. Divide by number of square wave cycles to get number of | |
194 | * RTC cycles per square wave cycle. | |
195 | * 3. Divide by 2*(int_out.fields.count+1), which is the formula | |
196 | * by which the IOC4 generates the square wave, to get the | |
197 | * number of RTC cycles per IOC4 INT_OUT count. | |
198 | * 4. Divide by sn_rtc_cycles_per_second to get seconds per | |
199 | * count. | |
200 | * 5. Multiply by 1E9 to get nanoseconds per count. | |
201 | */ | |
202 | period = ((end - start) * 1000000000) / | |
203 | (IOC4_CALIBRATE_CYCLES * 2 * (IOC4_CALIBRATE_COUNT + 1) | |
204 | * sn_rtc_cycles_per_second); | |
205 | ||
206 | /* Bounds check the result. */ | |
207 | if (period > IOC4_CALIBRATE_LOW_LIMIT || | |
208 | period < IOC4_CALIBRATE_HIGH_LIMIT) { | |
209 | printk("failed. Assuming PCI clock ticks are %d ns.\n", | |
210 | IOC4_CALIBRATE_DEFAULT / IOC4_EXTINT_COUNT_DIVISOR); | |
211 | period = IOC4_CALIBRATE_DEFAULT; | |
212 | } else { | |
213 | printk("succeeded. PCI clock ticks are %ld ns.\n", | |
214 | period / IOC4_EXTINT_COUNT_DIVISOR); | |
215 | } | |
216 | ||
217 | /* Remember results. We store the extint clock period rather | |
218 | * than the PCI clock period so that greater precision is | |
219 | * retained. Divide by IOC4_EXTINT_COUNT_DIVISOR to get | |
220 | * PCI clock period. | |
221 | */ | |
222 | idd->count_period = period; | |
223 | } | |
224 | ||
22329b51 BC |
225 | /* Adds a new instance of an IOC4 card */ |
226 | static int | |
227 | ioc4_probe(struct pci_dev *pdev, const struct pci_device_id *pci_id) | |
228 | { | |
229 | struct ioc4_driver_data *idd; | |
230 | struct ioc4_submodule *is; | |
231 | uint32_t pcmd; | |
1da177e4 LT |
232 | int ret; |
233 | ||
22329b51 | 234 | /* Enable IOC4 and take ownership of it */ |
1da177e4 LT |
235 | if ((ret = pci_enable_device(pdev))) { |
236 | printk(KERN_WARNING | |
22329b51 BC |
237 | "%s: Failed to enable IOC4 device for pci_dev %s.\n", |
238 | __FUNCTION__, pci_name(pdev)); | |
239 | goto out; | |
1da177e4 LT |
240 | } |
241 | pci_set_master(pdev); | |
242 | ||
22329b51 BC |
243 | /* Set up per-IOC4 data */ |
244 | idd = kmalloc(sizeof(struct ioc4_driver_data), GFP_KERNEL); | |
245 | if (!idd) { | |
246 | printk(KERN_WARNING | |
247 | "%s: Failed to allocate IOC4 data for pci_dev %s.\n", | |
248 | __FUNCTION__, pci_name(pdev)); | |
249 | ret = -ENODEV; | |
250 | goto out_idd; | |
251 | } | |
252 | idd->idd_pdev = pdev; | |
253 | idd->idd_pci_id = pci_id; | |
254 | ||
255 | /* Map IOC4 misc registers. These are shared between subdevices | |
256 | * so the main IOC4 module manages them. | |
257 | */ | |
258 | idd->idd_bar0 = pci_resource_start(idd->idd_pdev, 0); | |
259 | if (!idd->idd_bar0) { | |
260 | printk(KERN_WARNING | |
261 | "%s: Unable to find IOC4 misc resource " | |
262 | "for pci_dev %s.\n", | |
263 | __FUNCTION__, pci_name(idd->idd_pdev)); | |
264 | ret = -ENODEV; | |
265 | goto out_pci; | |
266 | } | |
267 | if (!request_region(idd->idd_bar0, sizeof(struct ioc4_misc_regs), | |
268 | "ioc4_misc")) { | |
269 | printk(KERN_WARNING | |
270 | "%s: Unable to request IOC4 misc region " | |
271 | "for pci_dev %s.\n", | |
272 | __FUNCTION__, pci_name(idd->idd_pdev)); | |
273 | ret = -ENODEV; | |
274 | goto out_pci; | |
275 | } | |
276 | idd->idd_misc_regs = ioremap(idd->idd_bar0, | |
277 | sizeof(struct ioc4_misc_regs)); | |
278 | if (!idd->idd_misc_regs) { | |
279 | printk(KERN_WARNING | |
280 | "%s: Unable to remap IOC4 misc region " | |
281 | "for pci_dev %s.\n", | |
282 | __FUNCTION__, pci_name(idd->idd_pdev)); | |
283 | ret = -ENODEV; | |
284 | goto out_misc_region; | |
285 | } | |
286 | ||
287 | /* Failsafe portion of per-IOC4 initialization */ | |
288 | ||
289 | /* Initialize IOC4 */ | |
290 | pci_read_config_dword(idd->idd_pdev, PCI_COMMAND, &pcmd); | |
291 | pci_write_config_dword(idd->idd_pdev, PCI_COMMAND, | |
292 | pcmd | PCI_COMMAND_PARITY | PCI_COMMAND_SERR); | |
293 | ||
d4c477ca BC |
294 | /* Determine PCI clock */ |
295 | ioc4_clock_calibrate(idd); | |
296 | ||
22329b51 BC |
297 | /* Disable/clear all interrupts. Need to do this here lest |
298 | * one submodule request the shared IOC4 IRQ, but interrupt | |
299 | * is generated by a different subdevice. | |
300 | */ | |
301 | /* Disable */ | |
302 | writel(~0, &idd->idd_misc_regs->other_iec.raw); | |
303 | writel(~0, &idd->idd_misc_regs->sio_iec); | |
304 | /* Clear (i.e. acknowledge) */ | |
305 | writel(~0, &idd->idd_misc_regs->other_ir.raw); | |
306 | writel(~0, &idd->idd_misc_regs->sio_ir); | |
307 | ||
308 | /* Track PCI-device specific data */ | |
309 | idd->idd_serial_data = NULL; | |
310 | pci_set_drvdata(idd->idd_pdev, idd); | |
6e586f32 JS |
311 | |
312 | mutex_lock(&ioc4_mutex); | |
22329b51 | 313 | list_add(&idd->idd_list, &ioc4_devices); |
22329b51 BC |
314 | |
315 | /* Add this IOC4 to all submodules */ | |
22329b51 BC |
316 | list_for_each_entry(is, &ioc4_submodules, is_list) { |
317 | if (is->is_probe && is->is_probe(idd)) { | |
318 | printk(KERN_WARNING | |
319 | "%s: IOC4 submodule 0x%s probe failed " | |
320 | "for pci_dev %s.\n", | |
321 | __FUNCTION__, module_name(is->is_owner), | |
322 | pci_name(idd->idd_pdev)); | |
323 | } | |
324 | } | |
6e586f32 | 325 | mutex_unlock(&ioc4_mutex); |
22329b51 BC |
326 | |
327 | return 0; | |
328 | ||
329 | out_misc_region: | |
330 | release_region(idd->idd_bar0, sizeof(struct ioc4_misc_regs)); | |
331 | out_pci: | |
332 | kfree(idd); | |
333 | out_idd: | |
334 | pci_disable_device(pdev); | |
335 | out: | |
336 | return ret; | |
1da177e4 LT |
337 | } |
338 | ||
22329b51 BC |
339 | /* Removes a particular instance of an IOC4 card. */ |
340 | static void | |
341 | ioc4_remove(struct pci_dev *pdev) | |
342 | { | |
343 | struct ioc4_submodule *is; | |
344 | struct ioc4_driver_data *idd; | |
345 | ||
346 | idd = pci_get_drvdata(pdev); | |
347 | ||
348 | /* Remove this IOC4 from all submodules */ | |
6e586f32 | 349 | mutex_lock(&ioc4_mutex); |
22329b51 BC |
350 | list_for_each_entry(is, &ioc4_submodules, is_list) { |
351 | if (is->is_remove && is->is_remove(idd)) { | |
352 | printk(KERN_WARNING | |
353 | "%s: IOC4 submodule 0x%s remove failed " | |
354 | "for pci_dev %s.\n", | |
355 | __FUNCTION__, module_name(is->is_owner), | |
356 | pci_name(idd->idd_pdev)); | |
357 | } | |
358 | } | |
6e586f32 | 359 | mutex_unlock(&ioc4_mutex); |
22329b51 BC |
360 | |
361 | /* Release resources */ | |
362 | iounmap(idd->idd_misc_regs); | |
363 | if (!idd->idd_bar0) { | |
364 | printk(KERN_WARNING | |
365 | "%s: Unable to get IOC4 misc mapping for pci_dev %s. " | |
366 | "Device removal may be incomplete.\n", | |
367 | __FUNCTION__, pci_name(idd->idd_pdev)); | |
368 | } | |
369 | release_region(idd->idd_bar0, sizeof(struct ioc4_misc_regs)); | |
370 | ||
371 | /* Disable IOC4 and relinquish */ | |
372 | pci_disable_device(pdev); | |
373 | ||
374 | /* Remove and free driver data */ | |
6e586f32 | 375 | mutex_lock(&ioc4_mutex); |
22329b51 | 376 | list_del(&idd->idd_list); |
6e586f32 | 377 | mutex_unlock(&ioc4_mutex); |
22329b51 BC |
378 | kfree(idd); |
379 | } | |
380 | ||
381 | static struct pci_device_id ioc4_id_table[] = { | |
1da177e4 LT |
382 | {PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC4, PCI_ANY_ID, |
383 | PCI_ANY_ID, 0x0b4000, 0xFFFFFF}, | |
384 | {0} | |
385 | }; | |
1da177e4 | 386 | |
22329b51 BC |
387 | static struct pci_driver __devinitdata ioc4_driver = { |
388 | .name = "IOC4", | |
389 | .id_table = ioc4_id_table, | |
390 | .probe = ioc4_probe, | |
391 | .remove = ioc4_remove, | |
1da177e4 LT |
392 | }; |
393 | ||
22329b51 BC |
394 | MODULE_DEVICE_TABLE(pci, ioc4_id_table); |
395 | ||
396 | /********************* | |
397 | * Module management * | |
398 | *********************/ | |
399 | ||
400 | /* Module load */ | |
401 | static int __devinit | |
402 | ioc4_init(void) | |
1da177e4 | 403 | { |
22329b51 BC |
404 | return pci_register_driver(&ioc4_driver); |
405 | } | |
1da177e4 | 406 | |
22329b51 BC |
407 | /* Module unload */ |
408 | static void __devexit | |
409 | ioc4_exit(void) | |
410 | { | |
411 | pci_unregister_driver(&ioc4_driver); | |
1da177e4 | 412 | } |
1da177e4 | 413 | |
22329b51 BC |
414 | module_init(ioc4_init); |
415 | module_exit(ioc4_exit); | |
416 | ||
417 | MODULE_AUTHOR("Brent Casavant - Silicon Graphics, Inc. <bcasavan@sgi.com>"); | |
418 | MODULE_DESCRIPTION("PCI driver master module for SGI IOC4 Base-IO Card"); | |
1da177e4 | 419 | MODULE_LICENSE("GPL"); |
22329b51 BC |
420 | |
421 | EXPORT_SYMBOL(ioc4_register_submodule); | |
422 | EXPORT_SYMBOL(ioc4_unregister_submodule); |