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c97c4090 BA |
1 | /* |
2 | * Copyright (c) 2015, Sony Mobile Communications Inc. | |
3 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 and | |
7 | * only version 2 as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/interrupt.h> | |
16 | #include <linux/mfd/syscon.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of_irq.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/regmap.h> | |
22 | #include <linux/soc/qcom/smem.h> | |
23 | #include <linux/soc/qcom/smem_state.h> | |
24 | ||
25 | /* | |
26 | * This driver implements the Qualcomm Shared Memory State Machine, a mechanism | |
27 | * for communicating single bit state information to remote processors. | |
28 | * | |
29 | * The implementation is based on two sections of shared memory; the first | |
30 | * holding the state bits and the second holding a matrix of subscription bits. | |
31 | * | |
32 | * The state bits are structured in entries of 32 bits, each belonging to one | |
33 | * system in the SoC. The entry belonging to the local system is considered | |
34 | * read-write, while the rest should be considered read-only. | |
35 | * | |
36 | * The subscription matrix consists of N bitmaps per entry, denoting interest | |
37 | * in updates of the entry for each of the N hosts. Upon updating a state bit | |
38 | * each host's subscription bitmap should be queried and the remote system | |
39 | * should be interrupted if they request so. | |
40 | * | |
41 | * The subscription matrix is laid out in entry-major order: | |
42 | * entry0: [host0 ... hostN] | |
43 | * . | |
44 | * . | |
45 | * entryM: [host0 ... hostN] | |
46 | * | |
47 | * A third, optional, shared memory region might contain information regarding | |
48 | * the number of entries in the state bitmap as well as number of columns in | |
49 | * the subscription matrix. | |
50 | */ | |
51 | ||
52 | /* | |
53 | * Shared memory identifiers, used to acquire handles to respective memory | |
54 | * region. | |
55 | */ | |
56 | #define SMEM_SMSM_SHARED_STATE 85 | |
57 | #define SMEM_SMSM_CPU_INTR_MASK 333 | |
58 | #define SMEM_SMSM_SIZE_INFO 419 | |
59 | ||
60 | /* | |
61 | * Default sizes, in case SMEM_SMSM_SIZE_INFO is not found. | |
62 | */ | |
63 | #define SMSM_DEFAULT_NUM_ENTRIES 8 | |
64 | #define SMSM_DEFAULT_NUM_HOSTS 3 | |
65 | ||
66 | struct smsm_entry; | |
67 | struct smsm_host; | |
68 | ||
69 | /** | |
70 | * struct qcom_smsm - smsm driver context | |
71 | * @dev: smsm device pointer | |
72 | * @local_host: column in the subscription matrix representing this system | |
73 | * @num_hosts: number of columns in the subscription matrix | |
74 | * @num_entries: number of entries in the state map and rows in the subscription | |
75 | * matrix | |
76 | * @local_state: pointer to the local processor's state bits | |
77 | * @subscription: pointer to local processor's row in subscription matrix | |
78 | * @state: smem state handle | |
79 | * @lock: spinlock for read-modify-write of the outgoing state | |
80 | * @entries: context for each of the entries | |
81 | * @hosts: context for each of the hosts | |
82 | */ | |
83 | struct qcom_smsm { | |
84 | struct device *dev; | |
85 | ||
86 | u32 local_host; | |
87 | ||
88 | u32 num_hosts; | |
89 | u32 num_entries; | |
90 | ||
91 | u32 *local_state; | |
92 | u32 *subscription; | |
93 | struct qcom_smem_state *state; | |
94 | ||
95 | spinlock_t lock; | |
96 | ||
97 | struct smsm_entry *entries; | |
98 | struct smsm_host *hosts; | |
99 | }; | |
100 | ||
101 | /** | |
102 | * struct smsm_entry - per remote processor entry context | |
103 | * @smsm: back-reference to driver context | |
104 | * @domain: IRQ domain for this entry, if representing a remote system | |
105 | * @irq_enabled: bitmap of which state bits IRQs are enabled | |
106 | * @irq_rising: bitmap tracking if rising bits should be propagated | |
107 | * @irq_falling: bitmap tracking if falling bits should be propagated | |
108 | * @last_value: snapshot of state bits last time the interrupts where propagated | |
109 | * @remote_state: pointer to this entry's state bits | |
110 | * @subscription: pointer to a row in the subscription matrix representing this | |
111 | * entry | |
112 | */ | |
113 | struct smsm_entry { | |
114 | struct qcom_smsm *smsm; | |
115 | ||
116 | struct irq_domain *domain; | |
117 | DECLARE_BITMAP(irq_enabled, 32); | |
118 | DECLARE_BITMAP(irq_rising, 32); | |
119 | DECLARE_BITMAP(irq_falling, 32); | |
120 | u32 last_value; | |
121 | ||
122 | u32 *remote_state; | |
123 | u32 *subscription; | |
124 | }; | |
125 | ||
126 | /** | |
127 | * struct smsm_host - representation of a remote host | |
128 | * @ipc_regmap: regmap for outgoing interrupt | |
129 | * @ipc_offset: offset in @ipc_regmap for outgoing interrupt | |
130 | * @ipc_bit: bit in @ipc_regmap + @ipc_offset for outgoing interrupt | |
131 | */ | |
132 | struct smsm_host { | |
133 | struct regmap *ipc_regmap; | |
134 | int ipc_offset; | |
135 | int ipc_bit; | |
136 | }; | |
137 | ||
138 | /** | |
139 | * smsm_update_bits() - change bit in outgoing entry and inform subscribers | |
140 | * @data: smsm context pointer | |
141 | * @offset: bit in the entry | |
142 | * @value: new value | |
143 | * | |
144 | * Used to set and clear the bits in the outgoing/local entry and inform | |
145 | * subscribers about the change. | |
146 | */ | |
147 | static int smsm_update_bits(void *data, u32 mask, u32 value) | |
148 | { | |
149 | struct qcom_smsm *smsm = data; | |
150 | struct smsm_host *hostp; | |
151 | unsigned long flags; | |
152 | u32 changes; | |
153 | u32 host; | |
154 | u32 orig; | |
155 | u32 val; | |
156 | ||
157 | spin_lock_irqsave(&smsm->lock, flags); | |
158 | ||
159 | /* Update the entry */ | |
160 | val = orig = readl(smsm->local_state); | |
161 | val &= ~mask; | |
162 | val |= value; | |
163 | ||
164 | /* Don't signal if we didn't change the value */ | |
165 | changes = val ^ orig; | |
166 | if (!changes) { | |
167 | spin_unlock_irqrestore(&smsm->lock, flags); | |
168 | goto done; | |
169 | } | |
170 | ||
171 | /* Write out the new value */ | |
172 | writel(val, smsm->local_state); | |
173 | spin_unlock_irqrestore(&smsm->lock, flags); | |
174 | ||
175 | /* Make sure the value update is ordered before any kicks */ | |
176 | wmb(); | |
177 | ||
178 | /* Iterate over all hosts to check whom wants a kick */ | |
179 | for (host = 0; host < smsm->num_hosts; host++) { | |
180 | hostp = &smsm->hosts[host]; | |
181 | ||
182 | val = readl(smsm->subscription + host); | |
183 | if (val & changes && hostp->ipc_regmap) { | |
184 | regmap_write(hostp->ipc_regmap, | |
185 | hostp->ipc_offset, | |
186 | BIT(hostp->ipc_bit)); | |
187 | } | |
188 | } | |
189 | ||
190 | done: | |
191 | return 0; | |
192 | } | |
193 | ||
194 | static const struct qcom_smem_state_ops smsm_state_ops = { | |
195 | .update_bits = smsm_update_bits, | |
196 | }; | |
197 | ||
198 | /** | |
199 | * smsm_intr() - cascading IRQ handler for SMSM | |
200 | * @irq: unused | |
201 | * @data: entry related to this IRQ | |
202 | * | |
203 | * This function cascades an incoming interrupt from a remote system, based on | |
204 | * the state bits and configuration. | |
205 | */ | |
206 | static irqreturn_t smsm_intr(int irq, void *data) | |
207 | { | |
208 | struct smsm_entry *entry = data; | |
209 | unsigned i; | |
210 | int irq_pin; | |
211 | u32 changed; | |
212 | u32 val; | |
213 | ||
214 | val = readl(entry->remote_state); | |
215 | changed = val ^ entry->last_value; | |
216 | entry->last_value = val; | |
217 | ||
218 | for_each_set_bit(i, entry->irq_enabled, 32) { | |
219 | if (!(changed & BIT(i))) | |
220 | continue; | |
221 | ||
222 | if (val & BIT(i)) { | |
223 | if (test_bit(i, entry->irq_rising)) { | |
224 | irq_pin = irq_find_mapping(entry->domain, i); | |
225 | handle_nested_irq(irq_pin); | |
226 | } | |
227 | } else { | |
228 | if (test_bit(i, entry->irq_falling)) { | |
229 | irq_pin = irq_find_mapping(entry->domain, i); | |
230 | handle_nested_irq(irq_pin); | |
231 | } | |
232 | } | |
233 | } | |
234 | ||
235 | return IRQ_HANDLED; | |
236 | } | |
237 | ||
238 | /** | |
239 | * smsm_mask_irq() - un-subscribe from cascades of IRQs of a certain staus bit | |
240 | * @irqd: IRQ handle to be masked | |
241 | * | |
242 | * This un-subscribes the local CPU from interrupts upon changes to the defines | |
243 | * status bit. The bit is also cleared from cascading. | |
244 | */ | |
245 | static void smsm_mask_irq(struct irq_data *irqd) | |
246 | { | |
247 | struct smsm_entry *entry = irq_data_get_irq_chip_data(irqd); | |
248 | irq_hw_number_t irq = irqd_to_hwirq(irqd); | |
249 | struct qcom_smsm *smsm = entry->smsm; | |
250 | u32 val; | |
251 | ||
252 | if (entry->subscription) { | |
253 | val = readl(entry->subscription + smsm->local_host); | |
254 | val &= ~BIT(irq); | |
255 | writel(val, entry->subscription + smsm->local_host); | |
256 | } | |
257 | ||
258 | clear_bit(irq, entry->irq_enabled); | |
259 | } | |
260 | ||
261 | /** | |
262 | * smsm_unmask_irq() - subscribe to cascades of IRQs of a certain status bit | |
263 | * @irqd: IRQ handle to be unmasked | |
264 | * | |
265 | ||
266 | * This subscribes the local CPU to interrupts upon changes to the defined | |
267 | * status bit. The bit is also marked for cascading. | |
268 | ||
269 | */ | |
270 | static void smsm_unmask_irq(struct irq_data *irqd) | |
271 | { | |
272 | struct smsm_entry *entry = irq_data_get_irq_chip_data(irqd); | |
273 | irq_hw_number_t irq = irqd_to_hwirq(irqd); | |
274 | struct qcom_smsm *smsm = entry->smsm; | |
275 | u32 val; | |
276 | ||
277 | set_bit(irq, entry->irq_enabled); | |
278 | ||
279 | if (entry->subscription) { | |
280 | val = readl(entry->subscription + smsm->local_host); | |
281 | val |= BIT(irq); | |
282 | writel(val, entry->subscription + smsm->local_host); | |
283 | } | |
284 | } | |
285 | ||
286 | /** | |
287 | * smsm_set_irq_type() - updates the requested IRQ type for the cascading | |
288 | * @irqd: consumer interrupt handle | |
289 | * @type: requested flags | |
290 | */ | |
291 | static int smsm_set_irq_type(struct irq_data *irqd, unsigned int type) | |
292 | { | |
293 | struct smsm_entry *entry = irq_data_get_irq_chip_data(irqd); | |
294 | irq_hw_number_t irq = irqd_to_hwirq(irqd); | |
295 | ||
296 | if (!(type & IRQ_TYPE_EDGE_BOTH)) | |
297 | return -EINVAL; | |
298 | ||
299 | if (type & IRQ_TYPE_EDGE_RISING) | |
300 | set_bit(irq, entry->irq_rising); | |
301 | else | |
302 | clear_bit(irq, entry->irq_rising); | |
303 | ||
304 | if (type & IRQ_TYPE_EDGE_FALLING) | |
305 | set_bit(irq, entry->irq_falling); | |
306 | else | |
307 | clear_bit(irq, entry->irq_falling); | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static struct irq_chip smsm_irq_chip = { | |
313 | .name = "smsm", | |
314 | .irq_mask = smsm_mask_irq, | |
315 | .irq_unmask = smsm_unmask_irq, | |
316 | .irq_set_type = smsm_set_irq_type, | |
317 | }; | |
318 | ||
319 | /** | |
320 | * smsm_irq_map() - sets up a mapping for a cascaded IRQ | |
321 | * @d: IRQ domain representing an entry | |
322 | * @irq: IRQ to set up | |
323 | * @hw: unused | |
324 | */ | |
325 | static int smsm_irq_map(struct irq_domain *d, | |
326 | unsigned int irq, | |
327 | irq_hw_number_t hw) | |
328 | { | |
329 | struct smsm_entry *entry = d->host_data; | |
330 | ||
331 | irq_set_chip_and_handler(irq, &smsm_irq_chip, handle_level_irq); | |
332 | irq_set_chip_data(irq, entry); | |
333 | irq_set_nested_thread(irq, 1); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | static const struct irq_domain_ops smsm_irq_ops = { | |
339 | .map = smsm_irq_map, | |
340 | .xlate = irq_domain_xlate_twocell, | |
341 | }; | |
342 | ||
343 | /** | |
344 | * smsm_parse_ipc() - parses a qcom,ipc-%d device tree property | |
345 | * @smsm: smsm driver context | |
346 | * @host_id: index of the remote host to be resolved | |
347 | * | |
348 | * Parses device tree to acquire the information needed for sending the | |
349 | * outgoing interrupts to a remote host - identified by @host_id. | |
350 | */ | |
351 | static int smsm_parse_ipc(struct qcom_smsm *smsm, unsigned host_id) | |
352 | { | |
353 | struct device_node *syscon; | |
354 | struct device_node *node = smsm->dev->of_node; | |
355 | struct smsm_host *host = &smsm->hosts[host_id]; | |
356 | char key[16]; | |
357 | int ret; | |
358 | ||
359 | snprintf(key, sizeof(key), "qcom,ipc-%d", host_id); | |
360 | syscon = of_parse_phandle(node, key, 0); | |
361 | if (!syscon) | |
362 | return 0; | |
363 | ||
364 | host->ipc_regmap = syscon_node_to_regmap(syscon); | |
365 | if (IS_ERR(host->ipc_regmap)) | |
366 | return PTR_ERR(host->ipc_regmap); | |
367 | ||
368 | ret = of_property_read_u32_index(node, key, 1, &host->ipc_offset); | |
369 | if (ret < 0) { | |
370 | dev_err(smsm->dev, "no offset in %s\n", key); | |
371 | return -EINVAL; | |
372 | } | |
373 | ||
374 | ret = of_property_read_u32_index(node, key, 2, &host->ipc_bit); | |
375 | if (ret < 0) { | |
376 | dev_err(smsm->dev, "no bit in %s\n", key); | |
377 | return -EINVAL; | |
378 | } | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | /** | |
384 | * smsm_inbound_entry() - parse DT and set up an entry representing a remote system | |
385 | * @smsm: smsm driver context | |
386 | * @entry: entry context to be set up | |
387 | * @node: dt node containing the entry's properties | |
388 | */ | |
389 | static int smsm_inbound_entry(struct qcom_smsm *smsm, | |
390 | struct smsm_entry *entry, | |
391 | struct device_node *node) | |
392 | { | |
393 | int ret; | |
394 | int irq; | |
395 | ||
396 | irq = irq_of_parse_and_map(node, 0); | |
397 | if (!irq) { | |
398 | dev_err(smsm->dev, "failed to parse smsm interrupt\n"); | |
399 | return -EINVAL; | |
400 | } | |
401 | ||
402 | ret = devm_request_threaded_irq(smsm->dev, irq, | |
403 | NULL, smsm_intr, | |
404 | IRQF_ONESHOT, | |
405 | "smsm", (void *)entry); | |
406 | if (ret) { | |
407 | dev_err(smsm->dev, "failed to request interrupt\n"); | |
408 | return ret; | |
409 | } | |
410 | ||
411 | entry->domain = irq_domain_add_linear(node, 32, &smsm_irq_ops, entry); | |
412 | if (!entry->domain) { | |
413 | dev_err(smsm->dev, "failed to add irq_domain\n"); | |
414 | return -ENOMEM; | |
415 | } | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
420 | /** | |
421 | * smsm_get_size_info() - parse the optional memory segment for sizes | |
422 | * @smsm: smsm driver context | |
423 | * | |
424 | * Attempt to acquire the number of hosts and entries from the optional shared | |
425 | * memory location. Not being able to find this segment should indicate that | |
426 | * we're on a older system where these values was hard coded to | |
427 | * SMSM_DEFAULT_NUM_ENTRIES and SMSM_DEFAULT_NUM_HOSTS. | |
428 | * | |
429 | * Returns 0 on success, negative errno on failure. | |
430 | */ | |
431 | static int smsm_get_size_info(struct qcom_smsm *smsm) | |
432 | { | |
433 | size_t size; | |
434 | struct { | |
435 | u32 num_hosts; | |
436 | u32 num_entries; | |
437 | u32 reserved0; | |
438 | u32 reserved1; | |
439 | } *info; | |
440 | ||
441 | info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SIZE_INFO, &size); | |
442 | if (PTR_ERR(info) == -ENOENT || size != sizeof(*info)) { | |
443 | dev_warn(smsm->dev, "no smsm size info, using defaults\n"); | |
444 | smsm->num_entries = SMSM_DEFAULT_NUM_ENTRIES; | |
445 | smsm->num_hosts = SMSM_DEFAULT_NUM_HOSTS; | |
446 | return 0; | |
447 | } else if (IS_ERR(info)) { | |
448 | dev_err(smsm->dev, "unable to retrieve smsm size info\n"); | |
449 | return PTR_ERR(info); | |
450 | } | |
451 | ||
452 | smsm->num_entries = info->num_entries; | |
453 | smsm->num_hosts = info->num_hosts; | |
454 | ||
455 | dev_dbg(smsm->dev, | |
456 | "found custom size of smsm: %d entries %d hosts\n", | |
457 | smsm->num_entries, smsm->num_hosts); | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
462 | static int qcom_smsm_probe(struct platform_device *pdev) | |
463 | { | |
464 | struct device_node *local_node; | |
465 | struct device_node *node; | |
466 | struct smsm_entry *entry; | |
467 | struct qcom_smsm *smsm; | |
468 | u32 *intr_mask; | |
469 | size_t size; | |
470 | u32 *states; | |
471 | u32 id; | |
472 | int ret; | |
473 | ||
474 | smsm = devm_kzalloc(&pdev->dev, sizeof(*smsm), GFP_KERNEL); | |
475 | if (!smsm) | |
476 | return -ENOMEM; | |
477 | smsm->dev = &pdev->dev; | |
478 | spin_lock_init(&smsm->lock); | |
479 | ||
480 | ret = smsm_get_size_info(smsm); | |
481 | if (ret) | |
482 | return ret; | |
483 | ||
484 | smsm->entries = devm_kcalloc(&pdev->dev, | |
485 | smsm->num_entries, | |
486 | sizeof(struct smsm_entry), | |
487 | GFP_KERNEL); | |
488 | if (!smsm->entries) | |
489 | return -ENOMEM; | |
490 | ||
491 | smsm->hosts = devm_kcalloc(&pdev->dev, | |
492 | smsm->num_hosts, | |
493 | sizeof(struct smsm_host), | |
494 | GFP_KERNEL); | |
495 | if (!smsm->hosts) | |
496 | return -ENOMEM; | |
497 | ||
3680a4a9 | 498 | local_node = of_find_node_with_property(pdev->dev.of_node, "#qcom,smem-state-cells"); |
c97c4090 BA |
499 | if (!local_node) { |
500 | dev_err(&pdev->dev, "no state entry\n"); | |
501 | return -EINVAL; | |
502 | } | |
503 | ||
504 | of_property_read_u32(pdev->dev.of_node, | |
505 | "qcom,local-host", | |
506 | &smsm->local_host); | |
507 | ||
508 | /* Parse the host properties */ | |
509 | for (id = 0; id < smsm->num_hosts; id++) { | |
510 | ret = smsm_parse_ipc(smsm, id); | |
511 | if (ret < 0) | |
512 | return ret; | |
513 | } | |
514 | ||
515 | /* Acquire the main SMSM state vector */ | |
516 | ret = qcom_smem_alloc(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SHARED_STATE, | |
517 | smsm->num_entries * sizeof(u32)); | |
518 | if (ret < 0 && ret != -EEXIST) { | |
519 | dev_err(&pdev->dev, "unable to allocate shared state entry\n"); | |
520 | return ret; | |
521 | } | |
522 | ||
523 | states = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SHARED_STATE, NULL); | |
524 | if (IS_ERR(states)) { | |
525 | dev_err(&pdev->dev, "Unable to acquire shared state entry\n"); | |
526 | return PTR_ERR(states); | |
527 | } | |
528 | ||
529 | /* Acquire the list of interrupt mask vectors */ | |
530 | size = smsm->num_entries * smsm->num_hosts * sizeof(u32); | |
531 | ret = qcom_smem_alloc(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, size); | |
532 | if (ret < 0 && ret != -EEXIST) { | |
533 | dev_err(&pdev->dev, "unable to allocate smsm interrupt mask\n"); | |
534 | return ret; | |
535 | } | |
536 | ||
537 | intr_mask = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_CPU_INTR_MASK, NULL); | |
538 | if (IS_ERR(intr_mask)) { | |
539 | dev_err(&pdev->dev, "unable to acquire shared memory interrupt mask\n"); | |
540 | return PTR_ERR(intr_mask); | |
541 | } | |
542 | ||
543 | /* Setup the reference to the local state bits */ | |
544 | smsm->local_state = states + smsm->local_host; | |
545 | smsm->subscription = intr_mask + smsm->local_host * smsm->num_hosts; | |
546 | ||
547 | /* Register the outgoing state */ | |
548 | smsm->state = qcom_smem_state_register(local_node, &smsm_state_ops, smsm); | |
549 | if (IS_ERR(smsm->state)) { | |
550 | dev_err(smsm->dev, "failed to register qcom_smem_state\n"); | |
551 | return PTR_ERR(smsm->state); | |
552 | } | |
553 | ||
554 | /* Register handlers for remote processor entries of interest. */ | |
555 | for_each_available_child_of_node(pdev->dev.of_node, node) { | |
556 | if (!of_property_read_bool(node, "interrupt-controller")) | |
557 | continue; | |
558 | ||
559 | ret = of_property_read_u32(node, "reg", &id); | |
560 | if (ret || id >= smsm->num_entries) { | |
561 | dev_err(&pdev->dev, "invalid reg of entry\n"); | |
562 | if (!ret) | |
563 | ret = -EINVAL; | |
564 | goto unwind_interfaces; | |
565 | } | |
566 | entry = &smsm->entries[id]; | |
567 | ||
568 | entry->smsm = smsm; | |
569 | entry->remote_state = states + id; | |
570 | ||
571 | /* Setup subscription pointers and unsubscribe to any kicks */ | |
572 | entry->subscription = intr_mask + id * smsm->num_hosts; | |
573 | writel(0, entry->subscription + smsm->local_host); | |
574 | ||
575 | ret = smsm_inbound_entry(smsm, entry, node); | |
576 | if (ret < 0) | |
577 | goto unwind_interfaces; | |
578 | } | |
579 | ||
580 | platform_set_drvdata(pdev, smsm); | |
581 | ||
582 | return 0; | |
583 | ||
584 | unwind_interfaces: | |
585 | for (id = 0; id < smsm->num_entries; id++) | |
586 | if (smsm->entries[id].domain) | |
587 | irq_domain_remove(smsm->entries[id].domain); | |
588 | ||
589 | qcom_smem_state_unregister(smsm->state); | |
590 | ||
591 | return ret; | |
592 | } | |
593 | ||
594 | static int qcom_smsm_remove(struct platform_device *pdev) | |
595 | { | |
596 | struct qcom_smsm *smsm = platform_get_drvdata(pdev); | |
597 | unsigned id; | |
598 | ||
599 | for (id = 0; id < smsm->num_entries; id++) | |
600 | if (smsm->entries[id].domain) | |
601 | irq_domain_remove(smsm->entries[id].domain); | |
602 | ||
603 | qcom_smem_state_unregister(smsm->state); | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
608 | static const struct of_device_id qcom_smsm_of_match[] = { | |
609 | { .compatible = "qcom,smsm" }, | |
610 | {} | |
611 | }; | |
612 | MODULE_DEVICE_TABLE(of, qcom_smsm_of_match); | |
613 | ||
614 | static struct platform_driver qcom_smsm_driver = { | |
615 | .probe = qcom_smsm_probe, | |
616 | .remove = qcom_smsm_remove, | |
617 | .driver = { | |
618 | .name = "qcom-smsm", | |
619 | .of_match_table = qcom_smsm_of_match, | |
620 | }, | |
621 | }; | |
622 | module_platform_driver(qcom_smsm_driver); | |
623 | ||
624 | MODULE_DESCRIPTION("Qualcomm Shared Memory State Machine driver"); | |
625 | MODULE_LICENSE("GPL v2"); |