Commit | Line | Data |
---|---|---|
8ae12a0d DB |
1 | # |
2 | # SPI driver configuration | |
3 | # | |
4 | # NOTE: the reason this doesn't show SPI slave support is mostly that | |
5 | # nobody's needed a slave side API yet. The master-role API is not | |
6 | # fully appropriate there, so it'd need some thought to do well. | |
7 | # | |
79d8c7a8 | 8 | menuconfig SPI |
8ae12a0d | 9 | bool "SPI support" |
79d8c7a8 | 10 | depends on HAS_IOMEM |
8ae12a0d DB |
11 | help |
12 | The "Serial Peripheral Interface" is a low level synchronous | |
13 | protocol. Chips that support SPI can have data transfer rates | |
14 | up to several tens of Mbit/sec. Chips are addressed with a | |
15 | controller and a chipselect. Most SPI slaves don't support | |
16 | dynamic device discovery; some are even write-only or read-only. | |
17 | ||
3cb2fccc | 18 | SPI is widely used by microcontrollers to talk with sensors, |
8ae12a0d DB |
19 | eeprom and flash memory, codecs and various other controller |
20 | chips, analog to digital (and d-to-a) converters, and more. | |
21 | MMC and SD cards can be accessed using SPI protocol; and for | |
22 | DataFlash cards used in MMC sockets, SPI must always be used. | |
23 | ||
24 | SPI is one of a family of similar protocols using a four wire | |
25 | interface (select, clock, data in, data out) including Microwire | |
26 | (half duplex), SSP, SSI, and PSP. This driver framework should | |
27 | work with most such devices and controllers. | |
28 | ||
79d8c7a8 AG |
29 | if SPI |
30 | ||
8ae12a0d DB |
31 | config SPI_DEBUG |
32 | boolean "Debug support for SPI drivers" | |
79d8c7a8 | 33 | depends on DEBUG_KERNEL |
8ae12a0d DB |
34 | help |
35 | Say "yes" to enable debug messaging (like dev_dbg and pr_debug), | |
36 | sysfs, and debugfs support in SPI controller and protocol drivers. | |
37 | ||
38 | # | |
39 | # MASTER side ... talking to discrete SPI slave chips including microcontrollers | |
40 | # | |
41 | ||
42 | config SPI_MASTER | |
43 | # boolean "SPI Master Support" | |
44 | boolean | |
45 | default SPI | |
46 | help | |
47 | If your system has an master-capable SPI controller (which | |
48 | provides the clock and chipselect), you can enable that | |
49 | controller and the protocol drivers for the SPI slave chips | |
50 | that are connected. | |
51 | ||
6291fe2a RD |
52 | if SPI_MASTER |
53 | ||
8ae12a0d | 54 | comment "SPI Master Controller Drivers" |
8ae12a0d | 55 | |
754ce4f2 HS |
56 | config SPI_ATMEL |
57 | tristate "Atmel SPI Controller" | |
6291fe2a | 58 | depends on (ARCH_AT91 || AVR32) |
754ce4f2 HS |
59 | help |
60 | This selects a driver for the Atmel SPI Controller, present on | |
61 | many AT32 (AVR32) and AT91 (ARM) chips. | |
62 | ||
a5f6abd4 WB |
63 | config SPI_BFIN |
64 | tristate "SPI controller driver for ADI Blackfin5xx" | |
6291fe2a | 65 | depends on BLACKFIN |
a5f6abd4 WB |
66 | help |
67 | This is the SPI controller master driver for Blackfin 5xx processor. | |
68 | ||
63bd2359 JN |
69 | config SPI_AU1550 |
70 | tristate "Au1550/Au12x0 SPI Controller" | |
6291fe2a | 71 | depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL |
63bd2359 JN |
72 | select SPI_BITBANG |
73 | help | |
74 | If you say yes to this option, support will be included for the | |
75 | Au1550 SPI controller (may also work with Au1200,Au1210,Au1250). | |
76 | ||
77 | This driver can also be built as a module. If so, the module | |
78 | will be called au1550_spi. | |
79 | ||
9904f22a DB |
80 | config SPI_BITBANG |
81 | tristate "Bitbanging SPI master" | |
9904f22a DB |
82 | help |
83 | With a few GPIO pins, your system can bitbang the SPI protocol. | |
84 | Select this to get SPI support through I/O pins (GPIO, parallel | |
85 | port, etc). Or, some systems' SPI master controller drivers use | |
86 | this code to manage the per-word or per-transfer accesses to the | |
87 | hardware shift registers. | |
88 | ||
89 | This is library code, and is automatically selected by drivers that | |
90 | need it. You only need to select this explicitly to support driver | |
91 | modules that aren't part of this kernel tree. | |
8ae12a0d | 92 | |
7111763d DB |
93 | config SPI_BUTTERFLY |
94 | tristate "Parallel port adapter for AVR Butterfly (DEVELOPMENT)" | |
6291fe2a | 95 | depends on PARPORT |
7111763d DB |
96 | select SPI_BITBANG |
97 | help | |
98 | This uses a custom parallel port cable to connect to an AVR | |
99 | Butterfly <http://www.atmel.com/products/avr/butterfly>, an | |
100 | inexpensive battery powered microcontroller evaluation board. | |
101 | This same cable can be used to flash new firmware. | |
102 | ||
69c202af AP |
103 | config SPI_IMX |
104 | tristate "Freescale iMX SPI controller" | |
6291fe2a | 105 | depends on ARCH_IMX && EXPERIMENTAL |
69c202af AP |
106 | help |
107 | This enables using the Freescale iMX SPI controller in master | |
108 | mode. | |
109 | ||
78961a57 KB |
110 | config SPI_LM70_LLP |
111 | tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)" | |
6291fe2a | 112 | depends on PARPORT && EXPERIMENTAL |
78961a57 KB |
113 | select SPI_BITBANG |
114 | help | |
115 | This driver supports the NS LM70 LLP Evaluation Board, | |
116 | which interfaces to an LM70 temperature sensor using | |
117 | a parallel port. | |
118 | ||
00b8fd23 DC |
119 | config SPI_MPC52xx_PSC |
120 | tristate "Freescale MPC52xx PSC SPI controller" | |
6291fe2a | 121 | depends on PPC_MPC52xx && EXPERIMENTAL |
00b8fd23 DC |
122 | help |
123 | This enables using the Freescale MPC52xx Programmable Serial | |
124 | Controller in master SPI mode. | |
125 | ||
ccf06998 | 126 | config SPI_MPC83xx |
328329a7 | 127 | tristate "Freescale MPC83xx/QUICC Engine SPI controller" |
6291fe2a | 128 | depends on (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL |
ccf06998 | 129 | help |
328329a7 AV |
130 | This enables using the Freescale MPC83xx and QUICC Engine SPI |
131 | controllers in master mode. | |
ccf06998 KG |
132 | |
133 | Note, this driver uniquely supports the SPI controller on the MPC83xx | |
328329a7 AV |
134 | family of PowerPC processors, plus processors with QUICC Engine |
135 | technology. This driver uses a simple set of shift registers for data | |
136 | (opposed to the CPM based descriptor model). | |
ccf06998 | 137 | |
fdb3c18d DB |
138 | config SPI_OMAP_UWIRE |
139 | tristate "OMAP1 MicroWire" | |
6291fe2a | 140 | depends on ARCH_OMAP1 |
fdb3c18d DB |
141 | select SPI_BITBANG |
142 | help | |
143 | This hooks up to the MicroWire controller on OMAP1 chips. | |
144 | ||
ccdc7bf9 | 145 | config SPI_OMAP24XX |
ccc7baed | 146 | tristate "McSPI driver for OMAP24xx/OMAP34xx" |
6291fe2a | 147 | depends on ARCH_OMAP24XX || ARCH_OMAP34XX |
ccdc7bf9 | 148 | help |
ccc7baed | 149 | SPI master controller for OMAP24xx/OMAP34xx Multichannel SPI |
ccdc7bf9 | 150 | (McSPI) modules. |
69c202af | 151 | |
60cadec9 SA |
152 | config SPI_ORION |
153 | tristate "Orion SPI master (EXPERIMENTAL)" | |
154 | depends on PLAT_ORION && EXPERIMENTAL | |
155 | help | |
156 | This enables using the SPI master controller on the Orion chips. | |
157 | ||
e0c9905e SS |
158 | config SPI_PXA2XX |
159 | tristate "PXA2xx SSP SPI master" | |
6291fe2a | 160 | depends on ARCH_PXA && EXPERIMENTAL |
2f1a74e5 | 161 | select PXA_SSP |
e0c9905e SS |
162 | help |
163 | This enables using a PXA2xx SSP port as a SPI master controller. | |
164 | The driver can be configured to use any SSP port and additional | |
165 | documentation can be found a Documentation/spi/pxa2xx. | |
166 | ||
85abfaa7 DB |
167 | config SPI_S3C24XX |
168 | tristate "Samsung S3C24XX series SPI" | |
6291fe2a | 169 | depends on ARCH_S3C2410 && EXPERIMENTAL |
da0abc27 | 170 | select SPI_BITBANG |
85abfaa7 DB |
171 | help |
172 | SPI driver for Samsung S3C24XX series ARM SoCs | |
173 | ||
1fc7547d BD |
174 | config SPI_S3C24XX_GPIO |
175 | tristate "Samsung S3C24XX series SPI by GPIO" | |
6291fe2a | 176 | depends on ARCH_S3C2410 && EXPERIMENTAL |
da0abc27 | 177 | select SPI_BITBANG |
1fc7547d BD |
178 | help |
179 | SPI driver for Samsung S3C24XX series ARM SoCs using | |
180 | GPIO lines to provide the SPI bus. This can be used where | |
181 | the inbuilt hardware cannot provide the transfer mode, or | |
182 | where the board is using non hardware connected pins. | |
ae918c02 | 183 | |
37e46640 MD |
184 | config SPI_SH_SCI |
185 | tristate "SuperH SCI SPI controller" | |
6291fe2a | 186 | depends on SUPERH |
37e46640 MD |
187 | select SPI_BITBANG |
188 | help | |
189 | SPI driver for SuperH SCI blocks. | |
190 | ||
f2cac67d AN |
191 | config SPI_TXX9 |
192 | tristate "Toshiba TXx9 SPI controller" | |
6291fe2a | 193 | depends on GENERIC_GPIO && CPU_TX49XX |
f2cac67d AN |
194 | help |
195 | SPI driver for Toshiba TXx9 MIPS SoCs | |
196 | ||
ae918c02 AK |
197 | config SPI_XILINX |
198 | tristate "Xilinx SPI controller" | |
6291fe2a | 199 | depends on XILINX_VIRTEX && EXPERIMENTAL |
ae918c02 AK |
200 | select SPI_BITBANG |
201 | help | |
202 | This exposes the SPI controller IP from the Xilinx EDK. | |
203 | ||
204 | See the "OPB Serial Peripheral Interface (SPI) (v1.00e)" | |
205 | Product Specification document (DS464) for hardware details. | |
206 | ||
8ae12a0d DB |
207 | # |
208 | # Add new SPI master controllers in alphabetical order above this line | |
209 | # | |
210 | ||
8ae12a0d DB |
211 | # |
212 | # There are lots of SPI device types, with sensors and memory | |
213 | # being probably the most widely used ones. | |
214 | # | |
215 | comment "SPI Protocol Masters" | |
8ae12a0d | 216 | |
b587b13a DB |
217 | config SPI_AT25 |
218 | tristate "SPI EEPROMs from most vendors" | |
6291fe2a | 219 | depends on SYSFS |
b587b13a DB |
220 | help |
221 | Enable this driver to get read/write support to most SPI EEPROMs, | |
222 | after you configure the board init code to know about each eeprom | |
223 | on your target board. | |
224 | ||
225 | This driver can also be built as a module. If so, the module | |
226 | will be called at25. | |
8ae12a0d | 227 | |
814a8d50 AP |
228 | config SPI_SPIDEV |
229 | tristate "User mode SPI device driver support" | |
6291fe2a | 230 | depends on EXPERIMENTAL |
814a8d50 AP |
231 | help |
232 | This supports user mode SPI protocol drivers. | |
233 | ||
234 | Note that this application programming interface is EXPERIMENTAL | |
235 | and hence SUBJECT TO CHANGE WITHOUT NOTICE while it stabilizes. | |
236 | ||
447aef1a BD |
237 | config SPI_TLE62X0 |
238 | tristate "Infineon TLE62X0 (for power switching)" | |
6291fe2a | 239 | depends on SYSFS |
447aef1a BD |
240 | help |
241 | SPI driver for Infineon TLE62X0 series line driver chips, | |
242 | such as the TLE6220, TLE6230 and TLE6240. This provides a | |
243 | sysfs interface, with each line presented as a kind of GPIO | |
244 | exposing both switch control and diagnostic feedback. | |
245 | ||
8ae12a0d DB |
246 | # |
247 | # Add new SPI protocol masters in alphabetical order above this line | |
248 | # | |
249 | ||
6291fe2a RD |
250 | endif # SPI_MASTER |
251 | ||
8ae12a0d DB |
252 | # (slave support would go here) |
253 | ||
79d8c7a8 | 254 | endif # SPI |