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b43d65f7 LW |
1 | /* |
2 | * drivers/spi/amba-pl022.c | |
3 | * | |
4 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. | |
5 | * | |
6 | * Copyright (C) 2008-2009 ST-Ericsson AB | |
7 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. | |
8 | * | |
9 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
10 | * | |
11 | * Initial version inspired by: | |
12 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c | |
13 | * Initial adoption to PL022 by: | |
14 | * Sachin Verma <sachin.verma@st.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | */ | |
26 | ||
27 | /* | |
28 | * TODO: | |
29 | * - add timeout on polled transfers | |
b43d65f7 LW |
30 | */ |
31 | ||
32 | #include <linux/init.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/device.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/spi/spi.h> | |
39 | #include <linux/workqueue.h> | |
b43d65f7 LW |
40 | #include <linux/delay.h> |
41 | #include <linux/clk.h> | |
42 | #include <linux/err.h> | |
43 | #include <linux/amba/bus.h> | |
44 | #include <linux/amba/pl022.h> | |
45 | #include <linux/io.h> | |
5a0e3ad6 | 46 | #include <linux/slab.h> |
b1b6b9aa LW |
47 | #include <linux/dmaengine.h> |
48 | #include <linux/dma-mapping.h> | |
49 | #include <linux/scatterlist.h> | |
b43d65f7 LW |
50 | |
51 | /* | |
52 | * This macro is used to define some register default values. | |
53 | * reg is masked with mask, the OR:ed with an (again masked) | |
54 | * val shifted sb steps to the left. | |
55 | */ | |
56 | #define SSP_WRITE_BITS(reg, val, mask, sb) \ | |
57 | ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) | |
58 | ||
59 | /* | |
60 | * This macro is also used to define some default values. | |
61 | * It will just shift val by sb steps to the left and mask | |
62 | * the result with mask. | |
63 | */ | |
64 | #define GEN_MASK_BITS(val, mask, sb) \ | |
65 | (((val)<<(sb)) & (mask)) | |
66 | ||
67 | #define DRIVE_TX 0 | |
68 | #define DO_NOT_DRIVE_TX 1 | |
69 | ||
70 | #define DO_NOT_QUEUE_DMA 0 | |
71 | #define QUEUE_DMA 1 | |
72 | ||
73 | #define RX_TRANSFER 1 | |
74 | #define TX_TRANSFER 2 | |
75 | ||
76 | /* | |
77 | * Macros to access SSP Registers with their offsets | |
78 | */ | |
79 | #define SSP_CR0(r) (r + 0x000) | |
80 | #define SSP_CR1(r) (r + 0x004) | |
81 | #define SSP_DR(r) (r + 0x008) | |
82 | #define SSP_SR(r) (r + 0x00C) | |
83 | #define SSP_CPSR(r) (r + 0x010) | |
84 | #define SSP_IMSC(r) (r + 0x014) | |
85 | #define SSP_RIS(r) (r + 0x018) | |
86 | #define SSP_MIS(r) (r + 0x01C) | |
87 | #define SSP_ICR(r) (r + 0x020) | |
88 | #define SSP_DMACR(r) (r + 0x024) | |
89 | #define SSP_ITCR(r) (r + 0x080) | |
90 | #define SSP_ITIP(r) (r + 0x084) | |
91 | #define SSP_ITOP(r) (r + 0x088) | |
92 | #define SSP_TDR(r) (r + 0x08C) | |
93 | ||
94 | #define SSP_PID0(r) (r + 0xFE0) | |
95 | #define SSP_PID1(r) (r + 0xFE4) | |
96 | #define SSP_PID2(r) (r + 0xFE8) | |
97 | #define SSP_PID3(r) (r + 0xFEC) | |
98 | ||
99 | #define SSP_CID0(r) (r + 0xFF0) | |
100 | #define SSP_CID1(r) (r + 0xFF4) | |
101 | #define SSP_CID2(r) (r + 0xFF8) | |
102 | #define SSP_CID3(r) (r + 0xFFC) | |
103 | ||
104 | /* | |
105 | * SSP Control Register 0 - SSP_CR0 | |
106 | */ | |
556f4aeb LW |
107 | #define SSP_CR0_MASK_DSS (0x0FUL << 0) |
108 | #define SSP_CR0_MASK_FRF (0x3UL << 4) | |
b43d65f7 LW |
109 | #define SSP_CR0_MASK_SPO (0x1UL << 6) |
110 | #define SSP_CR0_MASK_SPH (0x1UL << 7) | |
111 | #define SSP_CR0_MASK_SCR (0xFFUL << 8) | |
556f4aeb LW |
112 | |
113 | /* | |
114 | * The ST version of this block moves som bits | |
115 | * in SSP_CR0 and extends it to 32 bits | |
116 | */ | |
117 | #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) | |
118 | #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) | |
119 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) | |
120 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) | |
121 | ||
b43d65f7 LW |
122 | |
123 | /* | |
124 | * SSP Control Register 0 - SSP_CR1 | |
125 | */ | |
126 | #define SSP_CR1_MASK_LBM (0x1UL << 0) | |
127 | #define SSP_CR1_MASK_SSE (0x1UL << 1) | |
128 | #define SSP_CR1_MASK_MS (0x1UL << 2) | |
129 | #define SSP_CR1_MASK_SOD (0x1UL << 3) | |
b43d65f7 LW |
130 | |
131 | /* | |
556f4aeb LW |
132 | * The ST version of this block adds some bits |
133 | * in SSP_CR1 | |
b43d65f7 | 134 | */ |
556f4aeb LW |
135 | #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) |
136 | #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) | |
137 | #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) | |
138 | #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) | |
139 | #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) | |
781c7b12 LW |
140 | /* This one is only in the PL023 variant */ |
141 | #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) | |
b43d65f7 LW |
142 | |
143 | /* | |
144 | * SSP Status Register - SSP_SR | |
145 | */ | |
146 | #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ | |
147 | #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ | |
148 | #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ | |
556f4aeb | 149 | #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ |
b43d65f7 LW |
150 | #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ |
151 | ||
152 | /* | |
153 | * SSP Clock Prescale Register - SSP_CPSR | |
154 | */ | |
155 | #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) | |
156 | ||
157 | /* | |
158 | * SSP Interrupt Mask Set/Clear Register - SSP_IMSC | |
159 | */ | |
160 | #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ | |
161 | #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ | |
162 | #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ | |
163 | #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ | |
164 | ||
165 | /* | |
166 | * SSP Raw Interrupt Status Register - SSP_RIS | |
167 | */ | |
168 | /* Receive Overrun Raw Interrupt status */ | |
169 | #define SSP_RIS_MASK_RORRIS (0x1UL << 0) | |
170 | /* Receive Timeout Raw Interrupt status */ | |
171 | #define SSP_RIS_MASK_RTRIS (0x1UL << 1) | |
172 | /* Receive FIFO Raw Interrupt status */ | |
173 | #define SSP_RIS_MASK_RXRIS (0x1UL << 2) | |
174 | /* Transmit FIFO Raw Interrupt status */ | |
175 | #define SSP_RIS_MASK_TXRIS (0x1UL << 3) | |
176 | ||
177 | /* | |
178 | * SSP Masked Interrupt Status Register - SSP_MIS | |
179 | */ | |
180 | /* Receive Overrun Masked Interrupt status */ | |
181 | #define SSP_MIS_MASK_RORMIS (0x1UL << 0) | |
182 | /* Receive Timeout Masked Interrupt status */ | |
183 | #define SSP_MIS_MASK_RTMIS (0x1UL << 1) | |
184 | /* Receive FIFO Masked Interrupt status */ | |
185 | #define SSP_MIS_MASK_RXMIS (0x1UL << 2) | |
186 | /* Transmit FIFO Masked Interrupt status */ | |
187 | #define SSP_MIS_MASK_TXMIS (0x1UL << 3) | |
188 | ||
189 | /* | |
190 | * SSP Interrupt Clear Register - SSP_ICR | |
191 | */ | |
192 | /* Receive Overrun Raw Clear Interrupt bit */ | |
193 | #define SSP_ICR_MASK_RORIC (0x1UL << 0) | |
194 | /* Receive Timeout Clear Interrupt bit */ | |
195 | #define SSP_ICR_MASK_RTIC (0x1UL << 1) | |
196 | ||
197 | /* | |
198 | * SSP DMA Control Register - SSP_DMACR | |
199 | */ | |
200 | /* Receive DMA Enable bit */ | |
201 | #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) | |
202 | /* Transmit DMA Enable bit */ | |
203 | #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) | |
204 | ||
205 | /* | |
206 | * SSP Integration Test control Register - SSP_ITCR | |
207 | */ | |
208 | #define SSP_ITCR_MASK_ITEN (0x1UL << 0) | |
209 | #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) | |
210 | ||
211 | /* | |
212 | * SSP Integration Test Input Register - SSP_ITIP | |
213 | */ | |
214 | #define ITIP_MASK_SSPRXD (0x1UL << 0) | |
215 | #define ITIP_MASK_SSPFSSIN (0x1UL << 1) | |
216 | #define ITIP_MASK_SSPCLKIN (0x1UL << 2) | |
217 | #define ITIP_MASK_RXDMAC (0x1UL << 3) | |
218 | #define ITIP_MASK_TXDMAC (0x1UL << 4) | |
219 | #define ITIP_MASK_SSPTXDIN (0x1UL << 5) | |
220 | ||
221 | /* | |
222 | * SSP Integration Test output Register - SSP_ITOP | |
223 | */ | |
224 | #define ITOP_MASK_SSPTXD (0x1UL << 0) | |
225 | #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) | |
226 | #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) | |
227 | #define ITOP_MASK_SSPOEn (0x1UL << 3) | |
228 | #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) | |
229 | #define ITOP_MASK_RORINTR (0x1UL << 5) | |
230 | #define ITOP_MASK_RTINTR (0x1UL << 6) | |
231 | #define ITOP_MASK_RXINTR (0x1UL << 7) | |
232 | #define ITOP_MASK_TXINTR (0x1UL << 8) | |
233 | #define ITOP_MASK_INTR (0x1UL << 9) | |
234 | #define ITOP_MASK_RXDMABREQ (0x1UL << 10) | |
235 | #define ITOP_MASK_RXDMASREQ (0x1UL << 11) | |
236 | #define ITOP_MASK_TXDMABREQ (0x1UL << 12) | |
237 | #define ITOP_MASK_TXDMASREQ (0x1UL << 13) | |
238 | ||
239 | /* | |
240 | * SSP Test Data Register - SSP_TDR | |
241 | */ | |
556f4aeb | 242 | #define TDR_MASK_TESTDATA (0xFFFFFFFF) |
b43d65f7 LW |
243 | |
244 | /* | |
245 | * Message State | |
246 | * we use the spi_message.state (void *) pointer to | |
247 | * hold a single state value, that's why all this | |
248 | * (void *) casting is done here. | |
249 | */ | |
556f4aeb LW |
250 | #define STATE_START ((void *) 0) |
251 | #define STATE_RUNNING ((void *) 1) | |
252 | #define STATE_DONE ((void *) 2) | |
253 | #define STATE_ERROR ((void *) -1) | |
b43d65f7 | 254 | |
b43d65f7 LW |
255 | /* |
256 | * SSP State - Whether Enabled or Disabled | |
257 | */ | |
556f4aeb LW |
258 | #define SSP_DISABLED (0) |
259 | #define SSP_ENABLED (1) | |
b43d65f7 LW |
260 | |
261 | /* | |
262 | * SSP DMA State - Whether DMA Enabled or Disabled | |
263 | */ | |
556f4aeb LW |
264 | #define SSP_DMA_DISABLED (0) |
265 | #define SSP_DMA_ENABLED (1) | |
b43d65f7 LW |
266 | |
267 | /* | |
268 | * SSP Clock Defaults | |
269 | */ | |
556f4aeb LW |
270 | #define SSP_DEFAULT_CLKRATE 0x2 |
271 | #define SSP_DEFAULT_PRESCALE 0x40 | |
b43d65f7 LW |
272 | |
273 | /* | |
274 | * SSP Clock Parameter ranges | |
275 | */ | |
276 | #define CPSDVR_MIN 0x02 | |
277 | #define CPSDVR_MAX 0xFE | |
278 | #define SCR_MIN 0x00 | |
279 | #define SCR_MAX 0xFF | |
280 | ||
281 | /* | |
282 | * SSP Interrupt related Macros | |
283 | */ | |
284 | #define DEFAULT_SSP_REG_IMSC 0x0UL | |
285 | #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC | |
286 | #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) | |
287 | ||
288 | #define CLEAR_ALL_INTERRUPTS 0x3 | |
289 | ||
290 | ||
291 | /* | |
292 | * The type of reading going on on this chip | |
293 | */ | |
294 | enum ssp_reading { | |
295 | READING_NULL, | |
296 | READING_U8, | |
297 | READING_U16, | |
298 | READING_U32 | |
299 | }; | |
300 | ||
301 | /** | |
302 | * The type of writing going on on this chip | |
303 | */ | |
304 | enum ssp_writing { | |
305 | WRITING_NULL, | |
306 | WRITING_U8, | |
307 | WRITING_U16, | |
308 | WRITING_U32 | |
309 | }; | |
310 | ||
311 | /** | |
312 | * struct vendor_data - vendor-specific config parameters | |
313 | * for PL022 derivates | |
314 | * @fifodepth: depth of FIFOs (both) | |
315 | * @max_bpw: maximum number of bits per word | |
316 | * @unidir: supports unidirection transfers | |
556f4aeb LW |
317 | * @extended_cr: 32 bit wide control register 0 with extra |
318 | * features and extra features in CR1 as found in the ST variants | |
781c7b12 | 319 | * @pl023: supports a subset of the ST extensions called "PL023" |
b43d65f7 LW |
320 | */ |
321 | struct vendor_data { | |
322 | int fifodepth; | |
323 | int max_bpw; | |
324 | bool unidir; | |
556f4aeb | 325 | bool extended_cr; |
781c7b12 | 326 | bool pl023; |
b43d65f7 LW |
327 | }; |
328 | ||
329 | /** | |
330 | * struct pl022 - This is the private SSP driver data structure | |
331 | * @adev: AMBA device model hookup | |
12e8b325 LW |
332 | * @vendor: vendor data for the IP block |
333 | * @phybase: the physical memory where the SSP device resides | |
334 | * @virtbase: the virtual memory where the SSP is mapped | |
335 | * @clk: outgoing clock "SPICLK" for the SPI bus | |
b43d65f7 LW |
336 | * @master: SPI framework hookup |
337 | * @master_info: controller-specific data from machine setup | |
b43d65f7 | 338 | * @workqueue: a workqueue on which any spi_message request is queued |
12e8b325 LW |
339 | * @pump_messages: work struct for scheduling work to the workqueue |
340 | * @queue_lock: spinlock to syncronise access to message queue | |
341 | * @queue: message queue | |
b43d65f7 | 342 | * @busy: workqueue is busy |
5e8b821d | 343 | * @running: workqueue is running |
b43d65f7 LW |
344 | * @pump_transfers: Tasklet used in Interrupt Transfer mode |
345 | * @cur_msg: Pointer to current spi_message being processed | |
346 | * @cur_transfer: Pointer to current spi_transfer | |
347 | * @cur_chip: pointer to current clients chip(assigned from controller_state) | |
348 | * @tx: current position in TX buffer to be read | |
349 | * @tx_end: end position in TX buffer to be read | |
350 | * @rx: current position in RX buffer to be written | |
351 | * @rx_end: end position in RX buffer to be written | |
12e8b325 LW |
352 | * @read: the type of read currently going on |
353 | * @write: the type of write currently going on | |
354 | * @exp_fifo_level: expected FIFO level | |
355 | * @dma_rx_channel: optional channel for RX DMA | |
356 | * @dma_tx_channel: optional channel for TX DMA | |
357 | * @sgt_rx: scattertable for the RX transfer | |
358 | * @sgt_tx: scattertable for the TX transfer | |
359 | * @dummypage: a dummy page used for driving data on the bus with DMA | |
b43d65f7 LW |
360 | */ |
361 | struct pl022 { | |
362 | struct amba_device *adev; | |
363 | struct vendor_data *vendor; | |
364 | resource_size_t phybase; | |
365 | void __iomem *virtbase; | |
366 | struct clk *clk; | |
367 | struct spi_master *master; | |
368 | struct pl022_ssp_controller *master_info; | |
369 | /* Driver message queue */ | |
370 | struct workqueue_struct *workqueue; | |
371 | struct work_struct pump_messages; | |
372 | spinlock_t queue_lock; | |
373 | struct list_head queue; | |
dec5a581 | 374 | bool busy; |
5e8b821d | 375 | bool running; |
b43d65f7 LW |
376 | /* Message transfer pump */ |
377 | struct tasklet_struct pump_transfers; | |
378 | struct spi_message *cur_msg; | |
379 | struct spi_transfer *cur_transfer; | |
380 | struct chip_data *cur_chip; | |
381 | void *tx; | |
382 | void *tx_end; | |
383 | void *rx; | |
384 | void *rx_end; | |
385 | enum ssp_reading read; | |
386 | enum ssp_writing write; | |
fc05475f | 387 | u32 exp_fifo_level; |
b1b6b9aa LW |
388 | /* DMA settings */ |
389 | #ifdef CONFIG_DMA_ENGINE | |
390 | struct dma_chan *dma_rx_channel; | |
391 | struct dma_chan *dma_tx_channel; | |
392 | struct sg_table sgt_rx; | |
393 | struct sg_table sgt_tx; | |
394 | char *dummypage; | |
395 | #endif | |
b43d65f7 LW |
396 | }; |
397 | ||
398 | /** | |
399 | * struct chip_data - To maintain runtime state of SSP for each client chip | |
556f4aeb LW |
400 | * @cr0: Value of control register CR0 of SSP - on later ST variants this |
401 | * register is 32 bits wide rather than just 16 | |
b43d65f7 LW |
402 | * @cr1: Value of control register CR1 of SSP |
403 | * @dmacr: Value of DMA control Register of SSP | |
404 | * @cpsr: Value of Clock prescale register | |
405 | * @n_bytes: how many bytes(power of 2) reqd for a given data width of client | |
406 | * @enable_dma: Whether to enable DMA or not | |
b43d65f7 | 407 | * @read: function ptr to be used to read when doing xfer for this chip |
12e8b325 | 408 | * @write: function ptr to be used to write when doing xfer for this chip |
b43d65f7 LW |
409 | * @cs_control: chip select callback provided by chip |
410 | * @xfer_type: polling/interrupt/DMA | |
411 | * | |
412 | * Runtime state of the SSP controller, maintained per chip, | |
413 | * This would be set according to the current message that would be served | |
414 | */ | |
415 | struct chip_data { | |
556f4aeb | 416 | u32 cr0; |
b43d65f7 LW |
417 | u16 cr1; |
418 | u16 dmacr; | |
419 | u16 cpsr; | |
420 | u8 n_bytes; | |
b1b6b9aa | 421 | bool enable_dma; |
b43d65f7 LW |
422 | enum ssp_reading read; |
423 | enum ssp_writing write; | |
424 | void (*cs_control) (u32 command); | |
425 | int xfer_type; | |
426 | }; | |
427 | ||
428 | /** | |
429 | * null_cs_control - Dummy chip select function | |
430 | * @command: select/delect the chip | |
431 | * | |
432 | * If no chip select function is provided by client this is used as dummy | |
433 | * chip select | |
434 | */ | |
435 | static void null_cs_control(u32 command) | |
436 | { | |
437 | pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); | |
438 | } | |
439 | ||
440 | /** | |
441 | * giveback - current spi_message is over, schedule next message and call | |
442 | * callback of this message. Assumes that caller already | |
443 | * set message->status; dma and pio irqs are blocked | |
444 | * @pl022: SSP driver private data structure | |
445 | */ | |
446 | static void giveback(struct pl022 *pl022) | |
447 | { | |
448 | struct spi_transfer *last_transfer; | |
449 | unsigned long flags; | |
450 | struct spi_message *msg; | |
451 | void (*curr_cs_control) (u32 command); | |
452 | ||
453 | /* | |
454 | * This local reference to the chip select function | |
455 | * is needed because we set curr_chip to NULL | |
456 | * as a step toward termininating the message. | |
457 | */ | |
458 | curr_cs_control = pl022->cur_chip->cs_control; | |
459 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
460 | msg = pl022->cur_msg; | |
461 | pl022->cur_msg = NULL; | |
462 | pl022->cur_transfer = NULL; | |
463 | pl022->cur_chip = NULL; | |
464 | queue_work(pl022->workqueue, &pl022->pump_messages); | |
465 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
466 | ||
467 | last_transfer = list_entry(msg->transfers.prev, | |
468 | struct spi_transfer, | |
469 | transfer_list); | |
470 | ||
471 | /* Delay if requested before any change in chip select */ | |
472 | if (last_transfer->delay_usecs) | |
473 | /* | |
474 | * FIXME: This runs in interrupt context. | |
475 | * Is this really smart? | |
476 | */ | |
477 | udelay(last_transfer->delay_usecs); | |
478 | ||
479 | /* | |
480 | * Drop chip select UNLESS cs_change is true or we are returning | |
481 | * a message with an error, or next message is for another chip | |
482 | */ | |
483 | if (!last_transfer->cs_change) | |
484 | curr_cs_control(SSP_CHIP_DESELECT); | |
485 | else { | |
486 | struct spi_message *next_msg; | |
487 | ||
488 | /* Holding of cs was hinted, but we need to make sure | |
489 | * the next message is for the same chip. Don't waste | |
490 | * time with the following tests unless this was hinted. | |
491 | * | |
492 | * We cannot postpone this until pump_messages, because | |
493 | * after calling msg->complete (below) the driver that | |
494 | * sent the current message could be unloaded, which | |
495 | * could invalidate the cs_control() callback... | |
496 | */ | |
497 | ||
498 | /* get a pointer to the next message, if any */ | |
499 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
500 | if (list_empty(&pl022->queue)) | |
501 | next_msg = NULL; | |
502 | else | |
503 | next_msg = list_entry(pl022->queue.next, | |
504 | struct spi_message, queue); | |
505 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
506 | ||
507 | /* see if the next and current messages point | |
508 | * to the same chip | |
509 | */ | |
510 | if (next_msg && next_msg->spi != msg->spi) | |
511 | next_msg = NULL; | |
512 | if (!next_msg || msg->state == STATE_ERROR) | |
513 | curr_cs_control(SSP_CHIP_DESELECT); | |
514 | } | |
515 | msg->state = NULL; | |
516 | if (msg->complete) | |
517 | msg->complete(msg->context); | |
808f1037 | 518 | /* This message is completed, so let's turn off the clocks & power */ |
b43d65f7 | 519 | clk_disable(pl022->clk); |
545074fb | 520 | amba_pclk_disable(pl022->adev); |
808f1037 | 521 | amba_vcore_disable(pl022->adev); |
b43d65f7 LW |
522 | } |
523 | ||
524 | /** | |
525 | * flush - flush the FIFO to reach a clean state | |
526 | * @pl022: SSP driver private data structure | |
527 | */ | |
528 | static int flush(struct pl022 *pl022) | |
529 | { | |
530 | unsigned long limit = loops_per_jiffy << 1; | |
531 | ||
532 | dev_dbg(&pl022->adev->dev, "flush\n"); | |
533 | do { | |
534 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
535 | readw(SSP_DR(pl022->virtbase)); | |
536 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); | |
fc05475f LW |
537 | |
538 | pl022->exp_fifo_level = 0; | |
539 | ||
b43d65f7 LW |
540 | return limit; |
541 | } | |
542 | ||
543 | /** | |
544 | * restore_state - Load configuration of current chip | |
545 | * @pl022: SSP driver private data structure | |
546 | */ | |
547 | static void restore_state(struct pl022 *pl022) | |
548 | { | |
549 | struct chip_data *chip = pl022->cur_chip; | |
550 | ||
556f4aeb LW |
551 | if (pl022->vendor->extended_cr) |
552 | writel(chip->cr0, SSP_CR0(pl022->virtbase)); | |
553 | else | |
554 | writew(chip->cr0, SSP_CR0(pl022->virtbase)); | |
b43d65f7 LW |
555 | writew(chip->cr1, SSP_CR1(pl022->virtbase)); |
556 | writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); | |
557 | writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); | |
558 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
559 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
560 | } | |
561 | ||
b43d65f7 LW |
562 | /* |
563 | * Default SSP Register Values | |
564 | */ | |
565 | #define DEFAULT_SSP_REG_CR0 ( \ | |
566 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ | |
556f4aeb LW |
567 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ |
568 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | |
569 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ | |
570 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ | |
571 | ) | |
572 | ||
573 | /* ST versions have slightly different bit layout */ | |
574 | #define DEFAULT_SSP_REG_CR0_ST ( \ | |
575 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ | |
576 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ | |
b43d65f7 | 577 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
ee2b805c | 578 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
556f4aeb LW |
579 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
580 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ | |
581 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ | |
b43d65f7 LW |
582 | ) |
583 | ||
781c7b12 LW |
584 | /* The PL023 version is slightly different again */ |
585 | #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ | |
586 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ | |
587 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ | |
588 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ | |
589 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ | |
590 | ) | |
591 | ||
b43d65f7 LW |
592 | #define DEFAULT_SSP_REG_CR1 ( \ |
593 | GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ | |
594 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ | |
595 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ | |
556f4aeb | 596 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ |
b43d65f7 LW |
597 | ) |
598 | ||
556f4aeb LW |
599 | /* ST versions extend this register to use all 16 bits */ |
600 | #define DEFAULT_SSP_REG_CR1_ST ( \ | |
601 | DEFAULT_SSP_REG_CR1 | \ | |
602 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ | |
603 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ | |
604 | GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ | |
605 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ | |
606 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ | |
607 | ) | |
608 | ||
781c7b12 LW |
609 | /* |
610 | * The PL023 variant has further differences: no loopback mode, no microwire | |
611 | * support, and a new clock feedback delay setting. | |
612 | */ | |
613 | #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ | |
614 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ | |
615 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ | |
616 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ | |
617 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ | |
618 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ | |
619 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ | |
620 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ | |
621 | GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ | |
622 | ) | |
556f4aeb | 623 | |
b43d65f7 | 624 | #define DEFAULT_SSP_REG_CPSR ( \ |
556f4aeb | 625 | GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ |
b43d65f7 LW |
626 | ) |
627 | ||
628 | #define DEFAULT_SSP_REG_DMACR (\ | |
629 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ | |
630 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ | |
631 | ) | |
632 | ||
781c7b12 LW |
633 | /** |
634 | * load_ssp_default_config - Load default configuration for SSP | |
635 | * @pl022: SSP driver private data structure | |
636 | */ | |
b43d65f7 LW |
637 | static void load_ssp_default_config(struct pl022 *pl022) |
638 | { | |
781c7b12 LW |
639 | if (pl022->vendor->pl023) { |
640 | writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); | |
641 | writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); | |
642 | } else if (pl022->vendor->extended_cr) { | |
556f4aeb LW |
643 | writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); |
644 | writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); | |
645 | } else { | |
646 | writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); | |
647 | writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); | |
648 | } | |
b43d65f7 LW |
649 | writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); |
650 | writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); | |
651 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
652 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
653 | } | |
654 | ||
655 | /** | |
656 | * This will write to TX and read from RX according to the parameters | |
657 | * set in pl022. | |
658 | */ | |
659 | static void readwriter(struct pl022 *pl022) | |
660 | { | |
661 | ||
662 | /* | |
663 | * The FIFO depth is different inbetween primecell variants. | |
664 | * I believe filling in too much in the FIFO might cause | |
665 | * errons in 8bit wide transfers on ARM variants (just 8 words | |
666 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. | |
667 | * | |
fc05475f LW |
668 | * To prevent this issue, the TX FIFO is only filled to the |
669 | * unused RX FIFO fill length, regardless of what the TX | |
670 | * FIFO status flag indicates. | |
b43d65f7 LW |
671 | */ |
672 | dev_dbg(&pl022->adev->dev, | |
673 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", | |
674 | __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); | |
675 | ||
676 | /* Read as much as you can */ | |
677 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
678 | && (pl022->rx < pl022->rx_end)) { | |
679 | switch (pl022->read) { | |
680 | case READING_NULL: | |
681 | readw(SSP_DR(pl022->virtbase)); | |
682 | break; | |
683 | case READING_U8: | |
684 | *(u8 *) (pl022->rx) = | |
685 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; | |
686 | break; | |
687 | case READING_U16: | |
688 | *(u16 *) (pl022->rx) = | |
689 | (u16) readw(SSP_DR(pl022->virtbase)); | |
690 | break; | |
691 | case READING_U32: | |
692 | *(u32 *) (pl022->rx) = | |
693 | readl(SSP_DR(pl022->virtbase)); | |
694 | break; | |
695 | } | |
696 | pl022->rx += (pl022->cur_chip->n_bytes); | |
fc05475f | 697 | pl022->exp_fifo_level--; |
b43d65f7 LW |
698 | } |
699 | /* | |
fc05475f | 700 | * Write as much as possible up to the RX FIFO size |
b43d65f7 | 701 | */ |
fc05475f | 702 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
b43d65f7 LW |
703 | && (pl022->tx < pl022->tx_end)) { |
704 | switch (pl022->write) { | |
705 | case WRITING_NULL: | |
706 | writew(0x0, SSP_DR(pl022->virtbase)); | |
707 | break; | |
708 | case WRITING_U8: | |
709 | writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); | |
710 | break; | |
711 | case WRITING_U16: | |
712 | writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); | |
713 | break; | |
714 | case WRITING_U32: | |
715 | writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); | |
716 | break; | |
717 | } | |
718 | pl022->tx += (pl022->cur_chip->n_bytes); | |
fc05475f | 719 | pl022->exp_fifo_level++; |
b43d65f7 LW |
720 | /* |
721 | * This inner reader takes care of things appearing in the RX | |
722 | * FIFO as we're transmitting. This will happen a lot since the | |
723 | * clock starts running when you put things into the TX FIFO, | |
724 | * and then things are continously clocked into the RX FIFO. | |
725 | */ | |
726 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | |
727 | && (pl022->rx < pl022->rx_end)) { | |
728 | switch (pl022->read) { | |
729 | case READING_NULL: | |
730 | readw(SSP_DR(pl022->virtbase)); | |
731 | break; | |
732 | case READING_U8: | |
733 | *(u8 *) (pl022->rx) = | |
734 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; | |
735 | break; | |
736 | case READING_U16: | |
737 | *(u16 *) (pl022->rx) = | |
738 | (u16) readw(SSP_DR(pl022->virtbase)); | |
739 | break; | |
740 | case READING_U32: | |
741 | *(u32 *) (pl022->rx) = | |
742 | readl(SSP_DR(pl022->virtbase)); | |
743 | break; | |
744 | } | |
745 | pl022->rx += (pl022->cur_chip->n_bytes); | |
fc05475f | 746 | pl022->exp_fifo_level--; |
b43d65f7 LW |
747 | } |
748 | } | |
749 | /* | |
750 | * When we exit here the TX FIFO should be full and the RX FIFO | |
751 | * should be empty | |
752 | */ | |
753 | } | |
754 | ||
755 | ||
756 | /** | |
757 | * next_transfer - Move to the Next transfer in the current spi message | |
758 | * @pl022: SSP driver private data structure | |
759 | * | |
760 | * This function moves though the linked list of spi transfers in the | |
761 | * current spi message and returns with the state of current spi | |
762 | * message i.e whether its last transfer is done(STATE_DONE) or | |
763 | * Next transfer is ready(STATE_RUNNING) | |
764 | */ | |
765 | static void *next_transfer(struct pl022 *pl022) | |
766 | { | |
767 | struct spi_message *msg = pl022->cur_msg; | |
768 | struct spi_transfer *trans = pl022->cur_transfer; | |
769 | ||
770 | /* Move to next transfer */ | |
771 | if (trans->transfer_list.next != &msg->transfers) { | |
772 | pl022->cur_transfer = | |
773 | list_entry(trans->transfer_list.next, | |
774 | struct spi_transfer, transfer_list); | |
775 | return STATE_RUNNING; | |
776 | } | |
777 | return STATE_DONE; | |
778 | } | |
b1b6b9aa LW |
779 | |
780 | /* | |
781 | * This DMA functionality is only compiled in if we have | |
782 | * access to the generic DMA devices/DMA engine. | |
783 | */ | |
784 | #ifdef CONFIG_DMA_ENGINE | |
785 | static void unmap_free_dma_scatter(struct pl022 *pl022) | |
786 | { | |
787 | /* Unmap and free the SG tables */ | |
b7298896 | 788 | dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa | 789 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
b7298896 | 790 | dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa LW |
791 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
792 | sg_free_table(&pl022->sgt_rx); | |
793 | sg_free_table(&pl022->sgt_tx); | |
794 | } | |
795 | ||
796 | static void dma_callback(void *data) | |
797 | { | |
798 | struct pl022 *pl022 = data; | |
799 | struct spi_message *msg = pl022->cur_msg; | |
800 | ||
801 | BUG_ON(!pl022->sgt_rx.sgl); | |
802 | ||
803 | #ifdef VERBOSE_DEBUG | |
804 | /* | |
805 | * Optionally dump out buffers to inspect contents, this is | |
806 | * good if you want to convince yourself that the loopback | |
807 | * read/write contents are the same, when adopting to a new | |
808 | * DMA engine. | |
809 | */ | |
810 | { | |
811 | struct scatterlist *sg; | |
812 | unsigned int i; | |
813 | ||
814 | dma_sync_sg_for_cpu(&pl022->adev->dev, | |
815 | pl022->sgt_rx.sgl, | |
816 | pl022->sgt_rx.nents, | |
817 | DMA_FROM_DEVICE); | |
818 | ||
819 | for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { | |
820 | dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); | |
821 | print_hex_dump(KERN_ERR, "SPI RX: ", | |
822 | DUMP_PREFIX_OFFSET, | |
823 | 16, | |
824 | 1, | |
825 | sg_virt(sg), | |
826 | sg_dma_len(sg), | |
827 | 1); | |
828 | } | |
829 | for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { | |
830 | dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); | |
831 | print_hex_dump(KERN_ERR, "SPI TX: ", | |
832 | DUMP_PREFIX_OFFSET, | |
833 | 16, | |
834 | 1, | |
835 | sg_virt(sg), | |
836 | sg_dma_len(sg), | |
837 | 1); | |
838 | } | |
839 | } | |
840 | #endif | |
841 | ||
842 | unmap_free_dma_scatter(pl022); | |
843 | ||
844 | /* Update total bytes transfered */ | |
845 | msg->actual_length += pl022->cur_transfer->len; | |
846 | if (pl022->cur_transfer->cs_change) | |
847 | pl022->cur_chip-> | |
848 | cs_control(SSP_CHIP_DESELECT); | |
849 | ||
850 | /* Move to next transfer */ | |
851 | msg->state = next_transfer(pl022); | |
852 | tasklet_schedule(&pl022->pump_transfers); | |
853 | } | |
854 | ||
855 | static void setup_dma_scatter(struct pl022 *pl022, | |
856 | void *buffer, | |
857 | unsigned int length, | |
858 | struct sg_table *sgtab) | |
859 | { | |
860 | struct scatterlist *sg; | |
861 | int bytesleft = length; | |
862 | void *bufp = buffer; | |
863 | int mapbytes; | |
864 | int i; | |
865 | ||
866 | if (buffer) { | |
867 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { | |
868 | /* | |
869 | * If there are less bytes left than what fits | |
870 | * in the current page (plus page alignment offset) | |
871 | * we just feed in this, else we stuff in as much | |
872 | * as we can. | |
873 | */ | |
874 | if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) | |
875 | mapbytes = bytesleft; | |
876 | else | |
877 | mapbytes = PAGE_SIZE - offset_in_page(bufp); | |
878 | sg_set_page(sg, virt_to_page(bufp), | |
879 | mapbytes, offset_in_page(bufp)); | |
880 | bufp += mapbytes; | |
881 | bytesleft -= mapbytes; | |
882 | dev_dbg(&pl022->adev->dev, | |
883 | "set RX/TX target page @ %p, %d bytes, %d left\n", | |
884 | bufp, mapbytes, bytesleft); | |
885 | } | |
886 | } else { | |
887 | /* Map the dummy buffer on every page */ | |
888 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { | |
889 | if (bytesleft < PAGE_SIZE) | |
890 | mapbytes = bytesleft; | |
891 | else | |
892 | mapbytes = PAGE_SIZE; | |
893 | sg_set_page(sg, virt_to_page(pl022->dummypage), | |
894 | mapbytes, 0); | |
895 | bytesleft -= mapbytes; | |
896 | dev_dbg(&pl022->adev->dev, | |
897 | "set RX/TX to dummy page %d bytes, %d left\n", | |
898 | mapbytes, bytesleft); | |
899 | ||
900 | } | |
901 | } | |
902 | BUG_ON(bytesleft); | |
903 | } | |
904 | ||
905 | /** | |
906 | * configure_dma - configures the channels for the next transfer | |
907 | * @pl022: SSP driver's private data structure | |
908 | */ | |
909 | static int configure_dma(struct pl022 *pl022) | |
910 | { | |
911 | struct dma_slave_config rx_conf = { | |
912 | .src_addr = SSP_DR(pl022->phybase), | |
913 | .direction = DMA_FROM_DEVICE, | |
914 | .src_maxburst = pl022->vendor->fifodepth >> 1, | |
915 | }; | |
916 | struct dma_slave_config tx_conf = { | |
917 | .dst_addr = SSP_DR(pl022->phybase), | |
918 | .direction = DMA_TO_DEVICE, | |
919 | .dst_maxburst = pl022->vendor->fifodepth >> 1, | |
920 | }; | |
921 | unsigned int pages; | |
922 | int ret; | |
082086f2 | 923 | int rx_sglen, tx_sglen; |
b1b6b9aa LW |
924 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
925 | struct dma_chan *txchan = pl022->dma_tx_channel; | |
926 | struct dma_async_tx_descriptor *rxdesc; | |
927 | struct dma_async_tx_descriptor *txdesc; | |
b1b6b9aa LW |
928 | |
929 | /* Check that the channels are available */ | |
930 | if (!rxchan || !txchan) | |
931 | return -ENODEV; | |
932 | ||
933 | switch (pl022->read) { | |
934 | case READING_NULL: | |
935 | /* Use the same as for writing */ | |
936 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
937 | break; | |
938 | case READING_U8: | |
939 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
940 | break; | |
941 | case READING_U16: | |
942 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
943 | break; | |
944 | case READING_U32: | |
945 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
946 | break; | |
947 | } | |
948 | ||
949 | switch (pl022->write) { | |
950 | case WRITING_NULL: | |
951 | /* Use the same as for reading */ | |
952 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
953 | break; | |
954 | case WRITING_U8: | |
955 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
956 | break; | |
957 | case WRITING_U16: | |
958 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
959 | break; | |
960 | case WRITING_U32: | |
bc3f67a3 | 961 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
b1b6b9aa LW |
962 | break; |
963 | } | |
964 | ||
965 | /* SPI pecularity: we need to read and write the same width */ | |
966 | if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
967 | rx_conf.src_addr_width = tx_conf.dst_addr_width; | |
968 | if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
969 | tx_conf.dst_addr_width = rx_conf.src_addr_width; | |
970 | BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); | |
971 | ||
ecd442fd LW |
972 | dmaengine_slave_config(rxchan, &rx_conf); |
973 | dmaengine_slave_config(txchan, &tx_conf); | |
b1b6b9aa LW |
974 | |
975 | /* Create sglists for the transfers */ | |
976 | pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1; | |
977 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); | |
978 | ||
979 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL); | |
980 | if (ret) | |
981 | goto err_alloc_rx_sg; | |
982 | ||
983 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL); | |
984 | if (ret) | |
985 | goto err_alloc_tx_sg; | |
986 | ||
987 | /* Fill in the scatterlists for the RX+TX buffers */ | |
988 | setup_dma_scatter(pl022, pl022->rx, | |
989 | pl022->cur_transfer->len, &pl022->sgt_rx); | |
990 | setup_dma_scatter(pl022, pl022->tx, | |
991 | pl022->cur_transfer->len, &pl022->sgt_tx); | |
992 | ||
993 | /* Map DMA buffers */ | |
082086f2 | 994 | rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa | 995 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
082086f2 | 996 | if (!rx_sglen) |
b1b6b9aa LW |
997 | goto err_rx_sgmap; |
998 | ||
082086f2 | 999 | tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa | 1000 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
082086f2 | 1001 | if (!tx_sglen) |
b1b6b9aa LW |
1002 | goto err_tx_sgmap; |
1003 | ||
1004 | /* Send both scatterlists */ | |
1005 | rxdesc = rxchan->device->device_prep_slave_sg(rxchan, | |
1006 | pl022->sgt_rx.sgl, | |
082086f2 | 1007 | rx_sglen, |
b1b6b9aa LW |
1008 | DMA_FROM_DEVICE, |
1009 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1010 | if (!rxdesc) | |
1011 | goto err_rxdesc; | |
1012 | ||
1013 | txdesc = txchan->device->device_prep_slave_sg(txchan, | |
1014 | pl022->sgt_tx.sgl, | |
082086f2 | 1015 | tx_sglen, |
b1b6b9aa LW |
1016 | DMA_TO_DEVICE, |
1017 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1018 | if (!txdesc) | |
1019 | goto err_txdesc; | |
1020 | ||
1021 | /* Put the callback on the RX transfer only, that should finish last */ | |
1022 | rxdesc->callback = dma_callback; | |
1023 | rxdesc->callback_param = pl022; | |
1024 | ||
1025 | /* Submit and fire RX and TX with TX last so we're ready to read! */ | |
ecd442fd LW |
1026 | dmaengine_submit(rxdesc); |
1027 | dmaengine_submit(txdesc); | |
1028 | dma_async_issue_pending(rxchan); | |
1029 | dma_async_issue_pending(txchan); | |
b1b6b9aa LW |
1030 | |
1031 | return 0; | |
1032 | ||
b1b6b9aa | 1033 | err_txdesc: |
ecd442fd | 1034 | dmaengine_terminate_all(txchan); |
b1b6b9aa | 1035 | err_rxdesc: |
ecd442fd | 1036 | dmaengine_terminate_all(rxchan); |
b7298896 | 1037 | dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
b1b6b9aa LW |
1038 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
1039 | err_tx_sgmap: | |
b7298896 | 1040 | dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
b1b6b9aa LW |
1041 | pl022->sgt_tx.nents, DMA_FROM_DEVICE); |
1042 | err_rx_sgmap: | |
1043 | sg_free_table(&pl022->sgt_tx); | |
1044 | err_alloc_tx_sg: | |
1045 | sg_free_table(&pl022->sgt_rx); | |
1046 | err_alloc_rx_sg: | |
1047 | return -ENOMEM; | |
1048 | } | |
1049 | ||
1050 | static int __init pl022_dma_probe(struct pl022 *pl022) | |
1051 | { | |
1052 | dma_cap_mask_t mask; | |
1053 | ||
1054 | /* Try to acquire a generic DMA engine slave channel */ | |
1055 | dma_cap_zero(mask); | |
1056 | dma_cap_set(DMA_SLAVE, mask); | |
1057 | /* | |
1058 | * We need both RX and TX channels to do DMA, else do none | |
1059 | * of them. | |
1060 | */ | |
1061 | pl022->dma_rx_channel = dma_request_channel(mask, | |
1062 | pl022->master_info->dma_filter, | |
1063 | pl022->master_info->dma_rx_param); | |
1064 | if (!pl022->dma_rx_channel) { | |
1065 | dev_err(&pl022->adev->dev, "no RX DMA channel!\n"); | |
1066 | goto err_no_rxchan; | |
1067 | } | |
1068 | ||
1069 | pl022->dma_tx_channel = dma_request_channel(mask, | |
1070 | pl022->master_info->dma_filter, | |
1071 | pl022->master_info->dma_tx_param); | |
1072 | if (!pl022->dma_tx_channel) { | |
1073 | dev_err(&pl022->adev->dev, "no TX DMA channel!\n"); | |
1074 | goto err_no_txchan; | |
1075 | } | |
1076 | ||
1077 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
1078 | if (!pl022->dummypage) { | |
1079 | dev_err(&pl022->adev->dev, "no DMA dummypage!\n"); | |
1080 | goto err_no_dummypage; | |
1081 | } | |
1082 | ||
1083 | dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", | |
1084 | dma_chan_name(pl022->dma_rx_channel), | |
1085 | dma_chan_name(pl022->dma_tx_channel)); | |
1086 | ||
1087 | return 0; | |
1088 | ||
1089 | err_no_dummypage: | |
1090 | dma_release_channel(pl022->dma_tx_channel); | |
1091 | err_no_txchan: | |
1092 | dma_release_channel(pl022->dma_rx_channel); | |
1093 | pl022->dma_rx_channel = NULL; | |
1094 | err_no_rxchan: | |
1095 | return -ENODEV; | |
1096 | } | |
1097 | ||
1098 | static void terminate_dma(struct pl022 *pl022) | |
1099 | { | |
1100 | struct dma_chan *rxchan = pl022->dma_rx_channel; | |
1101 | struct dma_chan *txchan = pl022->dma_tx_channel; | |
1102 | ||
ecd442fd LW |
1103 | dmaengine_terminate_all(rxchan); |
1104 | dmaengine_terminate_all(txchan); | |
b1b6b9aa LW |
1105 | unmap_free_dma_scatter(pl022); |
1106 | } | |
1107 | ||
1108 | static void pl022_dma_remove(struct pl022 *pl022) | |
1109 | { | |
1110 | if (pl022->busy) | |
1111 | terminate_dma(pl022); | |
1112 | if (pl022->dma_tx_channel) | |
1113 | dma_release_channel(pl022->dma_tx_channel); | |
1114 | if (pl022->dma_rx_channel) | |
1115 | dma_release_channel(pl022->dma_rx_channel); | |
1116 | kfree(pl022->dummypage); | |
1117 | } | |
1118 | ||
1119 | #else | |
1120 | static inline int configure_dma(struct pl022 *pl022) | |
1121 | { | |
1122 | return -ENODEV; | |
1123 | } | |
1124 | ||
1125 | static inline int pl022_dma_probe(struct pl022 *pl022) | |
1126 | { | |
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | static inline void pl022_dma_remove(struct pl022 *pl022) | |
1131 | { | |
1132 | } | |
1133 | #endif | |
1134 | ||
b43d65f7 LW |
1135 | /** |
1136 | * pl022_interrupt_handler - Interrupt handler for SSP controller | |
1137 | * | |
1138 | * This function handles interrupts generated for an interrupt based transfer. | |
1139 | * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the | |
1140 | * current message's state as STATE_ERROR and schedule the tasklet | |
1141 | * pump_transfers which will do the postprocessing of the current message by | |
1142 | * calling giveback(). Otherwise it reads data from RX FIFO till there is no | |
1143 | * more data, and writes data in TX FIFO till it is not full. If we complete | |
1144 | * the transfer we move to the next transfer and schedule the tasklet. | |
1145 | */ | |
1146 | static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) | |
1147 | { | |
1148 | struct pl022 *pl022 = dev_id; | |
1149 | struct spi_message *msg = pl022->cur_msg; | |
1150 | u16 irq_status = 0; | |
1151 | u16 flag = 0; | |
1152 | ||
1153 | if (unlikely(!msg)) { | |
1154 | dev_err(&pl022->adev->dev, | |
1155 | "bad message state in interrupt handler"); | |
1156 | /* Never fail */ | |
1157 | return IRQ_HANDLED; | |
1158 | } | |
1159 | ||
1160 | /* Read the Interrupt Status Register */ | |
1161 | irq_status = readw(SSP_MIS(pl022->virtbase)); | |
1162 | ||
1163 | if (unlikely(!irq_status)) | |
1164 | return IRQ_NONE; | |
1165 | ||
b1b6b9aa LW |
1166 | /* |
1167 | * This handles the FIFO interrupts, the timeout | |
1168 | * interrupts are flatly ignored, they cannot be | |
1169 | * trusted. | |
1170 | */ | |
b43d65f7 LW |
1171 | if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { |
1172 | /* | |
1173 | * Overrun interrupt - bail out since our Data has been | |
1174 | * corrupted | |
1175 | */ | |
b1b6b9aa | 1176 | dev_err(&pl022->adev->dev, "FIFO overrun\n"); |
b43d65f7 LW |
1177 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) |
1178 | dev_err(&pl022->adev->dev, | |
1179 | "RXFIFO is full\n"); | |
1180 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) | |
1181 | dev_err(&pl022->adev->dev, | |
1182 | "TXFIFO is full\n"); | |
1183 | ||
1184 | /* | |
1185 | * Disable and clear interrupts, disable SSP, | |
1186 | * mark message with bad status so it can be | |
1187 | * retried. | |
1188 | */ | |
1189 | writew(DISABLE_ALL_INTERRUPTS, | |
1190 | SSP_IMSC(pl022->virtbase)); | |
1191 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
1192 | writew((readw(SSP_CR1(pl022->virtbase)) & | |
1193 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | |
1194 | msg->state = STATE_ERROR; | |
1195 | ||
1196 | /* Schedule message queue handler */ | |
1197 | tasklet_schedule(&pl022->pump_transfers); | |
1198 | return IRQ_HANDLED; | |
1199 | } | |
1200 | ||
1201 | readwriter(pl022); | |
1202 | ||
1203 | if ((pl022->tx == pl022->tx_end) && (flag == 0)) { | |
1204 | flag = 1; | |
1205 | /* Disable Transmit interrupt */ | |
1206 | writew(readw(SSP_IMSC(pl022->virtbase)) & | |
1207 | (~SSP_IMSC_MASK_TXIM), | |
1208 | SSP_IMSC(pl022->virtbase)); | |
1209 | } | |
1210 | ||
1211 | /* | |
1212 | * Since all transactions must write as much as shall be read, | |
1213 | * we can conclude the entire transaction once RX is complete. | |
1214 | * At this point, all TX will always be finished. | |
1215 | */ | |
1216 | if (pl022->rx >= pl022->rx_end) { | |
1217 | writew(DISABLE_ALL_INTERRUPTS, | |
1218 | SSP_IMSC(pl022->virtbase)); | |
1219 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); | |
1220 | if (unlikely(pl022->rx > pl022->rx_end)) { | |
1221 | dev_warn(&pl022->adev->dev, "read %u surplus " | |
1222 | "bytes (did you request an odd " | |
1223 | "number of bytes on a 16bit bus?)\n", | |
1224 | (u32) (pl022->rx - pl022->rx_end)); | |
1225 | } | |
1226 | /* Update total bytes transfered */ | |
1227 | msg->actual_length += pl022->cur_transfer->len; | |
1228 | if (pl022->cur_transfer->cs_change) | |
1229 | pl022->cur_chip-> | |
1230 | cs_control(SSP_CHIP_DESELECT); | |
1231 | /* Move to next transfer */ | |
1232 | msg->state = next_transfer(pl022); | |
1233 | tasklet_schedule(&pl022->pump_transfers); | |
1234 | return IRQ_HANDLED; | |
1235 | } | |
1236 | ||
1237 | return IRQ_HANDLED; | |
1238 | } | |
1239 | ||
1240 | /** | |
1241 | * This sets up the pointers to memory for the next message to | |
1242 | * send out on the SPI bus. | |
1243 | */ | |
1244 | static int set_up_next_transfer(struct pl022 *pl022, | |
1245 | struct spi_transfer *transfer) | |
1246 | { | |
1247 | int residue; | |
1248 | ||
1249 | /* Sanity check the message for this bus width */ | |
1250 | residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; | |
1251 | if (unlikely(residue != 0)) { | |
1252 | dev_err(&pl022->adev->dev, | |
1253 | "message of %u bytes to transmit but the current " | |
1254 | "chip bus has a data width of %u bytes!\n", | |
1255 | pl022->cur_transfer->len, | |
1256 | pl022->cur_chip->n_bytes); | |
1257 | dev_err(&pl022->adev->dev, "skipping this message\n"); | |
1258 | return -EIO; | |
1259 | } | |
1260 | pl022->tx = (void *)transfer->tx_buf; | |
1261 | pl022->tx_end = pl022->tx + pl022->cur_transfer->len; | |
1262 | pl022->rx = (void *)transfer->rx_buf; | |
1263 | pl022->rx_end = pl022->rx + pl022->cur_transfer->len; | |
1264 | pl022->write = | |
1265 | pl022->tx ? pl022->cur_chip->write : WRITING_NULL; | |
1266 | pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; | |
1267 | return 0; | |
1268 | } | |
1269 | ||
1270 | /** | |
b1b6b9aa LW |
1271 | * pump_transfers - Tasklet function which schedules next transfer |
1272 | * when running in interrupt or DMA transfer mode. | |
b43d65f7 LW |
1273 | * @data: SSP driver private data structure |
1274 | * | |
1275 | */ | |
1276 | static void pump_transfers(unsigned long data) | |
1277 | { | |
1278 | struct pl022 *pl022 = (struct pl022 *) data; | |
1279 | struct spi_message *message = NULL; | |
1280 | struct spi_transfer *transfer = NULL; | |
1281 | struct spi_transfer *previous = NULL; | |
1282 | ||
1283 | /* Get current state information */ | |
1284 | message = pl022->cur_msg; | |
1285 | transfer = pl022->cur_transfer; | |
1286 | ||
1287 | /* Handle for abort */ | |
1288 | if (message->state == STATE_ERROR) { | |
1289 | message->status = -EIO; | |
1290 | giveback(pl022); | |
1291 | return; | |
1292 | } | |
1293 | ||
1294 | /* Handle end of message */ | |
1295 | if (message->state == STATE_DONE) { | |
1296 | message->status = 0; | |
1297 | giveback(pl022); | |
1298 | return; | |
1299 | } | |
1300 | ||
1301 | /* Delay if requested at end of transfer before CS change */ | |
1302 | if (message->state == STATE_RUNNING) { | |
1303 | previous = list_entry(transfer->transfer_list.prev, | |
1304 | struct spi_transfer, | |
1305 | transfer_list); | |
1306 | if (previous->delay_usecs) | |
1307 | /* | |
1308 | * FIXME: This runs in interrupt context. | |
1309 | * Is this really smart? | |
1310 | */ | |
1311 | udelay(previous->delay_usecs); | |
1312 | ||
1313 | /* Drop chip select only if cs_change is requested */ | |
1314 | if (previous->cs_change) | |
1315 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
1316 | } else { | |
1317 | /* STATE_START */ | |
1318 | message->state = STATE_RUNNING; | |
1319 | } | |
1320 | ||
1321 | if (set_up_next_transfer(pl022, transfer)) { | |
1322 | message->state = STATE_ERROR; | |
1323 | message->status = -EIO; | |
1324 | giveback(pl022); | |
1325 | return; | |
1326 | } | |
1327 | /* Flush the FIFOs and let's go! */ | |
1328 | flush(pl022); | |
b43d65f7 | 1329 | |
b1b6b9aa LW |
1330 | if (pl022->cur_chip->enable_dma) { |
1331 | if (configure_dma(pl022)) { | |
1332 | dev_dbg(&pl022->adev->dev, | |
1333 | "configuration of DMA failed, fall back to interrupt mode\n"); | |
1334 | goto err_config_dma; | |
1335 | } | |
b43d65f7 LW |
1336 | return; |
1337 | } | |
b43d65f7 | 1338 | |
b1b6b9aa LW |
1339 | err_config_dma: |
1340 | writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); | |
b43d65f7 LW |
1341 | } |
1342 | ||
b1b6b9aa | 1343 | static void do_interrupt_dma_transfer(struct pl022 *pl022) |
b43d65f7 | 1344 | { |
b1b6b9aa | 1345 | u32 irqflags = ENABLE_ALL_INTERRUPTS; |
b43d65f7 LW |
1346 | |
1347 | /* Enable target chip */ | |
1348 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
1349 | if (set_up_next_transfer(pl022, pl022->cur_transfer)) { | |
1350 | /* Error path */ | |
1351 | pl022->cur_msg->state = STATE_ERROR; | |
1352 | pl022->cur_msg->status = -EIO; | |
1353 | giveback(pl022); | |
1354 | return; | |
1355 | } | |
b1b6b9aa LW |
1356 | /* If we're using DMA, set up DMA here */ |
1357 | if (pl022->cur_chip->enable_dma) { | |
1358 | /* Configure DMA transfer */ | |
1359 | if (configure_dma(pl022)) { | |
1360 | dev_dbg(&pl022->adev->dev, | |
1361 | "configuration of DMA failed, fall back to interrupt mode\n"); | |
1362 | goto err_config_dma; | |
1363 | } | |
1364 | /* Disable interrupts in DMA mode, IRQ from DMA controller */ | |
1365 | irqflags = DISABLE_ALL_INTERRUPTS; | |
1366 | } | |
1367 | err_config_dma: | |
b43d65f7 LW |
1368 | /* Enable SSP, turn on interrupts */ |
1369 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), | |
1370 | SSP_CR1(pl022->virtbase)); | |
b1b6b9aa | 1371 | writew(irqflags, SSP_IMSC(pl022->virtbase)); |
b43d65f7 LW |
1372 | } |
1373 | ||
b1b6b9aa | 1374 | static void do_polling_transfer(struct pl022 *pl022) |
b43d65f7 | 1375 | { |
b43d65f7 LW |
1376 | struct spi_message *message = NULL; |
1377 | struct spi_transfer *transfer = NULL; | |
1378 | struct spi_transfer *previous = NULL; | |
1379 | struct chip_data *chip; | |
1380 | ||
1381 | chip = pl022->cur_chip; | |
1382 | message = pl022->cur_msg; | |
1383 | ||
1384 | while (message->state != STATE_DONE) { | |
1385 | /* Handle for abort */ | |
1386 | if (message->state == STATE_ERROR) | |
1387 | break; | |
1388 | transfer = pl022->cur_transfer; | |
1389 | ||
1390 | /* Delay if requested at end of transfer */ | |
1391 | if (message->state == STATE_RUNNING) { | |
1392 | previous = | |
1393 | list_entry(transfer->transfer_list.prev, | |
1394 | struct spi_transfer, transfer_list); | |
1395 | if (previous->delay_usecs) | |
1396 | udelay(previous->delay_usecs); | |
1397 | if (previous->cs_change) | |
1398 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
1399 | } else { | |
1400 | /* STATE_START */ | |
1401 | message->state = STATE_RUNNING; | |
1402 | pl022->cur_chip->cs_control(SSP_CHIP_SELECT); | |
1403 | } | |
1404 | ||
1405 | /* Configuration Changing Per Transfer */ | |
1406 | if (set_up_next_transfer(pl022, transfer)) { | |
1407 | /* Error path */ | |
1408 | message->state = STATE_ERROR; | |
1409 | break; | |
1410 | } | |
1411 | /* Flush FIFOs and enable SSP */ | |
1412 | flush(pl022); | |
1413 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), | |
1414 | SSP_CR1(pl022->virtbase)); | |
1415 | ||
556f4aeb | 1416 | dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); |
b43d65f7 LW |
1417 | /* FIXME: insert a timeout so we don't hang here indefinately */ |
1418 | while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) | |
1419 | readwriter(pl022); | |
1420 | ||
1421 | /* Update total byte transfered */ | |
1422 | message->actual_length += pl022->cur_transfer->len; | |
1423 | if (pl022->cur_transfer->cs_change) | |
1424 | pl022->cur_chip->cs_control(SSP_CHIP_DESELECT); | |
1425 | /* Move to next transfer */ | |
1426 | message->state = next_transfer(pl022); | |
1427 | } | |
1428 | ||
1429 | /* Handle end of message */ | |
1430 | if (message->state == STATE_DONE) | |
1431 | message->status = 0; | |
1432 | else | |
1433 | message->status = -EIO; | |
1434 | ||
1435 | giveback(pl022); | |
1436 | return; | |
1437 | } | |
1438 | ||
1439 | /** | |
1440 | * pump_messages - Workqueue function which processes spi message queue | |
1441 | * @data: pointer to private data of SSP driver | |
1442 | * | |
1443 | * This function checks if there is any spi message in the queue that | |
1444 | * needs processing and delegate control to appropriate function | |
b1b6b9aa | 1445 | * do_polling_transfer()/do_interrupt_dma_transfer() |
b43d65f7 LW |
1446 | * based on the kind of the transfer |
1447 | * | |
1448 | */ | |
1449 | static void pump_messages(struct work_struct *work) | |
1450 | { | |
1451 | struct pl022 *pl022 = | |
1452 | container_of(work, struct pl022, pump_messages); | |
1453 | unsigned long flags; | |
1454 | ||
1455 | /* Lock queue and check for queue work */ | |
1456 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
5e8b821d | 1457 | if (list_empty(&pl022->queue) || !pl022->running) { |
dec5a581 | 1458 | pl022->busy = false; |
b43d65f7 LW |
1459 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1460 | return; | |
1461 | } | |
1462 | /* Make sure we are not already running a message */ | |
1463 | if (pl022->cur_msg) { | |
1464 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1465 | return; | |
1466 | } | |
1467 | /* Extract head of queue */ | |
1468 | pl022->cur_msg = | |
1469 | list_entry(pl022->queue.next, struct spi_message, queue); | |
1470 | ||
1471 | list_del_init(&pl022->cur_msg->queue); | |
dec5a581 | 1472 | pl022->busy = true; |
b43d65f7 LW |
1473 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1474 | ||
1475 | /* Initial message state */ | |
1476 | pl022->cur_msg->state = STATE_START; | |
1477 | pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next, | |
1478 | struct spi_transfer, | |
1479 | transfer_list); | |
1480 | ||
1481 | /* Setup the SPI using the per chip configuration */ | |
1482 | pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); | |
1483 | /* | |
808f1037 LW |
1484 | * We enable the core voltage and clocks here, then the clocks |
1485 | * and core will be disabled when giveback() is called in each method | |
1486 | * (poll/interrupt/DMA) | |
b43d65f7 | 1487 | */ |
808f1037 | 1488 | amba_vcore_enable(pl022->adev); |
545074fb | 1489 | amba_pclk_enable(pl022->adev); |
b43d65f7 LW |
1490 | clk_enable(pl022->clk); |
1491 | restore_state(pl022); | |
1492 | flush(pl022); | |
1493 | ||
1494 | if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) | |
1495 | do_polling_transfer(pl022); | |
b43d65f7 | 1496 | else |
b1b6b9aa | 1497 | do_interrupt_dma_transfer(pl022); |
b43d65f7 LW |
1498 | } |
1499 | ||
1500 | ||
1501 | static int __init init_queue(struct pl022 *pl022) | |
1502 | { | |
1503 | INIT_LIST_HEAD(&pl022->queue); | |
1504 | spin_lock_init(&pl022->queue_lock); | |
1505 | ||
5e8b821d | 1506 | pl022->running = false; |
dec5a581 | 1507 | pl022->busy = false; |
b43d65f7 LW |
1508 | |
1509 | tasklet_init(&pl022->pump_transfers, | |
1510 | pump_transfers, (unsigned long)pl022); | |
1511 | ||
1512 | INIT_WORK(&pl022->pump_messages, pump_messages); | |
1513 | pl022->workqueue = create_singlethread_workqueue( | |
1514 | dev_name(pl022->master->dev.parent)); | |
1515 | if (pl022->workqueue == NULL) | |
1516 | return -EBUSY; | |
1517 | ||
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | ||
1522 | static int start_queue(struct pl022 *pl022) | |
1523 | { | |
1524 | unsigned long flags; | |
1525 | ||
1526 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1527 | ||
5e8b821d | 1528 | if (pl022->running || pl022->busy) { |
b43d65f7 LW |
1529 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1530 | return -EBUSY; | |
1531 | } | |
1532 | ||
5e8b821d | 1533 | pl022->running = true; |
b43d65f7 LW |
1534 | pl022->cur_msg = NULL; |
1535 | pl022->cur_transfer = NULL; | |
1536 | pl022->cur_chip = NULL; | |
1537 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1538 | ||
1539 | queue_work(pl022->workqueue, &pl022->pump_messages); | |
1540 | ||
1541 | return 0; | |
1542 | } | |
1543 | ||
1544 | ||
1545 | static int stop_queue(struct pl022 *pl022) | |
1546 | { | |
1547 | unsigned long flags; | |
1548 | unsigned limit = 500; | |
1549 | int status = 0; | |
1550 | ||
1551 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1552 | ||
1553 | /* This is a bit lame, but is optimized for the common execution path. | |
1554 | * A wait_queue on the pl022->busy could be used, but then the common | |
1555 | * execution path (pump_messages) would be required to call wake_up or | |
1556 | * friends on every SPI message. Do this instead */ | |
b43d65f7 LW |
1557 | while (!list_empty(&pl022->queue) && pl022->busy && limit--) { |
1558 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1559 | msleep(10); | |
1560 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1561 | } | |
1562 | ||
1563 | if (!list_empty(&pl022->queue) || pl022->busy) | |
1564 | status = -EBUSY; | |
5e8b821d LW |
1565 | else |
1566 | pl022->running = false; | |
b43d65f7 LW |
1567 | |
1568 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1569 | ||
1570 | return status; | |
1571 | } | |
1572 | ||
1573 | static int destroy_queue(struct pl022 *pl022) | |
1574 | { | |
1575 | int status; | |
1576 | ||
1577 | status = stop_queue(pl022); | |
1578 | /* we are unloading the module or failing to load (only two calls | |
1579 | * to this routine), and neither call can handle a return value. | |
1580 | * However, destroy_workqueue calls flush_workqueue, and that will | |
1581 | * block until all work is done. If the reason that stop_queue | |
1582 | * timed out is that the work will never finish, then it does no | |
1583 | * good to call destroy_workqueue, so return anyway. */ | |
1584 | if (status != 0) | |
1585 | return status; | |
1586 | ||
1587 | destroy_workqueue(pl022->workqueue); | |
1588 | ||
1589 | return 0; | |
1590 | } | |
1591 | ||
1592 | static int verify_controller_parameters(struct pl022 *pl022, | |
f9d629c7 | 1593 | struct pl022_config_chip const *chip_info) |
b43d65f7 | 1594 | { |
b43d65f7 LW |
1595 | if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) |
1596 | || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { | |
5a1c98be | 1597 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1598 | "interface is configured incorrectly\n"); |
1599 | return -EINVAL; | |
1600 | } | |
1601 | if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && | |
1602 | (!pl022->vendor->unidir)) { | |
5a1c98be | 1603 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1604 | "unidirectional mode not supported in this " |
1605 | "hardware version\n"); | |
1606 | return -EINVAL; | |
1607 | } | |
1608 | if ((chip_info->hierarchy != SSP_MASTER) | |
1609 | && (chip_info->hierarchy != SSP_SLAVE)) { | |
5a1c98be | 1610 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1611 | "hierarchy is configured incorrectly\n"); |
1612 | return -EINVAL; | |
1613 | } | |
b43d65f7 LW |
1614 | if ((chip_info->com_mode != INTERRUPT_TRANSFER) |
1615 | && (chip_info->com_mode != DMA_TRANSFER) | |
1616 | && (chip_info->com_mode != POLLING_TRANSFER)) { | |
5a1c98be | 1617 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1618 | "Communication mode is configured incorrectly\n"); |
1619 | return -EINVAL; | |
1620 | } | |
1621 | if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM) | |
1622 | || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) { | |
5a1c98be | 1623 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1624 | "RX FIFO Trigger Level is configured incorrectly\n"); |
1625 | return -EINVAL; | |
1626 | } | |
1627 | if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC) | |
1628 | || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) { | |
5a1c98be | 1629 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1630 | "TX FIFO Trigger Level is configured incorrectly\n"); |
1631 | return -EINVAL; | |
1632 | } | |
b43d65f7 LW |
1633 | if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { |
1634 | if ((chip_info->ctrl_len < SSP_BITS_4) | |
1635 | || (chip_info->ctrl_len > SSP_BITS_32)) { | |
5a1c98be | 1636 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1637 | "CTRL LEN is configured incorrectly\n"); |
1638 | return -EINVAL; | |
1639 | } | |
1640 | if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) | |
1641 | && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { | |
5a1c98be | 1642 | dev_err(&pl022->adev->dev, |
b43d65f7 LW |
1643 | "Wait State is configured incorrectly\n"); |
1644 | return -EINVAL; | |
1645 | } | |
556f4aeb LW |
1646 | /* Half duplex is only available in the ST Micro version */ |
1647 | if (pl022->vendor->extended_cr) { | |
1648 | if ((chip_info->duplex != | |
1649 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) | |
1650 | && (chip_info->duplex != | |
4a4fd471 | 1651 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { |
5a1c98be | 1652 | dev_err(&pl022->adev->dev, |
556f4aeb LW |
1653 | "Microwire duplex mode is configured incorrectly\n"); |
1654 | return -EINVAL; | |
4a4fd471 | 1655 | } |
556f4aeb LW |
1656 | } else { |
1657 | if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) | |
5a1c98be | 1658 | dev_err(&pl022->adev->dev, |
556f4aeb LW |
1659 | "Microwire half duplex mode requested," |
1660 | " but this is only available in the" | |
1661 | " ST version of PL022\n"); | |
b43d65f7 LW |
1662 | return -EINVAL; |
1663 | } | |
1664 | } | |
b43d65f7 LW |
1665 | return 0; |
1666 | } | |
1667 | ||
1668 | /** | |
1669 | * pl022_transfer - transfer function registered to SPI master framework | |
1670 | * @spi: spi device which is requesting transfer | |
1671 | * @msg: spi message which is to handled is queued to driver queue | |
1672 | * | |
1673 | * This function is registered to the SPI framework for this SPI master | |
1674 | * controller. It will queue the spi_message in the queue of driver if | |
1675 | * the queue is not stopped and return. | |
1676 | */ | |
1677 | static int pl022_transfer(struct spi_device *spi, struct spi_message *msg) | |
1678 | { | |
1679 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); | |
1680 | unsigned long flags; | |
1681 | ||
1682 | spin_lock_irqsave(&pl022->queue_lock, flags); | |
1683 | ||
5e8b821d | 1684 | if (!pl022->running) { |
b43d65f7 LW |
1685 | spin_unlock_irqrestore(&pl022->queue_lock, flags); |
1686 | return -ESHUTDOWN; | |
1687 | } | |
1688 | msg->actual_length = 0; | |
1689 | msg->status = -EINPROGRESS; | |
1690 | msg->state = STATE_START; | |
1691 | ||
1692 | list_add_tail(&msg->queue, &pl022->queue); | |
5e8b821d | 1693 | if (pl022->running && !pl022->busy) |
b43d65f7 LW |
1694 | queue_work(pl022->workqueue, &pl022->pump_messages); |
1695 | ||
1696 | spin_unlock_irqrestore(&pl022->queue_lock, flags); | |
1697 | return 0; | |
1698 | } | |
1699 | ||
1700 | static int calculate_effective_freq(struct pl022 *pl022, | |
1701 | int freq, | |
1702 | struct ssp_clock_params *clk_freq) | |
1703 | { | |
1704 | /* Lets calculate the frequency parameters */ | |
1705 | u16 cpsdvsr = 2; | |
1706 | u16 scr = 0; | |
1707 | bool freq_found = false; | |
1708 | u32 rate; | |
1709 | u32 max_tclk; | |
1710 | u32 min_tclk; | |
1711 | ||
1712 | rate = clk_get_rate(pl022->clk); | |
1713 | /* cpsdvscr = 2 & scr 0 */ | |
1714 | max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN))); | |
1715 | /* cpsdvsr = 254 & scr = 255 */ | |
1716 | min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX))); | |
1717 | ||
1718 | if ((freq <= max_tclk) && (freq >= min_tclk)) { | |
1719 | while (cpsdvsr <= CPSDVR_MAX && !freq_found) { | |
1720 | while (scr <= SCR_MAX && !freq_found) { | |
1721 | if ((rate / | |
1722 | (cpsdvsr * (1 + scr))) > freq) | |
1723 | scr += 1; | |
1724 | else { | |
1725 | /* | |
1726 | * This bool is made true when | |
1727 | * effective frequency >= | |
1728 | * target frequency is found | |
1729 | */ | |
1730 | freq_found = true; | |
1731 | if ((rate / | |
1732 | (cpsdvsr * (1 + scr))) != freq) { | |
1733 | if (scr == SCR_MIN) { | |
1734 | cpsdvsr -= 2; | |
1735 | scr = SCR_MAX; | |
1736 | } else | |
1737 | scr -= 1; | |
1738 | } | |
1739 | } | |
1740 | } | |
1741 | if (!freq_found) { | |
1742 | cpsdvsr += 2; | |
1743 | scr = SCR_MIN; | |
1744 | } | |
1745 | } | |
1746 | if (cpsdvsr != 0) { | |
1747 | dev_dbg(&pl022->adev->dev, | |
1748 | "SSP Effective Frequency is %u\n", | |
1749 | (rate / (cpsdvsr * (1 + scr)))); | |
1750 | clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF); | |
1751 | clk_freq->scr = (u8) (scr & 0xFF); | |
1752 | dev_dbg(&pl022->adev->dev, | |
1753 | "SSP cpsdvsr = %d, scr = %d\n", | |
1754 | clk_freq->cpsdvsr, clk_freq->scr); | |
1755 | } | |
1756 | } else { | |
1757 | dev_err(&pl022->adev->dev, | |
1758 | "controller data is incorrect: out of range frequency"); | |
1759 | return -EINVAL; | |
1760 | } | |
1761 | return 0; | |
1762 | } | |
1763 | ||
f9d629c7 LW |
1764 | |
1765 | /* | |
1766 | * A piece of default chip info unless the platform | |
1767 | * supplies it. | |
1768 | */ | |
1769 | static const struct pl022_config_chip pl022_default_chip_info = { | |
1770 | .com_mode = POLLING_TRANSFER, | |
1771 | .iface = SSP_INTERFACE_MOTOROLA_SPI, | |
1772 | .hierarchy = SSP_SLAVE, | |
1773 | .slave_tx_disable = DO_NOT_DRIVE_TX, | |
1774 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, | |
1775 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, | |
1776 | .ctrl_len = SSP_BITS_8, | |
1777 | .wait_state = SSP_MWIRE_WAIT_ZERO, | |
1778 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | |
1779 | .cs_control = null_cs_control, | |
1780 | }; | |
1781 | ||
1782 | ||
b43d65f7 LW |
1783 | /** |
1784 | * pl022_setup - setup function registered to SPI master framework | |
1785 | * @spi: spi device which is requesting setup | |
1786 | * | |
1787 | * This function is registered to the SPI framework for this SPI master | |
1788 | * controller. If it is the first time when setup is called by this device, | |
1789 | * this function will initialize the runtime state for this chip and save | |
1790 | * the same in the device structure. Else it will update the runtime info | |
1791 | * with the updated chip info. Nothing is really being written to the | |
1792 | * controller hardware here, that is not done until the actual transfer | |
1793 | * commence. | |
1794 | */ | |
b43d65f7 LW |
1795 | static int pl022_setup(struct spi_device *spi) |
1796 | { | |
f9d629c7 | 1797 | struct pl022_config_chip const *chip_info; |
b43d65f7 | 1798 | struct chip_data *chip; |
94a1b6d8 | 1799 | struct ssp_clock_params clk_freq = {0, }; |
b43d65f7 LW |
1800 | int status = 0; |
1801 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); | |
bde435a9 KW |
1802 | unsigned int bits = spi->bits_per_word; |
1803 | u32 tmp; | |
b43d65f7 LW |
1804 | |
1805 | if (!spi->max_speed_hz) | |
1806 | return -EINVAL; | |
1807 | ||
1808 | /* Get controller_state if one is supplied */ | |
1809 | chip = spi_get_ctldata(spi); | |
1810 | ||
1811 | if (chip == NULL) { | |
1812 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
1813 | if (!chip) { | |
1814 | dev_err(&spi->dev, | |
1815 | "cannot allocate controller state\n"); | |
1816 | return -ENOMEM; | |
1817 | } | |
1818 | dev_dbg(&spi->dev, | |
1819 | "allocated memory for controller's runtime state\n"); | |
1820 | } | |
1821 | ||
1822 | /* Get controller data if one is supplied */ | |
1823 | chip_info = spi->controller_data; | |
1824 | ||
1825 | if (chip_info == NULL) { | |
f9d629c7 | 1826 | chip_info = &pl022_default_chip_info; |
b43d65f7 LW |
1827 | /* spi_board_info.controller_data not is supplied */ |
1828 | dev_dbg(&spi->dev, | |
1829 | "using default controller_data settings\n"); | |
f9d629c7 | 1830 | } else |
b43d65f7 LW |
1831 | dev_dbg(&spi->dev, |
1832 | "using user supplied controller_data settings\n"); | |
b43d65f7 LW |
1833 | |
1834 | /* | |
1835 | * We can override with custom divisors, else we use the board | |
1836 | * frequency setting | |
1837 | */ | |
1838 | if ((0 == chip_info->clk_freq.cpsdvsr) | |
1839 | && (0 == chip_info->clk_freq.scr)) { | |
1840 | status = calculate_effective_freq(pl022, | |
1841 | spi->max_speed_hz, | |
f9d629c7 | 1842 | &clk_freq); |
b43d65f7 LW |
1843 | if (status < 0) |
1844 | goto err_config_params; | |
1845 | } else { | |
f9d629c7 LW |
1846 | memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); |
1847 | if ((clk_freq.cpsdvsr % 2) != 0) | |
1848 | clk_freq.cpsdvsr = | |
1849 | clk_freq.cpsdvsr - 1; | |
b43d65f7 | 1850 | } |
f9d629c7 LW |
1851 | if ((clk_freq.cpsdvsr < CPSDVR_MIN) |
1852 | || (clk_freq.cpsdvsr > CPSDVR_MAX)) { | |
1853 | dev_err(&spi->dev, | |
1854 | "cpsdvsr is configured incorrectly\n"); | |
1855 | goto err_config_params; | |
1856 | } | |
1857 | ||
1858 | ||
b43d65f7 LW |
1859 | status = verify_controller_parameters(pl022, chip_info); |
1860 | if (status) { | |
1861 | dev_err(&spi->dev, "controller data is incorrect"); | |
1862 | goto err_config_params; | |
1863 | } | |
f9d629c7 | 1864 | |
b43d65f7 LW |
1865 | /* Now set controller state based on controller data */ |
1866 | chip->xfer_type = chip_info->com_mode; | |
f9d629c7 LW |
1867 | if (!chip_info->cs_control) { |
1868 | chip->cs_control = null_cs_control; | |
1869 | dev_warn(&spi->dev, | |
1870 | "chip select function is NULL for this chip\n"); | |
1871 | } else | |
1872 | chip->cs_control = chip_info->cs_control; | |
b43d65f7 | 1873 | |
bde435a9 KW |
1874 | if (bits <= 3) { |
1875 | /* PL022 doesn't support less than 4-bits */ | |
1876 | status = -ENOTSUPP; | |
1877 | goto err_config_params; | |
1878 | } else if (bits <= 8) { | |
1879 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); | |
b43d65f7 LW |
1880 | chip->n_bytes = 1; |
1881 | chip->read = READING_U8; | |
1882 | chip->write = WRITING_U8; | |
bde435a9 | 1883 | } else if (bits <= 16) { |
b43d65f7 LW |
1884 | dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); |
1885 | chip->n_bytes = 2; | |
1886 | chip->read = READING_U16; | |
1887 | chip->write = WRITING_U16; | |
1888 | } else { | |
1889 | if (pl022->vendor->max_bpw >= 32) { | |
1890 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); | |
1891 | chip->n_bytes = 4; | |
1892 | chip->read = READING_U32; | |
1893 | chip->write = WRITING_U32; | |
1894 | } else { | |
1895 | dev_err(&spi->dev, | |
1896 | "illegal data size for this controller!\n"); | |
1897 | dev_err(&spi->dev, | |
1898 | "a standard pl022 can only handle " | |
1899 | "1 <= n <= 16 bit words\n"); | |
bde435a9 | 1900 | status = -ENOTSUPP; |
b43d65f7 LW |
1901 | goto err_config_params; |
1902 | } | |
1903 | } | |
1904 | ||
1905 | /* Now Initialize all register settings required for this chip */ | |
1906 | chip->cr0 = 0; | |
1907 | chip->cr1 = 0; | |
1908 | chip->dmacr = 0; | |
1909 | chip->cpsr = 0; | |
1910 | if ((chip_info->com_mode == DMA_TRANSFER) | |
1911 | && ((pl022->master_info)->enable_dma)) { | |
b1b6b9aa | 1912 | chip->enable_dma = true; |
b43d65f7 | 1913 | dev_dbg(&spi->dev, "DMA mode set in controller state\n"); |
b43d65f7 LW |
1914 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
1915 | SSP_DMACR_MASK_RXDMAE, 0); | |
1916 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, | |
1917 | SSP_DMACR_MASK_TXDMAE, 1); | |
1918 | } else { | |
b1b6b9aa | 1919 | chip->enable_dma = false; |
b43d65f7 LW |
1920 | dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); |
1921 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, | |
1922 | SSP_DMACR_MASK_RXDMAE, 0); | |
1923 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, | |
1924 | SSP_DMACR_MASK_TXDMAE, 1); | |
1925 | } | |
1926 | ||
f9d629c7 | 1927 | chip->cpsr = clk_freq.cpsdvsr; |
b43d65f7 | 1928 | |
556f4aeb LW |
1929 | /* Special setup for the ST micro extended control registers */ |
1930 | if (pl022->vendor->extended_cr) { | |
bde435a9 KW |
1931 | u32 etx; |
1932 | ||
781c7b12 LW |
1933 | if (pl022->vendor->pl023) { |
1934 | /* These bits are only in the PL023 */ | |
1935 | SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, | |
1936 | SSP_CR1_MASK_FBCLKDEL_ST, 13); | |
1937 | } else { | |
1938 | /* These bits are in the PL022 but not PL023 */ | |
1939 | SSP_WRITE_BITS(chip->cr0, chip_info->duplex, | |
1940 | SSP_CR0_MASK_HALFDUP_ST, 5); | |
1941 | SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, | |
1942 | SSP_CR0_MASK_CSS_ST, 16); | |
1943 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, | |
1944 | SSP_CR0_MASK_FRF_ST, 21); | |
1945 | SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, | |
1946 | SSP_CR1_MASK_MWAIT_ST, 6); | |
1947 | } | |
bde435a9 | 1948 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
556f4aeb | 1949 | SSP_CR0_MASK_DSS_ST, 0); |
bde435a9 KW |
1950 | |
1951 | if (spi->mode & SPI_LSB_FIRST) { | |
1952 | tmp = SSP_RX_LSB; | |
1953 | etx = SSP_TX_LSB; | |
1954 | } else { | |
1955 | tmp = SSP_RX_MSB; | |
1956 | etx = SSP_TX_MSB; | |
1957 | } | |
1958 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); | |
1959 | SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); | |
556f4aeb LW |
1960 | SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, |
1961 | SSP_CR1_MASK_RXIFLSEL_ST, 7); | |
1962 | SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, | |
1963 | SSP_CR1_MASK_TXIFLSEL_ST, 10); | |
1964 | } else { | |
bde435a9 | 1965 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
556f4aeb LW |
1966 | SSP_CR0_MASK_DSS, 0); |
1967 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, | |
1968 | SSP_CR0_MASK_FRF, 4); | |
1969 | } | |
bde435a9 | 1970 | |
556f4aeb | 1971 | /* Stuff that is common for all versions */ |
bde435a9 KW |
1972 | if (spi->mode & SPI_CPOL) |
1973 | tmp = SSP_CLK_POL_IDLE_HIGH; | |
1974 | else | |
1975 | tmp = SSP_CLK_POL_IDLE_LOW; | |
1976 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); | |
1977 | ||
1978 | if (spi->mode & SPI_CPHA) | |
1979 | tmp = SSP_CLK_SECOND_EDGE; | |
1980 | else | |
1981 | tmp = SSP_CLK_FIRST_EDGE; | |
1982 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); | |
1983 | ||
f9d629c7 | 1984 | SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); |
781c7b12 | 1985 | /* Loopback is available on all versions except PL023 */ |
bde435a9 KW |
1986 | if (!pl022->vendor->pl023) { |
1987 | if (spi->mode & SPI_LOOP) | |
1988 | tmp = LOOPBACK_ENABLED; | |
1989 | else | |
1990 | tmp = LOOPBACK_DISABLED; | |
1991 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); | |
1992 | } | |
b43d65f7 LW |
1993 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); |
1994 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); | |
1995 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3); | |
b43d65f7 LW |
1996 | |
1997 | /* Save controller_state */ | |
1998 | spi_set_ctldata(spi, chip); | |
1999 | return status; | |
2000 | err_config_params: | |
bde435a9 | 2001 | spi_set_ctldata(spi, NULL); |
b43d65f7 LW |
2002 | kfree(chip); |
2003 | return status; | |
2004 | } | |
2005 | ||
2006 | /** | |
2007 | * pl022_cleanup - cleanup function registered to SPI master framework | |
2008 | * @spi: spi device which is requesting cleanup | |
2009 | * | |
2010 | * This function is registered to the SPI framework for this SPI master | |
2011 | * controller. It will free the runtime state of chip. | |
2012 | */ | |
2013 | static void pl022_cleanup(struct spi_device *spi) | |
2014 | { | |
2015 | struct chip_data *chip = spi_get_ctldata(spi); | |
2016 | ||
2017 | spi_set_ctldata(spi, NULL); | |
2018 | kfree(chip); | |
2019 | } | |
2020 | ||
2021 | ||
b4225885 | 2022 | static int __devinit |
aa25afad | 2023 | pl022_probe(struct amba_device *adev, const struct amba_id *id) |
b43d65f7 LW |
2024 | { |
2025 | struct device *dev = &adev->dev; | |
2026 | struct pl022_ssp_controller *platform_info = adev->dev.platform_data; | |
2027 | struct spi_master *master; | |
2028 | struct pl022 *pl022 = NULL; /*Data for this driver */ | |
2029 | int status = 0; | |
2030 | ||
2031 | dev_info(&adev->dev, | |
2032 | "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); | |
2033 | if (platform_info == NULL) { | |
2034 | dev_err(&adev->dev, "probe - no platform data supplied\n"); | |
2035 | status = -ENODEV; | |
2036 | goto err_no_pdata; | |
2037 | } | |
2038 | ||
2039 | /* Allocate master with space for data */ | |
2040 | master = spi_alloc_master(dev, sizeof(struct pl022)); | |
2041 | if (master == NULL) { | |
2042 | dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); | |
2043 | status = -ENOMEM; | |
2044 | goto err_no_master; | |
2045 | } | |
2046 | ||
2047 | pl022 = spi_master_get_devdata(master); | |
2048 | pl022->master = master; | |
2049 | pl022->master_info = platform_info; | |
2050 | pl022->adev = adev; | |
2051 | pl022->vendor = id->data; | |
2052 | ||
2053 | /* | |
2054 | * Bus Number Which has been Assigned to this SSP controller | |
2055 | * on this board | |
2056 | */ | |
2057 | master->bus_num = platform_info->bus_id; | |
2058 | master->num_chipselect = platform_info->num_chipselect; | |
2059 | master->cleanup = pl022_cleanup; | |
2060 | master->setup = pl022_setup; | |
2061 | master->transfer = pl022_transfer; | |
2062 | ||
bde435a9 KW |
2063 | /* |
2064 | * Supports mode 0-3, loopback, and active low CS. Transfers are | |
2065 | * always MS bit first on the original pl022. | |
2066 | */ | |
2067 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; | |
2068 | if (pl022->vendor->extended_cr) | |
2069 | master->mode_bits |= SPI_LSB_FIRST; | |
2070 | ||
b43d65f7 LW |
2071 | dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); |
2072 | ||
2073 | status = amba_request_regions(adev, NULL); | |
2074 | if (status) | |
2075 | goto err_no_ioregion; | |
2076 | ||
b1b6b9aa | 2077 | pl022->phybase = adev->res.start; |
b43d65f7 LW |
2078 | pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res)); |
2079 | if (pl022->virtbase == NULL) { | |
2080 | status = -ENOMEM; | |
2081 | goto err_no_ioremap; | |
2082 | } | |
2083 | printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n", | |
2084 | adev->res.start, pl022->virtbase); | |
2085 | ||
2086 | pl022->clk = clk_get(&adev->dev, NULL); | |
2087 | if (IS_ERR(pl022->clk)) { | |
2088 | status = PTR_ERR(pl022->clk); | |
2089 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); | |
2090 | goto err_no_clk; | |
2091 | } | |
2092 | ||
2093 | /* Disable SSP */ | |
b43d65f7 LW |
2094 | writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), |
2095 | SSP_CR1(pl022->virtbase)); | |
2096 | load_ssp_default_config(pl022); | |
b43d65f7 LW |
2097 | |
2098 | status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022", | |
2099 | pl022); | |
2100 | if (status < 0) { | |
2101 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); | |
2102 | goto err_no_irq; | |
2103 | } | |
b1b6b9aa LW |
2104 | |
2105 | /* Get DMA channels */ | |
2106 | if (platform_info->enable_dma) { | |
2107 | status = pl022_dma_probe(pl022); | |
2108 | if (status != 0) | |
2109 | goto err_no_dma; | |
2110 | } | |
2111 | ||
b43d65f7 LW |
2112 | /* Initialize and start queue */ |
2113 | status = init_queue(pl022); | |
2114 | if (status != 0) { | |
2115 | dev_err(&adev->dev, "probe - problem initializing queue\n"); | |
2116 | goto err_init_queue; | |
2117 | } | |
2118 | status = start_queue(pl022); | |
2119 | if (status != 0) { | |
2120 | dev_err(&adev->dev, "probe - problem starting queue\n"); | |
2121 | goto err_start_queue; | |
2122 | } | |
2123 | /* Register with the SPI framework */ | |
2124 | amba_set_drvdata(adev, pl022); | |
2125 | status = spi_register_master(master); | |
2126 | if (status != 0) { | |
2127 | dev_err(&adev->dev, | |
2128 | "probe - problem registering spi master\n"); | |
2129 | goto err_spi_register; | |
2130 | } | |
2131 | dev_dbg(dev, "probe succeded\n"); | |
808f1037 LW |
2132 | /* |
2133 | * Disable the silicon block pclk and any voltage domain and just | |
2134 | * power it up and clock it when it's needed | |
2135 | */ | |
545074fb | 2136 | amba_pclk_disable(adev); |
808f1037 | 2137 | amba_vcore_disable(adev); |
b43d65f7 LW |
2138 | return 0; |
2139 | ||
2140 | err_spi_register: | |
2141 | err_start_queue: | |
2142 | err_init_queue: | |
2143 | destroy_queue(pl022); | |
b1b6b9aa LW |
2144 | pl022_dma_remove(pl022); |
2145 | err_no_dma: | |
b43d65f7 LW |
2146 | free_irq(adev->irq[0], pl022); |
2147 | err_no_irq: | |
2148 | clk_put(pl022->clk); | |
2149 | err_no_clk: | |
2150 | iounmap(pl022->virtbase); | |
2151 | err_no_ioremap: | |
2152 | amba_release_regions(adev); | |
2153 | err_no_ioregion: | |
2154 | spi_master_put(master); | |
2155 | err_no_master: | |
2156 | err_no_pdata: | |
2157 | return status; | |
2158 | } | |
2159 | ||
b4225885 | 2160 | static int __devexit |
b43d65f7 LW |
2161 | pl022_remove(struct amba_device *adev) |
2162 | { | |
2163 | struct pl022 *pl022 = amba_get_drvdata(adev); | |
2164 | int status = 0; | |
2165 | if (!pl022) | |
2166 | return 0; | |
2167 | ||
2168 | /* Remove the queue */ | |
2169 | status = destroy_queue(pl022); | |
2170 | if (status != 0) { | |
2171 | dev_err(&adev->dev, | |
2172 | "queue remove failed (%d)\n", status); | |
2173 | return status; | |
2174 | } | |
2175 | load_ssp_default_config(pl022); | |
b1b6b9aa | 2176 | pl022_dma_remove(pl022); |
b43d65f7 LW |
2177 | free_irq(adev->irq[0], pl022); |
2178 | clk_disable(pl022->clk); | |
2179 | clk_put(pl022->clk); | |
2180 | iounmap(pl022->virtbase); | |
2181 | amba_release_regions(adev); | |
2182 | tasklet_disable(&pl022->pump_transfers); | |
2183 | spi_unregister_master(pl022->master); | |
2184 | spi_master_put(pl022->master); | |
2185 | amba_set_drvdata(adev, NULL); | |
2186 | dev_dbg(&adev->dev, "remove succeded\n"); | |
2187 | return 0; | |
2188 | } | |
2189 | ||
2190 | #ifdef CONFIG_PM | |
2191 | static int pl022_suspend(struct amba_device *adev, pm_message_t state) | |
2192 | { | |
2193 | struct pl022 *pl022 = amba_get_drvdata(adev); | |
2194 | int status = 0; | |
2195 | ||
2196 | status = stop_queue(pl022); | |
2197 | if (status) { | |
2198 | dev_warn(&adev->dev, "suspend cannot stop queue\n"); | |
2199 | return status; | |
2200 | } | |
2201 | ||
808f1037 | 2202 | amba_vcore_enable(adev); |
545074fb | 2203 | amba_pclk_enable(adev); |
b43d65f7 | 2204 | load_ssp_default_config(pl022); |
545074fb | 2205 | amba_pclk_disable(adev); |
808f1037 | 2206 | amba_vcore_disable(adev); |
b43d65f7 LW |
2207 | dev_dbg(&adev->dev, "suspended\n"); |
2208 | return 0; | |
2209 | } | |
2210 | ||
2211 | static int pl022_resume(struct amba_device *adev) | |
2212 | { | |
2213 | struct pl022 *pl022 = amba_get_drvdata(adev); | |
2214 | int status = 0; | |
2215 | ||
2216 | /* Start the queue running */ | |
2217 | status = start_queue(pl022); | |
2218 | if (status) | |
2219 | dev_err(&adev->dev, "problem starting queue (%d)\n", status); | |
2220 | else | |
2221 | dev_dbg(&adev->dev, "resumed\n"); | |
2222 | ||
2223 | return status; | |
2224 | } | |
2225 | #else | |
2226 | #define pl022_suspend NULL | |
2227 | #define pl022_resume NULL | |
2228 | #endif /* CONFIG_PM */ | |
2229 | ||
2230 | static struct vendor_data vendor_arm = { | |
2231 | .fifodepth = 8, | |
2232 | .max_bpw = 16, | |
2233 | .unidir = false, | |
556f4aeb | 2234 | .extended_cr = false, |
781c7b12 | 2235 | .pl023 = false, |
b43d65f7 LW |
2236 | }; |
2237 | ||
2238 | ||
2239 | static struct vendor_data vendor_st = { | |
2240 | .fifodepth = 32, | |
2241 | .max_bpw = 32, | |
2242 | .unidir = false, | |
556f4aeb | 2243 | .extended_cr = true, |
781c7b12 LW |
2244 | .pl023 = false, |
2245 | }; | |
2246 | ||
2247 | static struct vendor_data vendor_st_pl023 = { | |
2248 | .fifodepth = 32, | |
2249 | .max_bpw = 32, | |
2250 | .unidir = false, | |
2251 | .extended_cr = true, | |
2252 | .pl023 = true, | |
b43d65f7 LW |
2253 | }; |
2254 | ||
2255 | static struct amba_id pl022_ids[] = { | |
2256 | { | |
2257 | /* | |
2258 | * ARM PL022 variant, this has a 16bit wide | |
2259 | * and 8 locations deep TX/RX FIFO | |
2260 | */ | |
2261 | .id = 0x00041022, | |
2262 | .mask = 0x000fffff, | |
2263 | .data = &vendor_arm, | |
2264 | }, | |
2265 | { | |
2266 | /* | |
2267 | * ST Micro derivative, this has 32bit wide | |
2268 | * and 32 locations deep TX/RX FIFO | |
2269 | */ | |
e89e04fc | 2270 | .id = 0x01080022, |
b43d65f7 LW |
2271 | .mask = 0xffffffff, |
2272 | .data = &vendor_st, | |
2273 | }, | |
781c7b12 LW |
2274 | { |
2275 | /* | |
2276 | * ST-Ericsson derivative "PL023" (this is not | |
2277 | * an official ARM number), this is a PL022 SSP block | |
2278 | * stripped to SPI mode only, it has 32bit wide | |
2279 | * and 32 locations deep TX/RX FIFO but no extended | |
2280 | * CR0/CR1 register | |
2281 | */ | |
2282 | .id = 0x00080023, | |
2283 | .mask = 0xffffffff, | |
2284 | .data = &vendor_st_pl023, | |
2285 | }, | |
b43d65f7 LW |
2286 | { 0, 0 }, |
2287 | }; | |
2288 | ||
2289 | static struct amba_driver pl022_driver = { | |
2290 | .drv = { | |
2291 | .name = "ssp-pl022", | |
2292 | }, | |
2293 | .id_table = pl022_ids, | |
2294 | .probe = pl022_probe, | |
b4225885 | 2295 | .remove = __devexit_p(pl022_remove), |
b43d65f7 LW |
2296 | .suspend = pl022_suspend, |
2297 | .resume = pl022_resume, | |
2298 | }; | |
2299 | ||
2300 | ||
2301 | static int __init pl022_init(void) | |
2302 | { | |
2303 | return amba_driver_register(&pl022_driver); | |
2304 | } | |
2305 | ||
25c8e03b | 2306 | subsys_initcall(pl022_init); |
b43d65f7 LW |
2307 | |
2308 | static void __exit pl022_exit(void) | |
2309 | { | |
2310 | amba_driver_unregister(&pl022_driver); | |
2311 | } | |
2312 | ||
2313 | module_exit(pl022_exit); | |
2314 | ||
2315 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); | |
2316 | MODULE_DESCRIPTION("PL022 SSP Controller Driver"); | |
2317 | MODULE_LICENSE("GPL"); |