Commit | Line | Data |
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754ce4f2 HS |
1 | /* |
2 | * Driver for Atmel AT32 and AT91 SPI Controllers | |
3 | * | |
4 | * Copyright (C) 2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/spi/spi.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | #include <asm/arch/board.h> | |
24 | #include <asm/arch/gpio.h> | |
bb2d1c36 | 25 | #include <asm/arch/cpu.h> |
bb2d1c36 | 26 | |
754ce4f2 HS |
27 | #include "atmel_spi.h" |
28 | ||
29 | /* | |
30 | * The core SPI transfer engine just talks to a register bank to set up | |
31 | * DMA transfers; transfer queue progress is driven by IRQs. The clock | |
32 | * framework provides the base clock, subdivided for each spi_device. | |
33 | * | |
34 | * Newer controllers, marked with "new_1" flag, have: | |
35 | * - CR.LASTXFER | |
36 | * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) | |
37 | * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) | |
38 | * - SPI_CSRx.CSAAT | |
39 | * - SPI_CSRx.SBCR allows faster clocking | |
40 | */ | |
41 | struct atmel_spi { | |
42 | spinlock_t lock; | |
43 | ||
44 | void __iomem *regs; | |
45 | int irq; | |
46 | struct clk *clk; | |
47 | struct platform_device *pdev; | |
48 | unsigned new_1:1; | |
defbd3b4 | 49 | struct spi_device *stay; |
754ce4f2 HS |
50 | |
51 | u8 stopping; | |
52 | struct list_head queue; | |
53 | struct spi_transfer *current_transfer; | |
54 | unsigned long remaining_bytes; | |
55 | ||
56 | void *buffer; | |
57 | dma_addr_t buffer_dma; | |
58 | }; | |
59 | ||
60 | #define BUFFER_SIZE PAGE_SIZE | |
61 | #define INVALID_DMA_ADDRESS 0xffffffff | |
62 | ||
63 | /* | |
64 | * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby | |
65 | * they assume that spi slave device state will not change on deselect, so | |
defbd3b4 DB |
66 | * that automagic deselection is OK. ("NPCSx rises if no data is to be |
67 | * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer | |
68 | * controllers have CSAAT and friends. | |
754ce4f2 | 69 | * |
defbd3b4 DB |
70 | * Since the CSAAT functionality is a bit weird on newer controllers as |
71 | * well, we use GPIO to control nCSx pins on all controllers, updating | |
72 | * MR.PCS to avoid confusing the controller. Using GPIOs also lets us | |
73 | * support active-high chipselects despite the controller's belief that | |
74 | * only active-low devices/systems exists. | |
75 | * | |
76 | * However, at91rm9200 has a second erratum whereby nCS0 doesn't work | |
77 | * right when driven with GPIO. ("Mode Fault does not allow more than one | |
78 | * Master on Chip Select 0.") No workaround exists for that ... so for | |
79 | * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, | |
80 | * and (c) will trigger that first erratum in some cases. | |
754ce4f2 HS |
81 | */ |
82 | ||
defbd3b4 | 83 | static void cs_activate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 HS |
84 | { |
85 | unsigned gpio = (unsigned) spi->controller_data; | |
86 | unsigned active = spi->mode & SPI_CS_HIGH; | |
defbd3b4 DB |
87 | u32 mr; |
88 | ||
89 | mr = spi_readl(as, MR); | |
90 | mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr); | |
91 | ||
92 | dev_dbg(&spi->dev, "activate %u%s, mr %08x\n", | |
93 | gpio, active ? " (high)" : "", | |
94 | mr); | |
754ce4f2 | 95 | |
defbd3b4 DB |
96 | if (!(cpu_is_at91rm9200() && spi->chip_select == 0)) |
97 | gpio_set_value(gpio, active); | |
98 | spi_writel(as, MR, mr); | |
754ce4f2 HS |
99 | } |
100 | ||
defbd3b4 | 101 | static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) |
754ce4f2 HS |
102 | { |
103 | unsigned gpio = (unsigned) spi->controller_data; | |
104 | unsigned active = spi->mode & SPI_CS_HIGH; | |
defbd3b4 DB |
105 | u32 mr; |
106 | ||
107 | /* only deactivate *this* device; sometimes transfers to | |
108 | * another device may be active when this routine is called. | |
109 | */ | |
110 | mr = spi_readl(as, MR); | |
111 | if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) { | |
112 | mr = SPI_BFINS(PCS, 0xf, mr); | |
113 | spi_writel(as, MR, mr); | |
114 | } | |
754ce4f2 | 115 | |
defbd3b4 DB |
116 | dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n", |
117 | gpio, active ? " (low)" : "", | |
118 | mr); | |
119 | ||
120 | if (!(cpu_is_at91rm9200() && spi->chip_select == 0)) | |
121 | gpio_set_value(gpio, !active); | |
754ce4f2 HS |
122 | } |
123 | ||
124 | /* | |
125 | * Submit next transfer for DMA. | |
126 | * lock is held, spi irq is blocked | |
127 | */ | |
128 | static void atmel_spi_next_xfer(struct spi_master *master, | |
129 | struct spi_message *msg) | |
130 | { | |
131 | struct atmel_spi *as = spi_master_get_devdata(master); | |
132 | struct spi_transfer *xfer; | |
133 | u32 len; | |
134 | dma_addr_t tx_dma, rx_dma; | |
135 | ||
136 | xfer = as->current_transfer; | |
137 | if (!xfer || as->remaining_bytes == 0) { | |
138 | if (xfer) | |
139 | xfer = list_entry(xfer->transfer_list.next, | |
140 | struct spi_transfer, transfer_list); | |
141 | else | |
142 | xfer = list_entry(msg->transfers.next, | |
143 | struct spi_transfer, transfer_list); | |
144 | as->remaining_bytes = xfer->len; | |
145 | as->current_transfer = xfer; | |
146 | } | |
147 | ||
148 | len = as->remaining_bytes; | |
149 | ||
5a9a62bb HS |
150 | tx_dma = xfer->tx_dma + xfer->len - len; |
151 | rx_dma = xfer->rx_dma + xfer->len - len; | |
754ce4f2 HS |
152 | |
153 | /* use scratch buffer only when rx or tx data is unspecified */ | |
5a9a62bb | 154 | if (!xfer->rx_buf) { |
754ce4f2 HS |
155 | rx_dma = as->buffer_dma; |
156 | if (len > BUFFER_SIZE) | |
157 | len = BUFFER_SIZE; | |
158 | } | |
5a9a62bb | 159 | if (!xfer->tx_buf) { |
754ce4f2 HS |
160 | tx_dma = as->buffer_dma; |
161 | if (len > BUFFER_SIZE) | |
162 | len = BUFFER_SIZE; | |
163 | memset(as->buffer, 0, len); | |
164 | dma_sync_single_for_device(&as->pdev->dev, | |
165 | as->buffer_dma, len, DMA_TO_DEVICE); | |
166 | } | |
167 | ||
168 | spi_writel(as, RPR, rx_dma); | |
169 | spi_writel(as, TPR, tx_dma); | |
170 | ||
171 | as->remaining_bytes -= len; | |
172 | if (msg->spi->bits_per_word > 8) | |
173 | len >>= 1; | |
174 | ||
175 | /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer" | |
176 | * mechanism might help avoid the IRQ latency between transfers | |
defbd3b4 | 177 | * (and improve the nCS0 errata handling on at91rm9200 chips) |
754ce4f2 HS |
178 | * |
179 | * We're also waiting for ENDRX before we start the next | |
180 | * transfer because we need to handle some difficult timing | |
181 | * issues otherwise. If we wait for ENDTX in one transfer and | |
182 | * then starts waiting for ENDRX in the next, it's difficult | |
183 | * to tell the difference between the ENDRX interrupt we're | |
184 | * actually waiting for and the ENDRX interrupt of the | |
185 | * previous transfer. | |
186 | * | |
187 | * It should be doable, though. Just not now... | |
188 | */ | |
189 | spi_writel(as, TNCR, 0); | |
190 | spi_writel(as, RNCR, 0); | |
191 | spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES)); | |
192 | ||
193 | dev_dbg(&msg->spi->dev, | |
194 | " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n", | |
195 | xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, | |
196 | xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR)); | |
197 | ||
754ce4f2 | 198 | spi_writel(as, RCR, len); |
d84248bf | 199 | spi_writel(as, TCR, len); |
754ce4f2 HS |
200 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); |
201 | } | |
202 | ||
203 | static void atmel_spi_next_message(struct spi_master *master) | |
204 | { | |
205 | struct atmel_spi *as = spi_master_get_devdata(master); | |
206 | struct spi_message *msg; | |
defbd3b4 | 207 | struct spi_device *spi; |
754ce4f2 HS |
208 | |
209 | BUG_ON(as->current_transfer); | |
210 | ||
211 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
defbd3b4 | 212 | spi = msg->spi; |
754ce4f2 | 213 | |
49dce689 | 214 | dev_dbg(master->dev.parent, "start message %p for %s\n", |
defbd3b4 DB |
215 | msg, spi->dev.bus_id); |
216 | ||
217 | /* select chip if it's not still active */ | |
218 | if (as->stay) { | |
219 | if (as->stay != spi) { | |
220 | cs_deactivate(as, as->stay); | |
221 | cs_activate(as, spi); | |
222 | } | |
223 | as->stay = NULL; | |
224 | } else | |
225 | cs_activate(as, spi); | |
754ce4f2 HS |
226 | |
227 | atmel_spi_next_xfer(master, msg); | |
228 | } | |
229 | ||
8da0859a DB |
230 | /* |
231 | * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: | |
232 | * - The buffer is either valid for CPU access, else NULL | |
233 | * - If the buffer is valid, so is its DMA addresss | |
234 | * | |
235 | * This driver manages the dma addresss unless message->is_dma_mapped. | |
236 | */ | |
237 | static int | |
754ce4f2 HS |
238 | atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) |
239 | { | |
8da0859a DB |
240 | struct device *dev = &as->pdev->dev; |
241 | ||
754ce4f2 | 242 | xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; |
8da0859a DB |
243 | if (xfer->tx_buf) { |
244 | xfer->tx_dma = dma_map_single(dev, | |
754ce4f2 HS |
245 | (void *) xfer->tx_buf, xfer->len, |
246 | DMA_TO_DEVICE); | |
8da0859a DB |
247 | if (dma_mapping_error(xfer->tx_dma)) |
248 | return -ENOMEM; | |
249 | } | |
250 | if (xfer->rx_buf) { | |
251 | xfer->rx_dma = dma_map_single(dev, | |
754ce4f2 HS |
252 | xfer->rx_buf, xfer->len, |
253 | DMA_FROM_DEVICE); | |
85787a2b | 254 | if (dma_mapping_error(xfer->rx_dma)) { |
8da0859a DB |
255 | if (xfer->tx_buf) |
256 | dma_unmap_single(dev, | |
257 | xfer->tx_dma, xfer->len, | |
258 | DMA_TO_DEVICE); | |
259 | return -ENOMEM; | |
260 | } | |
261 | } | |
262 | return 0; | |
754ce4f2 HS |
263 | } |
264 | ||
265 | static void atmel_spi_dma_unmap_xfer(struct spi_master *master, | |
266 | struct spi_transfer *xfer) | |
267 | { | |
268 | if (xfer->tx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 269 | dma_unmap_single(master->dev.parent, xfer->tx_dma, |
754ce4f2 HS |
270 | xfer->len, DMA_TO_DEVICE); |
271 | if (xfer->rx_dma != INVALID_DMA_ADDRESS) | |
49dce689 | 272 | dma_unmap_single(master->dev.parent, xfer->rx_dma, |
754ce4f2 HS |
273 | xfer->len, DMA_FROM_DEVICE); |
274 | } | |
275 | ||
276 | static void | |
277 | atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as, | |
defbd3b4 | 278 | struct spi_message *msg, int status, int stay) |
754ce4f2 | 279 | { |
defbd3b4 DB |
280 | if (!stay || status < 0) |
281 | cs_deactivate(as, msg->spi); | |
282 | else | |
283 | as->stay = msg->spi; | |
284 | ||
754ce4f2 HS |
285 | list_del(&msg->queue); |
286 | msg->status = status; | |
287 | ||
49dce689 | 288 | dev_dbg(master->dev.parent, |
754ce4f2 HS |
289 | "xfer complete: %u bytes transferred\n", |
290 | msg->actual_length); | |
291 | ||
292 | spin_unlock(&as->lock); | |
293 | msg->complete(msg->context); | |
294 | spin_lock(&as->lock); | |
295 | ||
296 | as->current_transfer = NULL; | |
297 | ||
298 | /* continue if needed */ | |
299 | if (list_empty(&as->queue) || as->stopping) | |
300 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
301 | else | |
302 | atmel_spi_next_message(master); | |
303 | } | |
304 | ||
305 | static irqreturn_t | |
306 | atmel_spi_interrupt(int irq, void *dev_id) | |
307 | { | |
308 | struct spi_master *master = dev_id; | |
309 | struct atmel_spi *as = spi_master_get_devdata(master); | |
310 | struct spi_message *msg; | |
311 | struct spi_transfer *xfer; | |
312 | u32 status, pending, imr; | |
313 | int ret = IRQ_NONE; | |
314 | ||
315 | spin_lock(&as->lock); | |
316 | ||
317 | xfer = as->current_transfer; | |
318 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
319 | ||
320 | imr = spi_readl(as, IMR); | |
321 | status = spi_readl(as, SR); | |
322 | pending = status & imr; | |
323 | ||
324 | if (pending & SPI_BIT(OVRES)) { | |
325 | int timeout; | |
326 | ||
327 | ret = IRQ_HANDLED; | |
328 | ||
329 | spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX) | |
330 | | SPI_BIT(OVRES))); | |
331 | ||
332 | /* | |
333 | * When we get an overrun, we disregard the current | |
334 | * transfer. Data will not be copied back from any | |
335 | * bounce buffer and msg->actual_len will not be | |
336 | * updated with the last xfer. | |
337 | * | |
338 | * We will also not process any remaning transfers in | |
339 | * the message. | |
340 | * | |
341 | * First, stop the transfer and unmap the DMA buffers. | |
342 | */ | |
343 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
344 | if (!msg->is_dma_mapped) | |
345 | atmel_spi_dma_unmap_xfer(master, xfer); | |
346 | ||
347 | /* REVISIT: udelay in irq is unfriendly */ | |
348 | if (xfer->delay_usecs) | |
349 | udelay(xfer->delay_usecs); | |
350 | ||
49dce689 | 351 | dev_warn(master->dev.parent, "fifo overrun (%u/%u remaining)\n", |
754ce4f2 HS |
352 | spi_readl(as, TCR), spi_readl(as, RCR)); |
353 | ||
354 | /* | |
355 | * Clean up DMA registers and make sure the data | |
356 | * registers are empty. | |
357 | */ | |
358 | spi_writel(as, RNCR, 0); | |
359 | spi_writel(as, TNCR, 0); | |
360 | spi_writel(as, RCR, 0); | |
361 | spi_writel(as, TCR, 0); | |
362 | for (timeout = 1000; timeout; timeout--) | |
363 | if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) | |
364 | break; | |
365 | if (!timeout) | |
49dce689 | 366 | dev_warn(master->dev.parent, |
754ce4f2 HS |
367 | "timeout waiting for TXEMPTY"); |
368 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) | |
369 | spi_readl(as, RDR); | |
370 | ||
371 | /* Clear any overrun happening while cleaning up */ | |
372 | spi_readl(as, SR); | |
373 | ||
defbd3b4 | 374 | atmel_spi_msg_done(master, as, msg, -EIO, 0); |
754ce4f2 HS |
375 | } else if (pending & SPI_BIT(ENDRX)) { |
376 | ret = IRQ_HANDLED; | |
377 | ||
378 | spi_writel(as, IDR, pending); | |
379 | ||
380 | if (as->remaining_bytes == 0) { | |
381 | msg->actual_length += xfer->len; | |
382 | ||
383 | if (!msg->is_dma_mapped) | |
384 | atmel_spi_dma_unmap_xfer(master, xfer); | |
385 | ||
386 | /* REVISIT: udelay in irq is unfriendly */ | |
387 | if (xfer->delay_usecs) | |
388 | udelay(xfer->delay_usecs); | |
389 | ||
390 | if (msg->transfers.prev == &xfer->transfer_list) { | |
391 | /* report completed message */ | |
defbd3b4 DB |
392 | atmel_spi_msg_done(master, as, msg, 0, |
393 | xfer->cs_change); | |
754ce4f2 HS |
394 | } else { |
395 | if (xfer->cs_change) { | |
defbd3b4 | 396 | cs_deactivate(as, msg->spi); |
754ce4f2 | 397 | udelay(1); |
defbd3b4 | 398 | cs_activate(as, msg->spi); |
754ce4f2 HS |
399 | } |
400 | ||
401 | /* | |
402 | * Not done yet. Submit the next transfer. | |
403 | * | |
404 | * FIXME handle protocol options for xfer | |
405 | */ | |
406 | atmel_spi_next_xfer(master, msg); | |
407 | } | |
408 | } else { | |
409 | /* | |
410 | * Keep going, we still have data to send in | |
411 | * the current transfer. | |
412 | */ | |
413 | atmel_spi_next_xfer(master, msg); | |
414 | } | |
415 | } | |
416 | ||
417 | spin_unlock(&as->lock); | |
418 | ||
419 | return ret; | |
420 | } | |
421 | ||
dccd573b | 422 | /* the spi->mode bits understood by this driver: */ |
754ce4f2 HS |
423 | #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH) |
424 | ||
425 | static int atmel_spi_setup(struct spi_device *spi) | |
426 | { | |
427 | struct atmel_spi *as; | |
428 | u32 scbr, csr; | |
429 | unsigned int bits = spi->bits_per_word; | |
430 | unsigned long bus_hz, sck_hz; | |
431 | unsigned int npcs_pin; | |
432 | int ret; | |
433 | ||
434 | as = spi_master_get_devdata(spi->master); | |
435 | ||
436 | if (as->stopping) | |
437 | return -ESHUTDOWN; | |
438 | ||
439 | if (spi->chip_select > spi->master->num_chipselect) { | |
440 | dev_dbg(&spi->dev, | |
441 | "setup: invalid chipselect %u (%u defined)\n", | |
442 | spi->chip_select, spi->master->num_chipselect); | |
443 | return -EINVAL; | |
444 | } | |
445 | ||
446 | if (bits == 0) | |
447 | bits = 8; | |
448 | if (bits < 8 || bits > 16) { | |
449 | dev_dbg(&spi->dev, | |
450 | "setup: invalid bits_per_word %u (8 to 16)\n", | |
451 | bits); | |
452 | return -EINVAL; | |
453 | } | |
454 | ||
455 | if (spi->mode & ~MODEBITS) { | |
456 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
457 | spi->mode & ~MODEBITS); | |
458 | return -EINVAL; | |
459 | } | |
460 | ||
defbd3b4 DB |
461 | /* see notes above re chipselect */ |
462 | if (cpu_is_at91rm9200() | |
463 | && spi->chip_select == 0 | |
464 | && (spi->mode & SPI_CS_HIGH)) { | |
465 | dev_dbg(&spi->dev, "setup: can't be active-high\n"); | |
466 | return -EINVAL; | |
467 | } | |
468 | ||
754ce4f2 HS |
469 | /* speed zero convention is used by some upper layers */ |
470 | bus_hz = clk_get_rate(as->clk); | |
471 | if (spi->max_speed_hz) { | |
472 | /* assume div32/fdiv/mbz == 0 */ | |
473 | if (!as->new_1) | |
474 | bus_hz /= 2; | |
475 | scbr = ((bus_hz + spi->max_speed_hz - 1) | |
476 | / spi->max_speed_hz); | |
477 | if (scbr >= (1 << SPI_SCBR_SIZE)) { | |
8da0859a DB |
478 | dev_dbg(&spi->dev, |
479 | "setup: %d Hz too slow, scbr %u; min %ld Hz\n", | |
480 | spi->max_speed_hz, scbr, bus_hz/255); | |
754ce4f2 HS |
481 | return -EINVAL; |
482 | } | |
483 | } else | |
484 | scbr = 0xff; | |
485 | sck_hz = bus_hz / scbr; | |
486 | ||
487 | csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8); | |
488 | if (spi->mode & SPI_CPOL) | |
489 | csr |= SPI_BIT(CPOL); | |
490 | if (!(spi->mode & SPI_CPHA)) | |
491 | csr |= SPI_BIT(NCPHA); | |
492 | ||
1eed29df HS |
493 | /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. |
494 | * | |
495 | * DLYBCT would add delays between words, slowing down transfers. | |
496 | * It could potentially be useful to cope with DMA bottlenecks, but | |
497 | * in those cases it's probably best to just use a lower bitrate. | |
498 | */ | |
499 | csr |= SPI_BF(DLYBS, 0); | |
500 | csr |= SPI_BF(DLYBCT, 0); | |
754ce4f2 HS |
501 | |
502 | /* chipselect must have been muxed as GPIO (e.g. in board setup) */ | |
503 | npcs_pin = (unsigned int)spi->controller_data; | |
504 | if (!spi->controller_state) { | |
65f97a56 | 505 | ret = gpio_request(npcs_pin, spi->dev.bus_id); |
754ce4f2 HS |
506 | if (ret) |
507 | return ret; | |
508 | spi->controller_state = (void *)npcs_pin; | |
28735a72 | 509 | gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); |
defbd3b4 DB |
510 | } else { |
511 | unsigned long flags; | |
512 | ||
513 | spin_lock_irqsave(&as->lock, flags); | |
514 | if (as->stay == spi) | |
515 | as->stay = NULL; | |
516 | cs_deactivate(as, spi); | |
517 | spin_unlock_irqrestore(&as->lock, flags); | |
754ce4f2 HS |
518 | } |
519 | ||
520 | dev_dbg(&spi->dev, | |
521 | "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n", | |
522 | sck_hz, bits, spi->mode, spi->chip_select, csr); | |
523 | ||
524 | spi_writel(as, CSR0 + 4 * spi->chip_select, csr); | |
525 | ||
526 | return 0; | |
527 | } | |
528 | ||
529 | static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg) | |
530 | { | |
531 | struct atmel_spi *as; | |
532 | struct spi_transfer *xfer; | |
533 | unsigned long flags; | |
49dce689 | 534 | struct device *controller = spi->master->dev.parent; |
754ce4f2 HS |
535 | |
536 | as = spi_master_get_devdata(spi->master); | |
537 | ||
538 | dev_dbg(controller, "new message %p submitted for %s\n", | |
539 | msg, spi->dev.bus_id); | |
540 | ||
541 | if (unlikely(list_empty(&msg->transfers) | |
542 | || !spi->max_speed_hz)) | |
543 | return -EINVAL; | |
544 | ||
545 | if (as->stopping) | |
546 | return -ESHUTDOWN; | |
547 | ||
548 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
549 | if (!(xfer->tx_buf || xfer->rx_buf)) { | |
550 | dev_dbg(&spi->dev, "missing rx or tx buf\n"); | |
551 | return -EINVAL; | |
552 | } | |
553 | ||
554 | /* FIXME implement these protocol options!! */ | |
555 | if (xfer->bits_per_word || xfer->speed_hz) { | |
556 | dev_dbg(&spi->dev, "no protocol options yet\n"); | |
557 | return -ENOPROTOOPT; | |
558 | } | |
754ce4f2 | 559 | |
8da0859a DB |
560 | /* |
561 | * DMA map early, for performance (empties dcache ASAP) and | |
562 | * better fault reporting. This is a DMA-only driver. | |
563 | * | |
564 | * NOTE that if dma_unmap_single() ever starts to do work on | |
565 | * platforms supported by this driver, we would need to clean | |
566 | * up mappings for previously-mapped transfers. | |
567 | */ | |
568 | if (!msg->is_dma_mapped) { | |
569 | if (atmel_spi_dma_map_xfer(as, xfer) < 0) | |
570 | return -ENOMEM; | |
571 | } | |
754ce4f2 HS |
572 | } |
573 | ||
defbd3b4 | 574 | #ifdef VERBOSE |
754ce4f2 HS |
575 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
576 | dev_dbg(controller, | |
577 | " xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
578 | xfer, xfer->len, | |
579 | xfer->tx_buf, xfer->tx_dma, | |
580 | xfer->rx_buf, xfer->rx_dma); | |
581 | } | |
defbd3b4 | 582 | #endif |
754ce4f2 HS |
583 | |
584 | msg->status = -EINPROGRESS; | |
585 | msg->actual_length = 0; | |
586 | ||
587 | spin_lock_irqsave(&as->lock, flags); | |
588 | list_add_tail(&msg->queue, &as->queue); | |
589 | if (!as->current_transfer) | |
590 | atmel_spi_next_message(spi->master); | |
591 | spin_unlock_irqrestore(&as->lock, flags); | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
bb2d1c36 | 596 | static void atmel_spi_cleanup(struct spi_device *spi) |
754ce4f2 | 597 | { |
defbd3b4 DB |
598 | struct atmel_spi *as = spi_master_get_devdata(spi->master); |
599 | unsigned gpio = (unsigned) spi->controller_data; | |
600 | unsigned long flags; | |
601 | ||
602 | if (!spi->controller_state) | |
603 | return; | |
604 | ||
605 | spin_lock_irqsave(&as->lock, flags); | |
606 | if (as->stay == spi) { | |
607 | as->stay = NULL; | |
608 | cs_deactivate(as, spi); | |
609 | } | |
610 | spin_unlock_irqrestore(&as->lock, flags); | |
611 | ||
612 | gpio_free(gpio); | |
754ce4f2 HS |
613 | } |
614 | ||
615 | /*-------------------------------------------------------------------------*/ | |
616 | ||
617 | static int __init atmel_spi_probe(struct platform_device *pdev) | |
618 | { | |
619 | struct resource *regs; | |
620 | int irq; | |
621 | struct clk *clk; | |
622 | int ret; | |
623 | struct spi_master *master; | |
624 | struct atmel_spi *as; | |
625 | ||
626 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
627 | if (!regs) | |
628 | return -ENXIO; | |
629 | ||
630 | irq = platform_get_irq(pdev, 0); | |
631 | if (irq < 0) | |
632 | return irq; | |
633 | ||
634 | clk = clk_get(&pdev->dev, "spi_clk"); | |
635 | if (IS_ERR(clk)) | |
636 | return PTR_ERR(clk); | |
637 | ||
638 | /* setup spi core then atmel-specific driver state */ | |
639 | ret = -ENOMEM; | |
640 | master = spi_alloc_master(&pdev->dev, sizeof *as); | |
641 | if (!master) | |
642 | goto out_free; | |
643 | ||
644 | master->bus_num = pdev->id; | |
645 | master->num_chipselect = 4; | |
646 | master->setup = atmel_spi_setup; | |
647 | master->transfer = atmel_spi_transfer; | |
648 | master->cleanup = atmel_spi_cleanup; | |
649 | platform_set_drvdata(pdev, master); | |
650 | ||
651 | as = spi_master_get_devdata(master); | |
652 | ||
8da0859a DB |
653 | /* |
654 | * Scratch buffer is used for throwaway rx and tx data. | |
655 | * It's coherent to minimize dcache pollution. | |
656 | */ | |
754ce4f2 HS |
657 | as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE, |
658 | &as->buffer_dma, GFP_KERNEL); | |
659 | if (!as->buffer) | |
660 | goto out_free; | |
661 | ||
662 | spin_lock_init(&as->lock); | |
663 | INIT_LIST_HEAD(&as->queue); | |
664 | as->pdev = pdev; | |
665 | as->regs = ioremap(regs->start, (regs->end - regs->start) + 1); | |
666 | if (!as->regs) | |
667 | goto out_free_buffer; | |
668 | as->irq = irq; | |
669 | as->clk = clk; | |
754ce4f2 HS |
670 | if (!cpu_is_at91rm9200()) |
671 | as->new_1 = 1; | |
754ce4f2 HS |
672 | |
673 | ret = request_irq(irq, atmel_spi_interrupt, 0, | |
674 | pdev->dev.bus_id, master); | |
675 | if (ret) | |
676 | goto out_unmap_regs; | |
677 | ||
678 | /* Initialize the hardware */ | |
679 | clk_enable(clk); | |
680 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
681 | spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); | |
682 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
683 | spi_writel(as, CR, SPI_BIT(SPIEN)); | |
684 | ||
685 | /* go! */ | |
686 | dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", | |
687 | (unsigned long)regs->start, irq); | |
688 | ||
689 | ret = spi_register_master(master); | |
690 | if (ret) | |
691 | goto out_reset_hw; | |
692 | ||
693 | return 0; | |
694 | ||
695 | out_reset_hw: | |
696 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
697 | clk_disable(clk); | |
698 | free_irq(irq, master); | |
699 | out_unmap_regs: | |
700 | iounmap(as->regs); | |
701 | out_free_buffer: | |
702 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
703 | as->buffer_dma); | |
704 | out_free: | |
705 | clk_put(clk); | |
706 | spi_master_put(master); | |
707 | return ret; | |
708 | } | |
709 | ||
710 | static int __exit atmel_spi_remove(struct platform_device *pdev) | |
711 | { | |
712 | struct spi_master *master = platform_get_drvdata(pdev); | |
713 | struct atmel_spi *as = spi_master_get_devdata(master); | |
714 | struct spi_message *msg; | |
715 | ||
716 | /* reset the hardware and block queue progress */ | |
717 | spin_lock_irq(&as->lock); | |
718 | as->stopping = 1; | |
719 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
720 | spi_readl(as, SR); | |
721 | spin_unlock_irq(&as->lock); | |
722 | ||
723 | /* Terminate remaining queued transfers */ | |
724 | list_for_each_entry(msg, &as->queue, queue) { | |
725 | /* REVISIT unmapping the dma is a NOP on ARM and AVR32 | |
726 | * but we shouldn't depend on that... | |
727 | */ | |
728 | msg->status = -ESHUTDOWN; | |
729 | msg->complete(msg->context); | |
730 | } | |
731 | ||
732 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
733 | as->buffer_dma); | |
734 | ||
735 | clk_disable(as->clk); | |
736 | clk_put(as->clk); | |
737 | free_irq(as->irq, master); | |
738 | iounmap(as->regs); | |
739 | ||
740 | spi_unregister_master(master); | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
745 | #ifdef CONFIG_PM | |
746 | ||
747 | static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg) | |
748 | { | |
749 | struct spi_master *master = platform_get_drvdata(pdev); | |
750 | struct atmel_spi *as = spi_master_get_devdata(master); | |
751 | ||
752 | clk_disable(as->clk); | |
753 | return 0; | |
754 | } | |
755 | ||
756 | static int atmel_spi_resume(struct platform_device *pdev) | |
757 | { | |
758 | struct spi_master *master = platform_get_drvdata(pdev); | |
759 | struct atmel_spi *as = spi_master_get_devdata(master); | |
760 | ||
761 | clk_enable(as->clk); | |
762 | return 0; | |
763 | } | |
764 | ||
765 | #else | |
766 | #define atmel_spi_suspend NULL | |
767 | #define atmel_spi_resume NULL | |
768 | #endif | |
769 | ||
770 | ||
771 | static struct platform_driver atmel_spi_driver = { | |
772 | .driver = { | |
773 | .name = "atmel_spi", | |
774 | .owner = THIS_MODULE, | |
775 | }, | |
776 | .suspend = atmel_spi_suspend, | |
777 | .resume = atmel_spi_resume, | |
778 | .remove = __exit_p(atmel_spi_remove), | |
779 | }; | |
780 | ||
781 | static int __init atmel_spi_init(void) | |
782 | { | |
783 | return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe); | |
784 | } | |
785 | module_init(atmel_spi_init); | |
786 | ||
787 | static void __exit atmel_spi_exit(void) | |
788 | { | |
789 | platform_driver_unregister(&atmel_spi_driver); | |
790 | } | |
791 | module_exit(atmel_spi_exit); | |
792 | ||
793 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); | |
794 | MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>"); | |
795 | MODULE_LICENSE("GPL"); |