Commit | Line | Data |
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754ce4f2 HS |
1 | /* |
2 | * Driver for Atmel AT32 and AT91 SPI Controllers | |
3 | * | |
4 | * Copyright (C) 2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/spi/spi.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | #include <asm/arch/board.h> | |
24 | #include <asm/arch/gpio.h> | |
bb2d1c36 | 25 | #include <asm/arch/cpu.h> |
bb2d1c36 | 26 | |
754ce4f2 HS |
27 | #include "atmel_spi.h" |
28 | ||
29 | /* | |
30 | * The core SPI transfer engine just talks to a register bank to set up | |
31 | * DMA transfers; transfer queue progress is driven by IRQs. The clock | |
32 | * framework provides the base clock, subdivided for each spi_device. | |
33 | * | |
34 | * Newer controllers, marked with "new_1" flag, have: | |
35 | * - CR.LASTXFER | |
36 | * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) | |
37 | * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) | |
38 | * - SPI_CSRx.CSAAT | |
39 | * - SPI_CSRx.SBCR allows faster clocking | |
40 | */ | |
41 | struct atmel_spi { | |
42 | spinlock_t lock; | |
43 | ||
44 | void __iomem *regs; | |
45 | int irq; | |
46 | struct clk *clk; | |
47 | struct platform_device *pdev; | |
48 | unsigned new_1:1; | |
49 | ||
50 | u8 stopping; | |
51 | struct list_head queue; | |
52 | struct spi_transfer *current_transfer; | |
53 | unsigned long remaining_bytes; | |
54 | ||
55 | void *buffer; | |
56 | dma_addr_t buffer_dma; | |
57 | }; | |
58 | ||
59 | #define BUFFER_SIZE PAGE_SIZE | |
60 | #define INVALID_DMA_ADDRESS 0xffffffff | |
61 | ||
62 | /* | |
63 | * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby | |
64 | * they assume that spi slave device state will not change on deselect, so | |
65 | * that automagic deselection is OK. Not so! Workaround uses nCSx pins | |
66 | * as GPIOs; or newer controllers have CSAAT and friends. | |
67 | * | |
68 | * Since the CSAAT functionality is a bit weird on newer controllers | |
69 | * as well, we use GPIO to control nCSx pins on all controllers. | |
70 | */ | |
71 | ||
72 | static inline void cs_activate(struct spi_device *spi) | |
73 | { | |
74 | unsigned gpio = (unsigned) spi->controller_data; | |
75 | unsigned active = spi->mode & SPI_CS_HIGH; | |
76 | ||
77 | dev_dbg(&spi->dev, "activate %u%s\n", gpio, active ? " (high)" : ""); | |
78 | gpio_set_value(gpio, active); | |
79 | } | |
80 | ||
81 | static inline void cs_deactivate(struct spi_device *spi) | |
82 | { | |
83 | unsigned gpio = (unsigned) spi->controller_data; | |
84 | unsigned active = spi->mode & SPI_CS_HIGH; | |
85 | ||
86 | dev_dbg(&spi->dev, "DEactivate %u%s\n", gpio, active ? " (low)" : ""); | |
87 | gpio_set_value(gpio, !active); | |
88 | } | |
89 | ||
90 | /* | |
91 | * Submit next transfer for DMA. | |
92 | * lock is held, spi irq is blocked | |
93 | */ | |
94 | static void atmel_spi_next_xfer(struct spi_master *master, | |
95 | struct spi_message *msg) | |
96 | { | |
97 | struct atmel_spi *as = spi_master_get_devdata(master); | |
98 | struct spi_transfer *xfer; | |
99 | u32 len; | |
100 | dma_addr_t tx_dma, rx_dma; | |
101 | ||
102 | xfer = as->current_transfer; | |
103 | if (!xfer || as->remaining_bytes == 0) { | |
104 | if (xfer) | |
105 | xfer = list_entry(xfer->transfer_list.next, | |
106 | struct spi_transfer, transfer_list); | |
107 | else | |
108 | xfer = list_entry(msg->transfers.next, | |
109 | struct spi_transfer, transfer_list); | |
110 | as->remaining_bytes = xfer->len; | |
111 | as->current_transfer = xfer; | |
112 | } | |
113 | ||
114 | len = as->remaining_bytes; | |
115 | ||
5a9a62bb HS |
116 | tx_dma = xfer->tx_dma + xfer->len - len; |
117 | rx_dma = xfer->rx_dma + xfer->len - len; | |
754ce4f2 HS |
118 | |
119 | /* use scratch buffer only when rx or tx data is unspecified */ | |
5a9a62bb | 120 | if (!xfer->rx_buf) { |
754ce4f2 HS |
121 | rx_dma = as->buffer_dma; |
122 | if (len > BUFFER_SIZE) | |
123 | len = BUFFER_SIZE; | |
124 | } | |
5a9a62bb | 125 | if (!xfer->tx_buf) { |
754ce4f2 HS |
126 | tx_dma = as->buffer_dma; |
127 | if (len > BUFFER_SIZE) | |
128 | len = BUFFER_SIZE; | |
129 | memset(as->buffer, 0, len); | |
130 | dma_sync_single_for_device(&as->pdev->dev, | |
131 | as->buffer_dma, len, DMA_TO_DEVICE); | |
132 | } | |
133 | ||
134 | spi_writel(as, RPR, rx_dma); | |
135 | spi_writel(as, TPR, tx_dma); | |
136 | ||
137 | as->remaining_bytes -= len; | |
138 | if (msg->spi->bits_per_word > 8) | |
139 | len >>= 1; | |
140 | ||
141 | /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer" | |
142 | * mechanism might help avoid the IRQ latency between transfers | |
143 | * | |
144 | * We're also waiting for ENDRX before we start the next | |
145 | * transfer because we need to handle some difficult timing | |
146 | * issues otherwise. If we wait for ENDTX in one transfer and | |
147 | * then starts waiting for ENDRX in the next, it's difficult | |
148 | * to tell the difference between the ENDRX interrupt we're | |
149 | * actually waiting for and the ENDRX interrupt of the | |
150 | * previous transfer. | |
151 | * | |
152 | * It should be doable, though. Just not now... | |
153 | */ | |
154 | spi_writel(as, TNCR, 0); | |
155 | spi_writel(as, RNCR, 0); | |
156 | spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES)); | |
157 | ||
158 | dev_dbg(&msg->spi->dev, | |
159 | " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n", | |
160 | xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, | |
161 | xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR)); | |
162 | ||
163 | spi_writel(as, TCR, len); | |
164 | spi_writel(as, RCR, len); | |
165 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); | |
166 | } | |
167 | ||
168 | static void atmel_spi_next_message(struct spi_master *master) | |
169 | { | |
170 | struct atmel_spi *as = spi_master_get_devdata(master); | |
171 | struct spi_message *msg; | |
172 | u32 mr; | |
173 | ||
174 | BUG_ON(as->current_transfer); | |
175 | ||
176 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
177 | ||
178 | /* Select the chip */ | |
179 | mr = spi_readl(as, MR); | |
180 | mr = SPI_BFINS(PCS, ~(1 << msg->spi->chip_select), mr); | |
181 | spi_writel(as, MR, mr); | |
182 | cs_activate(msg->spi); | |
183 | ||
184 | atmel_spi_next_xfer(master, msg); | |
185 | } | |
186 | ||
187 | static void | |
188 | atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) | |
189 | { | |
190 | xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; | |
191 | if (xfer->tx_buf) | |
192 | xfer->tx_dma = dma_map_single(&as->pdev->dev, | |
193 | (void *) xfer->tx_buf, xfer->len, | |
194 | DMA_TO_DEVICE); | |
195 | if (xfer->rx_buf) | |
196 | xfer->rx_dma = dma_map_single(&as->pdev->dev, | |
197 | xfer->rx_buf, xfer->len, | |
198 | DMA_FROM_DEVICE); | |
199 | } | |
200 | ||
201 | static void atmel_spi_dma_unmap_xfer(struct spi_master *master, | |
202 | struct spi_transfer *xfer) | |
203 | { | |
204 | if (xfer->tx_dma != INVALID_DMA_ADDRESS) | |
205 | dma_unmap_single(master->cdev.dev, xfer->tx_dma, | |
206 | xfer->len, DMA_TO_DEVICE); | |
207 | if (xfer->rx_dma != INVALID_DMA_ADDRESS) | |
208 | dma_unmap_single(master->cdev.dev, xfer->rx_dma, | |
209 | xfer->len, DMA_FROM_DEVICE); | |
210 | } | |
211 | ||
212 | static void | |
213 | atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as, | |
214 | struct spi_message *msg, int status) | |
215 | { | |
216 | cs_deactivate(msg->spi); | |
217 | list_del(&msg->queue); | |
218 | msg->status = status; | |
219 | ||
220 | dev_dbg(master->cdev.dev, | |
221 | "xfer complete: %u bytes transferred\n", | |
222 | msg->actual_length); | |
223 | ||
224 | spin_unlock(&as->lock); | |
225 | msg->complete(msg->context); | |
226 | spin_lock(&as->lock); | |
227 | ||
228 | as->current_transfer = NULL; | |
229 | ||
230 | /* continue if needed */ | |
231 | if (list_empty(&as->queue) || as->stopping) | |
232 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
233 | else | |
234 | atmel_spi_next_message(master); | |
235 | } | |
236 | ||
237 | static irqreturn_t | |
238 | atmel_spi_interrupt(int irq, void *dev_id) | |
239 | { | |
240 | struct spi_master *master = dev_id; | |
241 | struct atmel_spi *as = spi_master_get_devdata(master); | |
242 | struct spi_message *msg; | |
243 | struct spi_transfer *xfer; | |
244 | u32 status, pending, imr; | |
245 | int ret = IRQ_NONE; | |
246 | ||
247 | spin_lock(&as->lock); | |
248 | ||
249 | xfer = as->current_transfer; | |
250 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
251 | ||
252 | imr = spi_readl(as, IMR); | |
253 | status = spi_readl(as, SR); | |
254 | pending = status & imr; | |
255 | ||
256 | if (pending & SPI_BIT(OVRES)) { | |
257 | int timeout; | |
258 | ||
259 | ret = IRQ_HANDLED; | |
260 | ||
261 | spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX) | |
262 | | SPI_BIT(OVRES))); | |
263 | ||
264 | /* | |
265 | * When we get an overrun, we disregard the current | |
266 | * transfer. Data will not be copied back from any | |
267 | * bounce buffer and msg->actual_len will not be | |
268 | * updated with the last xfer. | |
269 | * | |
270 | * We will also not process any remaning transfers in | |
271 | * the message. | |
272 | * | |
273 | * First, stop the transfer and unmap the DMA buffers. | |
274 | */ | |
275 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
276 | if (!msg->is_dma_mapped) | |
277 | atmel_spi_dma_unmap_xfer(master, xfer); | |
278 | ||
279 | /* REVISIT: udelay in irq is unfriendly */ | |
280 | if (xfer->delay_usecs) | |
281 | udelay(xfer->delay_usecs); | |
282 | ||
283 | dev_warn(master->cdev.dev, "fifo overrun (%u/%u remaining)\n", | |
284 | spi_readl(as, TCR), spi_readl(as, RCR)); | |
285 | ||
286 | /* | |
287 | * Clean up DMA registers and make sure the data | |
288 | * registers are empty. | |
289 | */ | |
290 | spi_writel(as, RNCR, 0); | |
291 | spi_writel(as, TNCR, 0); | |
292 | spi_writel(as, RCR, 0); | |
293 | spi_writel(as, TCR, 0); | |
294 | for (timeout = 1000; timeout; timeout--) | |
295 | if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) | |
296 | break; | |
297 | if (!timeout) | |
298 | dev_warn(master->cdev.dev, | |
299 | "timeout waiting for TXEMPTY"); | |
300 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) | |
301 | spi_readl(as, RDR); | |
302 | ||
303 | /* Clear any overrun happening while cleaning up */ | |
304 | spi_readl(as, SR); | |
305 | ||
306 | atmel_spi_msg_done(master, as, msg, -EIO); | |
307 | } else if (pending & SPI_BIT(ENDRX)) { | |
308 | ret = IRQ_HANDLED; | |
309 | ||
310 | spi_writel(as, IDR, pending); | |
311 | ||
312 | if (as->remaining_bytes == 0) { | |
313 | msg->actual_length += xfer->len; | |
314 | ||
315 | if (!msg->is_dma_mapped) | |
316 | atmel_spi_dma_unmap_xfer(master, xfer); | |
317 | ||
318 | /* REVISIT: udelay in irq is unfriendly */ | |
319 | if (xfer->delay_usecs) | |
320 | udelay(xfer->delay_usecs); | |
321 | ||
322 | if (msg->transfers.prev == &xfer->transfer_list) { | |
323 | /* report completed message */ | |
324 | atmel_spi_msg_done(master, as, msg, 0); | |
325 | } else { | |
326 | if (xfer->cs_change) { | |
327 | cs_deactivate(msg->spi); | |
328 | udelay(1); | |
329 | cs_activate(msg->spi); | |
330 | } | |
331 | ||
332 | /* | |
333 | * Not done yet. Submit the next transfer. | |
334 | * | |
335 | * FIXME handle protocol options for xfer | |
336 | */ | |
337 | atmel_spi_next_xfer(master, msg); | |
338 | } | |
339 | } else { | |
340 | /* | |
341 | * Keep going, we still have data to send in | |
342 | * the current transfer. | |
343 | */ | |
344 | atmel_spi_next_xfer(master, msg); | |
345 | } | |
346 | } | |
347 | ||
348 | spin_unlock(&as->lock); | |
349 | ||
350 | return ret; | |
351 | } | |
352 | ||
dccd573b | 353 | /* the spi->mode bits understood by this driver: */ |
754ce4f2 HS |
354 | #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH) |
355 | ||
356 | static int atmel_spi_setup(struct spi_device *spi) | |
357 | { | |
358 | struct atmel_spi *as; | |
359 | u32 scbr, csr; | |
360 | unsigned int bits = spi->bits_per_word; | |
361 | unsigned long bus_hz, sck_hz; | |
362 | unsigned int npcs_pin; | |
363 | int ret; | |
364 | ||
365 | as = spi_master_get_devdata(spi->master); | |
366 | ||
367 | if (as->stopping) | |
368 | return -ESHUTDOWN; | |
369 | ||
370 | if (spi->chip_select > spi->master->num_chipselect) { | |
371 | dev_dbg(&spi->dev, | |
372 | "setup: invalid chipselect %u (%u defined)\n", | |
373 | spi->chip_select, spi->master->num_chipselect); | |
374 | return -EINVAL; | |
375 | } | |
376 | ||
377 | if (bits == 0) | |
378 | bits = 8; | |
379 | if (bits < 8 || bits > 16) { | |
380 | dev_dbg(&spi->dev, | |
381 | "setup: invalid bits_per_word %u (8 to 16)\n", | |
382 | bits); | |
383 | return -EINVAL; | |
384 | } | |
385 | ||
386 | if (spi->mode & ~MODEBITS) { | |
387 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
388 | spi->mode & ~MODEBITS); | |
389 | return -EINVAL; | |
390 | } | |
391 | ||
392 | /* speed zero convention is used by some upper layers */ | |
393 | bus_hz = clk_get_rate(as->clk); | |
394 | if (spi->max_speed_hz) { | |
395 | /* assume div32/fdiv/mbz == 0 */ | |
396 | if (!as->new_1) | |
397 | bus_hz /= 2; | |
398 | scbr = ((bus_hz + spi->max_speed_hz - 1) | |
399 | / spi->max_speed_hz); | |
400 | if (scbr >= (1 << SPI_SCBR_SIZE)) { | |
401 | dev_dbg(&spi->dev, "setup: %d Hz too slow, scbr %u\n", | |
402 | spi->max_speed_hz, scbr); | |
403 | return -EINVAL; | |
404 | } | |
405 | } else | |
406 | scbr = 0xff; | |
407 | sck_hz = bus_hz / scbr; | |
408 | ||
409 | csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8); | |
410 | if (spi->mode & SPI_CPOL) | |
411 | csr |= SPI_BIT(CPOL); | |
412 | if (!(spi->mode & SPI_CPHA)) | |
413 | csr |= SPI_BIT(NCPHA); | |
414 | ||
415 | /* TODO: DLYBS and DLYBCT */ | |
416 | csr |= SPI_BF(DLYBS, 10); | |
417 | csr |= SPI_BF(DLYBCT, 10); | |
418 | ||
419 | /* chipselect must have been muxed as GPIO (e.g. in board setup) */ | |
420 | npcs_pin = (unsigned int)spi->controller_data; | |
421 | if (!spi->controller_state) { | |
422 | ret = gpio_request(npcs_pin, "spi_npcs"); | |
423 | if (ret) | |
424 | return ret; | |
425 | spi->controller_state = (void *)npcs_pin; | |
28735a72 | 426 | gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); |
754ce4f2 HS |
427 | } |
428 | ||
429 | dev_dbg(&spi->dev, | |
430 | "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n", | |
431 | sck_hz, bits, spi->mode, spi->chip_select, csr); | |
432 | ||
433 | spi_writel(as, CSR0 + 4 * spi->chip_select, csr); | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
438 | static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg) | |
439 | { | |
440 | struct atmel_spi *as; | |
441 | struct spi_transfer *xfer; | |
442 | unsigned long flags; | |
443 | struct device *controller = spi->master->cdev.dev; | |
444 | ||
445 | as = spi_master_get_devdata(spi->master); | |
446 | ||
447 | dev_dbg(controller, "new message %p submitted for %s\n", | |
448 | msg, spi->dev.bus_id); | |
449 | ||
450 | if (unlikely(list_empty(&msg->transfers) | |
451 | || !spi->max_speed_hz)) | |
452 | return -EINVAL; | |
453 | ||
454 | if (as->stopping) | |
455 | return -ESHUTDOWN; | |
456 | ||
457 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
458 | if (!(xfer->tx_buf || xfer->rx_buf)) { | |
459 | dev_dbg(&spi->dev, "missing rx or tx buf\n"); | |
460 | return -EINVAL; | |
461 | } | |
462 | ||
463 | /* FIXME implement these protocol options!! */ | |
464 | if (xfer->bits_per_word || xfer->speed_hz) { | |
465 | dev_dbg(&spi->dev, "no protocol options yet\n"); | |
466 | return -ENOPROTOOPT; | |
467 | } | |
468 | } | |
469 | ||
470 | /* scrub dcache "early" */ | |
471 | if (!msg->is_dma_mapped) { | |
472 | list_for_each_entry(xfer, &msg->transfers, transfer_list) | |
473 | atmel_spi_dma_map_xfer(as, xfer); | |
474 | } | |
475 | ||
476 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
477 | dev_dbg(controller, | |
478 | " xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
479 | xfer, xfer->len, | |
480 | xfer->tx_buf, xfer->tx_dma, | |
481 | xfer->rx_buf, xfer->rx_dma); | |
482 | } | |
483 | ||
484 | msg->status = -EINPROGRESS; | |
485 | msg->actual_length = 0; | |
486 | ||
487 | spin_lock_irqsave(&as->lock, flags); | |
488 | list_add_tail(&msg->queue, &as->queue); | |
489 | if (!as->current_transfer) | |
490 | atmel_spi_next_message(spi->master); | |
491 | spin_unlock_irqrestore(&as->lock, flags); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
bb2d1c36 | 496 | static void atmel_spi_cleanup(struct spi_device *spi) |
754ce4f2 HS |
497 | { |
498 | if (spi->controller_state) | |
499 | gpio_free((unsigned int)spi->controller_data); | |
500 | } | |
501 | ||
502 | /*-------------------------------------------------------------------------*/ | |
503 | ||
504 | static int __init atmel_spi_probe(struct platform_device *pdev) | |
505 | { | |
506 | struct resource *regs; | |
507 | int irq; | |
508 | struct clk *clk; | |
509 | int ret; | |
510 | struct spi_master *master; | |
511 | struct atmel_spi *as; | |
512 | ||
513 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
514 | if (!regs) | |
515 | return -ENXIO; | |
516 | ||
517 | irq = platform_get_irq(pdev, 0); | |
518 | if (irq < 0) | |
519 | return irq; | |
520 | ||
521 | clk = clk_get(&pdev->dev, "spi_clk"); | |
522 | if (IS_ERR(clk)) | |
523 | return PTR_ERR(clk); | |
524 | ||
525 | /* setup spi core then atmel-specific driver state */ | |
526 | ret = -ENOMEM; | |
527 | master = spi_alloc_master(&pdev->dev, sizeof *as); | |
528 | if (!master) | |
529 | goto out_free; | |
530 | ||
531 | master->bus_num = pdev->id; | |
532 | master->num_chipselect = 4; | |
533 | master->setup = atmel_spi_setup; | |
534 | master->transfer = atmel_spi_transfer; | |
535 | master->cleanup = atmel_spi_cleanup; | |
536 | platform_set_drvdata(pdev, master); | |
537 | ||
538 | as = spi_master_get_devdata(master); | |
539 | ||
540 | as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE, | |
541 | &as->buffer_dma, GFP_KERNEL); | |
542 | if (!as->buffer) | |
543 | goto out_free; | |
544 | ||
545 | spin_lock_init(&as->lock); | |
546 | INIT_LIST_HEAD(&as->queue); | |
547 | as->pdev = pdev; | |
548 | as->regs = ioremap(regs->start, (regs->end - regs->start) + 1); | |
549 | if (!as->regs) | |
550 | goto out_free_buffer; | |
551 | as->irq = irq; | |
552 | as->clk = clk; | |
754ce4f2 HS |
553 | if (!cpu_is_at91rm9200()) |
554 | as->new_1 = 1; | |
754ce4f2 HS |
555 | |
556 | ret = request_irq(irq, atmel_spi_interrupt, 0, | |
557 | pdev->dev.bus_id, master); | |
558 | if (ret) | |
559 | goto out_unmap_regs; | |
560 | ||
561 | /* Initialize the hardware */ | |
562 | clk_enable(clk); | |
563 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
564 | spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); | |
565 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
566 | spi_writel(as, CR, SPI_BIT(SPIEN)); | |
567 | ||
568 | /* go! */ | |
569 | dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", | |
570 | (unsigned long)regs->start, irq); | |
571 | ||
572 | ret = spi_register_master(master); | |
573 | if (ret) | |
574 | goto out_reset_hw; | |
575 | ||
576 | return 0; | |
577 | ||
578 | out_reset_hw: | |
579 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
580 | clk_disable(clk); | |
581 | free_irq(irq, master); | |
582 | out_unmap_regs: | |
583 | iounmap(as->regs); | |
584 | out_free_buffer: | |
585 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
586 | as->buffer_dma); | |
587 | out_free: | |
588 | clk_put(clk); | |
589 | spi_master_put(master); | |
590 | return ret; | |
591 | } | |
592 | ||
593 | static int __exit atmel_spi_remove(struct platform_device *pdev) | |
594 | { | |
595 | struct spi_master *master = platform_get_drvdata(pdev); | |
596 | struct atmel_spi *as = spi_master_get_devdata(master); | |
597 | struct spi_message *msg; | |
598 | ||
599 | /* reset the hardware and block queue progress */ | |
600 | spin_lock_irq(&as->lock); | |
601 | as->stopping = 1; | |
602 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
603 | spi_readl(as, SR); | |
604 | spin_unlock_irq(&as->lock); | |
605 | ||
606 | /* Terminate remaining queued transfers */ | |
607 | list_for_each_entry(msg, &as->queue, queue) { | |
608 | /* REVISIT unmapping the dma is a NOP on ARM and AVR32 | |
609 | * but we shouldn't depend on that... | |
610 | */ | |
611 | msg->status = -ESHUTDOWN; | |
612 | msg->complete(msg->context); | |
613 | } | |
614 | ||
615 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
616 | as->buffer_dma); | |
617 | ||
618 | clk_disable(as->clk); | |
619 | clk_put(as->clk); | |
620 | free_irq(as->irq, master); | |
621 | iounmap(as->regs); | |
622 | ||
623 | spi_unregister_master(master); | |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
628 | #ifdef CONFIG_PM | |
629 | ||
630 | static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg) | |
631 | { | |
632 | struct spi_master *master = platform_get_drvdata(pdev); | |
633 | struct atmel_spi *as = spi_master_get_devdata(master); | |
634 | ||
635 | clk_disable(as->clk); | |
636 | return 0; | |
637 | } | |
638 | ||
639 | static int atmel_spi_resume(struct platform_device *pdev) | |
640 | { | |
641 | struct spi_master *master = platform_get_drvdata(pdev); | |
642 | struct atmel_spi *as = spi_master_get_devdata(master); | |
643 | ||
644 | clk_enable(as->clk); | |
645 | return 0; | |
646 | } | |
647 | ||
648 | #else | |
649 | #define atmel_spi_suspend NULL | |
650 | #define atmel_spi_resume NULL | |
651 | #endif | |
652 | ||
653 | ||
654 | static struct platform_driver atmel_spi_driver = { | |
655 | .driver = { | |
656 | .name = "atmel_spi", | |
657 | .owner = THIS_MODULE, | |
658 | }, | |
659 | .suspend = atmel_spi_suspend, | |
660 | .resume = atmel_spi_resume, | |
661 | .remove = __exit_p(atmel_spi_remove), | |
662 | }; | |
663 | ||
664 | static int __init atmel_spi_init(void) | |
665 | { | |
666 | return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe); | |
667 | } | |
668 | module_init(atmel_spi_init); | |
669 | ||
670 | static void __exit atmel_spi_exit(void) | |
671 | { | |
672 | platform_driver_unregister(&atmel_spi_driver); | |
673 | } | |
674 | module_exit(atmel_spi_exit); | |
675 | ||
676 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); | |
677 | MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>"); | |
678 | MODULE_LICENSE("GPL"); |