Commit | Line | Data |
---|---|---|
63bd2359 JN |
1 | /* |
2 | * au1550_spi.c - au1550 psc spi controller driver | |
3 | * may work also with au1200, au1210, au1250 | |
4 | * will not work on au1000, au1100 and au1500 (no full spi controller there) | |
5 | * | |
6 | * Copyright (c) 2006 ATRON electronic GmbH | |
7 | * Author: Jan Nikitenko <jan.nikitenko@gmail.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/device.h> | |
28 | #include <linux/platform_device.h> | |
3a93a159 | 29 | #include <linux/resource.h> |
63bd2359 JN |
30 | #include <linux/spi/spi.h> |
31 | #include <linux/spi/spi_bitbang.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/completion.h> | |
34 | #include <asm/mach-au1x00/au1000.h> | |
35 | #include <asm/mach-au1x00/au1xxx_psc.h> | |
36 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
37 | ||
38 | #include <asm/mach-au1x00/au1550_spi.h> | |
39 | ||
40 | static unsigned usedma = 1; | |
41 | module_param(usedma, uint, 0644); | |
42 | ||
43 | /* | |
44 | #define AU1550_SPI_DEBUG_LOOPBACK | |
45 | */ | |
46 | ||
47 | ||
48 | #define AU1550_SPI_DBDMA_DESCRIPTORS 1 | |
49 | #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U | |
50 | ||
51 | struct au1550_spi { | |
52 | struct spi_bitbang bitbang; | |
53 | ||
54 | volatile psc_spi_t __iomem *regs; | |
55 | int irq; | |
56 | unsigned freq_max; | |
57 | unsigned freq_min; | |
58 | ||
59 | unsigned len; | |
60 | unsigned tx_count; | |
61 | unsigned rx_count; | |
62 | const u8 *tx; | |
63 | u8 *rx; | |
64 | ||
65 | void (*rx_word)(struct au1550_spi *hw); | |
66 | void (*tx_word)(struct au1550_spi *hw); | |
67 | int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t); | |
68 | irqreturn_t (*irq_callback)(struct au1550_spi *hw); | |
69 | ||
70 | struct completion master_done; | |
71 | ||
72 | unsigned usedma; | |
73 | u32 dma_tx_id; | |
74 | u32 dma_rx_id; | |
75 | u32 dma_tx_ch; | |
76 | u32 dma_rx_ch; | |
77 | ||
78 | u8 *dma_rx_tmpbuf; | |
79 | unsigned dma_rx_tmpbuf_size; | |
80 | u32 dma_rx_tmpbuf_addr; | |
81 | ||
82 | struct spi_master *master; | |
83 | struct device *dev; | |
84 | struct au1550_spi_info *pdata; | |
3a93a159 | 85 | struct resource *ioarea; |
63bd2359 JN |
86 | }; |
87 | ||
88 | ||
89 | /* we use an 8-bit memory device for dma transfers to/from spi fifo */ | |
90 | static dbdev_tab_t au1550_spi_mem_dbdev = | |
91 | { | |
92 | .dev_id = DBDMA_MEM_CHAN, | |
93 | .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC, | |
94 | .dev_tsize = 0, | |
95 | .dev_devwidth = 8, | |
96 | .dev_physaddr = 0x00000000, | |
97 | .dev_intlevel = 0, | |
98 | .dev_intpolarity = 0 | |
99 | }; | |
100 | ||
3a93a159 ML |
101 | static int ddma_memid; /* id to above mem dma device */ |
102 | ||
63bd2359 JN |
103 | static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw); |
104 | ||
105 | ||
40369e1c | 106 | /* |
63bd2359 JN |
107 | * compute BRG and DIV bits to setup spi clock based on main input clock rate |
108 | * that was specified in platform data structure | |
109 | * according to au1550 datasheet: | |
110 | * psc_tempclk = psc_mainclk / (2 << DIV) | |
111 | * spiclk = psc_tempclk / (2 * (BRG + 1)) | |
112 | * BRG valid range is 4..63 | |
113 | * DIV valid range is 0..3 | |
114 | */ | |
115 | static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz) | |
116 | { | |
117 | u32 mainclk_hz = hw->pdata->mainclk_hz; | |
118 | u32 div, brg; | |
119 | ||
120 | for (div = 0; div < 4; div++) { | |
121 | brg = mainclk_hz / speed_hz / (4 << div); | |
122 | /* now we have BRG+1 in brg, so count with that */ | |
123 | if (brg < (4 + 1)) { | |
124 | brg = (4 + 1); /* speed_hz too big */ | |
125 | break; /* set lowest brg (div is == 0) */ | |
126 | } | |
127 | if (brg <= (63 + 1)) | |
128 | break; /* we have valid brg and div */ | |
129 | } | |
130 | if (div == 4) { | |
131 | div = 3; /* speed_hz too small */ | |
132 | brg = (63 + 1); /* set highest brg and div */ | |
133 | } | |
134 | brg--; | |
135 | return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div); | |
136 | } | |
137 | ||
138 | static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw) | |
139 | { | |
140 | hw->regs->psc_spimsk = | |
141 | PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO | |
142 | | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO | |
143 | | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD; | |
144 | au_sync(); | |
145 | ||
146 | hw->regs->psc_spievent = | |
147 | PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO | |
148 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO | |
149 | | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD; | |
150 | au_sync(); | |
151 | } | |
152 | ||
153 | static void au1550_spi_reset_fifos(struct au1550_spi *hw) | |
154 | { | |
155 | u32 pcr; | |
156 | ||
157 | hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC; | |
158 | au_sync(); | |
159 | do { | |
160 | pcr = hw->regs->psc_spipcr; | |
161 | au_sync(); | |
162 | } while (pcr != 0); | |
163 | } | |
164 | ||
165 | /* | |
166 | * dma transfers are used for the most common spi word size of 8-bits | |
167 | * we cannot easily change already set up dma channels' width, so if we wanted | |
168 | * dma support for more than 8-bit words (up to 24 bits), we would need to | |
169 | * setup dma channels from scratch on each spi transfer, based on bits_per_word | |
170 | * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits | |
171 | * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode | |
172 | * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set() | |
173 | */ | |
174 | static void au1550_spi_chipsel(struct spi_device *spi, int value) | |
175 | { | |
176 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); | |
177 | unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; | |
178 | u32 cfg, stat; | |
179 | ||
180 | switch (value) { | |
181 | case BITBANG_CS_INACTIVE: | |
182 | if (hw->pdata->deactivate_cs) | |
183 | hw->pdata->deactivate_cs(hw->pdata, spi->chip_select, | |
184 | cspol); | |
185 | break; | |
186 | ||
187 | case BITBANG_CS_ACTIVE: | |
188 | au1550_spi_bits_handlers_set(hw, spi->bits_per_word); | |
189 | ||
190 | cfg = hw->regs->psc_spicfg; | |
191 | au_sync(); | |
192 | hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; | |
193 | au_sync(); | |
194 | ||
195 | if (spi->mode & SPI_CPOL) | |
196 | cfg |= PSC_SPICFG_BI; | |
197 | else | |
198 | cfg &= ~PSC_SPICFG_BI; | |
199 | if (spi->mode & SPI_CPHA) | |
200 | cfg &= ~PSC_SPICFG_CDE; | |
201 | else | |
202 | cfg |= PSC_SPICFG_CDE; | |
203 | ||
204 | if (spi->mode & SPI_LSB_FIRST) | |
205 | cfg |= PSC_SPICFG_MLF; | |
206 | else | |
207 | cfg &= ~PSC_SPICFG_MLF; | |
208 | ||
209 | if (hw->usedma && spi->bits_per_word <= 8) | |
210 | cfg &= ~PSC_SPICFG_DD_DISABLE; | |
211 | else | |
212 | cfg |= PSC_SPICFG_DD_DISABLE; | |
213 | cfg = PSC_SPICFG_CLR_LEN(cfg); | |
214 | cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word); | |
215 | ||
216 | cfg = PSC_SPICFG_CLR_BAUD(cfg); | |
217 | cfg &= ~PSC_SPICFG_SET_DIV(3); | |
218 | cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz); | |
219 | ||
220 | hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE; | |
221 | au_sync(); | |
222 | do { | |
223 | stat = hw->regs->psc_spistat; | |
224 | au_sync(); | |
225 | } while ((stat & PSC_SPISTAT_DR) == 0); | |
226 | ||
227 | if (hw->pdata->activate_cs) | |
228 | hw->pdata->activate_cs(hw->pdata, spi->chip_select, | |
229 | cspol); | |
230 | break; | |
231 | } | |
232 | } | |
233 | ||
234 | static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t) | |
235 | { | |
236 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); | |
237 | unsigned bpw, hz; | |
238 | u32 cfg, stat; | |
239 | ||
240 | bpw = t ? t->bits_per_word : spi->bits_per_word; | |
241 | hz = t ? t->speed_hz : spi->max_speed_hz; | |
242 | ||
243 | if (bpw < 4 || bpw > 24) { | |
244 | dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n", | |
245 | bpw); | |
246 | return -EINVAL; | |
247 | } | |
248 | if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) { | |
249 | dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n", | |
250 | hz); | |
251 | return -EINVAL; | |
252 | } | |
253 | ||
254 | au1550_spi_bits_handlers_set(hw, spi->bits_per_word); | |
255 | ||
256 | cfg = hw->regs->psc_spicfg; | |
257 | au_sync(); | |
258 | hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; | |
259 | au_sync(); | |
260 | ||
261 | if (hw->usedma && bpw <= 8) | |
262 | cfg &= ~PSC_SPICFG_DD_DISABLE; | |
263 | else | |
264 | cfg |= PSC_SPICFG_DD_DISABLE; | |
265 | cfg = PSC_SPICFG_CLR_LEN(cfg); | |
266 | cfg |= PSC_SPICFG_SET_LEN(bpw); | |
267 | ||
268 | cfg = PSC_SPICFG_CLR_BAUD(cfg); | |
269 | cfg &= ~PSC_SPICFG_SET_DIV(3); | |
270 | cfg |= au1550_spi_baudcfg(hw, hz); | |
271 | ||
272 | hw->regs->psc_spicfg = cfg; | |
273 | au_sync(); | |
274 | ||
275 | if (cfg & PSC_SPICFG_DE_ENABLE) { | |
276 | do { | |
277 | stat = hw->regs->psc_spistat; | |
278 | au_sync(); | |
279 | } while ((stat & PSC_SPISTAT_DR) == 0); | |
280 | } | |
281 | ||
282 | au1550_spi_reset_fifos(hw); | |
283 | au1550_spi_mask_ack_all(hw); | |
284 | return 0; | |
285 | } | |
286 | ||
287 | static int au1550_spi_setup(struct spi_device *spi) | |
288 | { | |
289 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); | |
290 | ||
63bd2359 JN |
291 | if (spi->bits_per_word < 4 || spi->bits_per_word > 24) { |
292 | dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n", | |
293 | spi->bits_per_word); | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
297 | if (spi->max_speed_hz == 0) | |
298 | spi->max_speed_hz = hw->freq_max; | |
299 | if (spi->max_speed_hz > hw->freq_max | |
300 | || spi->max_speed_hz < hw->freq_min) | |
301 | return -EINVAL; | |
302 | /* | |
303 | * NOTE: cannot change speed and other hw settings immediately, | |
304 | * otherwise sharing of spi bus is not possible, | |
305 | * so do not call setupxfer(spi, NULL) here | |
306 | */ | |
307 | return 0; | |
308 | } | |
309 | ||
310 | /* | |
311 | * for dma spi transfers, we have to setup rx channel, otherwise there is | |
312 | * no reliable way how to recognize that spi transfer is done | |
313 | * dma complete callbacks are called before real spi transfer is finished | |
314 | * and if only tx dma channel is set up (and rx fifo overflow event masked) | |
315 | * spi master done event irq is not generated unless rx fifo is empty (emptied) | |
316 | * so we need rx tmp buffer to use for rx dma if user does not provide one | |
317 | */ | |
318 | static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size) | |
319 | { | |
320 | hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL); | |
321 | if (!hw->dma_rx_tmpbuf) | |
322 | return -ENOMEM; | |
323 | hw->dma_rx_tmpbuf_size = size; | |
324 | hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf, | |
325 | size, DMA_FROM_DEVICE); | |
8d8bb39b | 326 | if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) { |
63bd2359 JN |
327 | kfree(hw->dma_rx_tmpbuf); |
328 | hw->dma_rx_tmpbuf = 0; | |
329 | hw->dma_rx_tmpbuf_size = 0; | |
330 | return -EFAULT; | |
331 | } | |
332 | return 0; | |
333 | } | |
334 | ||
335 | static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw) | |
336 | { | |
337 | dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr, | |
338 | hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE); | |
339 | kfree(hw->dma_rx_tmpbuf); | |
340 | hw->dma_rx_tmpbuf = 0; | |
341 | hw->dma_rx_tmpbuf_size = 0; | |
342 | } | |
343 | ||
344 | static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t) | |
345 | { | |
346 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); | |
347 | dma_addr_t dma_tx_addr; | |
348 | dma_addr_t dma_rx_addr; | |
349 | u32 res; | |
350 | ||
351 | hw->len = t->len; | |
352 | hw->tx_count = 0; | |
353 | hw->rx_count = 0; | |
354 | ||
355 | hw->tx = t->tx_buf; | |
356 | hw->rx = t->rx_buf; | |
357 | dma_tx_addr = t->tx_dma; | |
358 | dma_rx_addr = t->rx_dma; | |
359 | ||
360 | /* | |
4e253d23 JN |
361 | * check if buffers are already dma mapped, map them otherwise: |
362 | * - first map the TX buffer, so cache data gets written to memory | |
363 | * - then map the RX buffer, so that cache entries (with | |
364 | * soon-to-be-stale data) get removed | |
63bd2359 JN |
365 | * use rx buffer in place of tx if tx buffer was not provided |
366 | * use temp rx buffer (preallocated or realloc to fit) for rx dma | |
367 | */ | |
4e253d23 JN |
368 | if (t->tx_buf) { |
369 | if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ | |
370 | dma_tx_addr = dma_map_single(hw->dev, | |
371 | (void *)t->tx_buf, | |
372 | t->len, DMA_TO_DEVICE); | |
373 | if (dma_mapping_error(hw->dev, dma_tx_addr)) | |
374 | dev_err(hw->dev, "tx dma map error\n"); | |
375 | } | |
376 | } | |
377 | ||
63bd2359 JN |
378 | if (t->rx_buf) { |
379 | if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */ | |
380 | dma_rx_addr = dma_map_single(hw->dev, | |
381 | (void *)t->rx_buf, | |
382 | t->len, DMA_FROM_DEVICE); | |
8d8bb39b | 383 | if (dma_mapping_error(hw->dev, dma_rx_addr)) |
63bd2359 JN |
384 | dev_err(hw->dev, "rx dma map error\n"); |
385 | } | |
386 | } else { | |
387 | if (t->len > hw->dma_rx_tmpbuf_size) { | |
388 | int ret; | |
389 | ||
390 | au1550_spi_dma_rxtmp_free(hw); | |
391 | ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len, | |
392 | AU1550_SPI_DMA_RXTMP_MINSIZE)); | |
393 | if (ret < 0) | |
394 | return ret; | |
395 | } | |
396 | hw->rx = hw->dma_rx_tmpbuf; | |
397 | dma_rx_addr = hw->dma_rx_tmpbuf_addr; | |
398 | dma_sync_single_for_device(hw->dev, dma_rx_addr, | |
399 | t->len, DMA_FROM_DEVICE); | |
400 | } | |
4e253d23 JN |
401 | |
402 | if (!t->tx_buf) { | |
63bd2359 JN |
403 | dma_sync_single_for_device(hw->dev, dma_rx_addr, |
404 | t->len, DMA_BIDIRECTIONAL); | |
405 | hw->tx = hw->rx; | |
406 | } | |
407 | ||
408 | /* put buffers on the ring */ | |
409 | res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len); | |
410 | if (!res) | |
411 | dev_err(hw->dev, "rx dma put dest error\n"); | |
412 | ||
413 | res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len); | |
414 | if (!res) | |
415 | dev_err(hw->dev, "tx dma put source error\n"); | |
416 | ||
417 | au1xxx_dbdma_start(hw->dma_rx_ch); | |
418 | au1xxx_dbdma_start(hw->dma_tx_ch); | |
419 | ||
420 | /* by default enable nearly all events interrupt */ | |
421 | hw->regs->psc_spimsk = PSC_SPIMSK_SD; | |
422 | au_sync(); | |
423 | ||
424 | /* start the transfer */ | |
425 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; | |
426 | au_sync(); | |
427 | ||
428 | wait_for_completion(&hw->master_done); | |
429 | ||
430 | au1xxx_dbdma_stop(hw->dma_tx_ch); | |
431 | au1xxx_dbdma_stop(hw->dma_rx_ch); | |
432 | ||
433 | if (!t->rx_buf) { | |
434 | /* using the temporal preallocated and premapped buffer */ | |
435 | dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len, | |
436 | DMA_FROM_DEVICE); | |
437 | } | |
438 | /* unmap buffers if mapped above */ | |
439 | if (t->rx_buf && t->rx_dma == 0 ) | |
440 | dma_unmap_single(hw->dev, dma_rx_addr, t->len, | |
441 | DMA_FROM_DEVICE); | |
442 | if (t->tx_buf && t->tx_dma == 0 ) | |
443 | dma_unmap_single(hw->dev, dma_tx_addr, t->len, | |
444 | DMA_TO_DEVICE); | |
445 | ||
446 | return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count; | |
447 | } | |
448 | ||
449 | static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) | |
450 | { | |
451 | u32 stat, evnt; | |
452 | ||
453 | stat = hw->regs->psc_spistat; | |
454 | evnt = hw->regs->psc_spievent; | |
455 | au_sync(); | |
456 | if ((stat & PSC_SPISTAT_DI) == 0) { | |
457 | dev_err(hw->dev, "Unexpected IRQ!\n"); | |
458 | return IRQ_NONE; | |
459 | } | |
460 | ||
461 | if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO | |
462 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO | |
463 | | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD)) | |
464 | != 0) { | |
465 | /* | |
466 | * due to an spi error we consider transfer as done, | |
467 | * so mask all events until before next transfer start | |
468 | * and stop the possibly running dma immediatelly | |
469 | */ | |
470 | au1550_spi_mask_ack_all(hw); | |
471 | au1xxx_dbdma_stop(hw->dma_rx_ch); | |
472 | au1xxx_dbdma_stop(hw->dma_tx_ch); | |
473 | ||
474 | /* get number of transfered bytes */ | |
475 | hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch); | |
476 | hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch); | |
477 | ||
478 | au1xxx_dbdma_reset(hw->dma_rx_ch); | |
479 | au1xxx_dbdma_reset(hw->dma_tx_ch); | |
480 | au1550_spi_reset_fifos(hw); | |
481 | ||
bbe48ecc JN |
482 | if (evnt == PSC_SPIEVNT_RO) |
483 | dev_err(hw->dev, | |
484 | "dma transfer: receive FIFO overflow!\n"); | |
485 | else | |
486 | dev_err(hw->dev, | |
487 | "dma transfer: unexpected SPI error " | |
488 | "(event=0x%x stat=0x%x)!\n", evnt, stat); | |
63bd2359 JN |
489 | |
490 | complete(&hw->master_done); | |
491 | return IRQ_HANDLED; | |
492 | } | |
493 | ||
494 | if ((evnt & PSC_SPIEVNT_MD) != 0) { | |
495 | /* transfer completed successfully */ | |
496 | au1550_spi_mask_ack_all(hw); | |
497 | hw->rx_count = hw->len; | |
498 | hw->tx_count = hw->len; | |
499 | complete(&hw->master_done); | |
500 | } | |
501 | return IRQ_HANDLED; | |
502 | } | |
503 | ||
504 | ||
505 | /* routines to handle different word sizes in pio mode */ | |
506 | #define AU1550_SPI_RX_WORD(size, mask) \ | |
507 | static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \ | |
508 | { \ | |
509 | u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \ | |
510 | au_sync(); \ | |
511 | if (hw->rx) { \ | |
512 | *(u##size *)hw->rx = (u##size)fifoword; \ | |
513 | hw->rx += (size) / 8; \ | |
514 | } \ | |
515 | hw->rx_count += (size) / 8; \ | |
516 | } | |
517 | ||
518 | #define AU1550_SPI_TX_WORD(size, mask) \ | |
519 | static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \ | |
520 | { \ | |
521 | u32 fifoword = 0; \ | |
522 | if (hw->tx) { \ | |
523 | fifoword = *(u##size *)hw->tx & (u32)(mask); \ | |
524 | hw->tx += (size) / 8; \ | |
525 | } \ | |
526 | hw->tx_count += (size) / 8; \ | |
527 | if (hw->tx_count >= hw->len) \ | |
528 | fifoword |= PSC_SPITXRX_LC; \ | |
529 | hw->regs->psc_spitxrx = fifoword; \ | |
530 | au_sync(); \ | |
531 | } | |
532 | ||
533 | AU1550_SPI_RX_WORD(8,0xff) | |
534 | AU1550_SPI_RX_WORD(16,0xffff) | |
535 | AU1550_SPI_RX_WORD(32,0xffffff) | |
536 | AU1550_SPI_TX_WORD(8,0xff) | |
537 | AU1550_SPI_TX_WORD(16,0xffff) | |
538 | AU1550_SPI_TX_WORD(32,0xffffff) | |
539 | ||
540 | static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t) | |
541 | { | |
542 | u32 stat, mask; | |
543 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); | |
544 | ||
545 | hw->tx = t->tx_buf; | |
546 | hw->rx = t->rx_buf; | |
547 | hw->len = t->len; | |
548 | hw->tx_count = 0; | |
549 | hw->rx_count = 0; | |
550 | ||
551 | /* by default enable nearly all events after filling tx fifo */ | |
552 | mask = PSC_SPIMSK_SD; | |
553 | ||
554 | /* fill the transmit FIFO */ | |
555 | while (hw->tx_count < hw->len) { | |
556 | ||
557 | hw->tx_word(hw); | |
558 | ||
559 | if (hw->tx_count >= hw->len) { | |
560 | /* mask tx fifo request interrupt as we are done */ | |
561 | mask |= PSC_SPIMSK_TR; | |
562 | } | |
563 | ||
564 | stat = hw->regs->psc_spistat; | |
565 | au_sync(); | |
566 | if (stat & PSC_SPISTAT_TF) | |
567 | break; | |
568 | } | |
569 | ||
570 | /* enable event interrupts */ | |
571 | hw->regs->psc_spimsk = mask; | |
572 | au_sync(); | |
573 | ||
574 | /* start the transfer */ | |
575 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; | |
576 | au_sync(); | |
577 | ||
578 | wait_for_completion(&hw->master_done); | |
579 | ||
580 | return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count; | |
581 | } | |
582 | ||
583 | static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) | |
584 | { | |
585 | int busy; | |
586 | u32 stat, evnt; | |
587 | ||
588 | stat = hw->regs->psc_spistat; | |
589 | evnt = hw->regs->psc_spievent; | |
590 | au_sync(); | |
591 | if ((stat & PSC_SPISTAT_DI) == 0) { | |
592 | dev_err(hw->dev, "Unexpected IRQ!\n"); | |
593 | return IRQ_NONE; | |
594 | } | |
595 | ||
596 | if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO | |
597 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO | |
bbe48ecc | 598 | | PSC_SPIEVNT_SD)) |
63bd2359 | 599 | != 0) { |
63bd2359 JN |
600 | /* |
601 | * due to an error we consider transfer as done, | |
602 | * so mask all events until before next transfer start | |
603 | */ | |
604 | au1550_spi_mask_ack_all(hw); | |
605 | au1550_spi_reset_fifos(hw); | |
bbe48ecc JN |
606 | dev_err(hw->dev, |
607 | "pio transfer: unexpected SPI error " | |
608 | "(event=0x%x stat=0x%x)!\n", evnt, stat); | |
63bd2359 JN |
609 | complete(&hw->master_done); |
610 | return IRQ_HANDLED; | |
611 | } | |
612 | ||
613 | /* | |
614 | * while there is something to read from rx fifo | |
615 | * or there is a space to write to tx fifo: | |
616 | */ | |
617 | do { | |
618 | busy = 0; | |
619 | stat = hw->regs->psc_spistat; | |
620 | au_sync(); | |
621 | ||
bbe48ecc JN |
622 | /* |
623 | * Take care to not let the Rx FIFO overflow. | |
624 | * | |
625 | * We only write a byte if we have read one at least. Initially, | |
626 | * the write fifo is full, so we should read from the read fifo | |
627 | * first. | |
628 | * In case we miss a word from the read fifo, we should get a | |
629 | * RO event and should back out. | |
630 | */ | |
631 | if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) { | |
63bd2359 | 632 | hw->rx_word(hw); |
63bd2359 | 633 | busy = 1; |
63bd2359 | 634 | |
bbe48ecc JN |
635 | if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len) |
636 | hw->tx_word(hw); | |
63bd2359 JN |
637 | } |
638 | } while (busy); | |
639 | ||
bbe48ecc | 640 | hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR; |
63bd2359 JN |
641 | au_sync(); |
642 | ||
bbe48ecc JN |
643 | /* |
644 | * Restart the SPI transmission in case of a transmit underflow. | |
645 | * This seems to work despite the notes in the Au1550 data book | |
646 | * of Figure 8-4 with flowchart for SPI master operation: | |
647 | * | |
648 | * """Note 1: An XFR Error Interrupt occurs, unless masked, | |
649 | * for any of the following events: Tx FIFO Underflow, | |
650 | * Rx FIFO Overflow, or Multiple-master Error | |
651 | * Note 2: In case of a Tx Underflow Error, all zeroes are | |
652 | * transmitted.""" | |
653 | * | |
654 | * By simply restarting the spi transfer on Tx Underflow Error, | |
655 | * we assume that spi transfer was paused instead of zeroes | |
656 | * transmittion mentioned in the Note 2 of Au1550 data book. | |
657 | */ | |
658 | if (evnt & PSC_SPIEVNT_TU) { | |
659 | hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD; | |
660 | au_sync(); | |
661 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; | |
662 | au_sync(); | |
663 | } | |
664 | ||
665 | if (hw->rx_count >= hw->len) { | |
63bd2359 JN |
666 | /* transfer completed successfully */ |
667 | au1550_spi_mask_ack_all(hw); | |
668 | complete(&hw->master_done); | |
669 | } | |
670 | return IRQ_HANDLED; | |
671 | } | |
672 | ||
673 | static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) | |
674 | { | |
675 | struct au1550_spi *hw = spi_master_get_devdata(spi->master); | |
676 | return hw->txrx_bufs(spi, t); | |
677 | } | |
678 | ||
40369e1c | 679 | static irqreturn_t au1550_spi_irq(int irq, void *dev) |
63bd2359 JN |
680 | { |
681 | struct au1550_spi *hw = dev; | |
682 | return hw->irq_callback(hw); | |
683 | } | |
684 | ||
685 | static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw) | |
686 | { | |
687 | if (bpw <= 8) { | |
688 | if (hw->usedma) { | |
689 | hw->txrx_bufs = &au1550_spi_dma_txrxb; | |
690 | hw->irq_callback = &au1550_spi_dma_irq_callback; | |
691 | } else { | |
692 | hw->rx_word = &au1550_spi_rx_word_8; | |
693 | hw->tx_word = &au1550_spi_tx_word_8; | |
694 | hw->txrx_bufs = &au1550_spi_pio_txrxb; | |
695 | hw->irq_callback = &au1550_spi_pio_irq_callback; | |
696 | } | |
697 | } else if (bpw <= 16) { | |
698 | hw->rx_word = &au1550_spi_rx_word_16; | |
699 | hw->tx_word = &au1550_spi_tx_word_16; | |
700 | hw->txrx_bufs = &au1550_spi_pio_txrxb; | |
701 | hw->irq_callback = &au1550_spi_pio_irq_callback; | |
702 | } else { | |
703 | hw->rx_word = &au1550_spi_rx_word_32; | |
704 | hw->tx_word = &au1550_spi_tx_word_32; | |
705 | hw->txrx_bufs = &au1550_spi_pio_txrxb; | |
706 | hw->irq_callback = &au1550_spi_pio_irq_callback; | |
707 | } | |
708 | } | |
709 | ||
710 | static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) | |
711 | { | |
712 | u32 stat, cfg; | |
713 | ||
714 | /* set up the PSC for SPI mode */ | |
715 | hw->regs->psc_ctrl = PSC_CTRL_DISABLE; | |
716 | au_sync(); | |
717 | hw->regs->psc_sel = PSC_SEL_PS_SPIMODE; | |
718 | au_sync(); | |
719 | ||
720 | hw->regs->psc_spicfg = 0; | |
721 | au_sync(); | |
722 | ||
723 | hw->regs->psc_ctrl = PSC_CTRL_ENABLE; | |
724 | au_sync(); | |
725 | ||
726 | do { | |
727 | stat = hw->regs->psc_spistat; | |
728 | au_sync(); | |
729 | } while ((stat & PSC_SPISTAT_SR) == 0); | |
730 | ||
731 | ||
732 | cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE; | |
733 | cfg |= PSC_SPICFG_SET_LEN(8); | |
734 | cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8; | |
735 | /* use minimal allowed brg and div values as initial setting: */ | |
736 | cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0); | |
737 | ||
738 | #ifdef AU1550_SPI_DEBUG_LOOPBACK | |
739 | cfg |= PSC_SPICFG_LB; | |
740 | #endif | |
741 | ||
742 | hw->regs->psc_spicfg = cfg; | |
743 | au_sync(); | |
744 | ||
745 | au1550_spi_mask_ack_all(hw); | |
746 | ||
747 | hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE; | |
748 | au_sync(); | |
749 | ||
750 | do { | |
751 | stat = hw->regs->psc_spistat; | |
752 | au_sync(); | |
753 | } while ((stat & PSC_SPISTAT_DR) == 0); | |
bbe48ecc JN |
754 | |
755 | au1550_spi_reset_fifos(hw); | |
63bd2359 JN |
756 | } |
757 | ||
758 | ||
759 | static int __init au1550_spi_probe(struct platform_device *pdev) | |
760 | { | |
761 | struct au1550_spi *hw; | |
762 | struct spi_master *master; | |
3a93a159 | 763 | struct resource *r; |
63bd2359 JN |
764 | int err = 0; |
765 | ||
766 | master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi)); | |
767 | if (master == NULL) { | |
768 | dev_err(&pdev->dev, "No memory for spi_master\n"); | |
769 | err = -ENOMEM; | |
770 | goto err_nomem; | |
771 | } | |
772 | ||
e7db06b5 DB |
773 | /* the spi->mode bits understood by this driver: */ |
774 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; | |
775 | ||
63bd2359 JN |
776 | hw = spi_master_get_devdata(master); |
777 | ||
778 | hw->master = spi_master_get(master); | |
779 | hw->pdata = pdev->dev.platform_data; | |
780 | hw->dev = &pdev->dev; | |
781 | ||
782 | if (hw->pdata == NULL) { | |
783 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
784 | err = -ENOENT; | |
785 | goto err_no_pdata; | |
786 | } | |
787 | ||
3a93a159 ML |
788 | r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
789 | if (!r) { | |
790 | dev_err(&pdev->dev, "no IRQ\n"); | |
791 | err = -ENODEV; | |
792 | goto err_no_iores; | |
793 | } | |
794 | hw->irq = r->start; | |
795 | ||
796 | hw->usedma = 0; | |
797 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
798 | if (r) { | |
799 | hw->dma_tx_id = r->start; | |
800 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
801 | if (r) { | |
802 | hw->dma_rx_id = r->start; | |
803 | if (usedma && ddma_memid) { | |
804 | if (pdev->dev.dma_mask == NULL) | |
805 | dev_warn(&pdev->dev, "no dma mask\n"); | |
806 | else | |
807 | hw->usedma = 1; | |
808 | } | |
809 | } | |
810 | } | |
63bd2359 | 811 | |
3a93a159 ML |
812 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
813 | if (!r) { | |
814 | dev_err(&pdev->dev, "no mmio resource\n"); | |
815 | err = -ENODEV; | |
816 | goto err_no_iores; | |
63bd2359 JN |
817 | } |
818 | ||
3a93a159 ML |
819 | hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t), |
820 | pdev->name); | |
821 | if (!hw->ioarea) { | |
63bd2359 JN |
822 | dev_err(&pdev->dev, "Cannot reserve iomem region\n"); |
823 | err = -ENXIO; | |
824 | goto err_no_iores; | |
825 | } | |
826 | ||
3a93a159 ML |
827 | hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t)); |
828 | if (!hw->regs) { | |
829 | dev_err(&pdev->dev, "cannot ioremap\n"); | |
830 | err = -ENXIO; | |
831 | goto err_ioremap; | |
63bd2359 JN |
832 | } |
833 | ||
3a93a159 | 834 | platform_set_drvdata(pdev, hw); |
63bd2359 | 835 | |
3a93a159 ML |
836 | init_completion(&hw->master_done); |
837 | ||
838 | hw->bitbang.master = hw->master; | |
839 | hw->bitbang.setup_transfer = au1550_spi_setupxfer; | |
840 | hw->bitbang.chipselect = au1550_spi_chipsel; | |
841 | hw->bitbang.master->setup = au1550_spi_setup; | |
842 | hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs; | |
843 | ||
844 | if (hw->usedma) { | |
845 | hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid, | |
63bd2359 JN |
846 | hw->dma_tx_id, NULL, (void *)hw); |
847 | if (hw->dma_tx_ch == 0) { | |
848 | dev_err(&pdev->dev, | |
849 | "Cannot allocate tx dma channel\n"); | |
850 | err = -ENXIO; | |
851 | goto err_no_txdma; | |
852 | } | |
853 | au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8); | |
854 | if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch, | |
855 | AU1550_SPI_DBDMA_DESCRIPTORS) == 0) { | |
856 | dev_err(&pdev->dev, | |
857 | "Cannot allocate tx dma descriptors\n"); | |
858 | err = -ENXIO; | |
859 | goto err_no_txdma_descr; | |
860 | } | |
861 | ||
862 | ||
863 | hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id, | |
3a93a159 | 864 | ddma_memid, NULL, (void *)hw); |
63bd2359 JN |
865 | if (hw->dma_rx_ch == 0) { |
866 | dev_err(&pdev->dev, | |
867 | "Cannot allocate rx dma channel\n"); | |
868 | err = -ENXIO; | |
869 | goto err_no_rxdma; | |
870 | } | |
871 | au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8); | |
872 | if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch, | |
873 | AU1550_SPI_DBDMA_DESCRIPTORS) == 0) { | |
874 | dev_err(&pdev->dev, | |
875 | "Cannot allocate rx dma descriptors\n"); | |
876 | err = -ENXIO; | |
877 | goto err_no_rxdma_descr; | |
878 | } | |
879 | ||
880 | err = au1550_spi_dma_rxtmp_alloc(hw, | |
881 | AU1550_SPI_DMA_RXTMP_MINSIZE); | |
882 | if (err < 0) { | |
883 | dev_err(&pdev->dev, | |
884 | "Cannot allocate initial rx dma tmp buffer\n"); | |
885 | goto err_dma_rxtmp_alloc; | |
886 | } | |
887 | } | |
888 | ||
889 | au1550_spi_bits_handlers_set(hw, 8); | |
890 | ||
891 | err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw); | |
892 | if (err) { | |
893 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
894 | goto err_no_irq; | |
895 | } | |
896 | ||
3a93a159 | 897 | master->bus_num = pdev->id; |
63bd2359 JN |
898 | master->num_chipselect = hw->pdata->num_chipselect; |
899 | ||
900 | /* | |
901 | * precompute valid range for spi freq - from au1550 datasheet: | |
902 | * psc_tempclk = psc_mainclk / (2 << DIV) | |
903 | * spiclk = psc_tempclk / (2 * (BRG + 1)) | |
904 | * BRG valid range is 4..63 | |
905 | * DIV valid range is 0..3 | |
906 | * round the min and max frequencies to values that would still | |
907 | * produce valid brg and div | |
908 | */ | |
909 | { | |
910 | int min_div = (2 << 0) * (2 * (4 + 1)); | |
911 | int max_div = (2 << 3) * (2 * (63 + 1)); | |
912 | hw->freq_max = hw->pdata->mainclk_hz / min_div; | |
913 | hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1; | |
914 | } | |
915 | ||
916 | au1550_spi_setup_psc_as_spi(hw); | |
917 | ||
918 | err = spi_bitbang_start(&hw->bitbang); | |
919 | if (err) { | |
920 | dev_err(&pdev->dev, "Failed to register SPI master\n"); | |
921 | goto err_register; | |
922 | } | |
923 | ||
924 | dev_info(&pdev->dev, | |
925 | "spi master registered: bus_num=%d num_chipselect=%d\n", | |
926 | master->bus_num, master->num_chipselect); | |
927 | ||
928 | return 0; | |
929 | ||
930 | err_register: | |
931 | free_irq(hw->irq, hw); | |
932 | ||
933 | err_no_irq: | |
934 | au1550_spi_dma_rxtmp_free(hw); | |
935 | ||
936 | err_dma_rxtmp_alloc: | |
937 | err_no_rxdma_descr: | |
938 | if (hw->usedma) | |
939 | au1xxx_dbdma_chan_free(hw->dma_rx_ch); | |
940 | ||
941 | err_no_rxdma: | |
942 | err_no_txdma_descr: | |
943 | if (hw->usedma) | |
944 | au1xxx_dbdma_chan_free(hw->dma_tx_ch); | |
945 | ||
946 | err_no_txdma: | |
3a93a159 ML |
947 | iounmap((void __iomem *)hw->regs); |
948 | ||
949 | err_ioremap: | |
950 | release_resource(hw->ioarea); | |
951 | kfree(hw->ioarea); | |
63bd2359 JN |
952 | |
953 | err_no_iores: | |
954 | err_no_pdata: | |
955 | spi_master_put(hw->master); | |
956 | ||
957 | err_nomem: | |
958 | return err; | |
959 | } | |
960 | ||
961 | static int __exit au1550_spi_remove(struct platform_device *pdev) | |
962 | { | |
963 | struct au1550_spi *hw = platform_get_drvdata(pdev); | |
964 | ||
965 | dev_info(&pdev->dev, "spi master remove: bus_num=%d\n", | |
966 | hw->master->bus_num); | |
967 | ||
968 | spi_bitbang_stop(&hw->bitbang); | |
969 | free_irq(hw->irq, hw); | |
3a93a159 ML |
970 | iounmap((void __iomem *)hw->regs); |
971 | release_resource(hw->ioarea); | |
972 | kfree(hw->ioarea); | |
63bd2359 JN |
973 | |
974 | if (hw->usedma) { | |
975 | au1550_spi_dma_rxtmp_free(hw); | |
976 | au1xxx_dbdma_chan_free(hw->dma_rx_ch); | |
977 | au1xxx_dbdma_chan_free(hw->dma_tx_ch); | |
978 | } | |
979 | ||
980 | platform_set_drvdata(pdev, NULL); | |
981 | ||
982 | spi_master_put(hw->master); | |
983 | return 0; | |
984 | } | |
985 | ||
7e38c3c4 KS |
986 | /* work with hotplug and coldplug */ |
987 | MODULE_ALIAS("platform:au1550-spi"); | |
988 | ||
63bd2359 JN |
989 | static struct platform_driver au1550_spi_drv = { |
990 | .remove = __exit_p(au1550_spi_remove), | |
991 | .driver = { | |
992 | .name = "au1550-spi", | |
993 | .owner = THIS_MODULE, | |
994 | }, | |
995 | }; | |
996 | ||
997 | static int __init au1550_spi_init(void) | |
998 | { | |
3a93a159 ML |
999 | /* |
1000 | * create memory device with 8 bits dev_devwidth | |
1001 | * needed for proper byte ordering to spi fifo | |
1002 | */ | |
1003 | if (usedma) { | |
1004 | ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev); | |
1005 | if (!ddma_memid) | |
1006 | printk(KERN_ERR "au1550-spi: cannot add memory" | |
1007 | "dbdma device\n"); | |
1008 | } | |
63bd2359 JN |
1009 | return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe); |
1010 | } | |
1011 | module_init(au1550_spi_init); | |
1012 | ||
1013 | static void __exit au1550_spi_exit(void) | |
1014 | { | |
3a93a159 ML |
1015 | if (usedma && ddma_memid) |
1016 | au1xxx_ddma_del_device(ddma_memid); | |
63bd2359 JN |
1017 | platform_driver_unregister(&au1550_spi_drv); |
1018 | } | |
1019 | module_exit(au1550_spi_exit); | |
1020 | ||
1021 | MODULE_DESCRIPTION("Au1550 PSC SPI Driver"); | |
1022 | MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>"); | |
1023 | MODULE_LICENSE("GPL"); |