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358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
43abb11b | 3 | * Copyright (C) 2010 EF Johnson Technologies |
358934a6 SP |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/gpio.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | #include <linux/spi/spi.h> | |
30 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
358934a6 SP |
32 | |
33 | #include <mach/spi.h> | |
34 | #include <mach/edma.h> | |
35 | ||
36 | #define SPI_NO_RESOURCE ((resource_size_t)-1) | |
37 | ||
38 | #define SPI_MAX_CHIPSELECT 2 | |
39 | ||
40 | #define CS_DEFAULT 0xFF | |
41 | ||
358934a6 SP |
42 | #define SPIFMT_PHASE_MASK BIT(16) |
43 | #define SPIFMT_POLARITY_MASK BIT(17) | |
44 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
45 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
46 | #define SPIFMT_WAITENA_MASK BIT(21) | |
47 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
48 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
49 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
50 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 51 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 52 | |
358934a6 SP |
53 | /* SPIPC0 */ |
54 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
55 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
56 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
57 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
58 | |
59 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
60 | #define SPIINT_MASKINT 0x0000015F |
61 | #define SPI_INTLVL_1 0x000001FF | |
62 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 63 | |
cfbc5d1d BN |
64 | /* SPIDAT1 (upper 16 bit defines) */ |
65 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
66 | ||
67 | /* SPIGCR1 */ | |
358934a6 SP |
68 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
69 | #define SPIGCR1_MASTER_MASK BIT(0) | |
3f27b57c | 70 | #define SPIGCR1_POWERDOWN_MASK BIT(8) |
358934a6 | 71 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
8e206f1c | 72 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
73 | |
74 | /* SPIBUF */ | |
75 | #define SPIBUF_TXFULL_MASK BIT(29) | |
76 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
77 | ||
7abbf23c BN |
78 | /* SPIDELAY */ |
79 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
80 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
81 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
82 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
83 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
84 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
85 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
86 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
87 | ||
358934a6 SP |
88 | /* Error Masks */ |
89 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
90 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
91 | #define SPIFLG_PARERR_MASK BIT(2) | |
92 | #define SPIFLG_DESYNC_MASK BIT(3) | |
93 | #define SPIFLG_BITERR_MASK BIT(4) | |
94 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 95 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
96 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
97 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
98 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
99 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 100 | |
358934a6 | 101 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 102 | |
358934a6 SP |
103 | /* SPI Controller registers */ |
104 | #define SPIGCR0 0x00 | |
105 | #define SPIGCR1 0x04 | |
106 | #define SPIINT 0x08 | |
107 | #define SPILVL 0x0c | |
108 | #define SPIFLG 0x10 | |
109 | #define SPIPC0 0x14 | |
358934a6 SP |
110 | #define SPIDAT1 0x3c |
111 | #define SPIBUF 0x40 | |
358934a6 SP |
112 | #define SPIDELAY 0x48 |
113 | #define SPIDEF 0x4c | |
114 | #define SPIFMT0 0x50 | |
358934a6 | 115 | |
358934a6 SP |
116 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
117 | struct davinci_spi_dma { | |
212d4b69 SN |
118 | int tx_channel; |
119 | int rx_channel; | |
523c37e7 | 120 | int dummy_param_slot; |
358934a6 | 121 | enum dma_event_q eventq; |
358934a6 SP |
122 | }; |
123 | ||
124 | /* SPI Controller driver's private data. */ | |
125 | struct davinci_spi { | |
126 | struct spi_bitbang bitbang; | |
127 | struct clk *clk; | |
128 | ||
129 | u8 version; | |
130 | resource_size_t pbase; | |
131 | void __iomem *base; | |
e0d205e9 BN |
132 | u32 irq; |
133 | struct completion done; | |
358934a6 SP |
134 | |
135 | const void *tx; | |
136 | void *rx; | |
e91c659b BN |
137 | #define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) |
138 | u8 rx_tmp_buf[SPI_TMP_BUFSZ]; | |
e0d205e9 BN |
139 | int rcount; |
140 | int wcount; | |
212d4b69 | 141 | struct davinci_spi_dma dma; |
778e261e | 142 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
143 | |
144 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
145 | u32 (*get_tx)(struct davinci_spi *); | |
146 | ||
cda987eb | 147 | u8 bytes_per_word[SPI_MAX_CHIPSELECT]; |
358934a6 SP |
148 | }; |
149 | ||
53a31b07 BN |
150 | static struct davinci_spi_config davinci_spi_default_cfg; |
151 | ||
212d4b69 | 152 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) |
358934a6 | 153 | { |
212d4b69 SN |
154 | if (dspi->rx) { |
155 | u8 *rx = dspi->rx; | |
53d454a1 | 156 | *rx++ = (u8)data; |
212d4b69 | 157 | dspi->rx = rx; |
53d454a1 | 158 | } |
358934a6 SP |
159 | } |
160 | ||
212d4b69 | 161 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) |
358934a6 | 162 | { |
212d4b69 SN |
163 | if (dspi->rx) { |
164 | u16 *rx = dspi->rx; | |
53d454a1 | 165 | *rx++ = (u16)data; |
212d4b69 | 166 | dspi->rx = rx; |
53d454a1 | 167 | } |
358934a6 SP |
168 | } |
169 | ||
212d4b69 | 170 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) |
358934a6 | 171 | { |
53d454a1 | 172 | u32 data = 0; |
212d4b69 SN |
173 | if (dspi->tx) { |
174 | const u8 *tx = dspi->tx; | |
53d454a1 | 175 | data = *tx++; |
212d4b69 | 176 | dspi->tx = tx; |
53d454a1 | 177 | } |
358934a6 SP |
178 | return data; |
179 | } | |
180 | ||
212d4b69 | 181 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) |
358934a6 | 182 | { |
53d454a1 | 183 | u32 data = 0; |
212d4b69 SN |
184 | if (dspi->tx) { |
185 | const u16 *tx = dspi->tx; | |
53d454a1 | 186 | data = *tx++; |
212d4b69 | 187 | dspi->tx = tx; |
53d454a1 | 188 | } |
358934a6 SP |
189 | return data; |
190 | } | |
191 | ||
192 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
193 | { | |
194 | u32 v = ioread32(addr); | |
195 | ||
196 | v |= bits; | |
197 | iowrite32(v, addr); | |
198 | } | |
199 | ||
200 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
201 | { | |
202 | u32 v = ioread32(addr); | |
203 | ||
204 | v &= ~bits; | |
205 | iowrite32(v, addr); | |
206 | } | |
207 | ||
358934a6 SP |
208 | /* |
209 | * Interface to control the chip select signal | |
210 | */ | |
211 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
212 | { | |
212d4b69 | 213 | struct davinci_spi *dspi; |
358934a6 | 214 | struct davinci_spi_platform_data *pdata; |
7978b8c3 | 215 | u8 chip_sel = spi->chip_select; |
212d4b69 | 216 | u16 spidat1 = CS_DEFAULT; |
23853973 | 217 | bool gpio_chipsel = false; |
358934a6 | 218 | |
212d4b69 SN |
219 | dspi = spi_master_get_devdata(spi->master); |
220 | pdata = dspi->pdata; | |
358934a6 | 221 | |
23853973 BN |
222 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
223 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) | |
224 | gpio_chipsel = true; | |
225 | ||
358934a6 SP |
226 | /* |
227 | * Board specific chip select logic decides the polarity and cs | |
228 | * line for the controller | |
229 | */ | |
23853973 BN |
230 | if (gpio_chipsel) { |
231 | if (value == BITBANG_CS_ACTIVE) | |
232 | gpio_set_value(pdata->chip_sel[chip_sel], 0); | |
233 | else | |
234 | gpio_set_value(pdata->chip_sel[chip_sel], 1); | |
235 | } else { | |
236 | if (value == BITBANG_CS_ACTIVE) { | |
212d4b69 SN |
237 | spidat1 |= SPIDAT1_CSHOLD_MASK; |
238 | spidat1 &= ~(0x1 << chip_sel); | |
23853973 | 239 | } |
7978b8c3 | 240 | |
212d4b69 | 241 | iowrite16(spidat1, dspi->base + SPIDAT1 + 2); |
23853973 | 242 | } |
358934a6 SP |
243 | } |
244 | ||
7fe0092b BN |
245 | /** |
246 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
247 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
248 | * | |
249 | * This function calculates the prescale value that generates a clock rate | |
250 | * less than or equal to the specified maximum. | |
251 | * | |
252 | * Returns: calculated prescale - 1 for easy programming into SPI registers | |
253 | * or negative error number if valid prescalar cannot be updated. | |
254 | */ | |
212d4b69 | 255 | static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, |
7fe0092b BN |
256 | u32 max_speed_hz) |
257 | { | |
258 | int ret; | |
259 | ||
212d4b69 | 260 | ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); |
7fe0092b BN |
261 | |
262 | if (ret < 3 || ret > 256) | |
263 | return -EINVAL; | |
264 | ||
265 | return ret - 1; | |
266 | } | |
267 | ||
358934a6 SP |
268 | /** |
269 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
270 | * @spi: spi device on which data transfer to be done | |
271 | * @t: spi transfer in which transfer info is filled | |
272 | * | |
273 | * This function determines data transfer method (8/16/32 bit transfer). | |
274 | * It will also set the SPI Clock Control register according to | |
275 | * SPI slave device freq. | |
276 | */ | |
277 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
278 | struct spi_transfer *t) | |
279 | { | |
280 | ||
212d4b69 | 281 | struct davinci_spi *dspi; |
25f33512 | 282 | struct davinci_spi_config *spicfg; |
358934a6 | 283 | u8 bits_per_word = 0; |
25f33512 | 284 | u32 hz = 0, spifmt = 0, prescale = 0; |
358934a6 | 285 | |
212d4b69 | 286 | dspi = spi_master_get_devdata(spi->master); |
25f33512 BN |
287 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
288 | if (!spicfg) | |
289 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
290 | |
291 | if (t) { | |
292 | bits_per_word = t->bits_per_word; | |
293 | hz = t->speed_hz; | |
294 | } | |
295 | ||
296 | /* if bits_per_word is not set then set it default */ | |
297 | if (!bits_per_word) | |
298 | bits_per_word = spi->bits_per_word; | |
299 | ||
300 | /* | |
301 | * Assign function pointer to appropriate transfer method | |
302 | * 8bit, 16bit or 32bit transfer | |
303 | */ | |
304 | if (bits_per_word <= 8 && bits_per_word >= 2) { | |
212d4b69 SN |
305 | dspi->get_rx = davinci_spi_rx_buf_u8; |
306 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
307 | dspi->bytes_per_word[spi->chip_select] = 1; | |
358934a6 | 308 | } else if (bits_per_word <= 16 && bits_per_word >= 2) { |
212d4b69 SN |
309 | dspi->get_rx = davinci_spi_rx_buf_u16; |
310 | dspi->get_tx = davinci_spi_tx_buf_u16; | |
311 | dspi->bytes_per_word[spi->chip_select] = 2; | |
358934a6 SP |
312 | } else |
313 | return -EINVAL; | |
314 | ||
315 | if (!hz) | |
316 | hz = spi->max_speed_hz; | |
317 | ||
25f33512 BN |
318 | /* Set up SPIFMTn register, unique to this chipselect. */ |
319 | ||
212d4b69 | 320 | prescale = davinci_spi_get_prescale(dspi, hz); |
7fe0092b BN |
321 | if (prescale < 0) |
322 | return prescale; | |
323 | ||
25f33512 BN |
324 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
325 | ||
326 | if (spi->mode & SPI_LSB_FIRST) | |
327 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
328 | ||
329 | if (spi->mode & SPI_CPOL) | |
330 | spifmt |= SPIFMT_POLARITY_MASK; | |
331 | ||
332 | if (!(spi->mode & SPI_CPHA)) | |
333 | spifmt |= SPIFMT_PHASE_MASK; | |
334 | ||
335 | /* | |
336 | * Version 1 hardware supports two basic SPI modes: | |
337 | * - Standard SPI mode uses 4 pins, with chipselect | |
338 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
339 | * (distinct from SPI_3WIRE, with just one data wire; | |
340 | * or similar variants without MOSI or without MISO) | |
341 | * | |
342 | * Version 2 hardware supports an optional handshaking signal, | |
343 | * so it can support two more modes: | |
344 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
345 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
346 | */ | |
347 | ||
212d4b69 | 348 | if (dspi->version == SPI_VERSION_2) { |
25f33512 | 349 | |
7abbf23c BN |
350 | u32 delay = 0; |
351 | ||
25f33512 BN |
352 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
353 | & SPIFMT_WDELAY_MASK); | |
358934a6 | 354 | |
25f33512 BN |
355 | if (spicfg->odd_parity) |
356 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
357 | ||
358 | if (spicfg->parity_enable) | |
359 | spifmt |= SPIFMT_PARITYENA_MASK; | |
360 | ||
7abbf23c | 361 | if (spicfg->timer_disable) { |
25f33512 | 362 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
363 | } else { |
364 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
365 | & SPIDELAY_C2TDELAY_MASK; | |
366 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
367 | & SPIDELAY_T2CDELAY_MASK; | |
368 | } | |
25f33512 | 369 | |
7abbf23c | 370 | if (spi->mode & SPI_READY) { |
25f33512 | 371 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
372 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
373 | & SPIDELAY_T2EDELAY_MASK; | |
374 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
375 | & SPIDELAY_C2EDELAY_MASK; | |
376 | } | |
377 | ||
212d4b69 | 378 | iowrite32(delay, dspi->base + SPIDELAY); |
25f33512 BN |
379 | } |
380 | ||
212d4b69 | 381 | iowrite32(spifmt, dspi->base + SPIFMT0); |
358934a6 SP |
382 | |
383 | return 0; | |
384 | } | |
385 | ||
358934a6 SP |
386 | /** |
387 | * davinci_spi_setup - This functions will set default transfer method | |
388 | * @spi: spi device on which data transfer to be done | |
389 | * | |
390 | * This functions sets the default transfer method. | |
391 | */ | |
358934a6 SP |
392 | static int davinci_spi_setup(struct spi_device *spi) |
393 | { | |
b23a5d46 | 394 | int retval = 0; |
212d4b69 | 395 | struct davinci_spi *dspi; |
be88471b | 396 | struct davinci_spi_platform_data *pdata; |
358934a6 | 397 | |
212d4b69 SN |
398 | dspi = spi_master_get_devdata(spi->master); |
399 | pdata = dspi->pdata; | |
358934a6 SP |
400 | |
401 | /* if bits per word length is zero then set it default 8 */ | |
402 | if (!spi->bits_per_word) | |
403 | spi->bits_per_word = 8; | |
404 | ||
be88471b BN |
405 | if (!(spi->mode & SPI_NO_CS)) { |
406 | if ((pdata->chip_sel == NULL) || | |
407 | (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) | |
212d4b69 | 408 | set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); |
be88471b BN |
409 | |
410 | } | |
411 | ||
412 | if (spi->mode & SPI_READY) | |
212d4b69 | 413 | set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); |
be88471b BN |
414 | |
415 | if (spi->mode & SPI_LOOP) | |
212d4b69 | 416 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 417 | else |
212d4b69 | 418 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); |
be88471b | 419 | |
358934a6 SP |
420 | return retval; |
421 | } | |
422 | ||
212d4b69 | 423 | static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) |
358934a6 | 424 | { |
212d4b69 | 425 | struct device *sdev = dspi->bitbang.master->dev.parent; |
358934a6 SP |
426 | |
427 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
428 | dev_dbg(sdev, "SPI Time-out Error\n"); | |
429 | return -ETIMEDOUT; | |
430 | } | |
431 | if (int_status & SPIFLG_DESYNC_MASK) { | |
432 | dev_dbg(sdev, "SPI Desynchronization Error\n"); | |
433 | return -EIO; | |
434 | } | |
435 | if (int_status & SPIFLG_BITERR_MASK) { | |
436 | dev_dbg(sdev, "SPI Bit error\n"); | |
437 | return -EIO; | |
438 | } | |
439 | ||
212d4b69 | 440 | if (dspi->version == SPI_VERSION_2) { |
358934a6 SP |
441 | if (int_status & SPIFLG_DLEN_ERR_MASK) { |
442 | dev_dbg(sdev, "SPI Data Length Error\n"); | |
443 | return -EIO; | |
444 | } | |
445 | if (int_status & SPIFLG_PARERR_MASK) { | |
446 | dev_dbg(sdev, "SPI Parity Error\n"); | |
447 | return -EIO; | |
448 | } | |
449 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
450 | dev_dbg(sdev, "SPI Data Overrun error\n"); | |
451 | return -EIO; | |
452 | } | |
358934a6 SP |
453 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
454 | dev_dbg(sdev, "SPI Buffer Init Active\n"); | |
455 | return -EBUSY; | |
456 | } | |
457 | } | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
e0d205e9 BN |
462 | /** |
463 | * davinci_spi_process_events - check for and handle any SPI controller events | |
212d4b69 | 464 | * @dspi: the controller data |
e0d205e9 BN |
465 | * |
466 | * This function will check the SPIFLG register and handle any events that are | |
467 | * detected there | |
468 | */ | |
212d4b69 | 469 | static int davinci_spi_process_events(struct davinci_spi *dspi) |
e0d205e9 | 470 | { |
212d4b69 | 471 | u32 buf, status, errors = 0, spidat1; |
e0d205e9 | 472 | |
212d4b69 | 473 | buf = ioread32(dspi->base + SPIBUF); |
e0d205e9 | 474 | |
212d4b69 SN |
475 | if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { |
476 | dspi->get_rx(buf & 0xFFFF, dspi); | |
477 | dspi->rcount--; | |
e0d205e9 BN |
478 | } |
479 | ||
212d4b69 | 480 | status = ioread32(dspi->base + SPIFLG); |
e0d205e9 BN |
481 | |
482 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
483 | errors = status & SPIFLG_ERROR_MASK; | |
484 | goto out; | |
485 | } | |
486 | ||
212d4b69 SN |
487 | if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
488 | spidat1 = ioread32(dspi->base + SPIDAT1); | |
489 | dspi->wcount--; | |
490 | spidat1 &= ~0xFFFF; | |
491 | spidat1 |= 0xFFFF & dspi->get_tx(dspi); | |
492 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
e0d205e9 BN |
493 | } |
494 | ||
495 | out: | |
496 | return errors; | |
497 | } | |
498 | ||
87467bd9 BN |
499 | static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) |
500 | { | |
212d4b69 SN |
501 | struct davinci_spi *dspi = data; |
502 | struct davinci_spi_dma *dma = &dspi->dma; | |
87467bd9 BN |
503 | |
504 | edma_stop(lch); | |
505 | ||
506 | if (status == DMA_COMPLETE) { | |
212d4b69 SN |
507 | if (lch == dma->rx_channel) |
508 | dspi->rcount = 0; | |
509 | if (lch == dma->tx_channel) | |
510 | dspi->wcount = 0; | |
87467bd9 BN |
511 | } |
512 | ||
212d4b69 SN |
513 | if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE)) |
514 | complete(&dspi->done); | |
87467bd9 BN |
515 | } |
516 | ||
358934a6 SP |
517 | /** |
518 | * davinci_spi_bufs - functions which will handle transfer data | |
519 | * @spi: spi device on which data transfer to be done | |
520 | * @t: spi transfer in which transfer info is filled | |
521 | * | |
522 | * This function will put data to be transferred into data register | |
523 | * of SPI controller and then wait until the completion will be marked | |
524 | * by the IRQ Handler. | |
525 | */ | |
87467bd9 | 526 | static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) |
358934a6 | 527 | { |
212d4b69 | 528 | struct davinci_spi *dspi; |
87467bd9 | 529 | int data_type, ret; |
212d4b69 | 530 | u32 tx_data, spidat1; |
839c996c | 531 | u32 errors = 0; |
e0d205e9 | 532 | struct davinci_spi_config *spicfg; |
358934a6 | 533 | struct davinci_spi_platform_data *pdata; |
87467bd9 BN |
534 | unsigned uninitialized_var(rx_buf_count); |
535 | struct device *sdev; | |
358934a6 | 536 | |
212d4b69 SN |
537 | dspi = spi_master_get_devdata(spi->master); |
538 | pdata = dspi->pdata; | |
e0d205e9 BN |
539 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
540 | if (!spicfg) | |
541 | spicfg = &davinci_spi_default_cfg; | |
212d4b69 | 542 | sdev = dspi->bitbang.master->dev.parent; |
87467bd9 BN |
543 | |
544 | /* convert len to words based on bits_per_word */ | |
212d4b69 | 545 | data_type = dspi->bytes_per_word[spi->chip_select]; |
358934a6 | 546 | |
212d4b69 SN |
547 | dspi->tx = t->tx_buf; |
548 | dspi->rx = t->rx_buf; | |
549 | dspi->wcount = t->len / data_type; | |
550 | dspi->rcount = dspi->wcount; | |
7978b8c3 | 551 | |
212d4b69 | 552 | spidat1 = ioread32(dspi->base + SPIDAT1); |
839c996c | 553 | |
212d4b69 SN |
554 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); |
555 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
358934a6 | 556 | |
212d4b69 | 557 | INIT_COMPLETION(dspi->done); |
87467bd9 BN |
558 | |
559 | if (spicfg->io_type == SPI_IO_TYPE_INTR) | |
212d4b69 | 560 | set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
cf90fe73 | 561 | |
87467bd9 BN |
562 | if (spicfg->io_type != SPI_IO_TYPE_DMA) { |
563 | /* start the transfer */ | |
212d4b69 SN |
564 | dspi->wcount--; |
565 | tx_data = dspi->get_tx(dspi); | |
566 | spidat1 &= 0xFFFF0000; | |
567 | spidat1 |= tx_data & 0xFFFF; | |
568 | iowrite32(spidat1, dspi->base + SPIDAT1); | |
87467bd9 | 569 | } else { |
212d4b69 | 570 | struct davinci_spi_dma *dma; |
87467bd9 BN |
571 | unsigned long tx_reg, rx_reg; |
572 | struct edmacc_param param; | |
573 | void *rx_buf; | |
574 | ||
212d4b69 | 575 | dma = &dspi->dma; |
87467bd9 | 576 | |
212d4b69 SN |
577 | tx_reg = (unsigned long)dspi->pbase + SPIDAT1; |
578 | rx_reg = (unsigned long)dspi->pbase + SPIBUF; | |
87467bd9 BN |
579 | |
580 | /* | |
581 | * Transmit DMA setup | |
582 | * | |
583 | * If there is transmit data, map the transmit buffer, set it | |
584 | * as the source of data and set the source B index to data | |
585 | * size. If there is no transmit data, set the transmit register | |
586 | * as the source of data, and set the source B index to zero. | |
587 | * | |
588 | * The destination is always the transmit register itself. And | |
589 | * the destination never increments. | |
590 | */ | |
591 | ||
592 | if (t->tx_buf) { | |
593 | t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, | |
212d4b69 | 594 | dspi->wcount, DMA_TO_DEVICE); |
87467bd9 BN |
595 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { |
596 | dev_dbg(sdev, "Unable to DMA map %d bytes" | |
212d4b69 | 597 | "TX buffer\n", dspi->wcount); |
87467bd9 BN |
598 | return -ENOMEM; |
599 | } | |
600 | } | |
601 | ||
212d4b69 | 602 | param.opt = TCINTEN | EDMA_TCC(dma->tx_channel); |
87467bd9 | 603 | param.src = t->tx_buf ? t->tx_dma : tx_reg; |
212d4b69 | 604 | param.a_b_cnt = dspi->wcount << 16 | data_type; |
87467bd9 BN |
605 | param.dst = tx_reg; |
606 | param.src_dst_bidx = t->tx_buf ? data_type : 0; | |
607 | param.link_bcntrld = 0xffff; | |
608 | param.src_dst_cidx = 0; | |
609 | param.ccnt = 1; | |
212d4b69 SN |
610 | edma_write_slot(dma->tx_channel, ¶m); |
611 | edma_link(dma->tx_channel, dma->dummy_param_slot); | |
87467bd9 BN |
612 | |
613 | /* | |
614 | * Receive DMA setup | |
615 | * | |
616 | * If there is receive buffer, use it to receive data. If there | |
617 | * is none provided, use a temporary receive buffer. Set the | |
618 | * destination B index to 0 so effectively only one byte is used | |
619 | * in the temporary buffer (address does not increment). | |
620 | * | |
621 | * The source of receive data is the receive data register. The | |
622 | * source address never increments. | |
623 | */ | |
624 | ||
625 | if (t->rx_buf) { | |
626 | rx_buf = t->rx_buf; | |
212d4b69 | 627 | rx_buf_count = dspi->rcount; |
87467bd9 | 628 | } else { |
212d4b69 SN |
629 | rx_buf = dspi->rx_tmp_buf; |
630 | rx_buf_count = sizeof(dspi->rx_tmp_buf); | |
87467bd9 BN |
631 | } |
632 | ||
633 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count, | |
634 | DMA_FROM_DEVICE); | |
635 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { | |
636 | dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", | |
637 | rx_buf_count); | |
638 | if (t->tx_buf) | |
212d4b69 SN |
639 | dma_unmap_single(NULL, t->tx_dma, dspi->wcount, |
640 | DMA_TO_DEVICE); | |
87467bd9 BN |
641 | return -ENOMEM; |
642 | } | |
643 | ||
212d4b69 | 644 | param.opt = TCINTEN | EDMA_TCC(dma->rx_channel); |
87467bd9 | 645 | param.src = rx_reg; |
212d4b69 | 646 | param.a_b_cnt = dspi->rcount << 16 | data_type; |
87467bd9 BN |
647 | param.dst = t->rx_dma; |
648 | param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; | |
649 | param.link_bcntrld = 0xffff; | |
650 | param.src_dst_cidx = 0; | |
651 | param.ccnt = 1; | |
212d4b69 | 652 | edma_write_slot(dma->rx_channel, ¶m); |
87467bd9 BN |
653 | |
654 | if (pdata->cshold_bug) | |
212d4b69 | 655 | iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); |
87467bd9 | 656 | |
212d4b69 SN |
657 | edma_start(dma->rx_channel); |
658 | edma_start(dma->tx_channel); | |
659 | set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
87467bd9 | 660 | } |
358934a6 | 661 | |
e0d205e9 | 662 | /* Wait for the transfer to complete */ |
87467bd9 | 663 | if (spicfg->io_type != SPI_IO_TYPE_POLL) { |
212d4b69 | 664 | wait_for_completion_interruptible(&(dspi->done)); |
e0d205e9 | 665 | } else { |
212d4b69 SN |
666 | while (dspi->rcount > 0 || dspi->wcount > 0) { |
667 | errors = davinci_spi_process_events(dspi); | |
e0d205e9 BN |
668 | if (errors) |
669 | break; | |
670 | cpu_relax(); | |
358934a6 SP |
671 | } |
672 | } | |
673 | ||
212d4b69 | 674 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); |
87467bd9 BN |
675 | if (spicfg->io_type == SPI_IO_TYPE_DMA) { |
676 | ||
677 | if (t->tx_buf) | |
212d4b69 | 678 | dma_unmap_single(NULL, t->tx_dma, dspi->wcount, |
87467bd9 BN |
679 | DMA_TO_DEVICE); |
680 | ||
681 | dma_unmap_single(NULL, t->rx_dma, rx_buf_count, | |
682 | DMA_FROM_DEVICE); | |
683 | ||
212d4b69 | 684 | clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); |
87467bd9 | 685 | } |
e0d205e9 | 686 | |
212d4b69 SN |
687 | clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
688 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
3f27b57c | 689 | |
358934a6 SP |
690 | /* |
691 | * Check for bit error, desync error,parity error,timeout error and | |
692 | * receive overflow errors | |
693 | */ | |
839c996c | 694 | if (errors) { |
212d4b69 | 695 | ret = davinci_spi_check_error(dspi, errors); |
839c996c BN |
696 | WARN(!ret, "%s: error reported but no error found!\n", |
697 | dev_name(&spi->dev)); | |
358934a6 | 698 | return ret; |
839c996c | 699 | } |
358934a6 | 700 | |
212d4b69 | 701 | if (dspi->rcount != 0 || dspi->wcount != 0) { |
87467bd9 BN |
702 | dev_err(sdev, "SPI data transfer error\n"); |
703 | return -EIO; | |
704 | } | |
705 | ||
358934a6 SP |
706 | return t->len; |
707 | } | |
708 | ||
e0d205e9 BN |
709 | /** |
710 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
711 | * @irq: IRQ number for this SPI Master | |
712 | * @context_data: structure for SPI Master controller davinci_spi | |
713 | * | |
714 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
715 | * According to command it will do the appropriate action. It will check | |
716 | * transfer length and if it is not zero then dispatch transfer command again. | |
717 | * If transfer length is zero then it will indicate the COMPLETION so that | |
718 | * davinci_spi_bufs function can go ahead. | |
719 | */ | |
212d4b69 | 720 | static irqreturn_t davinci_spi_irq(s32 irq, void *data) |
e0d205e9 | 721 | { |
212d4b69 | 722 | struct davinci_spi *dspi = data; |
e0d205e9 BN |
723 | int status; |
724 | ||
212d4b69 | 725 | status = davinci_spi_process_events(dspi); |
e0d205e9 | 726 | if (unlikely(status != 0)) |
212d4b69 | 727 | clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); |
e0d205e9 | 728 | |
212d4b69 SN |
729 | if ((!dspi->rcount && !dspi->wcount) || status) |
730 | complete(&dspi->done); | |
e0d205e9 BN |
731 | |
732 | return IRQ_HANDLED; | |
733 | } | |
734 | ||
212d4b69 | 735 | static int davinci_spi_request_dma(struct davinci_spi *dspi) |
903ca25b SN |
736 | { |
737 | int r; | |
212d4b69 | 738 | struct davinci_spi_dma *dma = &dspi->dma; |
903ca25b | 739 | |
212d4b69 SN |
740 | r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi, |
741 | dma->eventq); | |
903ca25b SN |
742 | if (r < 0) { |
743 | pr_err("Unable to request DMA channel for SPI RX\n"); | |
523c37e7 BN |
744 | r = -EAGAIN; |
745 | goto rx_dma_failed; | |
903ca25b SN |
746 | } |
747 | ||
212d4b69 SN |
748 | r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi, |
749 | dma->eventq); | |
903ca25b | 750 | if (r < 0) { |
903ca25b | 751 | pr_err("Unable to request DMA channel for SPI TX\n"); |
523c37e7 BN |
752 | r = -EAGAIN; |
753 | goto tx_dma_failed; | |
903ca25b SN |
754 | } |
755 | ||
212d4b69 | 756 | r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY); |
523c37e7 BN |
757 | if (r < 0) { |
758 | pr_err("Unable to request SPI TX DMA param slot\n"); | |
759 | r = -EAGAIN; | |
760 | goto param_failed; | |
761 | } | |
212d4b69 SN |
762 | dma->dummy_param_slot = r; |
763 | edma_link(dma->dummy_param_slot, dma->dummy_param_slot); | |
523c37e7 | 764 | |
903ca25b | 765 | return 0; |
523c37e7 | 766 | param_failed: |
212d4b69 | 767 | edma_free_channel(dma->tx_channel); |
523c37e7 | 768 | tx_dma_failed: |
212d4b69 | 769 | edma_free_channel(dma->rx_channel); |
523c37e7 BN |
770 | rx_dma_failed: |
771 | return r; | |
903ca25b SN |
772 | } |
773 | ||
358934a6 SP |
774 | /** |
775 | * davinci_spi_probe - probe function for SPI Master Controller | |
776 | * @pdev: platform_device structure which contains plateform specific data | |
035540f6 BN |
777 | * |
778 | * According to Linux Device Model this function will be invoked by Linux | |
779 | * with platform_device struct which contains the device specific info. | |
780 | * This function will map the SPI controller's memory, register IRQ, | |
781 | * Reset SPI controller and setting its registers to default value. | |
782 | * It will invoke spi_bitbang_start to create work queue so that client driver | |
783 | * can register transfer method to work queue. | |
358934a6 SP |
784 | */ |
785 | static int davinci_spi_probe(struct platform_device *pdev) | |
786 | { | |
787 | struct spi_master *master; | |
212d4b69 | 788 | struct davinci_spi *dspi; |
358934a6 SP |
789 | struct davinci_spi_platform_data *pdata; |
790 | struct resource *r, *mem; | |
791 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; | |
792 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; | |
793 | resource_size_t dma_eventq = SPI_NO_RESOURCE; | |
794 | int i = 0, ret = 0; | |
f34bd4cc | 795 | u32 spipc0; |
358934a6 SP |
796 | |
797 | pdata = pdev->dev.platform_data; | |
798 | if (pdata == NULL) { | |
799 | ret = -ENODEV; | |
800 | goto err; | |
801 | } | |
802 | ||
803 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); | |
804 | if (master == NULL) { | |
805 | ret = -ENOMEM; | |
806 | goto err; | |
807 | } | |
808 | ||
809 | dev_set_drvdata(&pdev->dev, master); | |
810 | ||
212d4b69 SN |
811 | dspi = spi_master_get_devdata(master); |
812 | if (dspi == NULL) { | |
358934a6 SP |
813 | ret = -ENOENT; |
814 | goto free_master; | |
815 | } | |
816 | ||
817 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
818 | if (r == NULL) { | |
819 | ret = -ENOENT; | |
820 | goto free_master; | |
821 | } | |
822 | ||
212d4b69 SN |
823 | dspi->pbase = r->start; |
824 | dspi->pdata = pdata; | |
358934a6 | 825 | |
0e0eae4d | 826 | mem = request_mem_region(r->start, resource_size(r), pdev->name); |
358934a6 SP |
827 | if (mem == NULL) { |
828 | ret = -EBUSY; | |
829 | goto free_master; | |
830 | } | |
831 | ||
212d4b69 SN |
832 | dspi->base = ioremap(r->start, resource_size(r)); |
833 | if (dspi->base == NULL) { | |
358934a6 SP |
834 | ret = -ENOMEM; |
835 | goto release_region; | |
836 | } | |
837 | ||
212d4b69 SN |
838 | dspi->irq = platform_get_irq(pdev, 0); |
839 | if (dspi->irq <= 0) { | |
e0d205e9 BN |
840 | ret = -EINVAL; |
841 | goto unmap_io; | |
842 | } | |
843 | ||
212d4b69 SN |
844 | ret = request_irq(dspi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev), |
845 | dspi); | |
e0d205e9 BN |
846 | if (ret) |
847 | goto unmap_io; | |
848 | ||
212d4b69 SN |
849 | dspi->bitbang.master = spi_master_get(master); |
850 | if (dspi->bitbang.master == NULL) { | |
358934a6 | 851 | ret = -ENODEV; |
d3f7141c | 852 | goto irq_free; |
358934a6 SP |
853 | } |
854 | ||
212d4b69 SN |
855 | dspi->clk = clk_get(&pdev->dev, NULL); |
856 | if (IS_ERR(dspi->clk)) { | |
358934a6 SP |
857 | ret = -ENODEV; |
858 | goto put_master; | |
859 | } | |
212d4b69 | 860 | clk_enable(dspi->clk); |
358934a6 | 861 | |
358934a6 SP |
862 | master->bus_num = pdev->id; |
863 | master->num_chipselect = pdata->num_chipselect; | |
864 | master->setup = davinci_spi_setup; | |
358934a6 | 865 | |
212d4b69 SN |
866 | dspi->bitbang.chipselect = davinci_spi_chipselect; |
867 | dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
358934a6 | 868 | |
212d4b69 | 869 | dspi->version = pdata->version; |
358934a6 | 870 | |
212d4b69 SN |
871 | dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; |
872 | if (dspi->version == SPI_VERSION_2) | |
873 | dspi->bitbang.flags |= SPI_READY; | |
358934a6 | 874 | |
903ca25b SN |
875 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
876 | if (r) | |
877 | dma_rx_chan = r->start; | |
878 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
879 | if (r) | |
880 | dma_tx_chan = r->start; | |
881 | r = platform_get_resource(pdev, IORESOURCE_DMA, 2); | |
882 | if (r) | |
883 | dma_eventq = r->start; | |
884 | ||
212d4b69 | 885 | dspi->bitbang.txrx_bufs = davinci_spi_bufs; |
903ca25b SN |
886 | if (dma_rx_chan != SPI_NO_RESOURCE && |
887 | dma_tx_chan != SPI_NO_RESOURCE && | |
888 | dma_eventq != SPI_NO_RESOURCE) { | |
212d4b69 SN |
889 | dspi->dma.rx_channel = dma_rx_chan; |
890 | dspi->dma.tx_channel = dma_tx_chan; | |
891 | dspi->dma.eventq = dma_eventq; | |
96fd881f | 892 | |
212d4b69 | 893 | ret = davinci_spi_request_dma(dspi); |
903ca25b SN |
894 | if (ret) |
895 | goto free_clk; | |
896 | ||
87467bd9 BN |
897 | dev_info(&pdev->dev, "DMA: supported\n"); |
898 | dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, " | |
899 | "event queue: %d\n", dma_rx_chan, dma_tx_chan, | |
358934a6 SP |
900 | dma_eventq); |
901 | } | |
902 | ||
212d4b69 SN |
903 | dspi->get_rx = davinci_spi_rx_buf_u8; |
904 | dspi->get_tx = davinci_spi_tx_buf_u8; | |
358934a6 | 905 | |
212d4b69 | 906 | init_completion(&dspi->done); |
e0d205e9 | 907 | |
358934a6 | 908 | /* Reset In/OUT SPI module */ |
212d4b69 | 909 | iowrite32(0, dspi->base + SPIGCR0); |
358934a6 | 910 | udelay(100); |
212d4b69 | 911 | iowrite32(1, dspi->base + SPIGCR0); |
358934a6 | 912 | |
be88471b | 913 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc | 914 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
212d4b69 | 915 | iowrite32(spipc0, dspi->base + SPIPC0); |
f34bd4cc | 916 | |
23853973 BN |
917 | /* initialize chip selects */ |
918 | if (pdata->chip_sel) { | |
919 | for (i = 0; i < pdata->num_chipselect; i++) { | |
920 | if (pdata->chip_sel[i] != SPI_INTERN_CS) | |
921 | gpio_direction_output(pdata->chip_sel[i], 1); | |
922 | } | |
923 | } | |
924 | ||
e0d205e9 | 925 | if (pdata->intr_line) |
212d4b69 | 926 | iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); |
e0d205e9 | 927 | else |
212d4b69 | 928 | iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); |
e0d205e9 | 929 | |
212d4b69 | 930 | iowrite32(CS_DEFAULT, dspi->base + SPIDEF); |
843a713b | 931 | |
358934a6 | 932 | /* master mode default */ |
212d4b69 SN |
933 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); |
934 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
935 | set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); | |
358934a6 | 936 | |
212d4b69 | 937 | ret = spi_bitbang_start(&dspi->bitbang); |
358934a6 | 938 | if (ret) |
903ca25b | 939 | goto free_dma; |
358934a6 | 940 | |
212d4b69 | 941 | dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); |
358934a6 | 942 | |
358934a6 SP |
943 | return ret; |
944 | ||
903ca25b | 945 | free_dma: |
212d4b69 SN |
946 | edma_free_channel(dspi->dma.tx_channel); |
947 | edma_free_channel(dspi->dma.rx_channel); | |
948 | edma_free_slot(dspi->dma.dummy_param_slot); | |
358934a6 | 949 | free_clk: |
212d4b69 SN |
950 | clk_disable(dspi->clk); |
951 | clk_put(dspi->clk); | |
358934a6 SP |
952 | put_master: |
953 | spi_master_put(master); | |
e0d205e9 | 954 | irq_free: |
212d4b69 | 955 | free_irq(dspi->irq, dspi); |
358934a6 | 956 | unmap_io: |
212d4b69 | 957 | iounmap(dspi->base); |
358934a6 | 958 | release_region: |
212d4b69 | 959 | release_mem_region(dspi->pbase, resource_size(r)); |
358934a6 SP |
960 | free_master: |
961 | kfree(master); | |
962 | err: | |
963 | return ret; | |
964 | } | |
965 | ||
966 | /** | |
967 | * davinci_spi_remove - remove function for SPI Master Controller | |
968 | * @pdev: platform_device structure which contains plateform specific data | |
969 | * | |
970 | * This function will do the reverse action of davinci_spi_probe function | |
971 | * It will free the IRQ and SPI controller's memory region. | |
972 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
973 | * created by spi_bitbang_start. | |
974 | */ | |
975 | static int __exit davinci_spi_remove(struct platform_device *pdev) | |
976 | { | |
212d4b69 | 977 | struct davinci_spi *dspi; |
358934a6 | 978 | struct spi_master *master; |
0e0eae4d | 979 | struct resource *r; |
358934a6 SP |
980 | |
981 | master = dev_get_drvdata(&pdev->dev); | |
212d4b69 | 982 | dspi = spi_master_get_devdata(master); |
358934a6 | 983 | |
212d4b69 | 984 | spi_bitbang_stop(&dspi->bitbang); |
358934a6 | 985 | |
212d4b69 SN |
986 | clk_disable(dspi->clk); |
987 | clk_put(dspi->clk); | |
358934a6 | 988 | spi_master_put(master); |
212d4b69 SN |
989 | free_irq(dspi->irq, dspi); |
990 | iounmap(dspi->base); | |
0e0eae4d | 991 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
212d4b69 | 992 | release_mem_region(dspi->pbase, resource_size(r)); |
358934a6 SP |
993 | |
994 | return 0; | |
995 | } | |
996 | ||
997 | static struct platform_driver davinci_spi_driver = { | |
d8c174cd BN |
998 | .driver = { |
999 | .name = "spi_davinci", | |
1000 | .owner = THIS_MODULE, | |
1001 | }, | |
358934a6 SP |
1002 | .remove = __exit_p(davinci_spi_remove), |
1003 | }; | |
1004 | ||
1005 | static int __init davinci_spi_init(void) | |
1006 | { | |
1007 | return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe); | |
1008 | } | |
1009 | module_init(davinci_spi_init); | |
1010 | ||
1011 | static void __exit davinci_spi_exit(void) | |
1012 | { | |
1013 | platform_driver_unregister(&davinci_spi_driver); | |
1014 | } | |
1015 | module_exit(davinci_spi_exit); | |
1016 | ||
1017 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1018 | MODULE_LICENSE("GPL"); |