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spi: davinci: remove unnecessary completion variable initialization
[deliverable/linux.git] / drivers / spi / davinci_spi.c
CommitLineData
358934a6
SP		 1/*
2 * Copyright (C) 2009 Texas Instruments.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/module.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/err.h>
26#include <linux/clk.h>
27#include <linux/dma-mapping.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/spi_bitbang.h>
5a0e3ad6 30#include <linux/slab.h>
358934a6
SP		 31
32#include <mach/spi.h>
33#include <mach/edma.h>
34
35#define SPI_NO_RESOURCE ((resource_size_t)-1)
36
37#define SPI_MAX_CHIPSELECT 2
38
39#define CS_DEFAULT 0xFF
40
41#define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
358934a6
SP		 42
43#define SPIFMT_PHASE_MASK BIT(16)
44#define SPIFMT_POLARITY_MASK BIT(17)
45#define SPIFMT_DISTIMER_MASK BIT(18)
46#define SPIFMT_SHIFTDIR_MASK BIT(20)
47#define SPIFMT_WAITENA_MASK BIT(21)
48#define SPIFMT_PARITYENA_MASK BIT(22)
49#define SPIFMT_ODD_PARITY_MASK BIT(23)
50#define SPIFMT_WDELAY_MASK 0x3f000000u
51#define SPIFMT_WDELAY_SHIFT 24
7fe0092b 52#define SPIFMT_PRESCALE_SHIFT 8
358934a6 53
358934a6
SP		 54
55/* SPIPC0 */
56#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
57#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
58#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
59#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
358934a6
SP		 60
61#define SPIINT_MASKALL 0x0101035F
62#define SPI_INTLVL_1 0x000001FFu
63#define SPI_INTLVL_0 0x00000000u
64
cfbc5d1d
BN		 65/* SPIDAT1 (upper 16 bit defines) */
66#define SPIDAT1_CSHOLD_MASK BIT(12)
67
68/* SPIGCR1 */
358934a6
SP		 69#define SPIGCR1_CLKMOD_MASK BIT(1)
70#define SPIGCR1_MASTER_MASK BIT(0)
71#define SPIGCR1_LOOPBACK_MASK BIT(16)
8e206f1c 72#define SPIGCR1_SPIENA_MASK BIT(24)
358934a6
SP		 73
74/* SPIBUF */
75#define SPIBUF_TXFULL_MASK BIT(29)
76#define SPIBUF_RXEMPTY_MASK BIT(31)
77
7abbf23c
BN		 78/* SPIDELAY */
79#define SPIDELAY_C2TDELAY_SHIFT 24
80#define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
81#define SPIDELAY_T2CDELAY_SHIFT 16
82#define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
83#define SPIDELAY_T2EDELAY_SHIFT 8
84#define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
85#define SPIDELAY_C2EDELAY_SHIFT 0
86#define SPIDELAY_C2EDELAY_MASK 0xFF
87
358934a6
SP		 88/* Error Masks */
89#define SPIFLG_DLEN_ERR_MASK BIT(0)
90#define SPIFLG_TIMEOUT_MASK BIT(1)
91#define SPIFLG_PARERR_MASK BIT(2)
92#define SPIFLG_DESYNC_MASK BIT(3)
93#define SPIFLG_BITERR_MASK BIT(4)
94#define SPIFLG_OVRRUN_MASK BIT(6)
95#define SPIFLG_RX_INTR_MASK BIT(8)
96#define SPIFLG_TX_INTR_MASK BIT(9)
97#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
8e206f1c 98
358934a6
SP		 99#define SPIINT_BITERR_INTR BIT(4)
100#define SPIINT_OVRRUN_INTR BIT(6)
101#define SPIINT_RX_INTR BIT(8)
102#define SPIINT_TX_INTR BIT(9)
103#define SPIINT_DMA_REQ_EN BIT(16)
358934a6 104
358934a6
SP		 105/* SPI Controller registers */
106#define SPIGCR0 0x00
107#define SPIGCR1 0x04
108#define SPIINT 0x08
109#define SPILVL 0x0c
110#define SPIFLG 0x10
111#define SPIPC0 0x14
358934a6
SP		 112#define SPIDAT1 0x3c
113#define SPIBUF 0x40
358934a6
SP		 114#define SPIDELAY 0x48
115#define SPIDEF 0x4c
116#define SPIFMT0 0x50
358934a6 117
358934a6
SP		 118/* We have 2 DMA channels per CS, one for RX and one for TX */
119struct davinci_spi_dma {
120 int dma_tx_channel;
121 int dma_rx_channel;
122 int dma_tx_sync_dev;
123 int dma_rx_sync_dev;
124 enum dma_event_q eventq;
125
126 struct completion dma_tx_completion;
127 struct completion dma_rx_completion;
128};
129
130/* SPI Controller driver's private data. */
131struct davinci_spi {
132 struct spi_bitbang bitbang;
133 struct clk *clk;
134
135 u8 version;
136 resource_size_t pbase;
137 void __iomem *base;
138 size_t region_size;
139 u32 irq;
140 struct completion done;
141
142 const void *tx;
143 void *rx;
144 u8 *tmp_buf;
358934a6 145 struct davinci_spi_dma *dma_channels;
778e261e 146 struct davinci_spi_platform_data *pdata;
358934a6
SP		 147
148 void (*get_rx)(u32 rx_data, struct davinci_spi *);
149 u32 (*get_tx)(struct davinci_spi *);
150
cda987eb 151 u8 bytes_per_word[SPI_MAX_CHIPSELECT];
358934a6
SP		 152};
153
53a31b07
BN		 154static struct davinci_spi_config davinci_spi_default_cfg;
155
358934a6
SP		 156static unsigned use_dma;
157
158static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
159{
53d454a1
BN		 160 if (davinci_spi->rx) {
161 u8 *rx = davinci_spi->rx;
162 *rx++ = (u8)data;
163 davinci_spi->rx = rx;
164 }
358934a6
SP		 165}
166
167static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
168{
53d454a1
BN		 169 if (davinci_spi->rx) {
170 u16 *rx = davinci_spi->rx;
171 *rx++ = (u16)data;
172 davinci_spi->rx = rx;
173 }
358934a6
SP		 174}
175
176static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
177{
53d454a1
BN		 178 u32 data = 0;
179 if (davinci_spi->tx) {
180 const u8 *tx = davinci_spi->tx;
181 data = *tx++;
182 davinci_spi->tx = tx;
183 }
358934a6
SP		 184 return data;
185}
186
187static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
188{
53d454a1
BN		 189 u32 data = 0;
190 if (davinci_spi->tx) {
191 const u16 *tx = davinci_spi->tx;
192 data = *tx++;
193 davinci_spi->tx = tx;
194 }
358934a6
SP		 195 return data;
196}
197
198static inline void set_io_bits(void __iomem *addr, u32 bits)
199{
200 u32 v = ioread32(addr);
201
202 v |= bits;
203 iowrite32(v, addr);
204}
205
206static inline void clear_io_bits(void __iomem *addr, u32 bits)
207{
208 u32 v = ioread32(addr);
209
210 v &= ~bits;
211 iowrite32(v, addr);
212}
213
358934a6
SP		 214static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
215{
216 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
217
218 if (enable)
219 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
220 else
221 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
222}
223
224/*
225 * Interface to control the chip select signal
226 */
227static void davinci_spi_chipselect(struct spi_device *spi, int value)
228{
229 struct davinci_spi *davinci_spi;
230 struct davinci_spi_platform_data *pdata;
7978b8c3 231 u8 chip_sel = spi->chip_select;
cfbc5d1d 232 u16 spidat1_cfg = CS_DEFAULT;
23853973 233 bool gpio_chipsel = false;
358934a6
SP		 234
235 davinci_spi = spi_master_get_devdata(spi->master);
236 pdata = davinci_spi->pdata;
237
23853973
BN		 238 if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
239 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
240 gpio_chipsel = true;
241
358934a6
SP		 242 /*
243 * Board specific chip select logic decides the polarity and cs
244 * line for the controller
245 */
23853973
BN		 246 if (gpio_chipsel) {
247 if (value == BITBANG_CS_ACTIVE)
248 gpio_set_value(pdata->chip_sel[chip_sel], 0);
249 else
250 gpio_set_value(pdata->chip_sel[chip_sel], 1);
251 } else {
252 if (value == BITBANG_CS_ACTIVE) {
253 spidat1_cfg |= SPIDAT1_CSHOLD_MASK;
254 spidat1_cfg &= ~(0x1 << chip_sel);
255 }
7978b8c3 256
23853973
BN		 257 iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2);
258 }
358934a6
SP		 259}
260
7fe0092b
BN		 261/**
262 * davinci_spi_get_prescale - Calculates the correct prescale value
263 * @maxspeed_hz: the maximum rate the SPI clock can run at
264 *
265 * This function calculates the prescale value that generates a clock rate
266 * less than or equal to the specified maximum.
267 *
268 * Returns: calculated prescale - 1 for easy programming into SPI registers
269 * or negative error number if valid prescalar cannot be updated.
270 */
271static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi,
272 u32 max_speed_hz)
273{
274 int ret;
275
276 ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz);
277
278 if (ret < 3 || ret > 256)
279 return -EINVAL;
280
281 return ret - 1;
282}
283
358934a6
SP		 284/**
285 * davinci_spi_setup_transfer - This functions will determine transfer method
286 * @spi: spi device on which data transfer to be done
287 * @t: spi transfer in which transfer info is filled
288 *
289 * This function determines data transfer method (8/16/32 bit transfer).
290 * It will also set the SPI Clock Control register according to
291 * SPI slave device freq.
292 */
293static int davinci_spi_setup_transfer(struct spi_device *spi,
294 struct spi_transfer *t)
295{
296
297 struct davinci_spi *davinci_spi;
25f33512 298 struct davinci_spi_config *spicfg;
358934a6 299 u8 bits_per_word = 0;
25f33512 300 u32 hz = 0, spifmt = 0, prescale = 0;
358934a6
SP		 301
302 davinci_spi = spi_master_get_devdata(spi->master);
25f33512
BN		 303 spicfg = (struct davinci_spi_config *)spi->controller_data;
304 if (!spicfg)
305 spicfg = &davinci_spi_default_cfg;
358934a6
SP		 306
307 if (t) {
308 bits_per_word = t->bits_per_word;
309 hz = t->speed_hz;
310 }
311
312 /* if bits_per_word is not set then set it default */
313 if (!bits_per_word)
314 bits_per_word = spi->bits_per_word;
315
316 /*
317 * Assign function pointer to appropriate transfer method
318 * 8bit, 16bit or 32bit transfer
319 */
320 if (bits_per_word <= 8 && bits_per_word >= 2) {
321 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
322 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
cda987eb 323 davinci_spi->bytes_per_word[spi->chip_select] = 1;
358934a6
SP		 324 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
325 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
326 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
cda987eb 327 davinci_spi->bytes_per_word[spi->chip_select] = 2;
358934a6
SP		 328 } else
329 return -EINVAL;
330
331 if (!hz)
332 hz = spi->max_speed_hz;
333
25f33512
BN		 334 /* Set up SPIFMTn register, unique to this chipselect. */
335
7fe0092b
BN		 336 prescale = davinci_spi_get_prescale(davinci_spi, hz);
337 if (prescale < 0)
338 return prescale;
339
25f33512
BN		 340 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
341
342 if (spi->mode & SPI_LSB_FIRST)
343 spifmt |= SPIFMT_SHIFTDIR_MASK;
344
345 if (spi->mode & SPI_CPOL)
346 spifmt |= SPIFMT_POLARITY_MASK;
347
348 if (!(spi->mode & SPI_CPHA))
349 spifmt |= SPIFMT_PHASE_MASK;
350
351 /*
352 * Version 1 hardware supports two basic SPI modes:
353 * - Standard SPI mode uses 4 pins, with chipselect
354 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
355 * (distinct from SPI_3WIRE, with just one data wire;
356 * or similar variants without MOSI or without MISO)
357 *
358 * Version 2 hardware supports an optional handshaking signal,
359 * so it can support two more modes:
360 * - 5 pin SPI variant is standard SPI plus SPI_READY
361 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
362 */
363
364 if (davinci_spi->version == SPI_VERSION_2) {
365
7abbf23c
BN		 366 u32 delay = 0;
367
25f33512
BN		 368 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
369 & SPIFMT_WDELAY_MASK);
358934a6 370
25f33512
BN		 371 if (spicfg->odd_parity)
372 spifmt |= SPIFMT_ODD_PARITY_MASK;
373
374 if (spicfg->parity_enable)
375 spifmt |= SPIFMT_PARITYENA_MASK;
376
7abbf23c 377 if (spicfg->timer_disable) {
25f33512 378 spifmt |= SPIFMT_DISTIMER_MASK;
7abbf23c
BN		 379 } else {
380 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
381 & SPIDELAY_C2TDELAY_MASK;
382 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
383 & SPIDELAY_T2CDELAY_MASK;
384 }
25f33512 385
7abbf23c 386 if (spi->mode & SPI_READY) {
25f33512 387 spifmt |= SPIFMT_WAITENA_MASK;
7abbf23c
BN		 388 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
389 & SPIDELAY_T2EDELAY_MASK;
390 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
391 & SPIDELAY_C2EDELAY_MASK;
392 }
393
394 iowrite32(delay, davinci_spi->base + SPIDELAY);
25f33512
BN		 395 }
396
397 iowrite32(spifmt, davinci_spi->base + SPIFMT0);
358934a6
SP		 398
399 return 0;
400}
401
402static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
403{
404 struct spi_device *spi = (struct spi_device *)data;
405 struct davinci_spi *davinci_spi;
406 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 407
408 davinci_spi = spi_master_get_devdata(spi->master);
409 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
358934a6
SP		 410
411 if (ch_status == DMA_COMPLETE)
412 edma_stop(davinci_spi_dma->dma_rx_channel);
413 else
414 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
415
416 complete(&davinci_spi_dma->dma_rx_completion);
417 /* We must disable the DMA RX request */
418 davinci_spi_set_dma_req(spi, 0);
419}
420
421static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
422{
423 struct spi_device *spi = (struct spi_device *)data;
424 struct davinci_spi *davinci_spi;
425 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 426
427 davinci_spi = spi_master_get_devdata(spi->master);
428 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
358934a6
SP		 429
430 if (ch_status == DMA_COMPLETE)
431 edma_stop(davinci_spi_dma->dma_tx_channel);
432 else
433 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
434
435 complete(&davinci_spi_dma->dma_tx_completion);
436 /* We must disable the DMA TX request */
437 davinci_spi_set_dma_req(spi, 0);
438}
439
440static int davinci_spi_request_dma(struct spi_device *spi)
441{
442 struct davinci_spi *davinci_spi;
443 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 444 struct device *sdev;
445 int r;
446
447 davinci_spi = spi_master_get_devdata(spi->master);
448 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
358934a6
SP		 449 sdev = davinci_spi->bitbang.master->dev.parent;
450
451 r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
452 davinci_spi_dma_rx_callback, spi,
453 davinci_spi_dma->eventq);
454 if (r < 0) {
455 dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
456 return -EAGAIN;
457 }
458 davinci_spi_dma->dma_rx_channel = r;
459 r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
460 davinci_spi_dma_tx_callback, spi,
461 davinci_spi_dma->eventq);
462 if (r < 0) {
463 edma_free_channel(davinci_spi_dma->dma_rx_channel);
464 davinci_spi_dma->dma_rx_channel = -1;
465 dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
466 return -EAGAIN;
467 }
468 davinci_spi_dma->dma_tx_channel = r;
469
470 return 0;
471}
472
473/**
474 * davinci_spi_setup - This functions will set default transfer method
475 * @spi: spi device on which data transfer to be done
476 *
477 * This functions sets the default transfer method.
478 */
358934a6
SP		 479static int davinci_spi_setup(struct spi_device *spi)
480{
481 int retval;
482 struct davinci_spi *davinci_spi;
483 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 484
485 davinci_spi = spi_master_get_devdata(spi->master);
358934a6
SP		 486
487 /* if bits per word length is zero then set it default 8 */
488 if (!spi->bits_per_word)
489 spi->bits_per_word = 8;
490
358934a6
SP		 491 if (use_dma && davinci_spi->dma_channels) {
492 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
493
494 if ((davinci_spi_dma->dma_rx_channel == -1)
495 || (davinci_spi_dma->dma_tx_channel == -1)) {
496 retval = davinci_spi_request_dma(spi);
497 if (retval < 0)
498 return retval;
499 }
500 }
501
358934a6
SP		 502 retval = davinci_spi_setup_transfer(spi, NULL);
503
504 return retval;
505}
506
507static void davinci_spi_cleanup(struct spi_device *spi)
508{
509 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
510 struct davinci_spi_dma *davinci_spi_dma;
511
512 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
513
514 if (use_dma && davinci_spi->dma_channels) {
515 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
516
517 if ((davinci_spi_dma->dma_rx_channel != -1)
518 && (davinci_spi_dma->dma_tx_channel != -1)) {
519 edma_free_channel(davinci_spi_dma->dma_tx_channel);
520 edma_free_channel(davinci_spi_dma->dma_rx_channel);
521 }
522 }
523}
524
525static int davinci_spi_bufs_prep(struct spi_device *spi,
526 struct davinci_spi *davinci_spi)
527{
23853973 528 struct davinci_spi_platform_data *pdata;
358934a6
SP		 529 int op_mode = 0;
530
531 /*
532 * REVISIT unless devices disagree about SPI_LOOP or
533 * SPI_READY (SPI_NO_CS only allows one device!), this
534 * should not need to be done before each message...
535 * optimize for both flags staying cleared.
536 */
537
538 op_mode = SPIPC0_DIFUN_MASK
539 | SPIPC0_DOFUN_MASK
540 | SPIPC0_CLKFUN_MASK;
23853973
BN		 541 if (!(spi->mode & SPI_NO_CS)) {
542 pdata = davinci_spi->pdata;
543 if (!pdata->chip_sel ||
544 pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)
545 op_mode |= 1 << spi->chip_select;
546 }
358934a6
SP		 547 if (spi->mode & SPI_READY)
548 op_mode |= SPIPC0_SPIENA_MASK;
549
550 iowrite32(op_mode, davinci_spi->base + SPIPC0);
551
552 if (spi->mode & SPI_LOOP)
553 set_io_bits(davinci_spi->base + SPIGCR1,
554 SPIGCR1_LOOPBACK_MASK);
555 else
556 clear_io_bits(davinci_spi->base + SPIGCR1,
557 SPIGCR1_LOOPBACK_MASK);
558
559 return 0;
560}
561
562static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
563 int int_status)
564{
565 struct device *sdev = davinci_spi->bitbang.master->dev.parent;
566
567 if (int_status & SPIFLG_TIMEOUT_MASK) {
568 dev_dbg(sdev, "SPI Time-out Error\n");
569 return -ETIMEDOUT;
570 }
571 if (int_status & SPIFLG_DESYNC_MASK) {
572 dev_dbg(sdev, "SPI Desynchronization Error\n");
573 return -EIO;
574 }
575 if (int_status & SPIFLG_BITERR_MASK) {
576 dev_dbg(sdev, "SPI Bit error\n");
577 return -EIO;
578 }
579
580 if (davinci_spi->version == SPI_VERSION_2) {
581 if (int_status & SPIFLG_DLEN_ERR_MASK) {
582 dev_dbg(sdev, "SPI Data Length Error\n");
583 return -EIO;
584 }
585 if (int_status & SPIFLG_PARERR_MASK) {
586 dev_dbg(sdev, "SPI Parity Error\n");
587 return -EIO;
588 }
589 if (int_status & SPIFLG_OVRRUN_MASK) {
590 dev_dbg(sdev, "SPI Data Overrun error\n");
591 return -EIO;
592 }
358934a6
SP		 593 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
594 dev_dbg(sdev, "SPI Buffer Init Active\n");
595 return -EBUSY;
596 }
597 }
598
599 return 0;
600}
601
602/**
603 * davinci_spi_bufs - functions which will handle transfer data
604 * @spi: spi device on which data transfer to be done
605 * @t: spi transfer in which transfer info is filled
606 *
607 * This function will put data to be transferred into data register
608 * of SPI controller and then wait until the completion will be marked
609 * by the IRQ Handler.
610 */
611static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
612{
613 struct davinci_spi *davinci_spi;
614 int int_status, count, ret;
7978b8c3 615 u8 conv;
358934a6
SP		 616 u32 tx_data, data1_reg_val;
617 u32 buf_val, flg_val;
618 struct davinci_spi_platform_data *pdata;
619
620 davinci_spi = spi_master_get_devdata(spi->master);
621 pdata = davinci_spi->pdata;
622
623 davinci_spi->tx = t->tx_buf;
624 davinci_spi->rx = t->rx_buf;
625
626 /* convert len to words based on bits_per_word */
cda987eb 627 conv = davinci_spi->bytes_per_word[spi->chip_select];
7978b8c3
BN		 628 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
629
358934a6
SP		 630 INIT_COMPLETION(davinci_spi->done);
631
632 ret = davinci_spi_bufs_prep(spi, davinci_spi);
633 if (ret)
634 return ret;
635
636 /* Enable SPI */
637 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
638
f2bf4e84 639 count = t->len / conv;
358934a6
SP		 640
641 /* Determine the command to execute READ or WRITE */
642 if (t->tx_buf) {
643 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
644
645 while (1) {
646 tx_data = davinci_spi->get_tx(davinci_spi);
647
648 data1_reg_val &= ~(0xFFFF);
649 data1_reg_val |= (0xFFFF & tx_data);
650
651 buf_val = ioread32(davinci_spi->base + SPIBUF);
652 if ((buf_val & SPIBUF_TXFULL_MASK) == 0) {
653 iowrite32(data1_reg_val,
654 davinci_spi->base + SPIDAT1);
655
656 count--;
657 }
658 while (ioread32(davinci_spi->base + SPIBUF)
659 & SPIBUF_RXEMPTY_MASK)
660 cpu_relax();
661
662 /* getting the returned byte */
663 if (t->rx_buf) {
664 buf_val = ioread32(davinci_spi->base + SPIBUF);
665 davinci_spi->get_rx(buf_val, davinci_spi);
666 }
667 if (count <= 0)
668 break;
669 }
670 } else {
671 if (pdata->poll_mode) {
672 while (1) {
673 /* keeps the serial clock going */
674 if ((ioread32(davinci_spi->base + SPIBUF)
675 & SPIBUF_TXFULL_MASK) == 0)
676 iowrite32(data1_reg_val,
677 davinci_spi->base + SPIDAT1);
678
679 while (ioread32(davinci_spi->base + SPIBUF) &
680 SPIBUF_RXEMPTY_MASK)
681 cpu_relax();
682
683 flg_val = ioread32(davinci_spi->base + SPIFLG);
684 buf_val = ioread32(davinci_spi->base + SPIBUF);
685
686 davinci_spi->get_rx(buf_val, davinci_spi);
687
688 count--;
689 if (count <= 0)
690 break;
691 }
692 } else { /* Receive in Interrupt mode */
693 int i;
694
f2bf4e84 695 for (i = 0; i < count; i++) {
358934a6
SP		 696 set_io_bits(davinci_spi->base + SPIINT,
697 SPIINT_BITERR_INTR
698 | SPIINT_OVRRUN_INTR
699 | SPIINT_RX_INTR);
700
701 iowrite32(data1_reg_val,
702 davinci_spi->base + SPIDAT1);
703
704 while (ioread32(davinci_spi->base + SPIINT) &
705 SPIINT_RX_INTR)
706 cpu_relax();
707 }
708 iowrite32((data1_reg_val & 0x0ffcffff),
709 davinci_spi->base + SPIDAT1);
710 }
711 }
712
713 /*
714 * Check for bit error, desync error,parity error,timeout error and
715 * receive overflow errors
716 */
717 int_status = ioread32(davinci_spi->base + SPIFLG);
718
719 ret = davinci_spi_check_error(davinci_spi, int_status);
720 if (ret != 0)
721 return ret;
722
358934a6
SP		 723 return t->len;
724}
725
358934a6
SP		 726static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
727{
728 struct davinci_spi *davinci_spi;
729 int int_status = 0;
730 int count, temp_count;
358934a6
SP		 731 u32 data1_reg_val;
732 struct davinci_spi_dma *davinci_spi_dma;
b7ab24a0 733 int data_type, ret;
358934a6 734 unsigned long tx_reg, rx_reg;
358934a6
SP		 735 struct device *sdev;
736
737 davinci_spi = spi_master_get_devdata(spi->master);
358934a6
SP		 738 sdev = davinci_spi->bitbang.master->dev.parent;
739
740 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
741
742 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
743 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
744
745 davinci_spi->tx = t->tx_buf;
746 davinci_spi->rx = t->rx_buf;
747
748 /* convert len to words based on bits_per_word */
b7ab24a0 749 data_type = davinci_spi->bytes_per_word[spi->chip_select];
358934a6 750
7978b8c3
BN		 751 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
752
358934a6
SP		 753 init_completion(&davinci_spi_dma->dma_rx_completion);
754 init_completion(&davinci_spi_dma->dma_tx_completion);
755
358934a6
SP		 756 ret = davinci_spi_bufs_prep(spi, davinci_spi);
757 if (ret)
758 return ret;
759
f2bf4e84 760 count = t->len / data_type; /* the number of elements */
358934a6
SP		 761
762 /* disable all interrupts for dma transfers */
763 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
358934a6
SP		 764 /* Enable SPI */
765 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
766
358934a6
SP		 767 if (t->tx_buf) {
768 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
769 DMA_TO_DEVICE);
770 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
771 dev_dbg(sdev, "Unable to DMA map a %d bytes"
772 " TX buffer\n", count);
773 return -ENOMEM;
774 }
775 temp_count = count;
776 } else {
777 /* We need TX clocking for RX transaction */
778 t->tx_dma = dma_map_single(&spi->dev,
779 (void *)davinci_spi->tmp_buf, count + 1,
780 DMA_TO_DEVICE);
781 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
782 dev_dbg(sdev, "Unable to DMA map a %d bytes"
783 " TX tmp buffer\n", count);
784 return -ENOMEM;
785 }
786 temp_count = count + 1;
787 }
788
789 edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
790 data_type, temp_count, 1, 0, ASYNC);
791 edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
792 edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
793 edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
794 edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
795
796 if (t->rx_buf) {
797 /* initiate transaction */
798 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
799
800 t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
801 DMA_FROM_DEVICE);
802 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
803 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
804 count);
805 if (t->tx_buf != NULL)
806 dma_unmap_single(NULL, t->tx_dma,
807 count, DMA_TO_DEVICE);
808 return -ENOMEM;
809 }
810 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
811 data_type, count, 1, 0, ASYNC);
812 edma_set_src(davinci_spi_dma->dma_rx_channel,
813 rx_reg, INCR, W8BIT);
814 edma_set_dest(davinci_spi_dma->dma_rx_channel,
815 t->rx_dma, INCR, W8BIT);
816 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
817 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
818 data_type, 0);
819 }
820
821 if ((t->tx_buf) || (t->rx_buf))
822 edma_start(davinci_spi_dma->dma_tx_channel);
823
824 if (t->rx_buf)
825 edma_start(davinci_spi_dma->dma_rx_channel);
826
827 if ((t->rx_buf) || (t->tx_buf))
828 davinci_spi_set_dma_req(spi, 1);
829
830 if (t->tx_buf)
831 wait_for_completion_interruptible(
832 &davinci_spi_dma->dma_tx_completion);
833
834 if (t->rx_buf)
835 wait_for_completion_interruptible(
836 &davinci_spi_dma->dma_rx_completion);
837
838 dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
839
840 if (t->rx_buf)
841 dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
842
843 /*
844 * Check for bit error, desync error,parity error,timeout error and
845 * receive overflow errors
846 */
847 int_status = ioread32(davinci_spi->base + SPIFLG);
848
849 ret = davinci_spi_check_error(davinci_spi, int_status);
850 if (ret != 0)
851 return ret;
852
358934a6
SP		 853 return t->len;
854}
855
856/**
857 * davinci_spi_irq - IRQ handler for DaVinci SPI
858 * @irq: IRQ number for this SPI Master
859 * @context_data: structure for SPI Master controller davinci_spi
860 */
861static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
862{
863 struct davinci_spi *davinci_spi = context_data;
864 u32 int_status, rx_data = 0;
865 irqreturn_t ret = IRQ_NONE;
866
867 int_status = ioread32(davinci_spi->base + SPIFLG);
868
869 while ((int_status & SPIFLG_RX_INTR_MASK)) {
870 if (likely(int_status & SPIFLG_RX_INTR_MASK)) {
871 ret = IRQ_HANDLED;
872
873 rx_data = ioread32(davinci_spi->base + SPIBUF);
874 davinci_spi->get_rx(rx_data, davinci_spi);
875
876 /* Disable Receive Interrupt */
877 iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR),
878 davinci_spi->base + SPIINT);
879 } else
880 (void)davinci_spi_check_error(davinci_spi, int_status);
881
882 int_status = ioread32(davinci_spi->base + SPIFLG);
883 }
884
885 return ret;
886}
887
888/**
889 * davinci_spi_probe - probe function for SPI Master Controller
890 * @pdev: platform_device structure which contains plateform specific data
891 */
892static int davinci_spi_probe(struct platform_device *pdev)
893{
894 struct spi_master *master;
895 struct davinci_spi *davinci_spi;
896 struct davinci_spi_platform_data *pdata;
897 struct resource *r, *mem;
898 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
899 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
900 resource_size_t dma_eventq = SPI_NO_RESOURCE;
901 int i = 0, ret = 0;
902
903 pdata = pdev->dev.platform_data;
904 if (pdata == NULL) {
905 ret = -ENODEV;
906 goto err;
907 }
908
909 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
910 if (master == NULL) {
911 ret = -ENOMEM;
912 goto err;
913 }
914
915 dev_set_drvdata(&pdev->dev, master);
916
917 davinci_spi = spi_master_get_devdata(master);
918 if (davinci_spi == NULL) {
919 ret = -ENOENT;
920 goto free_master;
921 }
922
923 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
924 if (r == NULL) {
925 ret = -ENOENT;
926 goto free_master;
927 }
928
929 davinci_spi->pbase = r->start;
930 davinci_spi->region_size = resource_size(r);
931 davinci_spi->pdata = pdata;
932
933 mem = request_mem_region(r->start, davinci_spi->region_size,
934 pdev->name);
935 if (mem == NULL) {
936 ret = -EBUSY;
937 goto free_master;
938 }
939
50356dd7 940 davinci_spi->base = ioremap(r->start, davinci_spi->region_size);
358934a6
SP		 941 if (davinci_spi->base == NULL) {
942 ret = -ENOMEM;
943 goto release_region;
944 }
945
946 davinci_spi->irq = platform_get_irq(pdev, 0);
947 if (davinci_spi->irq <= 0) {
948 ret = -EINVAL;
949 goto unmap_io;
950 }
951
952 ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
953 dev_name(&pdev->dev), davinci_spi);
954 if (ret)
955 goto unmap_io;
956
957 /* Allocate tmp_buf for tx_buf */
958 davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
959 if (davinci_spi->tmp_buf == NULL) {
960 ret = -ENOMEM;
961 goto irq_free;
962 }
963
964 davinci_spi->bitbang.master = spi_master_get(master);
965 if (davinci_spi->bitbang.master == NULL) {
966 ret = -ENODEV;
967 goto free_tmp_buf;
968 }
969
970 davinci_spi->clk = clk_get(&pdev->dev, NULL);
971 if (IS_ERR(davinci_spi->clk)) {
972 ret = -ENODEV;
973 goto put_master;
974 }
975 clk_enable(davinci_spi->clk);
976
358934a6
SP		 977 master->bus_num = pdev->id;
978 master->num_chipselect = pdata->num_chipselect;
979 master->setup = davinci_spi_setup;
980 master->cleanup = davinci_spi_cleanup;
981
982 davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
983 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
984
985 davinci_spi->version = pdata->version;
986 use_dma = pdata->use_dma;
987
988 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
989 if (davinci_spi->version == SPI_VERSION_2)
990 davinci_spi->bitbang.flags |= SPI_READY;
991
992 if (use_dma) {
778e261e
BN		 993 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
994 if (r)
995 dma_rx_chan = r->start;
996 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
997 if (r)
998 dma_tx_chan = r->start;
999 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1000 if (r)
1001 dma_eventq = r->start;
358934a6
SP		 1002 }
1003
1004 if (!use_dma ||
1005 dma_rx_chan == SPI_NO_RESOURCE ||
1006 dma_tx_chan == SPI_NO_RESOURCE ||
1007 dma_eventq == SPI_NO_RESOURCE) {
1008 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
1009 use_dma = 0;
1010 } else {
1011 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
1012 davinci_spi->dma_channels = kzalloc(master->num_chipselect
1013 * sizeof(struct davinci_spi_dma), GFP_KERNEL);
1014 if (davinci_spi->dma_channels == NULL) {
1015 ret = -ENOMEM;
1016 goto free_clk;
1017 }
1018
1019 for (i = 0; i < master->num_chipselect; i++) {
1020 davinci_spi->dma_channels[i].dma_rx_channel = -1;
1021 davinci_spi->dma_channels[i].dma_rx_sync_dev =
1022 dma_rx_chan;
1023 davinci_spi->dma_channels[i].dma_tx_channel = -1;
1024 davinci_spi->dma_channels[i].dma_tx_sync_dev =
1025 dma_tx_chan;
1026 davinci_spi->dma_channels[i].eventq = dma_eventq;
1027 }
1028 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
1029 "Using RX channel = %d , TX channel = %d and "
1030 "event queue = %d", dma_rx_chan, dma_tx_chan,
1031 dma_eventq);
1032 }
1033
1034 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
1035 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
1036
1037 init_completion(&davinci_spi->done);
1038
1039 /* Reset In/OUT SPI module */
1040 iowrite32(0, davinci_spi->base + SPIGCR0);
1041 udelay(100);
1042 iowrite32(1, davinci_spi->base + SPIGCR0);
1043
23853973
BN		 1044 /* initialize chip selects */
1045 if (pdata->chip_sel) {
1046 for (i = 0; i < pdata->num_chipselect; i++) {
1047 if (pdata->chip_sel[i] != SPI_INTERN_CS)
1048 gpio_direction_output(pdata->chip_sel[i], 1);
1049 }
1050 }
1051
358934a6
SP		 1052 /* Clock internal */
1053 if (davinci_spi->pdata->clk_internal)
1054 set_io_bits(davinci_spi->base + SPIGCR1,
1055 SPIGCR1_CLKMOD_MASK);
1056 else
1057 clear_io_bits(davinci_spi->base + SPIGCR1,
1058 SPIGCR1_CLKMOD_MASK);
1059
843a713b
BN		 1060 iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
1061
358934a6
SP		 1062 /* master mode default */
1063 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1064
1065 if (davinci_spi->pdata->intr_level)
1066 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1067 else
1068 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1069
1070 ret = spi_bitbang_start(&davinci_spi->bitbang);
1071 if (ret)
1072 goto free_clk;
1073
3b740b10 1074 dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
358934a6
SP		 1075
1076 if (!pdata->poll_mode)
1077 dev_info(&pdev->dev, "Operating in interrupt mode"
1078 " using IRQ %d\n", davinci_spi->irq);
1079
1080 return ret;
1081
1082free_clk:
1083 clk_disable(davinci_spi->clk);
1084 clk_put(davinci_spi->clk);
1085put_master:
1086 spi_master_put(master);
1087free_tmp_buf:
1088 kfree(davinci_spi->tmp_buf);
1089irq_free:
1090 free_irq(davinci_spi->irq, davinci_spi);
1091unmap_io:
1092 iounmap(davinci_spi->base);
1093release_region:
1094 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1095free_master:
1096 kfree(master);
1097err:
1098 return ret;
1099}
1100
1101/**
1102 * davinci_spi_remove - remove function for SPI Master Controller
1103 * @pdev: platform_device structure which contains plateform specific data
1104 *
1105 * This function will do the reverse action of davinci_spi_probe function
1106 * It will free the IRQ and SPI controller's memory region.
1107 * It will also call spi_bitbang_stop to destroy the work queue which was
1108 * created by spi_bitbang_start.
1109 */
1110static int __exit davinci_spi_remove(struct platform_device *pdev)
1111{
1112 struct davinci_spi *davinci_spi;
1113 struct spi_master *master;
1114
1115 master = dev_get_drvdata(&pdev->dev);
1116 davinci_spi = spi_master_get_devdata(master);
1117
1118 spi_bitbang_stop(&davinci_spi->bitbang);
1119
1120 clk_disable(davinci_spi->clk);
1121 clk_put(davinci_spi->clk);
1122 spi_master_put(master);
1123 kfree(davinci_spi->tmp_buf);
1124 free_irq(davinci_spi->irq, davinci_spi);
1125 iounmap(davinci_spi->base);
1126 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1127
1128 return 0;
1129}
1130
1131static struct platform_driver davinci_spi_driver = {
1132 .driver.name = "spi_davinci",
1133 .remove = __exit_p(davinci_spi_remove),
1134};
1135
1136static int __init davinci_spi_init(void)
1137{
1138 return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1139}
1140module_init(davinci_spi_init);
1141
1142static void __exit davinci_spi_exit(void)
1143{
1144 platform_driver_unregister(&davinci_spi_driver);
1145}
1146module_exit(davinci_spi_exit);
1147
1148MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1149MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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