Commit | Line | Data |
---|---|---|
358934a6 SP |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/gpio.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/spi/spi.h> | |
29 | #include <linux/spi/spi_bitbang.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
358934a6 SP |
31 | |
32 | #include <mach/spi.h> | |
33 | #include <mach/edma.h> | |
34 | ||
35 | #define SPI_NO_RESOURCE ((resource_size_t)-1) | |
36 | ||
37 | #define SPI_MAX_CHIPSELECT 2 | |
38 | ||
39 | #define CS_DEFAULT 0xFF | |
40 | ||
358934a6 SP |
41 | #define SPIFMT_PHASE_MASK BIT(16) |
42 | #define SPIFMT_POLARITY_MASK BIT(17) | |
43 | #define SPIFMT_DISTIMER_MASK BIT(18) | |
44 | #define SPIFMT_SHIFTDIR_MASK BIT(20) | |
45 | #define SPIFMT_WAITENA_MASK BIT(21) | |
46 | #define SPIFMT_PARITYENA_MASK BIT(22) | |
47 | #define SPIFMT_ODD_PARITY_MASK BIT(23) | |
48 | #define SPIFMT_WDELAY_MASK 0x3f000000u | |
49 | #define SPIFMT_WDELAY_SHIFT 24 | |
7fe0092b | 50 | #define SPIFMT_PRESCALE_SHIFT 8 |
358934a6 | 51 | |
358934a6 SP |
52 | |
53 | /* SPIPC0 */ | |
54 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ | |
55 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ | |
56 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ | |
57 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ | |
358934a6 SP |
58 | |
59 | #define SPIINT_MASKALL 0x0101035F | |
e0d205e9 BN |
60 | #define SPIINT_MASKINT 0x0000015F |
61 | #define SPI_INTLVL_1 0x000001FF | |
62 | #define SPI_INTLVL_0 0x00000000 | |
358934a6 | 63 | |
cfbc5d1d BN |
64 | /* SPIDAT1 (upper 16 bit defines) */ |
65 | #define SPIDAT1_CSHOLD_MASK BIT(12) | |
66 | ||
67 | /* SPIGCR1 */ | |
358934a6 SP |
68 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
69 | #define SPIGCR1_MASTER_MASK BIT(0) | |
70 | #define SPIGCR1_LOOPBACK_MASK BIT(16) | |
8e206f1c | 71 | #define SPIGCR1_SPIENA_MASK BIT(24) |
358934a6 SP |
72 | |
73 | /* SPIBUF */ | |
74 | #define SPIBUF_TXFULL_MASK BIT(29) | |
75 | #define SPIBUF_RXEMPTY_MASK BIT(31) | |
76 | ||
7abbf23c BN |
77 | /* SPIDELAY */ |
78 | #define SPIDELAY_C2TDELAY_SHIFT 24 | |
79 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) | |
80 | #define SPIDELAY_T2CDELAY_SHIFT 16 | |
81 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) | |
82 | #define SPIDELAY_T2EDELAY_SHIFT 8 | |
83 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) | |
84 | #define SPIDELAY_C2EDELAY_SHIFT 0 | |
85 | #define SPIDELAY_C2EDELAY_MASK 0xFF | |
86 | ||
358934a6 SP |
87 | /* Error Masks */ |
88 | #define SPIFLG_DLEN_ERR_MASK BIT(0) | |
89 | #define SPIFLG_TIMEOUT_MASK BIT(1) | |
90 | #define SPIFLG_PARERR_MASK BIT(2) | |
91 | #define SPIFLG_DESYNC_MASK BIT(3) | |
92 | #define SPIFLG_BITERR_MASK BIT(4) | |
93 | #define SPIFLG_OVRRUN_MASK BIT(6) | |
358934a6 | 94 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
839c996c BN |
95 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
96 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ | |
97 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ | |
98 | | SPIFLG_OVRRUN_MASK) | |
8e206f1c | 99 | |
358934a6 | 100 | #define SPIINT_DMA_REQ_EN BIT(16) |
358934a6 | 101 | |
358934a6 SP |
102 | /* SPI Controller registers */ |
103 | #define SPIGCR0 0x00 | |
104 | #define SPIGCR1 0x04 | |
105 | #define SPIINT 0x08 | |
106 | #define SPILVL 0x0c | |
107 | #define SPIFLG 0x10 | |
108 | #define SPIPC0 0x14 | |
358934a6 SP |
109 | #define SPIDAT1 0x3c |
110 | #define SPIBUF 0x40 | |
358934a6 SP |
111 | #define SPIDELAY 0x48 |
112 | #define SPIDEF 0x4c | |
113 | #define SPIFMT0 0x50 | |
358934a6 | 114 | |
358934a6 SP |
115 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
116 | struct davinci_spi_dma { | |
117 | int dma_tx_channel; | |
118 | int dma_rx_channel; | |
119 | int dma_tx_sync_dev; | |
120 | int dma_rx_sync_dev; | |
121 | enum dma_event_q eventq; | |
122 | ||
123 | struct completion dma_tx_completion; | |
124 | struct completion dma_rx_completion; | |
125 | }; | |
126 | ||
127 | /* SPI Controller driver's private data. */ | |
128 | struct davinci_spi { | |
129 | struct spi_bitbang bitbang; | |
130 | struct clk *clk; | |
131 | ||
132 | u8 version; | |
133 | resource_size_t pbase; | |
134 | void __iomem *base; | |
135 | size_t region_size; | |
e0d205e9 BN |
136 | u32 irq; |
137 | struct completion done; | |
358934a6 SP |
138 | |
139 | const void *tx; | |
140 | void *rx; | |
e91c659b BN |
141 | #define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) |
142 | u8 rx_tmp_buf[SPI_TMP_BUFSZ]; | |
e0d205e9 BN |
143 | int rcount; |
144 | int wcount; | |
96fd881f | 145 | struct davinci_spi_dma dma_channels; |
778e261e | 146 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
147 | |
148 | void (*get_rx)(u32 rx_data, struct davinci_spi *); | |
149 | u32 (*get_tx)(struct davinci_spi *); | |
150 | ||
cda987eb | 151 | u8 bytes_per_word[SPI_MAX_CHIPSELECT]; |
358934a6 SP |
152 | }; |
153 | ||
53a31b07 BN |
154 | static struct davinci_spi_config davinci_spi_default_cfg; |
155 | ||
358934a6 SP |
156 | static unsigned use_dma; |
157 | ||
158 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) | |
159 | { | |
53d454a1 BN |
160 | if (davinci_spi->rx) { |
161 | u8 *rx = davinci_spi->rx; | |
162 | *rx++ = (u8)data; | |
163 | davinci_spi->rx = rx; | |
164 | } | |
358934a6 SP |
165 | } |
166 | ||
167 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) | |
168 | { | |
53d454a1 BN |
169 | if (davinci_spi->rx) { |
170 | u16 *rx = davinci_spi->rx; | |
171 | *rx++ = (u16)data; | |
172 | davinci_spi->rx = rx; | |
173 | } | |
358934a6 SP |
174 | } |
175 | ||
176 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) | |
177 | { | |
53d454a1 BN |
178 | u32 data = 0; |
179 | if (davinci_spi->tx) { | |
180 | const u8 *tx = davinci_spi->tx; | |
181 | data = *tx++; | |
182 | davinci_spi->tx = tx; | |
183 | } | |
358934a6 SP |
184 | return data; |
185 | } | |
186 | ||
187 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) | |
188 | { | |
53d454a1 BN |
189 | u32 data = 0; |
190 | if (davinci_spi->tx) { | |
191 | const u16 *tx = davinci_spi->tx; | |
192 | data = *tx++; | |
193 | davinci_spi->tx = tx; | |
194 | } | |
358934a6 SP |
195 | return data; |
196 | } | |
197 | ||
198 | static inline void set_io_bits(void __iomem *addr, u32 bits) | |
199 | { | |
200 | u32 v = ioread32(addr); | |
201 | ||
202 | v |= bits; | |
203 | iowrite32(v, addr); | |
204 | } | |
205 | ||
206 | static inline void clear_io_bits(void __iomem *addr, u32 bits) | |
207 | { | |
208 | u32 v = ioread32(addr); | |
209 | ||
210 | v &= ~bits; | |
211 | iowrite32(v, addr); | |
212 | } | |
213 | ||
358934a6 SP |
214 | static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) |
215 | { | |
216 | struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); | |
217 | ||
218 | if (enable) | |
219 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
220 | else | |
221 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); | |
222 | } | |
223 | ||
224 | /* | |
225 | * Interface to control the chip select signal | |
226 | */ | |
227 | static void davinci_spi_chipselect(struct spi_device *spi, int value) | |
228 | { | |
229 | struct davinci_spi *davinci_spi; | |
230 | struct davinci_spi_platform_data *pdata; | |
7978b8c3 | 231 | u8 chip_sel = spi->chip_select; |
cfbc5d1d | 232 | u16 spidat1_cfg = CS_DEFAULT; |
23853973 | 233 | bool gpio_chipsel = false; |
358934a6 SP |
234 | |
235 | davinci_spi = spi_master_get_devdata(spi->master); | |
236 | pdata = davinci_spi->pdata; | |
237 | ||
23853973 BN |
238 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
239 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) | |
240 | gpio_chipsel = true; | |
241 | ||
358934a6 SP |
242 | /* |
243 | * Board specific chip select logic decides the polarity and cs | |
244 | * line for the controller | |
245 | */ | |
23853973 BN |
246 | if (gpio_chipsel) { |
247 | if (value == BITBANG_CS_ACTIVE) | |
248 | gpio_set_value(pdata->chip_sel[chip_sel], 0); | |
249 | else | |
250 | gpio_set_value(pdata->chip_sel[chip_sel], 1); | |
251 | } else { | |
252 | if (value == BITBANG_CS_ACTIVE) { | |
253 | spidat1_cfg |= SPIDAT1_CSHOLD_MASK; | |
254 | spidat1_cfg &= ~(0x1 << chip_sel); | |
255 | } | |
7978b8c3 | 256 | |
23853973 BN |
257 | iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); |
258 | } | |
358934a6 SP |
259 | } |
260 | ||
7fe0092b BN |
261 | /** |
262 | * davinci_spi_get_prescale - Calculates the correct prescale value | |
263 | * @maxspeed_hz: the maximum rate the SPI clock can run at | |
264 | * | |
265 | * This function calculates the prescale value that generates a clock rate | |
266 | * less than or equal to the specified maximum. | |
267 | * | |
268 | * Returns: calculated prescale - 1 for easy programming into SPI registers | |
269 | * or negative error number if valid prescalar cannot be updated. | |
270 | */ | |
271 | static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi, | |
272 | u32 max_speed_hz) | |
273 | { | |
274 | int ret; | |
275 | ||
276 | ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz); | |
277 | ||
278 | if (ret < 3 || ret > 256) | |
279 | return -EINVAL; | |
280 | ||
281 | return ret - 1; | |
282 | } | |
283 | ||
358934a6 SP |
284 | /** |
285 | * davinci_spi_setup_transfer - This functions will determine transfer method | |
286 | * @spi: spi device on which data transfer to be done | |
287 | * @t: spi transfer in which transfer info is filled | |
288 | * | |
289 | * This function determines data transfer method (8/16/32 bit transfer). | |
290 | * It will also set the SPI Clock Control register according to | |
291 | * SPI slave device freq. | |
292 | */ | |
293 | static int davinci_spi_setup_transfer(struct spi_device *spi, | |
294 | struct spi_transfer *t) | |
295 | { | |
296 | ||
297 | struct davinci_spi *davinci_spi; | |
25f33512 | 298 | struct davinci_spi_config *spicfg; |
358934a6 | 299 | u8 bits_per_word = 0; |
25f33512 | 300 | u32 hz = 0, spifmt = 0, prescale = 0; |
358934a6 SP |
301 | |
302 | davinci_spi = spi_master_get_devdata(spi->master); | |
25f33512 BN |
303 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
304 | if (!spicfg) | |
305 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
306 | |
307 | if (t) { | |
308 | bits_per_word = t->bits_per_word; | |
309 | hz = t->speed_hz; | |
310 | } | |
311 | ||
312 | /* if bits_per_word is not set then set it default */ | |
313 | if (!bits_per_word) | |
314 | bits_per_word = spi->bits_per_word; | |
315 | ||
316 | /* | |
317 | * Assign function pointer to appropriate transfer method | |
318 | * 8bit, 16bit or 32bit transfer | |
319 | */ | |
320 | if (bits_per_word <= 8 && bits_per_word >= 2) { | |
321 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
322 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
cda987eb | 323 | davinci_spi->bytes_per_word[spi->chip_select] = 1; |
358934a6 SP |
324 | } else if (bits_per_word <= 16 && bits_per_word >= 2) { |
325 | davinci_spi->get_rx = davinci_spi_rx_buf_u16; | |
326 | davinci_spi->get_tx = davinci_spi_tx_buf_u16; | |
cda987eb | 327 | davinci_spi->bytes_per_word[spi->chip_select] = 2; |
358934a6 SP |
328 | } else |
329 | return -EINVAL; | |
330 | ||
331 | if (!hz) | |
332 | hz = spi->max_speed_hz; | |
333 | ||
25f33512 BN |
334 | /* Set up SPIFMTn register, unique to this chipselect. */ |
335 | ||
7fe0092b BN |
336 | prescale = davinci_spi_get_prescale(davinci_spi, hz); |
337 | if (prescale < 0) | |
338 | return prescale; | |
339 | ||
25f33512 BN |
340 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
341 | ||
342 | if (spi->mode & SPI_LSB_FIRST) | |
343 | spifmt |= SPIFMT_SHIFTDIR_MASK; | |
344 | ||
345 | if (spi->mode & SPI_CPOL) | |
346 | spifmt |= SPIFMT_POLARITY_MASK; | |
347 | ||
348 | if (!(spi->mode & SPI_CPHA)) | |
349 | spifmt |= SPIFMT_PHASE_MASK; | |
350 | ||
351 | /* | |
352 | * Version 1 hardware supports two basic SPI modes: | |
353 | * - Standard SPI mode uses 4 pins, with chipselect | |
354 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) | |
355 | * (distinct from SPI_3WIRE, with just one data wire; | |
356 | * or similar variants without MOSI or without MISO) | |
357 | * | |
358 | * Version 2 hardware supports an optional handshaking signal, | |
359 | * so it can support two more modes: | |
360 | * - 5 pin SPI variant is standard SPI plus SPI_READY | |
361 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) | |
362 | */ | |
363 | ||
364 | if (davinci_spi->version == SPI_VERSION_2) { | |
365 | ||
7abbf23c BN |
366 | u32 delay = 0; |
367 | ||
25f33512 BN |
368 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
369 | & SPIFMT_WDELAY_MASK); | |
358934a6 | 370 | |
25f33512 BN |
371 | if (spicfg->odd_parity) |
372 | spifmt |= SPIFMT_ODD_PARITY_MASK; | |
373 | ||
374 | if (spicfg->parity_enable) | |
375 | spifmt |= SPIFMT_PARITYENA_MASK; | |
376 | ||
7abbf23c | 377 | if (spicfg->timer_disable) { |
25f33512 | 378 | spifmt |= SPIFMT_DISTIMER_MASK; |
7abbf23c BN |
379 | } else { |
380 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) | |
381 | & SPIDELAY_C2TDELAY_MASK; | |
382 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) | |
383 | & SPIDELAY_T2CDELAY_MASK; | |
384 | } | |
25f33512 | 385 | |
7abbf23c | 386 | if (spi->mode & SPI_READY) { |
25f33512 | 387 | spifmt |= SPIFMT_WAITENA_MASK; |
7abbf23c BN |
388 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
389 | & SPIDELAY_T2EDELAY_MASK; | |
390 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) | |
391 | & SPIDELAY_C2EDELAY_MASK; | |
392 | } | |
393 | ||
394 | iowrite32(delay, davinci_spi->base + SPIDELAY); | |
25f33512 BN |
395 | } |
396 | ||
397 | iowrite32(spifmt, davinci_spi->base + SPIFMT0); | |
358934a6 SP |
398 | |
399 | return 0; | |
400 | } | |
401 | ||
402 | static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) | |
403 | { | |
404 | struct spi_device *spi = (struct spi_device *)data; | |
405 | struct davinci_spi *davinci_spi; | |
406 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
407 | |
408 | davinci_spi = spi_master_get_devdata(spi->master); | |
96fd881f | 409 | davinci_spi_dma = &davinci_spi->dma_channels; |
358934a6 SP |
410 | |
411 | if (ch_status == DMA_COMPLETE) | |
412 | edma_stop(davinci_spi_dma->dma_rx_channel); | |
413 | else | |
414 | edma_clean_channel(davinci_spi_dma->dma_rx_channel); | |
415 | ||
416 | complete(&davinci_spi_dma->dma_rx_completion); | |
417 | /* We must disable the DMA RX request */ | |
418 | davinci_spi_set_dma_req(spi, 0); | |
419 | } | |
420 | ||
421 | static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) | |
422 | { | |
423 | struct spi_device *spi = (struct spi_device *)data; | |
424 | struct davinci_spi *davinci_spi; | |
425 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
426 | |
427 | davinci_spi = spi_master_get_devdata(spi->master); | |
96fd881f | 428 | davinci_spi_dma = &davinci_spi->dma_channels; |
358934a6 SP |
429 | |
430 | if (ch_status == DMA_COMPLETE) | |
431 | edma_stop(davinci_spi_dma->dma_tx_channel); | |
432 | else | |
433 | edma_clean_channel(davinci_spi_dma->dma_tx_channel); | |
434 | ||
435 | complete(&davinci_spi_dma->dma_tx_completion); | |
436 | /* We must disable the DMA TX request */ | |
437 | davinci_spi_set_dma_req(spi, 0); | |
438 | } | |
439 | ||
440 | static int davinci_spi_request_dma(struct spi_device *spi) | |
441 | { | |
442 | struct davinci_spi *davinci_spi; | |
443 | struct davinci_spi_dma *davinci_spi_dma; | |
358934a6 SP |
444 | struct device *sdev; |
445 | int r; | |
446 | ||
447 | davinci_spi = spi_master_get_devdata(spi->master); | |
96fd881f | 448 | davinci_spi_dma = &davinci_spi->dma_channels; |
358934a6 SP |
449 | sdev = davinci_spi->bitbang.master->dev.parent; |
450 | ||
451 | r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, | |
452 | davinci_spi_dma_rx_callback, spi, | |
453 | davinci_spi_dma->eventq); | |
454 | if (r < 0) { | |
455 | dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); | |
456 | return -EAGAIN; | |
457 | } | |
458 | davinci_spi_dma->dma_rx_channel = r; | |
459 | r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, | |
460 | davinci_spi_dma_tx_callback, spi, | |
461 | davinci_spi_dma->eventq); | |
462 | if (r < 0) { | |
463 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
464 | davinci_spi_dma->dma_rx_channel = -1; | |
465 | dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); | |
466 | return -EAGAIN; | |
467 | } | |
468 | davinci_spi_dma->dma_tx_channel = r; | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
473 | /** | |
474 | * davinci_spi_setup - This functions will set default transfer method | |
475 | * @spi: spi device on which data transfer to be done | |
476 | * | |
477 | * This functions sets the default transfer method. | |
478 | */ | |
358934a6 SP |
479 | static int davinci_spi_setup(struct spi_device *spi) |
480 | { | |
b23a5d46 | 481 | int retval = 0; |
358934a6 SP |
482 | struct davinci_spi *davinci_spi; |
483 | struct davinci_spi_dma *davinci_spi_dma; | |
be88471b | 484 | struct davinci_spi_platform_data *pdata; |
358934a6 SP |
485 | |
486 | davinci_spi = spi_master_get_devdata(spi->master); | |
be88471b | 487 | pdata = davinci_spi->pdata; |
358934a6 SP |
488 | |
489 | /* if bits per word length is zero then set it default 8 */ | |
490 | if (!spi->bits_per_word) | |
491 | spi->bits_per_word = 8; | |
492 | ||
be88471b BN |
493 | if (!(spi->mode & SPI_NO_CS)) { |
494 | if ((pdata->chip_sel == NULL) || | |
495 | (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) | |
496 | set_io_bits(davinci_spi->base + SPIPC0, | |
497 | 1 << spi->chip_select); | |
498 | ||
499 | } | |
500 | ||
501 | if (spi->mode & SPI_READY) | |
502 | set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); | |
503 | ||
504 | if (spi->mode & SPI_LOOP) | |
505 | set_io_bits(davinci_spi->base + SPIGCR1, | |
506 | SPIGCR1_LOOPBACK_MASK); | |
507 | else | |
508 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
509 | SPIGCR1_LOOPBACK_MASK); | |
510 | ||
96fd881f BN |
511 | if (use_dma) { |
512 | davinci_spi_dma = &davinci_spi->dma_channels; | |
358934a6 | 513 | |
b23a5d46 BN |
514 | if ((davinci_spi_dma->dma_rx_channel == -1) || |
515 | (davinci_spi_dma->dma_tx_channel == -1)) | |
358934a6 | 516 | retval = davinci_spi_request_dma(spi); |
358934a6 SP |
517 | } |
518 | ||
358934a6 SP |
519 | return retval; |
520 | } | |
521 | ||
522 | static void davinci_spi_cleanup(struct spi_device *spi) | |
523 | { | |
96fd881f BN |
524 | if (use_dma) { |
525 | struct davinci_spi *davinci_spi = | |
526 | spi_master_get_devdata(spi->master); | |
527 | struct davinci_spi_dma *davinci_spi_dma = | |
528 | &davinci_spi->dma_channels; | |
358934a6 SP |
529 | |
530 | if ((davinci_spi_dma->dma_rx_channel != -1) | |
531 | && (davinci_spi_dma->dma_tx_channel != -1)) { | |
532 | edma_free_channel(davinci_spi_dma->dma_tx_channel); | |
533 | edma_free_channel(davinci_spi_dma->dma_rx_channel); | |
534 | } | |
535 | } | |
536 | } | |
537 | ||
358934a6 SP |
538 | static int davinci_spi_check_error(struct davinci_spi *davinci_spi, |
539 | int int_status) | |
540 | { | |
541 | struct device *sdev = davinci_spi->bitbang.master->dev.parent; | |
542 | ||
543 | if (int_status & SPIFLG_TIMEOUT_MASK) { | |
544 | dev_dbg(sdev, "SPI Time-out Error\n"); | |
545 | return -ETIMEDOUT; | |
546 | } | |
547 | if (int_status & SPIFLG_DESYNC_MASK) { | |
548 | dev_dbg(sdev, "SPI Desynchronization Error\n"); | |
549 | return -EIO; | |
550 | } | |
551 | if (int_status & SPIFLG_BITERR_MASK) { | |
552 | dev_dbg(sdev, "SPI Bit error\n"); | |
553 | return -EIO; | |
554 | } | |
555 | ||
556 | if (davinci_spi->version == SPI_VERSION_2) { | |
557 | if (int_status & SPIFLG_DLEN_ERR_MASK) { | |
558 | dev_dbg(sdev, "SPI Data Length Error\n"); | |
559 | return -EIO; | |
560 | } | |
561 | if (int_status & SPIFLG_PARERR_MASK) { | |
562 | dev_dbg(sdev, "SPI Parity Error\n"); | |
563 | return -EIO; | |
564 | } | |
565 | if (int_status & SPIFLG_OVRRUN_MASK) { | |
566 | dev_dbg(sdev, "SPI Data Overrun error\n"); | |
567 | return -EIO; | |
568 | } | |
358934a6 SP |
569 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
570 | dev_dbg(sdev, "SPI Buffer Init Active\n"); | |
571 | return -EBUSY; | |
572 | } | |
573 | } | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
e0d205e9 BN |
578 | /** |
579 | * davinci_spi_process_events - check for and handle any SPI controller events | |
580 | * @davinci_spi: the controller data | |
581 | * | |
582 | * This function will check the SPIFLG register and handle any events that are | |
583 | * detected there | |
584 | */ | |
585 | static int davinci_spi_process_events(struct davinci_spi *davinci_spi) | |
586 | { | |
587 | u32 buf, status, errors = 0, data1_reg_val; | |
588 | ||
589 | buf = ioread32(davinci_spi->base + SPIBUF); | |
590 | ||
591 | if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { | |
592 | davinci_spi->get_rx(buf & 0xFFFF, davinci_spi); | |
593 | davinci_spi->rcount--; | |
594 | } | |
595 | ||
596 | status = ioread32(davinci_spi->base + SPIFLG); | |
597 | ||
598 | if (unlikely(status & SPIFLG_ERROR_MASK)) { | |
599 | errors = status & SPIFLG_ERROR_MASK; | |
600 | goto out; | |
601 | } | |
602 | ||
603 | if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { | |
604 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); | |
605 | davinci_spi->wcount--; | |
606 | data1_reg_val &= ~0xFFFF; | |
607 | data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi); | |
608 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
609 | } | |
610 | ||
611 | out: | |
612 | return errors; | |
613 | } | |
614 | ||
358934a6 SP |
615 | /** |
616 | * davinci_spi_bufs - functions which will handle transfer data | |
617 | * @spi: spi device on which data transfer to be done | |
618 | * @t: spi transfer in which transfer info is filled | |
619 | * | |
620 | * This function will put data to be transferred into data register | |
621 | * of SPI controller and then wait until the completion will be marked | |
622 | * by the IRQ Handler. | |
623 | */ | |
624 | static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) | |
625 | { | |
626 | struct davinci_spi *davinci_spi; | |
839c996c | 627 | int ret; |
358934a6 | 628 | u32 tx_data, data1_reg_val; |
839c996c | 629 | u32 errors = 0; |
e0d205e9 | 630 | struct davinci_spi_config *spicfg; |
358934a6 SP |
631 | struct davinci_spi_platform_data *pdata; |
632 | ||
633 | davinci_spi = spi_master_get_devdata(spi->master); | |
634 | pdata = davinci_spi->pdata; | |
e0d205e9 BN |
635 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
636 | if (!spicfg) | |
637 | spicfg = &davinci_spi_default_cfg; | |
358934a6 SP |
638 | |
639 | davinci_spi->tx = t->tx_buf; | |
640 | davinci_spi->rx = t->rx_buf; | |
e0d205e9 BN |
641 | davinci_spi->wcount = t->len / |
642 | davinci_spi->bytes_per_word[spi->chip_select]; | |
643 | davinci_spi->rcount = davinci_spi->wcount; | |
7978b8c3 | 644 | |
839c996c BN |
645 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
646 | ||
358934a6 SP |
647 | /* Enable SPI */ |
648 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
649 | ||
e0d205e9 BN |
650 | if (spicfg->io_type == SPI_IO_TYPE_INTR) { |
651 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); | |
652 | INIT_COMPLETION(davinci_spi->done); | |
653 | } | |
cf90fe73 | 654 | |
839c996c | 655 | /* start the transfer */ |
e0d205e9 | 656 | davinci_spi->wcount--; |
839c996c BN |
657 | tx_data = davinci_spi->get_tx(davinci_spi); |
658 | data1_reg_val &= 0xFFFF0000; | |
659 | data1_reg_val |= tx_data & 0xFFFF; | |
660 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); | |
358934a6 | 661 | |
e0d205e9 BN |
662 | /* Wait for the transfer to complete */ |
663 | if (spicfg->io_type == SPI_IO_TYPE_INTR) { | |
664 | wait_for_completion_interruptible(&(davinci_spi->done)); | |
665 | } else { | |
666 | while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) { | |
667 | errors = davinci_spi_process_events(davinci_spi); | |
668 | if (errors) | |
669 | break; | |
670 | cpu_relax(); | |
358934a6 SP |
671 | } |
672 | } | |
673 | ||
e0d205e9 BN |
674 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); |
675 | ||
358934a6 SP |
676 | /* |
677 | * Check for bit error, desync error,parity error,timeout error and | |
678 | * receive overflow errors | |
679 | */ | |
839c996c BN |
680 | if (errors) { |
681 | ret = davinci_spi_check_error(davinci_spi, errors); | |
682 | WARN(!ret, "%s: error reported but no error found!\n", | |
683 | dev_name(&spi->dev)); | |
358934a6 | 684 | return ret; |
839c996c | 685 | } |
358934a6 | 686 | |
358934a6 SP |
687 | return t->len; |
688 | } | |
689 | ||
e0d205e9 BN |
690 | /** |
691 | * davinci_spi_irq - Interrupt handler for SPI Master Controller | |
692 | * @irq: IRQ number for this SPI Master | |
693 | * @context_data: structure for SPI Master controller davinci_spi | |
694 | * | |
695 | * ISR will determine that interrupt arrives either for READ or WRITE command. | |
696 | * According to command it will do the appropriate action. It will check | |
697 | * transfer length and if it is not zero then dispatch transfer command again. | |
698 | * If transfer length is zero then it will indicate the COMPLETION so that | |
699 | * davinci_spi_bufs function can go ahead. | |
700 | */ | |
701 | static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) | |
702 | { | |
703 | struct davinci_spi *davinci_spi = context_data; | |
704 | int status; | |
705 | ||
706 | status = davinci_spi_process_events(davinci_spi); | |
707 | if (unlikely(status != 0)) | |
708 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); | |
709 | ||
710 | if ((!davinci_spi->rcount && !davinci_spi->wcount) || status) | |
711 | complete(&davinci_spi->done); | |
712 | ||
713 | return IRQ_HANDLED; | |
714 | } | |
715 | ||
358934a6 SP |
716 | static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) |
717 | { | |
718 | struct davinci_spi *davinci_spi; | |
719 | int int_status = 0; | |
d3f7141c | 720 | int count; |
e91c659b | 721 | unsigned rx_buf_count; |
358934a6 | 722 | struct davinci_spi_dma *davinci_spi_dma; |
b7ab24a0 | 723 | int data_type, ret; |
358934a6 | 724 | unsigned long tx_reg, rx_reg; |
c29e3c60 | 725 | struct davinci_spi_platform_data *pdata; |
e91c659b | 726 | void *rx_buf; |
358934a6 | 727 | struct device *sdev; |
49fc3f49 | 728 | struct edmacc_param param; |
358934a6 SP |
729 | |
730 | davinci_spi = spi_master_get_devdata(spi->master); | |
c29e3c60 | 731 | pdata = davinci_spi->pdata; |
358934a6 SP |
732 | sdev = davinci_spi->bitbang.master->dev.parent; |
733 | ||
96fd881f | 734 | davinci_spi_dma = &davinci_spi->dma_channels; |
358934a6 SP |
735 | |
736 | tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; | |
737 | rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; | |
738 | ||
739 | davinci_spi->tx = t->tx_buf; | |
740 | davinci_spi->rx = t->rx_buf; | |
741 | ||
742 | /* convert len to words based on bits_per_word */ | |
b7ab24a0 | 743 | data_type = davinci_spi->bytes_per_word[spi->chip_select]; |
358934a6 | 744 | |
358934a6 SP |
745 | init_completion(&davinci_spi_dma->dma_rx_completion); |
746 | init_completion(&davinci_spi_dma->dma_tx_completion); | |
747 | ||
f2bf4e84 | 748 | count = t->len / data_type; /* the number of elements */ |
358934a6 SP |
749 | |
750 | /* disable all interrupts for dma transfers */ | |
751 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); | |
358934a6 SP |
752 | /* Enable SPI */ |
753 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); | |
754 | ||
d3f7141c BN |
755 | /* |
756 | * Transmit DMA setup | |
757 | * | |
758 | * If there is transmit data, map the transmit buffer, set it as the | |
759 | * source of data and set the source B index to data size. | |
760 | * If there is no transmit data, set the transmit register as the | |
761 | * source of data, and set the source B index to zero. | |
762 | * | |
763 | * The destination is always the transmit register itself. And the | |
764 | * destination never increments. | |
765 | */ | |
766 | ||
358934a6 SP |
767 | if (t->tx_buf) { |
768 | t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, | |
769 | DMA_TO_DEVICE); | |
770 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { | |
771 | dev_dbg(sdev, "Unable to DMA map a %d bytes" | |
772 | " TX buffer\n", count); | |
773 | return -ENOMEM; | |
774 | } | |
358934a6 SP |
775 | } |
776 | ||
49fc3f49 BN |
777 | param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_tx_channel); |
778 | param.src = t->tx_buf ? t->tx_dma : tx_reg; | |
779 | param.a_b_cnt = count << 16 | data_type; | |
780 | param.dst = tx_reg; | |
781 | param.src_dst_bidx = t->tx_buf ? data_type : 0; | |
782 | param.link_bcntrld = 0xffff; | |
783 | param.src_dst_cidx = 0; | |
784 | param.ccnt = 1; | |
785 | edma_write_slot(davinci_spi_dma->dma_tx_channel, ¶m); | |
358934a6 | 786 | |
e91c659b BN |
787 | /* |
788 | * Receive DMA setup | |
789 | * | |
790 | * If there is receive buffer, use it to receive data. If there | |
791 | * is none provided, use a temporary receive buffer. Set the | |
792 | * destination B index to 0 so effectively only one byte is used | |
793 | * in the temporary buffer (address does not increment). | |
794 | * | |
795 | * The source of receive data is the receive data register. The | |
796 | * source address never increments. | |
797 | */ | |
798 | ||
358934a6 | 799 | if (t->rx_buf) { |
e91c659b BN |
800 | rx_buf = t->rx_buf; |
801 | rx_buf_count = count; | |
802 | } else { | |
803 | rx_buf = davinci_spi->rx_tmp_buf; | |
804 | rx_buf_count = sizeof(davinci_spi->rx_tmp_buf); | |
805 | } | |
806 | ||
807 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count, | |
808 | DMA_FROM_DEVICE); | |
809 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { | |
810 | dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", | |
811 | rx_buf_count); | |
812 | if (t->tx_buf) | |
813 | dma_unmap_single(NULL, t->tx_dma, count, DMA_TO_DEVICE); | |
814 | return -ENOMEM; | |
358934a6 SP |
815 | } |
816 | ||
49fc3f49 BN |
817 | param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_rx_channel); |
818 | param.src = rx_reg; | |
819 | param.a_b_cnt = count << 16 | data_type; | |
820 | param.dst = t->rx_dma; | |
821 | param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16; | |
822 | param.link_bcntrld = 0xffff; | |
823 | param.src_dst_cidx = 0; | |
824 | param.ccnt = 1; | |
825 | edma_write_slot(davinci_spi_dma->dma_rx_channel, ¶m); | |
e91c659b | 826 | |
c29e3c60 BN |
827 | if (pdata->cshold_bug) { |
828 | u16 spidat1 = ioread16(davinci_spi->base + SPIDAT1 + 2); | |
829 | iowrite16(spidat1, davinci_spi->base + SPIDAT1 + 2); | |
830 | } | |
358934a6 | 831 | |
e91c659b | 832 | edma_start(davinci_spi_dma->dma_rx_channel); |
c29e3c60 BN |
833 | edma_start(davinci_spi_dma->dma_tx_channel); |
834 | davinci_spi_set_dma_req(spi, 1); | |
358934a6 | 835 | |
c29e3c60 | 836 | wait_for_completion_interruptible(&davinci_spi_dma->dma_tx_completion); |
e91c659b | 837 | wait_for_completion_interruptible(&davinci_spi_dma->dma_rx_completion); |
358934a6 | 838 | |
d3f7141c BN |
839 | if (t->tx_buf) |
840 | dma_unmap_single(NULL, t->tx_dma, count, DMA_TO_DEVICE); | |
358934a6 | 841 | |
e91c659b | 842 | dma_unmap_single(NULL, t->rx_dma, rx_buf_count, DMA_FROM_DEVICE); |
358934a6 SP |
843 | |
844 | /* | |
845 | * Check for bit error, desync error,parity error,timeout error and | |
846 | * receive overflow errors | |
847 | */ | |
848 | int_status = ioread32(davinci_spi->base + SPIFLG); | |
849 | ||
850 | ret = davinci_spi_check_error(davinci_spi, int_status); | |
851 | if (ret != 0) | |
852 | return ret; | |
853 | ||
358934a6 SP |
854 | return t->len; |
855 | } | |
856 | ||
358934a6 SP |
857 | /** |
858 | * davinci_spi_probe - probe function for SPI Master Controller | |
859 | * @pdev: platform_device structure which contains plateform specific data | |
860 | */ | |
861 | static int davinci_spi_probe(struct platform_device *pdev) | |
862 | { | |
863 | struct spi_master *master; | |
864 | struct davinci_spi *davinci_spi; | |
865 | struct davinci_spi_platform_data *pdata; | |
866 | struct resource *r, *mem; | |
867 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; | |
868 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; | |
869 | resource_size_t dma_eventq = SPI_NO_RESOURCE; | |
870 | int i = 0, ret = 0; | |
f34bd4cc | 871 | u32 spipc0; |
358934a6 SP |
872 | |
873 | pdata = pdev->dev.platform_data; | |
874 | if (pdata == NULL) { | |
875 | ret = -ENODEV; | |
876 | goto err; | |
877 | } | |
878 | ||
879 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); | |
880 | if (master == NULL) { | |
881 | ret = -ENOMEM; | |
882 | goto err; | |
883 | } | |
884 | ||
885 | dev_set_drvdata(&pdev->dev, master); | |
886 | ||
887 | davinci_spi = spi_master_get_devdata(master); | |
888 | if (davinci_spi == NULL) { | |
889 | ret = -ENOENT; | |
890 | goto free_master; | |
891 | } | |
892 | ||
893 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
894 | if (r == NULL) { | |
895 | ret = -ENOENT; | |
896 | goto free_master; | |
897 | } | |
898 | ||
899 | davinci_spi->pbase = r->start; | |
900 | davinci_spi->region_size = resource_size(r); | |
901 | davinci_spi->pdata = pdata; | |
902 | ||
903 | mem = request_mem_region(r->start, davinci_spi->region_size, | |
904 | pdev->name); | |
905 | if (mem == NULL) { | |
906 | ret = -EBUSY; | |
907 | goto free_master; | |
908 | } | |
909 | ||
50356dd7 | 910 | davinci_spi->base = ioremap(r->start, davinci_spi->region_size); |
358934a6 SP |
911 | if (davinci_spi->base == NULL) { |
912 | ret = -ENOMEM; | |
913 | goto release_region; | |
914 | } | |
915 | ||
e0d205e9 BN |
916 | davinci_spi->irq = platform_get_irq(pdev, 0); |
917 | if (davinci_spi->irq <= 0) { | |
918 | ret = -EINVAL; | |
919 | goto unmap_io; | |
920 | } | |
921 | ||
922 | ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, | |
923 | dev_name(&pdev->dev), davinci_spi); | |
924 | if (ret) | |
925 | goto unmap_io; | |
926 | ||
358934a6 SP |
927 | davinci_spi->bitbang.master = spi_master_get(master); |
928 | if (davinci_spi->bitbang.master == NULL) { | |
929 | ret = -ENODEV; | |
d3f7141c | 930 | goto irq_free; |
358934a6 SP |
931 | } |
932 | ||
933 | davinci_spi->clk = clk_get(&pdev->dev, NULL); | |
934 | if (IS_ERR(davinci_spi->clk)) { | |
935 | ret = -ENODEV; | |
936 | goto put_master; | |
937 | } | |
938 | clk_enable(davinci_spi->clk); | |
939 | ||
358934a6 SP |
940 | master->bus_num = pdev->id; |
941 | master->num_chipselect = pdata->num_chipselect; | |
942 | master->setup = davinci_spi_setup; | |
943 | master->cleanup = davinci_spi_cleanup; | |
944 | ||
945 | davinci_spi->bitbang.chipselect = davinci_spi_chipselect; | |
946 | davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; | |
947 | ||
948 | davinci_spi->version = pdata->version; | |
949 | use_dma = pdata->use_dma; | |
950 | ||
951 | davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; | |
952 | if (davinci_spi->version == SPI_VERSION_2) | |
953 | davinci_spi->bitbang.flags |= SPI_READY; | |
954 | ||
955 | if (use_dma) { | |
778e261e BN |
956 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
957 | if (r) | |
958 | dma_rx_chan = r->start; | |
959 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
960 | if (r) | |
961 | dma_tx_chan = r->start; | |
962 | r = platform_get_resource(pdev, IORESOURCE_DMA, 2); | |
963 | if (r) | |
964 | dma_eventq = r->start; | |
358934a6 SP |
965 | } |
966 | ||
967 | if (!use_dma || | |
968 | dma_rx_chan == SPI_NO_RESOURCE || | |
969 | dma_tx_chan == SPI_NO_RESOURCE || | |
970 | dma_eventq == SPI_NO_RESOURCE) { | |
971 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; | |
972 | use_dma = 0; | |
973 | } else { | |
974 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; | |
358934a6 | 975 | |
96fd881f BN |
976 | davinci_spi->dma_channels.dma_rx_channel = -1; |
977 | davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; | |
978 | davinci_spi->dma_channels.dma_tx_channel = -1; | |
979 | davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; | |
980 | davinci_spi->dma_channels.eventq = dma_eventq; | |
981 | ||
358934a6 SP |
982 | dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" |
983 | "Using RX channel = %d , TX channel = %d and " | |
984 | "event queue = %d", dma_rx_chan, dma_tx_chan, | |
985 | dma_eventq); | |
986 | } | |
987 | ||
988 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; | |
989 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; | |
990 | ||
e0d205e9 BN |
991 | init_completion(&davinci_spi->done); |
992 | ||
358934a6 SP |
993 | /* Reset In/OUT SPI module */ |
994 | iowrite32(0, davinci_spi->base + SPIGCR0); | |
995 | udelay(100); | |
996 | iowrite32(1, davinci_spi->base + SPIGCR0); | |
997 | ||
be88471b | 998 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
f34bd4cc BN |
999 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
1000 | iowrite32(spipc0, davinci_spi->base + SPIPC0); | |
1001 | ||
23853973 BN |
1002 | /* initialize chip selects */ |
1003 | if (pdata->chip_sel) { | |
1004 | for (i = 0; i < pdata->num_chipselect; i++) { | |
1005 | if (pdata->chip_sel[i] != SPI_INTERN_CS) | |
1006 | gpio_direction_output(pdata->chip_sel[i], 1); | |
1007 | } | |
1008 | } | |
1009 | ||
358934a6 SP |
1010 | /* Clock internal */ |
1011 | if (davinci_spi->pdata->clk_internal) | |
1012 | set_io_bits(davinci_spi->base + SPIGCR1, | |
1013 | SPIGCR1_CLKMOD_MASK); | |
1014 | else | |
1015 | clear_io_bits(davinci_spi->base + SPIGCR1, | |
1016 | SPIGCR1_CLKMOD_MASK); | |
1017 | ||
e0d205e9 BN |
1018 | if (pdata->intr_line) |
1019 | iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); | |
1020 | else | |
1021 | iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); | |
1022 | ||
843a713b BN |
1023 | iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF); |
1024 | ||
358934a6 SP |
1025 | /* master mode default */ |
1026 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); | |
1027 | ||
358934a6 SP |
1028 | ret = spi_bitbang_start(&davinci_spi->bitbang); |
1029 | if (ret) | |
1030 | goto free_clk; | |
1031 | ||
3b740b10 | 1032 | dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); |
358934a6 | 1033 | |
358934a6 SP |
1034 | return ret; |
1035 | ||
1036 | free_clk: | |
1037 | clk_disable(davinci_spi->clk); | |
1038 | clk_put(davinci_spi->clk); | |
1039 | put_master: | |
1040 | spi_master_put(master); | |
e0d205e9 BN |
1041 | irq_free: |
1042 | free_irq(davinci_spi->irq, davinci_spi); | |
358934a6 SP |
1043 | unmap_io: |
1044 | iounmap(davinci_spi->base); | |
1045 | release_region: | |
1046 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
1047 | free_master: | |
1048 | kfree(master); | |
1049 | err: | |
1050 | return ret; | |
1051 | } | |
1052 | ||
1053 | /** | |
1054 | * davinci_spi_remove - remove function for SPI Master Controller | |
1055 | * @pdev: platform_device structure which contains plateform specific data | |
1056 | * | |
1057 | * This function will do the reverse action of davinci_spi_probe function | |
1058 | * It will free the IRQ and SPI controller's memory region. | |
1059 | * It will also call spi_bitbang_stop to destroy the work queue which was | |
1060 | * created by spi_bitbang_start. | |
1061 | */ | |
1062 | static int __exit davinci_spi_remove(struct platform_device *pdev) | |
1063 | { | |
1064 | struct davinci_spi *davinci_spi; | |
1065 | struct spi_master *master; | |
1066 | ||
1067 | master = dev_get_drvdata(&pdev->dev); | |
1068 | davinci_spi = spi_master_get_devdata(master); | |
1069 | ||
1070 | spi_bitbang_stop(&davinci_spi->bitbang); | |
1071 | ||
1072 | clk_disable(davinci_spi->clk); | |
1073 | clk_put(davinci_spi->clk); | |
1074 | spi_master_put(master); | |
e0d205e9 | 1075 | free_irq(davinci_spi->irq, davinci_spi); |
358934a6 SP |
1076 | iounmap(davinci_spi->base); |
1077 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); | |
1078 | ||
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | static struct platform_driver davinci_spi_driver = { | |
1083 | .driver.name = "spi_davinci", | |
1084 | .remove = __exit_p(davinci_spi_remove), | |
1085 | }; | |
1086 | ||
1087 | static int __init davinci_spi_init(void) | |
1088 | { | |
1089 | return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe); | |
1090 | } | |
1091 | module_init(davinci_spi_init); | |
1092 | ||
1093 | static void __exit davinci_spi_exit(void) | |
1094 | { | |
1095 | platform_driver_unregister(&davinci_spi_driver); | |
1096 | } | |
1097 | module_exit(davinci_spi_exit); | |
1098 | ||
1099 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); | |
1100 | MODULE_LICENSE("GPL"); |