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spi: davinci: enable both activation and deactivation of chip-selects
[deliverable/linux.git] / drivers / spi / davinci_spi.c
CommitLineData
358934a6
SP		 1/*
2 * Copyright (C) 2009 Texas Instruments.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/module.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/err.h>
26#include <linux/clk.h>
27#include <linux/dma-mapping.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/spi_bitbang.h>
5a0e3ad6 30#include <linux/slab.h>
358934a6
SP		 31
32#include <mach/spi.h>
33#include <mach/edma.h>
34
35#define SPI_NO_RESOURCE ((resource_size_t)-1)
36
37#define SPI_MAX_CHIPSELECT 2
38
39#define CS_DEFAULT 0xFF
40
41#define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
42#define DAVINCI_DMA_DATA_TYPE_S8 0x01
43#define DAVINCI_DMA_DATA_TYPE_S16 0x02
44#define DAVINCI_DMA_DATA_TYPE_S32 0x04
45
46#define SPIFMT_PHASE_MASK BIT(16)
47#define SPIFMT_POLARITY_MASK BIT(17)
48#define SPIFMT_DISTIMER_MASK BIT(18)
49#define SPIFMT_SHIFTDIR_MASK BIT(20)
50#define SPIFMT_WAITENA_MASK BIT(21)
51#define SPIFMT_PARITYENA_MASK BIT(22)
52#define SPIFMT_ODD_PARITY_MASK BIT(23)
53#define SPIFMT_WDELAY_MASK 0x3f000000u
54#define SPIFMT_WDELAY_SHIFT 24
55#define SPIFMT_CHARLEN_MASK 0x0000001Fu
56
358934a6
SP		 57
58/* SPIPC0 */
59#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
60#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
61#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
62#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
358934a6
SP		 63
64#define SPIINT_MASKALL 0x0101035F
65#define SPI_INTLVL_1 0x000001FFu
66#define SPI_INTLVL_0 0x00000000u
67
68/* SPIDAT1 */
7978b8c3 69#define SPIDAT1_CSHOLD_MASK BIT(28)
358934a6
SP		 70#define SPIDAT1_CSNR_SHIFT 16
71#define SPIGCR1_CLKMOD_MASK BIT(1)
72#define SPIGCR1_MASTER_MASK BIT(0)
73#define SPIGCR1_LOOPBACK_MASK BIT(16)
8e206f1c 74#define SPIGCR1_SPIENA_MASK BIT(24)
358934a6
SP		 75
76/* SPIBUF */
77#define SPIBUF_TXFULL_MASK BIT(29)
78#define SPIBUF_RXEMPTY_MASK BIT(31)
79
80/* Error Masks */
81#define SPIFLG_DLEN_ERR_MASK BIT(0)
82#define SPIFLG_TIMEOUT_MASK BIT(1)
83#define SPIFLG_PARERR_MASK BIT(2)
84#define SPIFLG_DESYNC_MASK BIT(3)
85#define SPIFLG_BITERR_MASK BIT(4)
86#define SPIFLG_OVRRUN_MASK BIT(6)
87#define SPIFLG_RX_INTR_MASK BIT(8)
88#define SPIFLG_TX_INTR_MASK BIT(9)
89#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
8e206f1c 90
358934a6
SP		 91#define SPIINT_BITERR_INTR BIT(4)
92#define SPIINT_OVRRUN_INTR BIT(6)
93#define SPIINT_RX_INTR BIT(8)
94#define SPIINT_TX_INTR BIT(9)
95#define SPIINT_DMA_REQ_EN BIT(16)
358934a6
SP		 96
97#define SPI_T2CDELAY_SHIFT 16
98#define SPI_C2TDELAY_SHIFT 24
99
100/* SPI Controller registers */
101#define SPIGCR0 0x00
102#define SPIGCR1 0x04
103#define SPIINT 0x08
104#define SPILVL 0x0c
105#define SPIFLG 0x10
106#define SPIPC0 0x14
358934a6
SP		 107#define SPIDAT1 0x3c
108#define SPIBUF 0x40
358934a6
SP		 109#define SPIDELAY 0x48
110#define SPIDEF 0x4c
111#define SPIFMT0 0x50
358934a6
SP		 112
113struct davinci_spi_slave {
114 u32 cmd_to_write;
115 u32 clk_ctrl_to_write;
116 u32 bytes_per_word;
117 u8 active_cs;
118};
119
120/* We have 2 DMA channels per CS, one for RX and one for TX */
121struct davinci_spi_dma {
122 int dma_tx_channel;
123 int dma_rx_channel;
124 int dma_tx_sync_dev;
125 int dma_rx_sync_dev;
126 enum dma_event_q eventq;
127
128 struct completion dma_tx_completion;
129 struct completion dma_rx_completion;
130};
131
132/* SPI Controller driver's private data. */
133struct davinci_spi {
134 struct spi_bitbang bitbang;
135 struct clk *clk;
136
137 u8 version;
138 resource_size_t pbase;
139 void __iomem *base;
140 size_t region_size;
141 u32 irq;
142 struct completion done;
143
144 const void *tx;
145 void *rx;
146 u8 *tmp_buf;
147 int count;
148 struct davinci_spi_dma *dma_channels;
778e261e 149 struct davinci_spi_platform_data *pdata;
358934a6
SP		 150
151 void (*get_rx)(u32 rx_data, struct davinci_spi *);
152 u32 (*get_tx)(struct davinci_spi *);
153
154 struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT];
155};
156
157static unsigned use_dma;
158
159static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
160{
161 u8 *rx = davinci_spi->rx;
162
163 *rx++ = (u8)data;
164 davinci_spi->rx = rx;
165}
166
167static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
168{
169 u16 *rx = davinci_spi->rx;
170
171 *rx++ = (u16)data;
172 davinci_spi->rx = rx;
173}
174
175static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
176{
177 u32 data;
178 const u8 *tx = davinci_spi->tx;
179
180 data = *tx++;
181 davinci_spi->tx = tx;
182 return data;
183}
184
185static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
186{
187 u32 data;
188 const u16 *tx = davinci_spi->tx;
189
190 data = *tx++;
191 davinci_spi->tx = tx;
192 return data;
193}
194
195static inline void set_io_bits(void __iomem *addr, u32 bits)
196{
197 u32 v = ioread32(addr);
198
199 v |= bits;
200 iowrite32(v, addr);
201}
202
203static inline void clear_io_bits(void __iomem *addr, u32 bits)
204{
205 u32 v = ioread32(addr);
206
207 v &= ~bits;
208 iowrite32(v, addr);
209}
210
211static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
212{
213 set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
214}
215
216static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
217{
218 clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
219}
220
221static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
222{
223 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
224
225 if (enable)
226 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
227 else
228 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
229}
230
231/*
232 * Interface to control the chip select signal
233 */
234static void davinci_spi_chipselect(struct spi_device *spi, int value)
235{
236 struct davinci_spi *davinci_spi;
237 struct davinci_spi_platform_data *pdata;
7978b8c3
BN		 238 u32 data1_reg_val;
239 u8 chip_sel = spi->chip_select;
358934a6
SP		 240
241 davinci_spi = spi_master_get_devdata(spi->master);
242 pdata = davinci_spi->pdata;
243
244 /*
245 * Board specific chip select logic decides the polarity and cs
246 * line for the controller
247 */
7978b8c3
BN		 248 data1_reg_val = CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
249 if (value == BITBANG_CS_ACTIVE) {
250 data1_reg_val |= SPIDAT1_CSHOLD_MASK;
251 data1_reg_val &= ~((0x1 << chip_sel) << SPIDAT1_CSNR_SHIFT);
358934a6 252 }
7978b8c3
BN		 253
254 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
255 while ((ioread32(davinci_spi->base + SPIBUF)
256 & SPIBUF_RXEMPTY_MASK) == 0)
257 cpu_relax();
258
358934a6
SP		 259}
260
261/**
262 * davinci_spi_setup_transfer - This functions will determine transfer method
263 * @spi: spi device on which data transfer to be done
264 * @t: spi transfer in which transfer info is filled
265 *
266 * This function determines data transfer method (8/16/32 bit transfer).
267 * It will also set the SPI Clock Control register according to
268 * SPI slave device freq.
269 */
270static int davinci_spi_setup_transfer(struct spi_device *spi,
271 struct spi_transfer *t)
272{
273
274 struct davinci_spi *davinci_spi;
358934a6 275 u8 bits_per_word = 0;
0c2a2ae3 276 u32 hz = 0, prescale = 0, clkspeed;
358934a6
SP		 277
278 davinci_spi = spi_master_get_devdata(spi->master);
358934a6
SP		 279
280 if (t) {
281 bits_per_word = t->bits_per_word;
282 hz = t->speed_hz;
283 }
284
285 /* if bits_per_word is not set then set it default */
286 if (!bits_per_word)
287 bits_per_word = spi->bits_per_word;
288
289 /*
290 * Assign function pointer to appropriate transfer method
291 * 8bit, 16bit or 32bit transfer
292 */
293 if (bits_per_word <= 8 && bits_per_word >= 2) {
294 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
295 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
296 davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
297 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
298 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
299 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
300 davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
301 } else
302 return -EINVAL;
303
304 if (!hz)
305 hz = spi->max_speed_hz;
306
307 clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
308 spi->chip_select);
309 set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
310 spi->chip_select);
311
0c2a2ae3
TK		 312 clkspeed = clk_get_rate(davinci_spi->clk);
313 if (hz > clkspeed / 2)
314 prescale = 1 << 8;
315 if (hz < clkspeed / 256)
316 prescale = 255 << 8;
317 if (!prescale)
318 prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00;
358934a6
SP		 319
320 clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
0c2a2ae3 321 set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);
358934a6
SP		 322
323 return 0;
324}
325
326static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
327{
328 struct spi_device *spi = (struct spi_device *)data;
329 struct davinci_spi *davinci_spi;
330 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 331
332 davinci_spi = spi_master_get_devdata(spi->master);
333 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
358934a6
SP		 334
335 if (ch_status == DMA_COMPLETE)
336 edma_stop(davinci_spi_dma->dma_rx_channel);
337 else
338 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
339
340 complete(&davinci_spi_dma->dma_rx_completion);
341 /* We must disable the DMA RX request */
342 davinci_spi_set_dma_req(spi, 0);
343}
344
345static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
346{
347 struct spi_device *spi = (struct spi_device *)data;
348 struct davinci_spi *davinci_spi;
349 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 350
351 davinci_spi = spi_master_get_devdata(spi->master);
352 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
358934a6
SP		 353
354 if (ch_status == DMA_COMPLETE)
355 edma_stop(davinci_spi_dma->dma_tx_channel);
356 else
357 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
358
359 complete(&davinci_spi_dma->dma_tx_completion);
360 /* We must disable the DMA TX request */
361 davinci_spi_set_dma_req(spi, 0);
362}
363
364static int davinci_spi_request_dma(struct spi_device *spi)
365{
366 struct davinci_spi *davinci_spi;
367 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 368 struct device *sdev;
369 int r;
370
371 davinci_spi = spi_master_get_devdata(spi->master);
372 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
358934a6
SP		 373 sdev = davinci_spi->bitbang.master->dev.parent;
374
375 r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
376 davinci_spi_dma_rx_callback, spi,
377 davinci_spi_dma->eventq);
378 if (r < 0) {
379 dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
380 return -EAGAIN;
381 }
382 davinci_spi_dma->dma_rx_channel = r;
383 r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
384 davinci_spi_dma_tx_callback, spi,
385 davinci_spi_dma->eventq);
386 if (r < 0) {
387 edma_free_channel(davinci_spi_dma->dma_rx_channel);
388 davinci_spi_dma->dma_rx_channel = -1;
389 dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
390 return -EAGAIN;
391 }
392 davinci_spi_dma->dma_tx_channel = r;
393
394 return 0;
395}
396
397/**
398 * davinci_spi_setup - This functions will set default transfer method
399 * @spi: spi device on which data transfer to be done
400 *
401 * This functions sets the default transfer method.
402 */
358934a6
SP		 403static int davinci_spi_setup(struct spi_device *spi)
404{
405 int retval;
406 struct davinci_spi *davinci_spi;
407 struct davinci_spi_dma *davinci_spi_dma;
408 struct device *sdev;
409
410 davinci_spi = spi_master_get_devdata(spi->master);
411 sdev = davinci_spi->bitbang.master->dev.parent;
412
413 /* if bits per word length is zero then set it default 8 */
414 if (!spi->bits_per_word)
415 spi->bits_per_word = 8;
416
417 davinci_spi->slave[spi->chip_select].cmd_to_write = 0;
418
419 if (use_dma && davinci_spi->dma_channels) {
420 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
421
422 if ((davinci_spi_dma->dma_rx_channel == -1)
423 || (davinci_spi_dma->dma_tx_channel == -1)) {
424 retval = davinci_spi_request_dma(spi);
425 if (retval < 0)
426 return retval;
427 }
428 }
429
430 /*
431 * SPI in DaVinci and DA8xx operate between
432 * 600 KHz and 50 MHz
433 */
434 if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) {
435 dev_dbg(sdev, "Operating frequency is not in acceptable "
436 "range\n");
437 return -EINVAL;
438 }
439
440 /*
441 * Set up SPIFMTn register, unique to this chipselect.
442 *
443 * NOTE: we could do all of these with one write. Also, some
444 * of the "version 2" features are found in chips that don't
445 * support all of them...
446 */
447 if (spi->mode & SPI_LSB_FIRST)
448 set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
449 spi->chip_select);
450 else
451 clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
452 spi->chip_select);
453
454 if (spi->mode & SPI_CPOL)
455 set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
456 spi->chip_select);
457 else
458 clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
459 spi->chip_select);
460
461 if (!(spi->mode & SPI_CPHA))
462 set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
463 spi->chip_select);
464 else
465 clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
466 spi->chip_select);
467
468 /*
469 * Version 1 hardware supports two basic SPI modes:
470 * - Standard SPI mode uses 4 pins, with chipselect
471 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
472 * (distinct from SPI_3WIRE, with just one data wire;
473 * or similar variants without MOSI or without MISO)
474 *
475 * Version 2 hardware supports an optional handshaking signal,
476 * so it can support two more modes:
477 * - 5 pin SPI variant is standard SPI plus SPI_READY
478 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
479 */
480
481 if (davinci_spi->version == SPI_VERSION_2) {
482 clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
483 spi->chip_select);
484 set_fmt_bits(davinci_spi->base,
485 (davinci_spi->pdata->wdelay
486 << SPIFMT_WDELAY_SHIFT)
487 & SPIFMT_WDELAY_MASK,
488 spi->chip_select);
489
490 if (davinci_spi->pdata->odd_parity)
491 set_fmt_bits(davinci_spi->base,
492 SPIFMT_ODD_PARITY_MASK,
493 spi->chip_select);
494 else
495 clear_fmt_bits(davinci_spi->base,
496 SPIFMT_ODD_PARITY_MASK,
497 spi->chip_select);
498
499 if (davinci_spi->pdata->parity_enable)
500 set_fmt_bits(davinci_spi->base,
501 SPIFMT_PARITYENA_MASK,
502 spi->chip_select);
503 else
504 clear_fmt_bits(davinci_spi->base,
505 SPIFMT_PARITYENA_MASK,
506 spi->chip_select);
507
508 if (davinci_spi->pdata->wait_enable)
509 set_fmt_bits(davinci_spi->base,
510 SPIFMT_WAITENA_MASK,
511 spi->chip_select);
512 else
513 clear_fmt_bits(davinci_spi->base,
514 SPIFMT_WAITENA_MASK,
515 spi->chip_select);
516
517 if (davinci_spi->pdata->timer_disable)
518 set_fmt_bits(davinci_spi->base,
519 SPIFMT_DISTIMER_MASK,
520 spi->chip_select);
521 else
522 clear_fmt_bits(davinci_spi->base,
523 SPIFMT_DISTIMER_MASK,
524 spi->chip_select);
525 }
526
527 retval = davinci_spi_setup_transfer(spi, NULL);
528
529 return retval;
530}
531
532static void davinci_spi_cleanup(struct spi_device *spi)
533{
534 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
535 struct davinci_spi_dma *davinci_spi_dma;
536
537 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
538
539 if (use_dma && davinci_spi->dma_channels) {
540 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
541
542 if ((davinci_spi_dma->dma_rx_channel != -1)
543 && (davinci_spi_dma->dma_tx_channel != -1)) {
544 edma_free_channel(davinci_spi_dma->dma_tx_channel);
545 edma_free_channel(davinci_spi_dma->dma_rx_channel);
546 }
547 }
548}
549
550static int davinci_spi_bufs_prep(struct spi_device *spi,
551 struct davinci_spi *davinci_spi)
552{
553 int op_mode = 0;
554
555 /*
556 * REVISIT unless devices disagree about SPI_LOOP or
557 * SPI_READY (SPI_NO_CS only allows one device!), this
558 * should not need to be done before each message...
559 * optimize for both flags staying cleared.
560 */
561
562 op_mode = SPIPC0_DIFUN_MASK
563 | SPIPC0_DOFUN_MASK
564 | SPIPC0_CLKFUN_MASK;
565 if (!(spi->mode & SPI_NO_CS))
566 op_mode |= 1 << spi->chip_select;
567 if (spi->mode & SPI_READY)
568 op_mode |= SPIPC0_SPIENA_MASK;
569
570 iowrite32(op_mode, davinci_spi->base + SPIPC0);
571
572 if (spi->mode & SPI_LOOP)
573 set_io_bits(davinci_spi->base + SPIGCR1,
574 SPIGCR1_LOOPBACK_MASK);
575 else
576 clear_io_bits(davinci_spi->base + SPIGCR1,
577 SPIGCR1_LOOPBACK_MASK);
578
579 return 0;
580}
581
582static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
583 int int_status)
584{
585 struct device *sdev = davinci_spi->bitbang.master->dev.parent;
586
587 if (int_status & SPIFLG_TIMEOUT_MASK) {
588 dev_dbg(sdev, "SPI Time-out Error\n");
589 return -ETIMEDOUT;
590 }
591 if (int_status & SPIFLG_DESYNC_MASK) {
592 dev_dbg(sdev, "SPI Desynchronization Error\n");
593 return -EIO;
594 }
595 if (int_status & SPIFLG_BITERR_MASK) {
596 dev_dbg(sdev, "SPI Bit error\n");
597 return -EIO;
598 }
599
600 if (davinci_spi->version == SPI_VERSION_2) {
601 if (int_status & SPIFLG_DLEN_ERR_MASK) {
602 dev_dbg(sdev, "SPI Data Length Error\n");
603 return -EIO;
604 }
605 if (int_status & SPIFLG_PARERR_MASK) {
606 dev_dbg(sdev, "SPI Parity Error\n");
607 return -EIO;
608 }
609 if (int_status & SPIFLG_OVRRUN_MASK) {
610 dev_dbg(sdev, "SPI Data Overrun error\n");
611 return -EIO;
612 }
613 if (int_status & SPIFLG_TX_INTR_MASK) {
614 dev_dbg(sdev, "SPI TX intr bit set\n");
615 return -EIO;
616 }
617 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
618 dev_dbg(sdev, "SPI Buffer Init Active\n");
619 return -EBUSY;
620 }
621 }
622
623 return 0;
624}
625
626/**
627 * davinci_spi_bufs - functions which will handle transfer data
628 * @spi: spi device on which data transfer to be done
629 * @t: spi transfer in which transfer info is filled
630 *
631 * This function will put data to be transferred into data register
632 * of SPI controller and then wait until the completion will be marked
633 * by the IRQ Handler.
634 */
635static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
636{
637 struct davinci_spi *davinci_spi;
638 int int_status, count, ret;
7978b8c3 639 u8 conv;
358934a6
SP		 640 u32 tx_data, data1_reg_val;
641 u32 buf_val, flg_val;
642 struct davinci_spi_platform_data *pdata;
643
644 davinci_spi = spi_master_get_devdata(spi->master);
645 pdata = davinci_spi->pdata;
646
647 davinci_spi->tx = t->tx_buf;
648 davinci_spi->rx = t->rx_buf;
649
650 /* convert len to words based on bits_per_word */
651 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
652 davinci_spi->count = t->len / conv;
653
7978b8c3
BN		 654 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
655
358934a6
SP		 656 INIT_COMPLETION(davinci_spi->done);
657
658 ret = davinci_spi_bufs_prep(spi, davinci_spi);
659 if (ret)
660 return ret;
661
662 /* Enable SPI */
663 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
664
665 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
666 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
667 davinci_spi->base + SPIDELAY);
668
669 count = davinci_spi->count;
358934a6
SP		 670
671 /* Determine the command to execute READ or WRITE */
672 if (t->tx_buf) {
673 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
674
675 while (1) {
676 tx_data = davinci_spi->get_tx(davinci_spi);
677
678 data1_reg_val &= ~(0xFFFF);
679 data1_reg_val |= (0xFFFF & tx_data);
680
681 buf_val = ioread32(davinci_spi->base + SPIBUF);
682 if ((buf_val & SPIBUF_TXFULL_MASK) == 0) {
683 iowrite32(data1_reg_val,
684 davinci_spi->base + SPIDAT1);
685
686 count--;
687 }
688 while (ioread32(davinci_spi->base + SPIBUF)
689 & SPIBUF_RXEMPTY_MASK)
690 cpu_relax();
691
692 /* getting the returned byte */
693 if (t->rx_buf) {
694 buf_val = ioread32(davinci_spi->base + SPIBUF);
695 davinci_spi->get_rx(buf_val, davinci_spi);
696 }
697 if (count <= 0)
698 break;
699 }
700 } else {
701 if (pdata->poll_mode) {
702 while (1) {
703 /* keeps the serial clock going */
704 if ((ioread32(davinci_spi->base + SPIBUF)
705 & SPIBUF_TXFULL_MASK) == 0)
706 iowrite32(data1_reg_val,
707 davinci_spi->base + SPIDAT1);
708
709 while (ioread32(davinci_spi->base + SPIBUF) &
710 SPIBUF_RXEMPTY_MASK)
711 cpu_relax();
712
713 flg_val = ioread32(davinci_spi->base + SPIFLG);
714 buf_val = ioread32(davinci_spi->base + SPIBUF);
715
716 davinci_spi->get_rx(buf_val, davinci_spi);
717
718 count--;
719 if (count <= 0)
720 break;
721 }
722 } else { /* Receive in Interrupt mode */
723 int i;
724
725 for (i = 0; i < davinci_spi->count; i++) {
726 set_io_bits(davinci_spi->base + SPIINT,
727 SPIINT_BITERR_INTR
728 | SPIINT_OVRRUN_INTR
729 | SPIINT_RX_INTR);
730
731 iowrite32(data1_reg_val,
732 davinci_spi->base + SPIDAT1);
733
734 while (ioread32(davinci_spi->base + SPIINT) &
735 SPIINT_RX_INTR)
736 cpu_relax();
737 }
738 iowrite32((data1_reg_val & 0x0ffcffff),
739 davinci_spi->base + SPIDAT1);
740 }
741 }
742
743 /*
744 * Check for bit error, desync error,parity error,timeout error and
745 * receive overflow errors
746 */
747 int_status = ioread32(davinci_spi->base + SPIFLG);
748
749 ret = davinci_spi_check_error(davinci_spi, int_status);
750 if (ret != 0)
751 return ret;
752
753 /* SPI Framework maintains the count only in bytes so convert back */
754 davinci_spi->count *= conv;
755
756 return t->len;
757}
758
759#define DAVINCI_DMA_DATA_TYPE_S8 0x01
760#define DAVINCI_DMA_DATA_TYPE_S16 0x02
761#define DAVINCI_DMA_DATA_TYPE_S32 0x04
762
763static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
764{
765 struct davinci_spi *davinci_spi;
766 int int_status = 0;
767 int count, temp_count;
768 u8 conv = 1;
358934a6
SP		 769 u32 data1_reg_val;
770 struct davinci_spi_dma *davinci_spi_dma;
771 int word_len, data_type, ret;
772 unsigned long tx_reg, rx_reg;
773 struct davinci_spi_platform_data *pdata;
774 struct device *sdev;
775
776 davinci_spi = spi_master_get_devdata(spi->master);
777 pdata = davinci_spi->pdata;
778 sdev = davinci_spi->bitbang.master->dev.parent;
779
780 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
781
782 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
783 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
784
785 davinci_spi->tx = t->tx_buf;
786 davinci_spi->rx = t->rx_buf;
787
788 /* convert len to words based on bits_per_word */
789 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
790 davinci_spi->count = t->len / conv;
791
7978b8c3
BN		 792 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
793
358934a6
SP		 794 INIT_COMPLETION(davinci_spi->done);
795
796 init_completion(&davinci_spi_dma->dma_rx_completion);
797 init_completion(&davinci_spi_dma->dma_tx_completion);
798
799 word_len = conv * 8;
800
801 if (word_len <= 8)
802 data_type = DAVINCI_DMA_DATA_TYPE_S8;
803 else if (word_len <= 16)
804 data_type = DAVINCI_DMA_DATA_TYPE_S16;
805 else if (word_len <= 32)
806 data_type = DAVINCI_DMA_DATA_TYPE_S32;
807 else
808 return -EINVAL;
809
810 ret = davinci_spi_bufs_prep(spi, davinci_spi);
811 if (ret)
812 return ret;
813
814 /* Put delay val if required */
815 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
816 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
817 davinci_spi->base + SPIDELAY);
818
819 count = davinci_spi->count; /* the number of elements */
358934a6
SP		 820
821 /* disable all interrupts for dma transfers */
822 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
823 /* Disable SPI to write configuration bits in SPIDAT */
824 clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
358934a6
SP		 825 /* Enable SPI */
826 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
827
358934a6
SP		 828 if (t->tx_buf) {
829 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
830 DMA_TO_DEVICE);
831 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
832 dev_dbg(sdev, "Unable to DMA map a %d bytes"
833 " TX buffer\n", count);
834 return -ENOMEM;
835 }
836 temp_count = count;
837 } else {
838 /* We need TX clocking for RX transaction */
839 t->tx_dma = dma_map_single(&spi->dev,
840 (void *)davinci_spi->tmp_buf, count + 1,
841 DMA_TO_DEVICE);
842 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
843 dev_dbg(sdev, "Unable to DMA map a %d bytes"
844 " TX tmp buffer\n", count);
845 return -ENOMEM;
846 }
847 temp_count = count + 1;
848 }
849
850 edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
851 data_type, temp_count, 1, 0, ASYNC);
852 edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
853 edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
854 edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
855 edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
856
857 if (t->rx_buf) {
858 /* initiate transaction */
859 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
860
861 t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
862 DMA_FROM_DEVICE);
863 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
864 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
865 count);
866 if (t->tx_buf != NULL)
867 dma_unmap_single(NULL, t->tx_dma,
868 count, DMA_TO_DEVICE);
869 return -ENOMEM;
870 }
871 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
872 data_type, count, 1, 0, ASYNC);
873 edma_set_src(davinci_spi_dma->dma_rx_channel,
874 rx_reg, INCR, W8BIT);
875 edma_set_dest(davinci_spi_dma->dma_rx_channel,
876 t->rx_dma, INCR, W8BIT);
877 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
878 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
879 data_type, 0);
880 }
881
882 if ((t->tx_buf) || (t->rx_buf))
883 edma_start(davinci_spi_dma->dma_tx_channel);
884
885 if (t->rx_buf)
886 edma_start(davinci_spi_dma->dma_rx_channel);
887
888 if ((t->rx_buf) || (t->tx_buf))
889 davinci_spi_set_dma_req(spi, 1);
890
891 if (t->tx_buf)
892 wait_for_completion_interruptible(
893 &davinci_spi_dma->dma_tx_completion);
894
895 if (t->rx_buf)
896 wait_for_completion_interruptible(
897 &davinci_spi_dma->dma_rx_completion);
898
899 dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
900
901 if (t->rx_buf)
902 dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
903
904 /*
905 * Check for bit error, desync error,parity error,timeout error and
906 * receive overflow errors
907 */
908 int_status = ioread32(davinci_spi->base + SPIFLG);
909
910 ret = davinci_spi_check_error(davinci_spi, int_status);
911 if (ret != 0)
912 return ret;
913
914 /* SPI Framework maintains the count only in bytes so convert back */
915 davinci_spi->count *= conv;
916
917 return t->len;
918}
919
920/**
921 * davinci_spi_irq - IRQ handler for DaVinci SPI
922 * @irq: IRQ number for this SPI Master
923 * @context_data: structure for SPI Master controller davinci_spi
924 */
925static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
926{
927 struct davinci_spi *davinci_spi = context_data;
928 u32 int_status, rx_data = 0;
929 irqreturn_t ret = IRQ_NONE;
930
931 int_status = ioread32(davinci_spi->base + SPIFLG);
932
933 while ((int_status & SPIFLG_RX_INTR_MASK)) {
934 if (likely(int_status & SPIFLG_RX_INTR_MASK)) {
935 ret = IRQ_HANDLED;
936
937 rx_data = ioread32(davinci_spi->base + SPIBUF);
938 davinci_spi->get_rx(rx_data, davinci_spi);
939
940 /* Disable Receive Interrupt */
941 iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR),
942 davinci_spi->base + SPIINT);
943 } else
944 (void)davinci_spi_check_error(davinci_spi, int_status);
945
946 int_status = ioread32(davinci_spi->base + SPIFLG);
947 }
948
949 return ret;
950}
951
952/**
953 * davinci_spi_probe - probe function for SPI Master Controller
954 * @pdev: platform_device structure which contains plateform specific data
955 */
956static int davinci_spi_probe(struct platform_device *pdev)
957{
958 struct spi_master *master;
959 struct davinci_spi *davinci_spi;
960 struct davinci_spi_platform_data *pdata;
961 struct resource *r, *mem;
962 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
963 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
964 resource_size_t dma_eventq = SPI_NO_RESOURCE;
965 int i = 0, ret = 0;
966
967 pdata = pdev->dev.platform_data;
968 if (pdata == NULL) {
969 ret = -ENODEV;
970 goto err;
971 }
972
973 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
974 if (master == NULL) {
975 ret = -ENOMEM;
976 goto err;
977 }
978
979 dev_set_drvdata(&pdev->dev, master);
980
981 davinci_spi = spi_master_get_devdata(master);
982 if (davinci_spi == NULL) {
983 ret = -ENOENT;
984 goto free_master;
985 }
986
987 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
988 if (r == NULL) {
989 ret = -ENOENT;
990 goto free_master;
991 }
992
993 davinci_spi->pbase = r->start;
994 davinci_spi->region_size = resource_size(r);
995 davinci_spi->pdata = pdata;
996
997 mem = request_mem_region(r->start, davinci_spi->region_size,
998 pdev->name);
999 if (mem == NULL) {
1000 ret = -EBUSY;
1001 goto free_master;
1002 }
1003
50356dd7 1004 davinci_spi->base = ioremap(r->start, davinci_spi->region_size);
358934a6
SP		 1005 if (davinci_spi->base == NULL) {
1006 ret = -ENOMEM;
1007 goto release_region;
1008 }
1009
1010 davinci_spi->irq = platform_get_irq(pdev, 0);
1011 if (davinci_spi->irq <= 0) {
1012 ret = -EINVAL;
1013 goto unmap_io;
1014 }
1015
1016 ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
1017 dev_name(&pdev->dev), davinci_spi);
1018 if (ret)
1019 goto unmap_io;
1020
1021 /* Allocate tmp_buf for tx_buf */
1022 davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
1023 if (davinci_spi->tmp_buf == NULL) {
1024 ret = -ENOMEM;
1025 goto irq_free;
1026 }
1027
1028 davinci_spi->bitbang.master = spi_master_get(master);
1029 if (davinci_spi->bitbang.master == NULL) {
1030 ret = -ENODEV;
1031 goto free_tmp_buf;
1032 }
1033
1034 davinci_spi->clk = clk_get(&pdev->dev, NULL);
1035 if (IS_ERR(davinci_spi->clk)) {
1036 ret = -ENODEV;
1037 goto put_master;
1038 }
1039 clk_enable(davinci_spi->clk);
1040
358934a6
SP		 1041 master->bus_num = pdev->id;
1042 master->num_chipselect = pdata->num_chipselect;
1043 master->setup = davinci_spi_setup;
1044 master->cleanup = davinci_spi_cleanup;
1045
1046 davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
1047 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
1048
1049 davinci_spi->version = pdata->version;
1050 use_dma = pdata->use_dma;
1051
1052 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
1053 if (davinci_spi->version == SPI_VERSION_2)
1054 davinci_spi->bitbang.flags |= SPI_READY;
1055
1056 if (use_dma) {
778e261e
BN		 1057 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1058 if (r)
1059 dma_rx_chan = r->start;
1060 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1061 if (r)
1062 dma_tx_chan = r->start;
1063 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1064 if (r)
1065 dma_eventq = r->start;
358934a6
SP		 1066 }
1067
1068 if (!use_dma ||
1069 dma_rx_chan == SPI_NO_RESOURCE ||
1070 dma_tx_chan == SPI_NO_RESOURCE ||
1071 dma_eventq == SPI_NO_RESOURCE) {
1072 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
1073 use_dma = 0;
1074 } else {
1075 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
1076 davinci_spi->dma_channels = kzalloc(master->num_chipselect
1077 * sizeof(struct davinci_spi_dma), GFP_KERNEL);
1078 if (davinci_spi->dma_channels == NULL) {
1079 ret = -ENOMEM;
1080 goto free_clk;
1081 }
1082
1083 for (i = 0; i < master->num_chipselect; i++) {
1084 davinci_spi->dma_channels[i].dma_rx_channel = -1;
1085 davinci_spi->dma_channels[i].dma_rx_sync_dev =
1086 dma_rx_chan;
1087 davinci_spi->dma_channels[i].dma_tx_channel = -1;
1088 davinci_spi->dma_channels[i].dma_tx_sync_dev =
1089 dma_tx_chan;
1090 davinci_spi->dma_channels[i].eventq = dma_eventq;
1091 }
1092 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
1093 "Using RX channel = %d , TX channel = %d and "
1094 "event queue = %d", dma_rx_chan, dma_tx_chan,
1095 dma_eventq);
1096 }
1097
1098 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
1099 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
1100
1101 init_completion(&davinci_spi->done);
1102
1103 /* Reset In/OUT SPI module */
1104 iowrite32(0, davinci_spi->base + SPIGCR0);
1105 udelay(100);
1106 iowrite32(1, davinci_spi->base + SPIGCR0);
1107
1108 /* Clock internal */
1109 if (davinci_spi->pdata->clk_internal)
1110 set_io_bits(davinci_spi->base + SPIGCR1,
1111 SPIGCR1_CLKMOD_MASK);
1112 else
1113 clear_io_bits(davinci_spi->base + SPIGCR1,
1114 SPIGCR1_CLKMOD_MASK);
1115
843a713b
BN		 1116 iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
1117
358934a6
SP		 1118 /* master mode default */
1119 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1120
1121 if (davinci_spi->pdata->intr_level)
1122 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1123 else
1124 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1125
1126 ret = spi_bitbang_start(&davinci_spi->bitbang);
1127 if (ret)
1128 goto free_clk;
1129
3b740b10 1130 dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
358934a6
SP		 1131
1132 if (!pdata->poll_mode)
1133 dev_info(&pdev->dev, "Operating in interrupt mode"
1134 " using IRQ %d\n", davinci_spi->irq);
1135
1136 return ret;
1137
1138free_clk:
1139 clk_disable(davinci_spi->clk);
1140 clk_put(davinci_spi->clk);
1141put_master:
1142 spi_master_put(master);
1143free_tmp_buf:
1144 kfree(davinci_spi->tmp_buf);
1145irq_free:
1146 free_irq(davinci_spi->irq, davinci_spi);
1147unmap_io:
1148 iounmap(davinci_spi->base);
1149release_region:
1150 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1151free_master:
1152 kfree(master);
1153err:
1154 return ret;
1155}
1156
1157/**
1158 * davinci_spi_remove - remove function for SPI Master Controller
1159 * @pdev: platform_device structure which contains plateform specific data
1160 *
1161 * This function will do the reverse action of davinci_spi_probe function
1162 * It will free the IRQ and SPI controller's memory region.
1163 * It will also call spi_bitbang_stop to destroy the work queue which was
1164 * created by spi_bitbang_start.
1165 */
1166static int __exit davinci_spi_remove(struct platform_device *pdev)
1167{
1168 struct davinci_spi *davinci_spi;
1169 struct spi_master *master;
1170
1171 master = dev_get_drvdata(&pdev->dev);
1172 davinci_spi = spi_master_get_devdata(master);
1173
1174 spi_bitbang_stop(&davinci_spi->bitbang);
1175
1176 clk_disable(davinci_spi->clk);
1177 clk_put(davinci_spi->clk);
1178 spi_master_put(master);
1179 kfree(davinci_spi->tmp_buf);
1180 free_irq(davinci_spi->irq, davinci_spi);
1181 iounmap(davinci_spi->base);
1182 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1183
1184 return 0;
1185}
1186
1187static struct platform_driver davinci_spi_driver = {
1188 .driver.name = "spi_davinci",
1189 .remove = __exit_p(davinci_spi_remove),
1190};
1191
1192static int __init davinci_spi_init(void)
1193{
1194 return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1195}
1196module_init(davinci_spi_init);
1197
1198static void __exit davinci_spi_exit(void)
1199{
1200 platform_driver_unregister(&davinci_spi_driver);
1201}
1202module_exit(davinci_spi_exit);
1203
1204MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1205MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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