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spi/dw_spi: remove the un-necessary flush()
[deliverable/linux.git] / drivers / spi / dw_spi.c
CommitLineData
e24c7452
FT		 1/*
2 * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#include <linux/dma-mapping.h>
21#include <linux/interrupt.h>
22#include <linux/highmem.h>
23#include <linux/delay.h>
5a0e3ad6 24#include <linux/slab.h>
e24c7452
FT		 25#include <linux/spi/spi.h>
26
568a60ed
GL		 27#include "dw_spi.h"
28
e24c7452
FT		 29#ifdef CONFIG_DEBUG_FS
30#include <linux/debugfs.h>
31#endif
32
33#define START_STATE ((void *)0)
34#define RUNNING_STATE ((void *)1)
35#define DONE_STATE ((void *)2)
36#define ERROR_STATE ((void *)-1)
37
38#define QUEUE_RUNNING 0
39#define QUEUE_STOPPED 1
40
41#define MRST_SPI_DEASSERT 0
42#define MRST_SPI_ASSERT 1
43
44/* Slave spi_dev related */
45struct chip_data {
46 u16 cr0;
47 u8 cs; /* chip select pin */
48 u8 n_bytes; /* current is a 1/2/4 byte op */
49 u8 tmode; /* TR/TO/RO/EEPROM */
50 u8 type; /* SPI/SSP/MicroWire */
51
52 u8 poll_mode; /* 1 means use poll mode */
53
54 u32 dma_width;
55 u32 rx_threshold;
56 u32 tx_threshold;
57 u8 enable_dma;
58 u8 bits_per_word;
59 u16 clk_div; /* baud rate divider */
60 u32 speed_hz; /* baud rate */
e24c7452
FT		 61 void (*cs_control)(u32 command);
62};
63
64#ifdef CONFIG_DEBUG_FS
65static int spi_show_regs_open(struct inode *inode, struct file *file)
66{
67 file->private_data = inode->i_private;
68 return 0;
69}
70
71#define SPI_REGS_BUFSIZE 1024
72static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
73 size_t count, loff_t *ppos)
74{
75 struct dw_spi *dws;
76 char *buf;
77 u32 len = 0;
78 ssize_t ret;
79
80 dws = file->private_data;
81
82 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
83 if (!buf)
84 return 0;
85
86 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
87 "MRST SPI0 registers:\n");
88 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
89 "=================================\n");
90 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
91 "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
92 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
93 "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
94 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
95 "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
96 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
97 "SER: \t\t0x%08x\n", dw_readl(dws, ser));
98 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
99 "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
100 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
101 "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
102 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
103 "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
104 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
105 "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
106 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
107 "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
108 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
109 "SR: \t\t0x%08x\n", dw_readl(dws, sr));
110 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
111 "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
112 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
113 "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
114 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
115 "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
116 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
117 "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
118 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
119 "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
120 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
121 "=================================\n");
122
123 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
124 kfree(buf);
125 return ret;
126}
127
128static const struct file_operations mrst_spi_regs_ops = {
129 .owner = THIS_MODULE,
130 .open = spi_show_regs_open,
131 .read = spi_show_regs,
6038f373 132 .llseek = default_llseek,
e24c7452
FT		 133};
134
135static int mrst_spi_debugfs_init(struct dw_spi *dws)
136{
137 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
138 if (!dws->debugfs)
139 return -ENOMEM;
140
141 debugfs_create_file("registers", S_IFREG | S_IRUGO,
142 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
143 return 0;
144}
145
146static void mrst_spi_debugfs_remove(struct dw_spi *dws)
147{
148 if (dws->debugfs)
149 debugfs_remove_recursive(dws->debugfs);
150}
151
152#else
153static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
154{
20a588fc 155 return 0;
e24c7452
FT		 156}
157
158static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
159{
160}
161#endif /* CONFIG_DEBUG_FS */
162
163static void wait_till_not_busy(struct dw_spi *dws)
164{
ebf45b7d 165 unsigned long end = jiffies + 1 + usecs_to_jiffies(5000);
e24c7452
FT		 166
167 while (time_before(jiffies, end)) {
168 if (!(dw_readw(dws, sr) & SR_BUSY))
169 return;
ebf45b7d 170 cpu_relax();
e24c7452
FT		 171 }
172 dev_err(&dws->master->dev,
ebf45b7d 173 "DW SPI: Status keeps busy for 5000us after a read/write!\n");
e24c7452
FT		 174}
175
de6efe0a 176static int dw_writer(struct dw_spi *dws)
e24c7452 177{
de6efe0a 178 u16 txw = 0;
e24c7452 179
e24c7452
FT		 180 if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
181 || (dws->tx == dws->tx_end))
182 return 0;
183
de6efe0a
FT		 184 /* Set the tx word if the transfer's original "tx" is not null */
185 if (dws->tx_end - dws->len) {
186 if (dws->n_bytes == 1)
187 txw = *(u8 *)(dws->tx);
188 else
189 txw = *(u16 *)(dws->tx);
e24c7452
FT		 190 }
191
de6efe0a
FT		 192 dw_writew(dws, dr, txw);
193 dws->tx += dws->n_bytes;
e24c7452
FT		 194
195 wait_till_not_busy(dws);
196 return 1;
197}
198
de6efe0a 199static int dw_reader(struct dw_spi *dws)
e24c7452 200{
de6efe0a 201 u16 rxw;
e24c7452
FT		 202
203 while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
204 && (dws->rx < dws->rx_end)) {
de6efe0a
FT		 205 rxw = dw_readw(dws, dr);
206 /* Care rx only if the transfer's original "rx" is not null */
207 if (dws->rx_end - dws->len) {
208 if (dws->n_bytes == 1)
209 *(u8 *)(dws->rx) = rxw;
210 else
211 *(u16 *)(dws->rx) = rxw;
212 }
213 dws->rx += dws->n_bytes;
e24c7452
FT		 214 }
215
216 wait_till_not_busy(dws);
217 return dws->rx == dws->rx_end;
218}
219
220static void *next_transfer(struct dw_spi *dws)
221{
222 struct spi_message *msg = dws->cur_msg;
223 struct spi_transfer *trans = dws->cur_transfer;
224
225 /* Move to next transfer */
226 if (trans->transfer_list.next != &msg->transfers) {
227 dws->cur_transfer =
228 list_entry(trans->transfer_list.next,
229 struct spi_transfer,
230 transfer_list);
231 return RUNNING_STATE;
232 } else
233 return DONE_STATE;
234}
235
236/*
237 * Note: first step is the protocol driver prepares
238 * a dma-capable memory, and this func just need translate
239 * the virt addr to physical
240 */
241static int map_dma_buffers(struct dw_spi *dws)
242{
7063c0d9
FT		 243 if (!dws->cur_msg->is_dma_mapped
244 || !dws->dma_inited
245 || !dws->cur_chip->enable_dma
246 || !dws->dma_ops)
e24c7452
FT		 247 return 0;
248
249 if (dws->cur_transfer->tx_dma)
250 dws->tx_dma = dws->cur_transfer->tx_dma;
251
252 if (dws->cur_transfer->rx_dma)
253 dws->rx_dma = dws->cur_transfer->rx_dma;
254
255 return 1;
256}
257
258/* Caller already set message->status; dma and pio irqs are blocked */
259static void giveback(struct dw_spi *dws)
260{
261 struct spi_transfer *last_transfer;
262 unsigned long flags;
263 struct spi_message *msg;
264
265 spin_lock_irqsave(&dws->lock, flags);
266 msg = dws->cur_msg;
267 dws->cur_msg = NULL;
268 dws->cur_transfer = NULL;
269 dws->prev_chip = dws->cur_chip;
270 dws->cur_chip = NULL;
271 dws->dma_mapped = 0;
272 queue_work(dws->workqueue, &dws->pump_messages);
273 spin_unlock_irqrestore(&dws->lock, flags);
274
275 last_transfer = list_entry(msg->transfers.prev,
276 struct spi_transfer,
277 transfer_list);
278
e3e55ff5 279 if (!last_transfer->cs_change && dws->cs_control)
e24c7452
FT		 280 dws->cs_control(MRST_SPI_DEASSERT);
281
282 msg->state = NULL;
283 if (msg->complete)
284 msg->complete(msg->context);
285}
286
287static void int_error_stop(struct dw_spi *dws, const char *msg)
288{
8a33a373 289 /* Stop the hw */
e24c7452
FT		 290 spi_enable_chip(dws, 0);
291
292 dev_err(&dws->master->dev, "%s\n", msg);
293 dws->cur_msg->state = ERROR_STATE;
294 tasklet_schedule(&dws->pump_transfers);
295}
296
7063c0d9 297void dw_spi_xfer_done(struct dw_spi *dws)
e24c7452
FT		 298{
299 /* Update total byte transfered return count actual bytes read */
300 dws->cur_msg->actual_length += dws->len;
301
302 /* Move to next transfer */
303 dws->cur_msg->state = next_transfer(dws);
304
305 /* Handle end of message */
306 if (dws->cur_msg->state == DONE_STATE) {
307 dws->cur_msg->status = 0;
308 giveback(dws);
309 } else
310 tasklet_schedule(&dws->pump_transfers);
311}
7063c0d9 312EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
e24c7452
FT		 313
314static irqreturn_t interrupt_transfer(struct dw_spi *dws)
315{
316 u16 irq_status, irq_mask = 0x3f;
552e4509
FT		 317 u32 int_level = dws->fifo_len / 2;
318 u32 left;
e24c7452
FT		 319
320 irq_status = dw_readw(dws, isr) & irq_mask;
321 /* Error handling */
322 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
323 dw_readw(dws, txoicr);
324 dw_readw(dws, rxoicr);
325 dw_readw(dws, rxuicr);
326 int_error_stop(dws, "interrupt_transfer: fifo overrun");
327 return IRQ_HANDLED;
328 }
329
552e4509
FT		 330 if (irq_status & SPI_INT_TXEI) {
331 spi_mask_intr(dws, SPI_INT_TXEI);
332
333 left = (dws->tx_end - dws->tx) / dws->n_bytes;
334 left = (left > int_level) ? int_level : left;
335
336 while (left--)
de6efe0a
FT		 337 dw_writer(dws);
338 dw_reader(dws);
e24c7452 339
552e4509
FT		 340 /* Re-enable the IRQ if there is still data left to tx */
341 if (dws->tx_end > dws->tx)
342 spi_umask_intr(dws, SPI_INT_TXEI);
343 else
7063c0d9 344 dw_spi_xfer_done(dws);
e24c7452
FT		 345 }
346
e24c7452
FT		 347 return IRQ_HANDLED;
348}
349
350static irqreturn_t dw_spi_irq(int irq, void *dev_id)
351{
352 struct dw_spi *dws = dev_id;
cbcc062a
YW		 353 u16 irq_status, irq_mask = 0x3f;
354
355 irq_status = dw_readw(dws, isr) & irq_mask;
356 if (!irq_status)
357 return IRQ_NONE;
e24c7452
FT		 358
359 if (!dws->cur_msg) {
360 spi_mask_intr(dws, SPI_INT_TXEI);
361 /* Never fail */
362 return IRQ_HANDLED;
363 }
364
365 return dws->transfer_handler(dws);
366}
367
368/* Must be called inside pump_transfers() */
369static void poll_transfer(struct dw_spi *dws)
370{
de6efe0a
FT		 371 while (dw_writer(dws))
372 dw_reader(dws);
3d0b6087
ML		 373 /*
374 * There is a possibility that the last word of a transaction
375 * will be lost if data is not ready. Re-read to solve this issue.
376 */
de6efe0a 377 dw_reader(dws);
e24c7452 378
7063c0d9 379 dw_spi_xfer_done(dws);
e24c7452
FT		 380}
381
382static void pump_transfers(unsigned long data)
383{
384 struct dw_spi *dws = (struct dw_spi *)data;
385 struct spi_message *message = NULL;
386 struct spi_transfer *transfer = NULL;
387 struct spi_transfer *previous = NULL;
388 struct spi_device *spi = NULL;
389 struct chip_data *chip = NULL;
390 u8 bits = 0;
391 u8 imask = 0;
392 u8 cs_change = 0;
552e4509 393 u16 txint_level = 0;
e24c7452
FT		 394 u16 clk_div = 0;
395 u32 speed = 0;
396 u32 cr0 = 0;
397
398 /* Get current state information */
399 message = dws->cur_msg;
400 transfer = dws->cur_transfer;
401 chip = dws->cur_chip;
402 spi = message->spi;
403
552e4509
FT		 404 if (unlikely(!chip->clk_div))
405 chip->clk_div = dws->max_freq / chip->speed_hz;
406
e24c7452
FT		 407 if (message->state == ERROR_STATE) {
408 message->status = -EIO;
409 goto early_exit;
410 }
411
412 /* Handle end of message */
413 if (message->state == DONE_STATE) {
414 message->status = 0;
415 goto early_exit;
416 }
417
418 /* Delay if requested at end of transfer*/
419 if (message->state == RUNNING_STATE) {
420 previous = list_entry(transfer->transfer_list.prev,
421 struct spi_transfer,
422 transfer_list);
423 if (previous->delay_usecs)
424 udelay(previous->delay_usecs);
425 }
426
427 dws->n_bytes = chip->n_bytes;
428 dws->dma_width = chip->dma_width;
429 dws->cs_control = chip->cs_control;
430
431 dws->rx_dma = transfer->rx_dma;
432 dws->tx_dma = transfer->tx_dma;
433 dws->tx = (void *)transfer->tx_buf;
434 dws->tx_end = dws->tx + transfer->len;
435 dws->rx = transfer->rx_buf;
436 dws->rx_end = dws->rx + transfer->len;
e24c7452
FT		 437 dws->cs_change = transfer->cs_change;
438 dws->len = dws->cur_transfer->len;
439 if (chip != dws->prev_chip)
440 cs_change = 1;
441
442 cr0 = chip->cr0;
443
444 /* Handle per transfer options for bpw and speed */
445 if (transfer->speed_hz) {
446 speed = chip->speed_hz;
447
448 if (transfer->speed_hz != speed) {
449 speed = transfer->speed_hz;
450 if (speed > dws->max_freq) {
451 printk(KERN_ERR "MRST SPI0: unsupported"
452 "freq: %dHz\n", speed);
453 message->status = -EIO;
454 goto early_exit;
455 }
456
457 /* clk_div doesn't support odd number */
458 clk_div = dws->max_freq / speed;
552e4509 459 clk_div = (clk_div + 1) & 0xfffe;
e24c7452
FT		 460
461 chip->speed_hz = speed;
462 chip->clk_div = clk_div;
463 }
464 }
465 if (transfer->bits_per_word) {
466 bits = transfer->bits_per_word;
467
468 switch (bits) {
469 case 8:
470 dws->n_bytes = 1;
471 dws->dma_width = 1;
e24c7452
FT		 472 break;
473 case 16:
474 dws->n_bytes = 2;
475 dws->dma_width = 2;
e24c7452
FT		 476 break;
477 default:
478 printk(KERN_ERR "MRST SPI0: unsupported bits:"
479 "%db\n", bits);
480 message->status = -EIO;
481 goto early_exit;
482 }
483
484 cr0 = (bits - 1)
485 | (chip->type << SPI_FRF_OFFSET)
486 | (spi->mode << SPI_MODE_OFFSET)
487 | (chip->tmode << SPI_TMOD_OFFSET);
488 }
489 message->state = RUNNING_STATE;
490
052dc7c4
GS		 491 /*
492 * Adjust transfer mode if necessary. Requires platform dependent
493 * chipselect mechanism.
494 */
495 if (dws->cs_control) {
496 if (dws->rx && dws->tx)
e3e55ff5 497 chip->tmode = SPI_TMOD_TR;
052dc7c4 498 else if (dws->rx)
e3e55ff5 499 chip->tmode = SPI_TMOD_RO;
052dc7c4 500 else
e3e55ff5 501 chip->tmode = SPI_TMOD_TO;
052dc7c4 502
e3e55ff5 503 cr0 &= ~SPI_TMOD_MASK;
052dc7c4
GS		 504 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
505 }
506
e24c7452
FT		 507 /* Check if current transfer is a DMA transaction */
508 dws->dma_mapped = map_dma_buffers(dws);
509
552e4509
FT		 510 /*
511 * Interrupt mode
512 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
513 */
e24c7452 514 if (!dws->dma_mapped && !chip->poll_mode) {
552e4509
FT		 515 int templen = dws->len / dws->n_bytes;
516 txint_level = dws->fifo_len / 2;
517 txint_level = (templen > txint_level) ? txint_level : templen;
518
519 imask |= SPI_INT_TXEI;
e24c7452
FT		 520 dws->transfer_handler = interrupt_transfer;
521 }
522
523 /*
524 * Reprogram registers only if
525 * 1. chip select changes
526 * 2. clk_div is changed
527 * 3. control value changes
528 */
552e4509 529 if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
e24c7452
FT		 530 spi_enable_chip(dws, 0);
531
532 if (dw_readw(dws, ctrl0) != cr0)
533 dw_writew(dws, ctrl0, cr0);
534
552e4509
FT		 535 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
536 spi_chip_sel(dws, spi->chip_select);
537
2f263d9d 538 /* Set the interrupt mask, for poll mode just disable all int */
e24c7452 539 spi_mask_intr(dws, 0xff);
552e4509 540 if (imask)
e24c7452 541 spi_umask_intr(dws, imask);
552e4509
FT		 542 if (txint_level)
543 dw_writew(dws, txfltr, txint_level);
e24c7452 544
e24c7452 545 spi_enable_chip(dws, 1);
e24c7452
FT		 546 if (cs_change)
547 dws->prev_chip = chip;
548 }
549
550 if (dws->dma_mapped)
7063c0d9 551 dws->dma_ops->dma_transfer(dws, cs_change);
e24c7452
FT		 552
553 if (chip->poll_mode)
554 poll_transfer(dws);
555
556 return;
557
558early_exit:
559 giveback(dws);
560 return;
561}
562
563static void pump_messages(struct work_struct *work)
564{
565 struct dw_spi *dws =
566 container_of(work, struct dw_spi, pump_messages);
567 unsigned long flags;
568
569 /* Lock queue and check for queue work */
570 spin_lock_irqsave(&dws->lock, flags);
571 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
572 dws->busy = 0;
573 spin_unlock_irqrestore(&dws->lock, flags);
574 return;
575 }
576
577 /* Make sure we are not already running a message */
578 if (dws->cur_msg) {
579 spin_unlock_irqrestore(&dws->lock, flags);
580 return;
581 }
582
583 /* Extract head of queue */
584 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
585 list_del_init(&dws->cur_msg->queue);
586
587 /* Initial message state*/
588 dws->cur_msg->state = START_STATE;
589 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
590 struct spi_transfer,
591 transfer_list);
592 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
593
594 /* Mark as busy and launch transfers */
595 tasklet_schedule(&dws->pump_transfers);
596
597 dws->busy = 1;
598 spin_unlock_irqrestore(&dws->lock, flags);
599}
600
601/* spi_device use this to queue in their spi_msg */
602static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
603{
604 struct dw_spi *dws = spi_master_get_devdata(spi->master);
605 unsigned long flags;
606
607 spin_lock_irqsave(&dws->lock, flags);
608
609 if (dws->run == QUEUE_STOPPED) {
610 spin_unlock_irqrestore(&dws->lock, flags);
611 return -ESHUTDOWN;
612 }
613
614 msg->actual_length = 0;
615 msg->status = -EINPROGRESS;
616 msg->state = START_STATE;
617
618 list_add_tail(&msg->queue, &dws->queue);
619
620 if (dws->run == QUEUE_RUNNING && !dws->busy) {
621
622 if (dws->cur_transfer || dws->cur_msg)
623 queue_work(dws->workqueue,
624 &dws->pump_messages);
625 else {
626 /* If no other data transaction in air, just go */
627 spin_unlock_irqrestore(&dws->lock, flags);
628 pump_messages(&dws->pump_messages);
629 return 0;
630 }
631 }
632
633 spin_unlock_irqrestore(&dws->lock, flags);
634 return 0;
635}
636
637/* This may be called twice for each spi dev */
638static int dw_spi_setup(struct spi_device *spi)
639{
640 struct dw_spi_chip *chip_info = NULL;
641 struct chip_data *chip;
642
643 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
644 return -EINVAL;
645
646 /* Only alloc on first setup */
647 chip = spi_get_ctldata(spi);
648 if (!chip) {
649 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
650 if (!chip)
651 return -ENOMEM;
e24c7452
FT		 652 }
653
654 /*
655 * Protocol drivers may change the chip settings, so...
656 * if chip_info exists, use it
657 */
658 chip_info = spi->controller_data;
659
660 /* chip_info doesn't always exist */
661 if (chip_info) {
662 if (chip_info->cs_control)
663 chip->cs_control = chip_info->cs_control;
664
665 chip->poll_mode = chip_info->poll_mode;
666 chip->type = chip_info->type;
667
668 chip->rx_threshold = 0;
669 chip->tx_threshold = 0;
670
671 chip->enable_dma = chip_info->enable_dma;
672 }
673
674 if (spi->bits_per_word <= 8) {
675 chip->n_bytes = 1;
676 chip->dma_width = 1;
e24c7452
FT		 677 } else if (spi->bits_per_word <= 16) {
678 chip->n_bytes = 2;
679 chip->dma_width = 2;
e24c7452
FT		 680 } else {
681 /* Never take >16b case for MRST SPIC */
682 dev_err(&spi->dev, "invalid wordsize\n");
683 return -EINVAL;
684 }
685 chip->bits_per_word = spi->bits_per_word;
686
552e4509
FT		 687 if (!spi->max_speed_hz) {
688 dev_err(&spi->dev, "No max speed HZ parameter\n");
689 return -EINVAL;
690 }
e24c7452 691 chip->speed_hz = spi->max_speed_hz;
e24c7452
FT		 692
693 chip->tmode = 0; /* Tx & Rx */
694 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
695 chip->cr0 = (chip->bits_per_word - 1)
696 | (chip->type << SPI_FRF_OFFSET)
697 | (spi->mode << SPI_MODE_OFFSET)
698 | (chip->tmode << SPI_TMOD_OFFSET);
699
700 spi_set_ctldata(spi, chip);
701 return 0;
702}
703
704static void dw_spi_cleanup(struct spi_device *spi)
705{
706 struct chip_data *chip = spi_get_ctldata(spi);
707 kfree(chip);
708}
709
99147b5c 710static int __devinit init_queue(struct dw_spi *dws)
e24c7452
FT		 711{
712 INIT_LIST_HEAD(&dws->queue);
713 spin_lock_init(&dws->lock);
714
715 dws->run = QUEUE_STOPPED;
716 dws->busy = 0;
717
718 tasklet_init(&dws->pump_transfers,
719 pump_transfers, (unsigned long)dws);
720
721 INIT_WORK(&dws->pump_messages, pump_messages);
722 dws->workqueue = create_singlethread_workqueue(
723 dev_name(dws->master->dev.parent));
724 if (dws->workqueue == NULL)
725 return -EBUSY;
726
727 return 0;
728}
729
730static int start_queue(struct dw_spi *dws)
731{
732 unsigned long flags;
733
734 spin_lock_irqsave(&dws->lock, flags);
735
736 if (dws->run == QUEUE_RUNNING || dws->busy) {
737 spin_unlock_irqrestore(&dws->lock, flags);
738 return -EBUSY;
739 }
740
741 dws->run = QUEUE_RUNNING;
742 dws->cur_msg = NULL;
743 dws->cur_transfer = NULL;
744 dws->cur_chip = NULL;
745 dws->prev_chip = NULL;
746 spin_unlock_irqrestore(&dws->lock, flags);
747
748 queue_work(dws->workqueue, &dws->pump_messages);
749
750 return 0;
751}
752
753static int stop_queue(struct dw_spi *dws)
754{
755 unsigned long flags;
756 unsigned limit = 50;
757 int status = 0;
758
759 spin_lock_irqsave(&dws->lock, flags);
760 dws->run = QUEUE_STOPPED;
761 while (!list_empty(&dws->queue) && dws->busy && limit--) {
762 spin_unlock_irqrestore(&dws->lock, flags);
763 msleep(10);
764 spin_lock_irqsave(&dws->lock, flags);
765 }
766
767 if (!list_empty(&dws->queue) || dws->busy)
768 status = -EBUSY;
769 spin_unlock_irqrestore(&dws->lock, flags);
770
771 return status;
772}
773
774static int destroy_queue(struct dw_spi *dws)
775{
776 int status;
777
778 status = stop_queue(dws);
779 if (status != 0)
780 return status;
781 destroy_workqueue(dws->workqueue);
782 return 0;
783}
784
785/* Restart the controller, disable all interrupts, clean rx fifo */
786static void spi_hw_init(struct dw_spi *dws)
787{
788 spi_enable_chip(dws, 0);
789 spi_mask_intr(dws, 0xff);
790 spi_enable_chip(dws, 1);
c587b6fa
FT		 791
792 /*
793 * Try to detect the FIFO depth if not set by interface driver,
794 * the depth could be from 2 to 256 from HW spec
795 */
796 if (!dws->fifo_len) {
797 u32 fifo;
798 for (fifo = 2; fifo <= 257; fifo++) {
799 dw_writew(dws, txfltr, fifo);
800 if (fifo != dw_readw(dws, txfltr))
801 break;
802 }
803
804 dws->fifo_len = (fifo == 257) ? 0 : fifo;
805 dw_writew(dws, txfltr, 0);
806 }
e24c7452
FT		 807}
808
809int __devinit dw_spi_add_host(struct dw_spi *dws)
810{
811 struct spi_master *master;
812 int ret;
813
814 BUG_ON(dws == NULL);
815
816 master = spi_alloc_master(dws->parent_dev, 0);
817 if (!master) {
818 ret = -ENOMEM;
819 goto exit;
820 }
821
822 dws->master = master;
823 dws->type = SSI_MOTO_SPI;
824 dws->prev_chip = NULL;
825 dws->dma_inited = 0;
826 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
827
cbcc062a 828 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
e24c7452
FT		 829 "dw_spi", dws);
830 if (ret < 0) {
831 dev_err(&master->dev, "can not get IRQ\n");
832 goto err_free_master;
833 }
834
835 master->mode_bits = SPI_CPOL | SPI_CPHA;
836 master->bus_num = dws->bus_num;
837 master->num_chipselect = dws->num_cs;
838 master->cleanup = dw_spi_cleanup;
839 master->setup = dw_spi_setup;
840 master->transfer = dw_spi_transfer;
841
e24c7452
FT		 842 /* Basic HW init */
843 spi_hw_init(dws);
844
7063c0d9
FT		 845 if (dws->dma_ops && dws->dma_ops->dma_init) {
846 ret = dws->dma_ops->dma_init(dws);
847 if (ret) {
848 dev_warn(&master->dev, "DMA init failed\n");
849 dws->dma_inited = 0;
850 }
851 }
852
e24c7452
FT		 853 /* Initial and start queue */
854 ret = init_queue(dws);
855 if (ret) {
856 dev_err(&master->dev, "problem initializing queue\n");
857 goto err_diable_hw;
858 }
859 ret = start_queue(dws);
860 if (ret) {
861 dev_err(&master->dev, "problem starting queue\n");
862 goto err_diable_hw;
863 }
864
865 spi_master_set_devdata(master, dws);
866 ret = spi_register_master(master);
867 if (ret) {
868 dev_err(&master->dev, "problem registering spi master\n");
869 goto err_queue_alloc;
870 }
871
872 mrst_spi_debugfs_init(dws);
873 return 0;
874
875err_queue_alloc:
876 destroy_queue(dws);
7063c0d9
FT		 877 if (dws->dma_ops && dws->dma_ops->dma_exit)
878 dws->dma_ops->dma_exit(dws);
e24c7452
FT		 879err_diable_hw:
880 spi_enable_chip(dws, 0);
881 free_irq(dws->irq, dws);
882err_free_master:
883 spi_master_put(master);
884exit:
885 return ret;
886}
79290a2a 887EXPORT_SYMBOL_GPL(dw_spi_add_host);
e24c7452
FT		 888
889void __devexit dw_spi_remove_host(struct dw_spi *dws)
890{
891 int status = 0;
892
893 if (!dws)
894 return;
895 mrst_spi_debugfs_remove(dws);
896
897 /* Remove the queue */
898 status = destroy_queue(dws);
899 if (status != 0)
900 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
901 "complete, message memory not freed\n");
902
7063c0d9
FT		 903 if (dws->dma_ops && dws->dma_ops->dma_exit)
904 dws->dma_ops->dma_exit(dws);
e24c7452
FT		 905 spi_enable_chip(dws, 0);
906 /* Disable clk */
907 spi_set_clk(dws, 0);
908 free_irq(dws->irq, dws);
909
910 /* Disconnect from the SPI framework */
911 spi_unregister_master(dws->master);
912}
79290a2a 913EXPORT_SYMBOL_GPL(dw_spi_remove_host);
e24c7452
FT		 914
915int dw_spi_suspend_host(struct dw_spi *dws)
916{
917 int ret = 0;
918
919 ret = stop_queue(dws);
920 if (ret)
921 return ret;
922 spi_enable_chip(dws, 0);
923 spi_set_clk(dws, 0);
924 return ret;
925}
79290a2a 926EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
e24c7452
FT		 927
928int dw_spi_resume_host(struct dw_spi *dws)
929{
930 int ret;
931
932 spi_hw_init(dws);
933 ret = start_queue(dws);
934 if (ret)
935 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
936 return ret;
937}
79290a2a 938EXPORT_SYMBOL_GPL(dw_spi_resume_host);
e24c7452
FT		 939
940MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
941MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
942MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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