Commit | Line | Data |
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fa4bd4f1 SJ |
1 | /* |
2 | * Analog Devices SPI3 controller driver | |
3 | * | |
766e3721 | 4 | * Copyright (c) 2014 Analog Devices Inc. |
fa4bd4f1 SJ |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
c34cc248 | 16 | #include <linux/clk.h> |
fa4bd4f1 SJ |
17 | #include <linux/delay.h> |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/gpio.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/spi/spi.h> | |
766e3721 | 30 | #include <linux/spi/adi_spi3.h> |
fa4bd4f1 SJ |
31 | #include <linux/types.h> |
32 | ||
fa4bd4f1 SJ |
33 | #include <asm/dma.h> |
34 | #include <asm/portmux.h> | |
35 | ||
766e3721 | 36 | enum adi_spi_state { |
fa4bd4f1 SJ |
37 | START_STATE, |
38 | RUNNING_STATE, | |
39 | DONE_STATE, | |
40 | ERROR_STATE | |
41 | }; | |
42 | ||
766e3721 | 43 | struct adi_spi_master; |
fa4bd4f1 | 44 | |
766e3721 SJ |
45 | struct adi_spi_transfer_ops { |
46 | void (*write) (struct adi_spi_master *); | |
47 | void (*read) (struct adi_spi_master *); | |
48 | void (*duplex) (struct adi_spi_master *); | |
fa4bd4f1 SJ |
49 | }; |
50 | ||
51 | /* runtime info for spi master */ | |
766e3721 | 52 | struct adi_spi_master { |
fa4bd4f1 SJ |
53 | /* SPI framework hookup */ |
54 | struct spi_master *master; | |
55 | ||
56 | /* Regs base of SPI controller */ | |
766e3721 | 57 | struct adi_spi_regs __iomem *regs; |
fa4bd4f1 SJ |
58 | |
59 | /* Pin request list */ | |
60 | u16 *pin_req; | |
61 | ||
62 | /* Message Transfer pump */ | |
63 | struct tasklet_struct pump_transfers; | |
64 | ||
65 | /* Current message transfer state info */ | |
66 | struct spi_message *cur_msg; | |
67 | struct spi_transfer *cur_transfer; | |
766e3721 | 68 | struct adi_spi_device *cur_chip; |
fa4bd4f1 SJ |
69 | unsigned transfer_len; |
70 | ||
71 | /* transfer buffer */ | |
72 | void *tx; | |
73 | void *tx_end; | |
74 | void *rx; | |
75 | void *rx_end; | |
76 | ||
77 | /* dma info */ | |
78 | unsigned int tx_dma; | |
79 | unsigned int rx_dma; | |
80 | dma_addr_t tx_dma_addr; | |
81 | dma_addr_t rx_dma_addr; | |
82 | unsigned long dummy_buffer; /* used in unidirectional transfer */ | |
83 | unsigned long tx_dma_size; | |
84 | unsigned long rx_dma_size; | |
85 | int tx_num; | |
86 | int rx_num; | |
87 | ||
88 | /* store register value for suspend/resume */ | |
89 | u32 control; | |
90 | u32 ssel; | |
91 | ||
92 | unsigned long sclk; | |
766e3721 | 93 | enum adi_spi_state state; |
fa4bd4f1 | 94 | |
766e3721 | 95 | const struct adi_spi_transfer_ops *ops; |
fa4bd4f1 SJ |
96 | }; |
97 | ||
766e3721 | 98 | struct adi_spi_device { |
fa4bd4f1 SJ |
99 | u32 control; |
100 | u32 clock; | |
101 | u32 ssel; | |
102 | ||
103 | u8 cs; | |
104 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ | |
105 | u32 cs_gpio; | |
106 | u32 tx_dummy_val; /* tx value for rx only transfer */ | |
107 | bool enable_dma; | |
766e3721 | 108 | const struct adi_spi_transfer_ops *ops; |
fa4bd4f1 SJ |
109 | }; |
110 | ||
766e3721 | 111 | static void adi_spi_enable(struct adi_spi_master *drv_data) |
fa4bd4f1 | 112 | { |
766e3721 SJ |
113 | u32 ctl; |
114 | ||
115 | ctl = ioread32(&drv_data->regs->control); | |
116 | ctl |= SPI_CTL_EN; | |
117 | iowrite32(ctl, &drv_data->regs->control); | |
fa4bd4f1 SJ |
118 | } |
119 | ||
766e3721 | 120 | static void adi_spi_disable(struct adi_spi_master *drv_data) |
fa4bd4f1 | 121 | { |
766e3721 SJ |
122 | u32 ctl; |
123 | ||
124 | ctl = ioread32(&drv_data->regs->control); | |
125 | ctl &= ~SPI_CTL_EN; | |
126 | iowrite32(ctl, &drv_data->regs->control); | |
fa4bd4f1 SJ |
127 | } |
128 | ||
129 | /* Caculate the SPI_CLOCK register value based on input HZ */ | |
130 | static u32 hz_to_spi_clock(u32 sclk, u32 speed_hz) | |
131 | { | |
132 | u32 spi_clock = sclk / speed_hz; | |
133 | ||
134 | if (spi_clock) | |
135 | spi_clock--; | |
136 | return spi_clock; | |
137 | } | |
138 | ||
766e3721 | 139 | static int adi_spi_flush(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
140 | { |
141 | unsigned long limit = loops_per_jiffy << 1; | |
142 | ||
143 | /* wait for stop and clear stat */ | |
766e3721 | 144 | while (!(ioread32(&drv_data->regs->status) & SPI_STAT_SPIF) && --limit) |
fa4bd4f1 SJ |
145 | cpu_relax(); |
146 | ||
766e3721 | 147 | iowrite32(0xFFFFFFFF, &drv_data->regs->status); |
fa4bd4f1 SJ |
148 | |
149 | return limit; | |
150 | } | |
151 | ||
152 | /* Chip select operation functions for cs_change flag */ | |
766e3721 | 153 | static void adi_spi_cs_active(struct adi_spi_master *drv_data, struct adi_spi_device *chip) |
fa4bd4f1 | 154 | { |
766e3721 SJ |
155 | if (likely(chip->cs < MAX_CTRL_CS)) { |
156 | u32 reg; | |
157 | reg = ioread32(&drv_data->regs->ssel); | |
158 | reg &= ~chip->ssel; | |
159 | iowrite32(reg, &drv_data->regs->ssel); | |
160 | } else { | |
fa4bd4f1 | 161 | gpio_set_value(chip->cs_gpio, 0); |
766e3721 | 162 | } |
fa4bd4f1 SJ |
163 | } |
164 | ||
766e3721 SJ |
165 | static void adi_spi_cs_deactive(struct adi_spi_master *drv_data, |
166 | struct adi_spi_device *chip) | |
fa4bd4f1 | 167 | { |
766e3721 SJ |
168 | if (likely(chip->cs < MAX_CTRL_CS)) { |
169 | u32 reg; | |
170 | reg = ioread32(&drv_data->regs->ssel); | |
171 | reg |= chip->ssel; | |
172 | iowrite32(reg, &drv_data->regs->ssel); | |
173 | } else { | |
fa4bd4f1 | 174 | gpio_set_value(chip->cs_gpio, 1); |
766e3721 | 175 | } |
fa4bd4f1 SJ |
176 | |
177 | /* Move delay here for consistency */ | |
178 | if (chip->cs_chg_udelay) | |
179 | udelay(chip->cs_chg_udelay); | |
180 | } | |
181 | ||
182 | /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ | |
766e3721 SJ |
183 | static inline void adi_spi_cs_enable(struct adi_spi_master *drv_data, |
184 | struct adi_spi_device *chip) | |
fa4bd4f1 | 185 | { |
766e3721 SJ |
186 | if (chip->cs < MAX_CTRL_CS) { |
187 | u32 reg; | |
188 | reg = ioread32(&drv_data->regs->ssel); | |
189 | reg |= chip->ssel >> 8; | |
190 | iowrite32(reg, &drv_data->regs->ssel); | |
191 | } | |
fa4bd4f1 SJ |
192 | } |
193 | ||
766e3721 SJ |
194 | static inline void adi_spi_cs_disable(struct adi_spi_master *drv_data, |
195 | struct adi_spi_device *chip) | |
fa4bd4f1 | 196 | { |
766e3721 SJ |
197 | if (chip->cs < MAX_CTRL_CS) { |
198 | u32 reg; | |
199 | reg = ioread32(&drv_data->regs->ssel); | |
200 | reg &= ~(chip->ssel >> 8); | |
201 | iowrite32(reg, &drv_data->regs->ssel); | |
202 | } | |
fa4bd4f1 SJ |
203 | } |
204 | ||
205 | /* stop controller and re-config current chip*/ | |
766e3721 | 206 | static void adi_spi_restore_state(struct adi_spi_master *drv_data) |
fa4bd4f1 | 207 | { |
766e3721 | 208 | struct adi_spi_device *chip = drv_data->cur_chip; |
fa4bd4f1 SJ |
209 | |
210 | /* Clear status and disable clock */ | |
766e3721 SJ |
211 | iowrite32(0xFFFFFFFF, &drv_data->regs->status); |
212 | iowrite32(0x0, &drv_data->regs->rx_control); | |
213 | iowrite32(0x0, &drv_data->regs->tx_control); | |
214 | adi_spi_disable(drv_data); | |
fa4bd4f1 SJ |
215 | |
216 | /* Load the registers */ | |
766e3721 SJ |
217 | iowrite32(chip->control, &drv_data->regs->control); |
218 | iowrite32(chip->clock, &drv_data->regs->clock); | |
fa4bd4f1 | 219 | |
766e3721 | 220 | adi_spi_enable(drv_data); |
fa4bd4f1 SJ |
221 | drv_data->tx_num = drv_data->rx_num = 0; |
222 | /* we always choose tx transfer initiate */ | |
766e3721 SJ |
223 | iowrite32(SPI_RXCTL_REN, &drv_data->regs->rx_control); |
224 | iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI, &drv_data->regs->tx_control); | |
225 | adi_spi_cs_active(drv_data, chip); | |
fa4bd4f1 SJ |
226 | } |
227 | ||
228 | /* discard invalid rx data and empty rfifo */ | |
766e3721 | 229 | static inline void dummy_read(struct adi_spi_master *drv_data) |
fa4bd4f1 | 230 | { |
766e3721 SJ |
231 | while (!(ioread32(&drv_data->regs->status) & SPI_STAT_RFE)) |
232 | ioread32(&drv_data->regs->rfifo); | |
fa4bd4f1 SJ |
233 | } |
234 | ||
766e3721 | 235 | static void adi_spi_u8_write(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
236 | { |
237 | dummy_read(drv_data); | |
238 | while (drv_data->tx < drv_data->tx_end) { | |
766e3721 SJ |
239 | iowrite32(*(u8 *)(drv_data->tx++), &drv_data->regs->tfifo); |
240 | while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) | |
fa4bd4f1 | 241 | cpu_relax(); |
766e3721 | 242 | ioread32(&drv_data->regs->rfifo); |
fa4bd4f1 SJ |
243 | } |
244 | } | |
245 | ||
766e3721 | 246 | static void adi_spi_u8_read(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
247 | { |
248 | u32 tx_val = drv_data->cur_chip->tx_dummy_val; | |
249 | ||
250 | dummy_read(drv_data); | |
251 | while (drv_data->rx < drv_data->rx_end) { | |
766e3721 SJ |
252 | iowrite32(tx_val, &drv_data->regs->tfifo); |
253 | while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) | |
fa4bd4f1 | 254 | cpu_relax(); |
766e3721 | 255 | *(u8 *)(drv_data->rx++) = ioread32(&drv_data->regs->rfifo); |
fa4bd4f1 SJ |
256 | } |
257 | } | |
258 | ||
766e3721 | 259 | static void adi_spi_u8_duplex(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
260 | { |
261 | dummy_read(drv_data); | |
262 | while (drv_data->rx < drv_data->rx_end) { | |
766e3721 SJ |
263 | iowrite32(*(u8 *)(drv_data->tx++), &drv_data->regs->tfifo); |
264 | while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) | |
fa4bd4f1 | 265 | cpu_relax(); |
766e3721 | 266 | *(u8 *)(drv_data->rx++) = ioread32(&drv_data->regs->rfifo); |
fa4bd4f1 SJ |
267 | } |
268 | } | |
269 | ||
766e3721 SJ |
270 | static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u8 = { |
271 | .write = adi_spi_u8_write, | |
272 | .read = adi_spi_u8_read, | |
273 | .duplex = adi_spi_u8_duplex, | |
fa4bd4f1 SJ |
274 | }; |
275 | ||
766e3721 | 276 | static void adi_spi_u16_write(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
277 | { |
278 | dummy_read(drv_data); | |
279 | while (drv_data->tx < drv_data->tx_end) { | |
766e3721 | 280 | iowrite32(*(u16 *)drv_data->tx, &drv_data->regs->tfifo); |
fa4bd4f1 | 281 | drv_data->tx += 2; |
766e3721 | 282 | while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) |
fa4bd4f1 | 283 | cpu_relax(); |
766e3721 | 284 | ioread32(&drv_data->regs->rfifo); |
fa4bd4f1 SJ |
285 | } |
286 | } | |
287 | ||
766e3721 | 288 | static void adi_spi_u16_read(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
289 | { |
290 | u32 tx_val = drv_data->cur_chip->tx_dummy_val; | |
291 | ||
292 | dummy_read(drv_data); | |
293 | while (drv_data->rx < drv_data->rx_end) { | |
766e3721 SJ |
294 | iowrite32(tx_val, &drv_data->regs->tfifo); |
295 | while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) | |
fa4bd4f1 | 296 | cpu_relax(); |
766e3721 | 297 | *(u16 *)drv_data->rx = ioread32(&drv_data->regs->rfifo); |
fa4bd4f1 SJ |
298 | drv_data->rx += 2; |
299 | } | |
300 | } | |
301 | ||
766e3721 | 302 | static void adi_spi_u16_duplex(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
303 | { |
304 | dummy_read(drv_data); | |
305 | while (drv_data->rx < drv_data->rx_end) { | |
766e3721 | 306 | iowrite32(*(u16 *)drv_data->tx, &drv_data->regs->tfifo); |
fa4bd4f1 | 307 | drv_data->tx += 2; |
766e3721 | 308 | while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) |
fa4bd4f1 | 309 | cpu_relax(); |
766e3721 | 310 | *(u16 *)drv_data->rx = ioread32(&drv_data->regs->rfifo); |
fa4bd4f1 SJ |
311 | drv_data->rx += 2; |
312 | } | |
313 | } | |
314 | ||
766e3721 SJ |
315 | static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u16 = { |
316 | .write = adi_spi_u16_write, | |
317 | .read = adi_spi_u16_read, | |
318 | .duplex = adi_spi_u16_duplex, | |
fa4bd4f1 SJ |
319 | }; |
320 | ||
766e3721 | 321 | static void adi_spi_u32_write(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
322 | { |
323 | dummy_read(drv_data); | |
324 | while (drv_data->tx < drv_data->tx_end) { | |
766e3721 | 325 | iowrite32(*(u32 *)drv_data->tx, &drv_data->regs->tfifo); |
fa4bd4f1 | 326 | drv_data->tx += 4; |
766e3721 | 327 | while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) |
fa4bd4f1 | 328 | cpu_relax(); |
766e3721 | 329 | ioread32(&drv_data->regs->rfifo); |
fa4bd4f1 SJ |
330 | } |
331 | } | |
332 | ||
766e3721 | 333 | static void adi_spi_u32_read(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
334 | { |
335 | u32 tx_val = drv_data->cur_chip->tx_dummy_val; | |
336 | ||
337 | dummy_read(drv_data); | |
338 | while (drv_data->rx < drv_data->rx_end) { | |
766e3721 SJ |
339 | iowrite32(tx_val, &drv_data->regs->tfifo); |
340 | while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) | |
fa4bd4f1 | 341 | cpu_relax(); |
766e3721 | 342 | *(u32 *)drv_data->rx = ioread32(&drv_data->regs->rfifo); |
fa4bd4f1 SJ |
343 | drv_data->rx += 4; |
344 | } | |
345 | } | |
346 | ||
766e3721 | 347 | static void adi_spi_u32_duplex(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
348 | { |
349 | dummy_read(drv_data); | |
350 | while (drv_data->rx < drv_data->rx_end) { | |
766e3721 | 351 | iowrite32(*(u32 *)drv_data->tx, &drv_data->regs->tfifo); |
fa4bd4f1 | 352 | drv_data->tx += 4; |
766e3721 | 353 | while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) |
fa4bd4f1 | 354 | cpu_relax(); |
766e3721 | 355 | *(u32 *)drv_data->rx = ioread32(&drv_data->regs->rfifo); |
fa4bd4f1 SJ |
356 | drv_data->rx += 4; |
357 | } | |
358 | } | |
359 | ||
766e3721 SJ |
360 | static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u32 = { |
361 | .write = adi_spi_u32_write, | |
362 | .read = adi_spi_u32_read, | |
363 | .duplex = adi_spi_u32_duplex, | |
fa4bd4f1 SJ |
364 | }; |
365 | ||
366 | ||
367 | /* test if there is more transfer to be done */ | |
766e3721 | 368 | static void adi_spi_next_transfer(struct adi_spi_master *drv) |
fa4bd4f1 SJ |
369 | { |
370 | struct spi_message *msg = drv->cur_msg; | |
371 | struct spi_transfer *t = drv->cur_transfer; | |
372 | ||
373 | /* Move to next transfer */ | |
374 | if (t->transfer_list.next != &msg->transfers) { | |
375 | drv->cur_transfer = list_entry(t->transfer_list.next, | |
376 | struct spi_transfer, transfer_list); | |
377 | drv->state = RUNNING_STATE; | |
378 | } else { | |
379 | drv->state = DONE_STATE; | |
380 | drv->cur_transfer = NULL; | |
381 | } | |
382 | } | |
383 | ||
766e3721 | 384 | static void adi_spi_giveback(struct adi_spi_master *drv_data) |
fa4bd4f1 | 385 | { |
766e3721 | 386 | struct adi_spi_device *chip = drv_data->cur_chip; |
fa4bd4f1 | 387 | |
766e3721 | 388 | adi_spi_cs_deactive(drv_data, chip); |
fa4bd4f1 SJ |
389 | spi_finalize_current_message(drv_data->master); |
390 | } | |
391 | ||
766e3721 | 392 | static int adi_spi_setup_transfer(struct adi_spi_master *drv) |
fa4bd4f1 SJ |
393 | { |
394 | struct spi_transfer *t = drv->cur_transfer; | |
395 | u32 cr, cr_width; | |
396 | ||
397 | if (t->tx_buf) { | |
398 | drv->tx = (void *)t->tx_buf; | |
399 | drv->tx_end = drv->tx + t->len; | |
400 | } else { | |
401 | drv->tx = NULL; | |
402 | } | |
403 | ||
404 | if (t->rx_buf) { | |
405 | drv->rx = t->rx_buf; | |
406 | drv->rx_end = drv->rx + t->len; | |
407 | } else { | |
408 | drv->rx = NULL; | |
409 | } | |
410 | ||
411 | drv->transfer_len = t->len; | |
412 | ||
413 | /* bits per word setup */ | |
414 | switch (t->bits_per_word) { | |
415 | case 8: | |
416 | cr_width = SPI_CTL_SIZE08; | |
766e3721 | 417 | drv->ops = &adi_spi_transfer_ops_u8; |
fa4bd4f1 SJ |
418 | break; |
419 | case 16: | |
420 | cr_width = SPI_CTL_SIZE16; | |
766e3721 | 421 | drv->ops = &adi_spi_transfer_ops_u16; |
fa4bd4f1 SJ |
422 | break; |
423 | case 32: | |
424 | cr_width = SPI_CTL_SIZE32; | |
766e3721 | 425 | drv->ops = &adi_spi_transfer_ops_u32; |
fa4bd4f1 SJ |
426 | break; |
427 | default: | |
428 | return -EINVAL; | |
429 | } | |
766e3721 | 430 | cr = ioread32(&drv->regs->control) & ~SPI_CTL_SIZE; |
fa4bd4f1 | 431 | cr |= cr_width; |
766e3721 | 432 | iowrite32(cr, &drv->regs->control); |
fa4bd4f1 SJ |
433 | |
434 | /* speed setup */ | |
766e3721 | 435 | iowrite32(hz_to_spi_clock(drv->sclk, t->speed_hz), &drv->regs->clock); |
fa4bd4f1 SJ |
436 | return 0; |
437 | } | |
438 | ||
766e3721 | 439 | static int adi_spi_dma_xfer(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
440 | { |
441 | struct spi_transfer *t = drv_data->cur_transfer; | |
442 | struct spi_message *msg = drv_data->cur_msg; | |
766e3721 | 443 | struct adi_spi_device *chip = drv_data->cur_chip; |
fa4bd4f1 SJ |
444 | u32 dma_config; |
445 | unsigned long word_count, word_size; | |
446 | void *tx_buf, *rx_buf; | |
447 | ||
448 | switch (t->bits_per_word) { | |
449 | case 8: | |
450 | dma_config = WDSIZE_8 | PSIZE_8; | |
451 | word_count = drv_data->transfer_len; | |
452 | word_size = 1; | |
453 | break; | |
454 | case 16: | |
455 | dma_config = WDSIZE_16 | PSIZE_16; | |
456 | word_count = drv_data->transfer_len / 2; | |
457 | word_size = 2; | |
458 | break; | |
459 | default: | |
460 | dma_config = WDSIZE_32 | PSIZE_32; | |
461 | word_count = drv_data->transfer_len / 4; | |
462 | word_size = 4; | |
463 | break; | |
464 | } | |
465 | ||
466 | if (!drv_data->rx) { | |
467 | tx_buf = drv_data->tx; | |
468 | rx_buf = &drv_data->dummy_buffer; | |
469 | drv_data->tx_dma_size = drv_data->transfer_len; | |
470 | drv_data->rx_dma_size = sizeof(drv_data->dummy_buffer); | |
471 | set_dma_x_modify(drv_data->tx_dma, word_size); | |
472 | set_dma_x_modify(drv_data->rx_dma, 0); | |
473 | } else if (!drv_data->tx) { | |
474 | drv_data->dummy_buffer = chip->tx_dummy_val; | |
475 | tx_buf = &drv_data->dummy_buffer; | |
476 | rx_buf = drv_data->rx; | |
477 | drv_data->tx_dma_size = sizeof(drv_data->dummy_buffer); | |
478 | drv_data->rx_dma_size = drv_data->transfer_len; | |
479 | set_dma_x_modify(drv_data->tx_dma, 0); | |
480 | set_dma_x_modify(drv_data->rx_dma, word_size); | |
481 | } else { | |
482 | tx_buf = drv_data->tx; | |
483 | rx_buf = drv_data->rx; | |
484 | drv_data->tx_dma_size = drv_data->rx_dma_size | |
485 | = drv_data->transfer_len; | |
486 | set_dma_x_modify(drv_data->tx_dma, word_size); | |
487 | set_dma_x_modify(drv_data->rx_dma, word_size); | |
488 | } | |
489 | ||
490 | drv_data->tx_dma_addr = dma_map_single(&msg->spi->dev, | |
491 | (void *)tx_buf, | |
492 | drv_data->tx_dma_size, | |
493 | DMA_TO_DEVICE); | |
494 | if (dma_mapping_error(&msg->spi->dev, | |
495 | drv_data->tx_dma_addr)) | |
496 | return -ENOMEM; | |
497 | ||
498 | drv_data->rx_dma_addr = dma_map_single(&msg->spi->dev, | |
499 | (void *)rx_buf, | |
500 | drv_data->rx_dma_size, | |
501 | DMA_FROM_DEVICE); | |
502 | if (dma_mapping_error(&msg->spi->dev, | |
503 | drv_data->rx_dma_addr)) { | |
504 | dma_unmap_single(&msg->spi->dev, | |
505 | drv_data->tx_dma_addr, | |
506 | drv_data->tx_dma_size, | |
507 | DMA_TO_DEVICE); | |
508 | return -ENOMEM; | |
509 | } | |
510 | ||
511 | dummy_read(drv_data); | |
512 | set_dma_x_count(drv_data->tx_dma, word_count); | |
513 | set_dma_x_count(drv_data->rx_dma, word_count); | |
514 | set_dma_start_addr(drv_data->tx_dma, drv_data->tx_dma_addr); | |
515 | set_dma_start_addr(drv_data->rx_dma, drv_data->rx_dma_addr); | |
516 | dma_config |= DMAFLOW_STOP | RESTART | DI_EN; | |
517 | set_dma_config(drv_data->tx_dma, dma_config); | |
518 | set_dma_config(drv_data->rx_dma, dma_config | WNR); | |
519 | enable_dma(drv_data->tx_dma); | |
520 | enable_dma(drv_data->rx_dma); | |
fa4bd4f1 | 521 | |
766e3721 SJ |
522 | iowrite32(SPI_RXCTL_REN | SPI_RXCTL_RDR_NE, |
523 | &drv_data->regs->rx_control); | |
524 | iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI | SPI_TXCTL_TDR_NF, | |
525 | &drv_data->regs->tx_control); | |
fa4bd4f1 SJ |
526 | |
527 | return 0; | |
528 | } | |
529 | ||
766e3721 | 530 | static int adi_spi_pio_xfer(struct adi_spi_master *drv_data) |
fa4bd4f1 SJ |
531 | { |
532 | struct spi_message *msg = drv_data->cur_msg; | |
533 | ||
534 | if (!drv_data->rx) { | |
535 | /* write only half duplex */ | |
536 | drv_data->ops->write(drv_data); | |
537 | if (drv_data->tx != drv_data->tx_end) | |
538 | return -EIO; | |
539 | } else if (!drv_data->tx) { | |
540 | /* read only half duplex */ | |
541 | drv_data->ops->read(drv_data); | |
542 | if (drv_data->rx != drv_data->rx_end) | |
543 | return -EIO; | |
544 | } else { | |
545 | /* full duplex mode */ | |
546 | drv_data->ops->duplex(drv_data); | |
547 | if (drv_data->tx != drv_data->tx_end) | |
548 | return -EIO; | |
549 | } | |
550 | ||
766e3721 | 551 | if (!adi_spi_flush(drv_data)) |
fa4bd4f1 SJ |
552 | return -EIO; |
553 | msg->actual_length += drv_data->transfer_len; | |
554 | tasklet_schedule(&drv_data->pump_transfers); | |
555 | return 0; | |
556 | } | |
557 | ||
766e3721 | 558 | static void adi_spi_pump_transfers(unsigned long data) |
fa4bd4f1 | 559 | { |
766e3721 | 560 | struct adi_spi_master *drv_data = (struct adi_spi_master *)data; |
fa4bd4f1 SJ |
561 | struct spi_message *msg = NULL; |
562 | struct spi_transfer *t = NULL; | |
766e3721 | 563 | struct adi_spi_device *chip = NULL; |
fa4bd4f1 SJ |
564 | int ret; |
565 | ||
566 | /* Get current state information */ | |
567 | msg = drv_data->cur_msg; | |
568 | t = drv_data->cur_transfer; | |
569 | chip = drv_data->cur_chip; | |
570 | ||
571 | /* Handle for abort */ | |
572 | if (drv_data->state == ERROR_STATE) { | |
573 | msg->status = -EIO; | |
766e3721 | 574 | adi_spi_giveback(drv_data); |
fa4bd4f1 SJ |
575 | return; |
576 | } | |
577 | ||
578 | if (drv_data->state == RUNNING_STATE) { | |
579 | if (t->delay_usecs) | |
580 | udelay(t->delay_usecs); | |
581 | if (t->cs_change) | |
766e3721 SJ |
582 | adi_spi_cs_deactive(drv_data, chip); |
583 | adi_spi_next_transfer(drv_data); | |
fa4bd4f1 SJ |
584 | t = drv_data->cur_transfer; |
585 | } | |
586 | /* Handle end of message */ | |
587 | if (drv_data->state == DONE_STATE) { | |
588 | msg->status = 0; | |
766e3721 | 589 | adi_spi_giveback(drv_data); |
fa4bd4f1 SJ |
590 | return; |
591 | } | |
592 | ||
593 | if ((t->len == 0) || (t->tx_buf == NULL && t->rx_buf == NULL)) { | |
594 | /* Schedule next transfer tasklet */ | |
595 | tasklet_schedule(&drv_data->pump_transfers); | |
596 | return; | |
597 | } | |
598 | ||
766e3721 | 599 | ret = adi_spi_setup_transfer(drv_data); |
fa4bd4f1 SJ |
600 | if (ret) { |
601 | msg->status = ret; | |
766e3721 | 602 | adi_spi_giveback(drv_data); |
fa4bd4f1 SJ |
603 | } |
604 | ||
766e3721 SJ |
605 | iowrite32(0xFFFFFFFF, &drv_data->regs->status); |
606 | adi_spi_cs_active(drv_data, chip); | |
fa4bd4f1 SJ |
607 | drv_data->state = RUNNING_STATE; |
608 | ||
609 | if (chip->enable_dma) | |
766e3721 | 610 | ret = adi_spi_dma_xfer(drv_data); |
fa4bd4f1 | 611 | else |
766e3721 | 612 | ret = adi_spi_pio_xfer(drv_data); |
fa4bd4f1 SJ |
613 | if (ret) { |
614 | msg->status = ret; | |
766e3721 | 615 | adi_spi_giveback(drv_data); |
fa4bd4f1 SJ |
616 | } |
617 | } | |
618 | ||
766e3721 | 619 | static int adi_spi_transfer_one_message(struct spi_master *master, |
fa4bd4f1 SJ |
620 | struct spi_message *m) |
621 | { | |
766e3721 | 622 | struct adi_spi_master *drv_data = spi_master_get_devdata(master); |
fa4bd4f1 SJ |
623 | |
624 | drv_data->cur_msg = m; | |
625 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
766e3721 | 626 | adi_spi_restore_state(drv_data); |
fa4bd4f1 SJ |
627 | |
628 | drv_data->state = START_STATE; | |
629 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
630 | struct spi_transfer, transfer_list); | |
631 | ||
632 | tasklet_schedule(&drv_data->pump_transfers); | |
633 | return 0; | |
634 | } | |
635 | ||
636 | #define MAX_SPI_SSEL 7 | |
637 | ||
638 | static const u16 ssel[][MAX_SPI_SSEL] = { | |
639 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, | |
640 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
641 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
642 | ||
643 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
644 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
645 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
646 | ||
647 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
648 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
649 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
650 | }; | |
651 | ||
766e3721 | 652 | static int adi_spi_setup(struct spi_device *spi) |
fa4bd4f1 | 653 | { |
766e3721 SJ |
654 | struct adi_spi_master *drv_data = spi_master_get_devdata(spi->master); |
655 | struct adi_spi_device *chip = spi_get_ctldata(spi); | |
656 | u32 ctl_reg = SPI_CTL_ODM | SPI_CTL_PSSE; | |
fa4bd4f1 SJ |
657 | int ret = -EINVAL; |
658 | ||
659 | if (!chip) { | |
766e3721 | 660 | struct adi_spi3_chip *chip_info = spi->controller_data; |
fa4bd4f1 SJ |
661 | |
662 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); | |
1380caa0 | 663 | if (!chip) |
fa4bd4f1 | 664 | return -ENOMEM; |
1380caa0 | 665 | |
fa4bd4f1 | 666 | if (chip_info) { |
766e3721 | 667 | if (chip_info->control & ~ctl_reg) { |
fa4bd4f1 SJ |
668 | dev_err(&spi->dev, |
669 | "do not set bits that the SPI framework manages\n"); | |
670 | goto error; | |
671 | } | |
672 | chip->control = chip_info->control; | |
673 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | |
674 | chip->tx_dummy_val = chip_info->tx_dummy_val; | |
675 | chip->enable_dma = chip_info->enable_dma; | |
676 | } | |
677 | chip->cs = spi->chip_select; | |
766e3721 | 678 | |
fa4bd4f1 SJ |
679 | if (chip->cs < MAX_CTRL_CS) { |
680 | chip->ssel = (1 << chip->cs) << 8; | |
681 | ret = peripheral_request(ssel[spi->master->bus_num] | |
682 | [chip->cs-1], dev_name(&spi->dev)); | |
683 | if (ret) { | |
684 | dev_err(&spi->dev, "peripheral_request() error\n"); | |
685 | goto error; | |
686 | } | |
687 | } else { | |
688 | chip->cs_gpio = chip->cs - MAX_CTRL_CS; | |
689 | ret = gpio_request_one(chip->cs_gpio, GPIOF_OUT_INIT_HIGH, | |
690 | dev_name(&spi->dev)); | |
691 | if (ret) { | |
692 | dev_err(&spi->dev, "gpio_request_one() error\n"); | |
693 | goto error; | |
694 | } | |
695 | } | |
696 | spi_set_ctldata(spi, chip); | |
697 | } | |
698 | ||
699 | /* force a default base state */ | |
766e3721 | 700 | chip->control &= ctl_reg; |
fa4bd4f1 SJ |
701 | |
702 | if (spi->mode & SPI_CPOL) | |
703 | chip->control |= SPI_CTL_CPOL; | |
704 | if (spi->mode & SPI_CPHA) | |
705 | chip->control |= SPI_CTL_CPHA; | |
706 | if (spi->mode & SPI_LSB_FIRST) | |
707 | chip->control |= SPI_CTL_LSBF; | |
708 | chip->control |= SPI_CTL_MSTR; | |
709 | /* we choose software to controll cs */ | |
710 | chip->control &= ~SPI_CTL_ASSEL; | |
711 | ||
712 | chip->clock = hz_to_spi_clock(drv_data->sclk, spi->max_speed_hz); | |
713 | ||
766e3721 SJ |
714 | adi_spi_cs_enable(drv_data, chip); |
715 | adi_spi_cs_deactive(drv_data, chip); | |
fa4bd4f1 SJ |
716 | |
717 | return 0; | |
718 | error: | |
719 | if (chip) { | |
720 | kfree(chip); | |
721 | spi_set_ctldata(spi, NULL); | |
722 | } | |
723 | ||
724 | return ret; | |
725 | } | |
726 | ||
766e3721 | 727 | static void adi_spi_cleanup(struct spi_device *spi) |
fa4bd4f1 | 728 | { |
766e3721 SJ |
729 | struct adi_spi_device *chip = spi_get_ctldata(spi); |
730 | struct adi_spi_master *drv_data = spi_master_get_devdata(spi->master); | |
fa4bd4f1 SJ |
731 | |
732 | if (!chip) | |
733 | return; | |
734 | ||
735 | if (chip->cs < MAX_CTRL_CS) { | |
736 | peripheral_free(ssel[spi->master->bus_num] | |
737 | [chip->cs-1]); | |
766e3721 | 738 | adi_spi_cs_disable(drv_data, chip); |
fa4bd4f1 SJ |
739 | } else { |
740 | gpio_free(chip->cs_gpio); | |
741 | } | |
742 | ||
743 | kfree(chip); | |
744 | spi_set_ctldata(spi, NULL); | |
745 | } | |
746 | ||
766e3721 | 747 | static irqreturn_t adi_spi_tx_dma_isr(int irq, void *dev_id) |
fa4bd4f1 | 748 | { |
766e3721 | 749 | struct adi_spi_master *drv_data = dev_id; |
fa4bd4f1 | 750 | u32 dma_stat = get_dma_curr_irqstat(drv_data->tx_dma); |
766e3721 | 751 | u32 tx_ctl; |
fa4bd4f1 SJ |
752 | |
753 | clear_dma_irqstat(drv_data->tx_dma); | |
754 | if (dma_stat & DMA_DONE) { | |
755 | drv_data->tx_num++; | |
756 | } else { | |
757 | dev_err(&drv_data->master->dev, | |
758 | "spi tx dma error: %d\n", dma_stat); | |
759 | if (drv_data->tx) | |
760 | drv_data->state = ERROR_STATE; | |
761 | } | |
766e3721 SJ |
762 | tx_ctl = ioread32(&drv_data->regs->tx_control); |
763 | tx_ctl &= ~SPI_TXCTL_TDR_NF; | |
764 | iowrite32(tx_ctl, &drv_data->regs->tx_control); | |
fa4bd4f1 SJ |
765 | return IRQ_HANDLED; |
766 | } | |
767 | ||
766e3721 | 768 | static irqreturn_t adi_spi_rx_dma_isr(int irq, void *dev_id) |
fa4bd4f1 | 769 | { |
766e3721 | 770 | struct adi_spi_master *drv_data = dev_id; |
fa4bd4f1 SJ |
771 | struct spi_message *msg = drv_data->cur_msg; |
772 | u32 dma_stat = get_dma_curr_irqstat(drv_data->rx_dma); | |
773 | ||
774 | clear_dma_irqstat(drv_data->rx_dma); | |
775 | if (dma_stat & DMA_DONE) { | |
776 | drv_data->rx_num++; | |
777 | /* we may fail on tx dma */ | |
778 | if (drv_data->state != ERROR_STATE) | |
779 | msg->actual_length += drv_data->transfer_len; | |
780 | } else { | |
781 | drv_data->state = ERROR_STATE; | |
782 | dev_err(&drv_data->master->dev, | |
783 | "spi rx dma error: %d\n", dma_stat); | |
784 | } | |
766e3721 SJ |
785 | iowrite32(0, &drv_data->regs->tx_control); |
786 | iowrite32(0, &drv_data->regs->rx_control); | |
fa4bd4f1 SJ |
787 | if (drv_data->rx_num != drv_data->tx_num) |
788 | dev_dbg(&drv_data->master->dev, | |
789 | "dma interrupt missing: tx=%d,rx=%d\n", | |
790 | drv_data->tx_num, drv_data->rx_num); | |
791 | tasklet_schedule(&drv_data->pump_transfers); | |
792 | return IRQ_HANDLED; | |
793 | } | |
794 | ||
766e3721 | 795 | static int adi_spi_probe(struct platform_device *pdev) |
fa4bd4f1 SJ |
796 | { |
797 | struct device *dev = &pdev->dev; | |
766e3721 | 798 | struct adi_spi3_master *info = dev_get_platdata(dev); |
fa4bd4f1 | 799 | struct spi_master *master; |
766e3721 | 800 | struct adi_spi_master *drv_data; |
fa4bd4f1 SJ |
801 | struct resource *mem, *res; |
802 | unsigned int tx_dma, rx_dma; | |
c34cc248 | 803 | struct clk *sclk; |
fa4bd4f1 SJ |
804 | int ret; |
805 | ||
806 | if (!info) { | |
807 | dev_err(dev, "platform data missing!\n"); | |
808 | return -ENODEV; | |
809 | } | |
810 | ||
c34cc248 SJ |
811 | sclk = devm_clk_get(dev, "spi"); |
812 | if (IS_ERR(sclk)) { | |
813 | dev_err(dev, "can not get spi clock\n"); | |
814 | return PTR_ERR(sclk); | |
fa4bd4f1 SJ |
815 | } |
816 | ||
fa4bd4f1 SJ |
817 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
818 | if (!res) { | |
819 | dev_err(dev, "can not get tx dma resource\n"); | |
820 | return -ENXIO; | |
821 | } | |
822 | tx_dma = res->start; | |
823 | ||
824 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
825 | if (!res) { | |
826 | dev_err(dev, "can not get rx dma resource\n"); | |
827 | return -ENXIO; | |
828 | } | |
829 | rx_dma = res->start; | |
830 | ||
831 | /* allocate master with space for drv_data */ | |
832 | master = spi_alloc_master(dev, sizeof(*drv_data)); | |
833 | if (!master) { | |
834 | dev_err(dev, "can not alloc spi_master\n"); | |
835 | return -ENOMEM; | |
836 | } | |
837 | platform_set_drvdata(pdev, master); | |
838 | ||
839 | /* the mode bits supported by this driver */ | |
840 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
841 | ||
842 | master->bus_num = pdev->id; | |
843 | master->num_chipselect = info->num_chipselect; | |
766e3721 SJ |
844 | master->cleanup = adi_spi_cleanup; |
845 | master->setup = adi_spi_setup; | |
846 | master->transfer_one_message = adi_spi_transfer_one_message; | |
aa188f90 AL |
847 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |
848 | SPI_BPW_MASK(8); | |
fa4bd4f1 SJ |
849 | |
850 | drv_data = spi_master_get_devdata(master); | |
851 | drv_data->master = master; | |
852 | drv_data->tx_dma = tx_dma; | |
853 | drv_data->rx_dma = rx_dma; | |
854 | drv_data->pin_req = info->pin_req; | |
c34cc248 | 855 | drv_data->sclk = clk_get_rate(sclk); |
fa4bd4f1 | 856 | |
de0fa83c | 857 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
fa4bd4f1 SJ |
858 | drv_data->regs = devm_ioremap_resource(dev, mem); |
859 | if (IS_ERR(drv_data->regs)) { | |
860 | ret = PTR_ERR(drv_data->regs); | |
861 | goto err_put_master; | |
862 | } | |
863 | ||
864 | /* request tx and rx dma */ | |
865 | ret = request_dma(tx_dma, "SPI_TX_DMA"); | |
866 | if (ret) { | |
867 | dev_err(dev, "can not request SPI TX DMA channel\n"); | |
868 | goto err_put_master; | |
869 | } | |
766e3721 | 870 | set_dma_callback(tx_dma, adi_spi_tx_dma_isr, drv_data); |
fa4bd4f1 SJ |
871 | |
872 | ret = request_dma(rx_dma, "SPI_RX_DMA"); | |
873 | if (ret) { | |
874 | dev_err(dev, "can not request SPI RX DMA channel\n"); | |
875 | goto err_free_tx_dma; | |
876 | } | |
766e3721 | 877 | set_dma_callback(drv_data->rx_dma, adi_spi_rx_dma_isr, drv_data); |
fa4bd4f1 SJ |
878 | |
879 | /* request CLK, MOSI and MISO */ | |
766e3721 | 880 | ret = peripheral_request_list(drv_data->pin_req, "adi-spi3"); |
fa4bd4f1 SJ |
881 | if (ret < 0) { |
882 | dev_err(dev, "can not request spi pins\n"); | |
883 | goto err_free_rx_dma; | |
884 | } | |
885 | ||
766e3721 SJ |
886 | iowrite32(SPI_CTL_MSTR | SPI_CTL_CPHA, &drv_data->regs->control); |
887 | iowrite32(0x0000FE00, &drv_data->regs->ssel); | |
888 | iowrite32(0x0, &drv_data->regs->delay); | |
fa4bd4f1 SJ |
889 | |
890 | tasklet_init(&drv_data->pump_transfers, | |
766e3721 | 891 | adi_spi_pump_transfers, (unsigned long)drv_data); |
fa4bd4f1 | 892 | /* register with the SPI framework */ |
6221df6d | 893 | ret = devm_spi_register_master(dev, master); |
fa4bd4f1 SJ |
894 | if (ret) { |
895 | dev_err(dev, "can not register spi master\n"); | |
896 | goto err_free_peripheral; | |
897 | } | |
898 | ||
899 | return ret; | |
900 | ||
901 | err_free_peripheral: | |
902 | peripheral_free_list(drv_data->pin_req); | |
903 | err_free_rx_dma: | |
904 | free_dma(rx_dma); | |
905 | err_free_tx_dma: | |
906 | free_dma(tx_dma); | |
907 | err_put_master: | |
fa4bd4f1 SJ |
908 | spi_master_put(master); |
909 | ||
910 | return ret; | |
911 | } | |
912 | ||
766e3721 | 913 | static int adi_spi_remove(struct platform_device *pdev) |
fa4bd4f1 SJ |
914 | { |
915 | struct spi_master *master = platform_get_drvdata(pdev); | |
766e3721 | 916 | struct adi_spi_master *drv_data = spi_master_get_devdata(master); |
fa4bd4f1 | 917 | |
766e3721 | 918 | adi_spi_disable(drv_data); |
fa4bd4f1 SJ |
919 | peripheral_free_list(drv_data->pin_req); |
920 | free_dma(drv_data->rx_dma); | |
921 | free_dma(drv_data->tx_dma); | |
fa4bd4f1 SJ |
922 | return 0; |
923 | } | |
924 | ||
925 | #ifdef CONFIG_PM | |
766e3721 | 926 | static int adi_spi_suspend(struct device *dev) |
fa4bd4f1 SJ |
927 | { |
928 | struct spi_master *master = dev_get_drvdata(dev); | |
766e3721 | 929 | struct adi_spi_master *drv_data = spi_master_get_devdata(master); |
fa4bd4f1 SJ |
930 | |
931 | spi_master_suspend(master); | |
932 | ||
766e3721 SJ |
933 | drv_data->control = ioread32(&drv_data->regs->control); |
934 | drv_data->ssel = ioread32(&drv_data->regs->ssel); | |
fa4bd4f1 | 935 | |
766e3721 SJ |
936 | iowrite32(SPI_CTL_MSTR | SPI_CTL_CPHA, &drv_data->regs->control); |
937 | iowrite32(0x0000FE00, &drv_data->regs->ssel); | |
fa4bd4f1 SJ |
938 | dma_disable_irq(drv_data->rx_dma); |
939 | dma_disable_irq(drv_data->tx_dma); | |
940 | ||
941 | return 0; | |
942 | } | |
943 | ||
766e3721 | 944 | static int adi_spi_resume(struct device *dev) |
fa4bd4f1 SJ |
945 | { |
946 | struct spi_master *master = dev_get_drvdata(dev); | |
766e3721 | 947 | struct adi_spi_master *drv_data = spi_master_get_devdata(master); |
fa4bd4f1 SJ |
948 | int ret = 0; |
949 | ||
950 | /* bootrom may modify spi and dma status when resume in spi boot mode */ | |
951 | disable_dma(drv_data->rx_dma); | |
952 | ||
953 | dma_enable_irq(drv_data->rx_dma); | |
954 | dma_enable_irq(drv_data->tx_dma); | |
766e3721 SJ |
955 | iowrite32(drv_data->control, &drv_data->regs->control); |
956 | iowrite32(drv_data->ssel, &drv_data->regs->ssel); | |
fa4bd4f1 SJ |
957 | |
958 | ret = spi_master_resume(master); | |
959 | if (ret) { | |
960 | free_dma(drv_data->rx_dma); | |
961 | free_dma(drv_data->tx_dma); | |
962 | } | |
963 | ||
964 | return ret; | |
965 | } | |
966 | #endif | |
766e3721 SJ |
967 | static const struct dev_pm_ops adi_spi_pm_ops = { |
968 | SET_SYSTEM_SLEEP_PM_OPS(adi_spi_suspend, adi_spi_resume) | |
fa4bd4f1 SJ |
969 | }; |
970 | ||
766e3721 SJ |
971 | MODULE_ALIAS("platform:adi-spi3"); |
972 | static struct platform_driver adi_spi_driver = { | |
fa4bd4f1 | 973 | .driver = { |
766e3721 | 974 | .name = "adi-spi3", |
766e3721 | 975 | .pm = &adi_spi_pm_ops, |
fa4bd4f1 | 976 | }, |
766e3721 | 977 | .remove = adi_spi_remove, |
fa4bd4f1 SJ |
978 | }; |
979 | ||
766e3721 | 980 | module_platform_driver_probe(adi_spi_driver, adi_spi_probe); |
fa4bd4f1 SJ |
981 | |
982 | MODULE_DESCRIPTION("Analog Devices SPI3 controller driver"); | |
983 | MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>"); | |
984 | MODULE_LICENSE("GPL v2"); |