[deliverable/linux.git] / drivers / spi / spi-ath79.c

/*
 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
 *
 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 *
 * This driver has been based on the spi-gpio.c:
 *	Copyright (C) 2006,2008 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/err.h>

#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79_spi_platform.h>

#define DRV_NAME	"ath79-spi"

#define ATH79_SPI_RRW_DELAY_FACTOR	12000
#define MHZ				(1000 * 1000)

struct ath79_spi {
	struct spi_bitbang	bitbang;
	u32			ioc_base;
	u32			reg_ctrl;
	void __iomem		*base;
	struct clk		*clk;
	unsigned		rrw_delay;
};

static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
{
	return ioread32(sp->base + reg);
}

static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
{
	iowrite32(val, sp->base + reg);
}

static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
{
	return spi_master_get_devdata(spi->master);
}

static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
{
	if (nsecs > sp->rrw_delay)
		ndelay(nsecs - sp->rrw_delay);
}

static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;

	if (is_active) {
		/* set initial clock polarity */
		if (spi->mode & SPI_CPOL)
			sp->ioc_base |= AR71XX_SPI_IOC_CLK;
		else
			sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;

		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	}

	if (spi->chip_select) {
		struct ath79_spi_controller_data *cdata = spi->controller_data;

		/* SPI is normally active-low */
		gpio_set_value(cdata->gpio, cs_high);
	} else {
		if (cs_high)
			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
		else
			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;

		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	}

}

static int ath79_spi_setup_cs(struct spi_device *spi)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	struct ath79_spi_controller_data *cdata;

	cdata = spi->controller_data;
	if (spi->chip_select && !cdata)
		return -EINVAL;

	/* enable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);

	/* save CTRL register */
	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);

	/* TODO: setup speed? */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);

	if (spi->chip_select) {
		int status = 0;

		status = gpio_request(cdata->gpio, dev_name(&spi->dev));
		if (status)
			return status;

		status = gpio_direction_output(cdata->gpio,
					       spi->mode & SPI_CS_HIGH);
		if (status) {
			gpio_free(cdata->gpio);
			return status;
		}
	} else {
		if (spi->mode & SPI_CS_HIGH)
			sp->ioc_base |= AR71XX_SPI_IOC_CS0;
		else
			sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	}

	return 0;
}

static void ath79_spi_cleanup_cs(struct spi_device *spi)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);

	if (spi->chip_select) {
		struct ath79_spi_controller_data *cdata = spi->controller_data;
		gpio_free(cdata->gpio);
	}

	/* restore CTRL register */
	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
	/* disable GPIO mode */
	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
}

static int ath79_spi_setup(struct spi_device *spi)
{
	int status = 0;

	if (spi->bits_per_word > 32)
		return -EINVAL;

	if (!spi->controller_state) {
		status = ath79_spi_setup_cs(spi);
		if (status)
			return status;
	}

	status = spi_bitbang_setup(spi);
	if (status && !spi->controller_state)
		ath79_spi_cleanup_cs(spi);

	return status;
}

static void ath79_spi_cleanup(struct spi_device *spi)
{
	ath79_spi_cleanup_cs(spi);
	spi_bitbang_cleanup(spi);
}

static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
			       u32 word, u8 bits)
{
	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	u32 ioc = sp->ioc_base;

	/* clock starts at inactive polarity */
	for (word <<= (32 - bits); likely(bits); bits--) {
		u32 out;

		if (word & (1 << 31))
			out = ioc | AR71XX_SPI_IOC_DO;
		else
			out = ioc & ~AR71XX_SPI_IOC_DO;

		/* setup MSB (to slave) on trailing edge */
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
		ath79_spi_delay(sp, nsecs);
		ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
		ath79_spi_delay(sp, nsecs);

		word <<= 1;
	}

	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
}

static int ath79_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct ath79_spi *sp;
	struct ath79_spi_platform_data *pdata;
	struct resource	*r;
	unsigned long rate;
	int ret;

	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	if (master == NULL) {
		dev_err(&pdev->dev, "failed to allocate spi master\n");
		return -ENOMEM;
	}

	sp = spi_master_get_devdata(master);
	platform_set_drvdata(pdev, sp);

	pdata = pdev->dev.platform_data;

	master->setup = ath79_spi_setup;
	master->cleanup = ath79_spi_cleanup;
	if (pdata) {
		master->bus_num = pdata->bus_num;
		master->num_chipselect = pdata->num_chipselect;
	}

	sp->bitbang.master = spi_master_get(master);
	sp->bitbang.chipselect = ath79_spi_chipselect;
	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
	sp->bitbang.flags = SPI_CS_HIGH;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		ret = -ENOENT;
		goto err_put_master;
	}

	sp->base = ioremap(r->start, resource_size(r));
	if (!sp->base) {
		ret = -ENXIO;
		goto err_put_master;
	}

	sp->clk = clk_get(&pdev->dev, "ahb");
	if (IS_ERR(sp->clk)) {
		ret = PTR_ERR(sp->clk);
		goto err_unmap;
	}

	ret = clk_enable(sp->clk);
	if (ret)
		goto err_clk_put;

	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	if (!rate) {
		ret = -EINVAL;
		goto err_clk_disable;
	}

	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
		sp->rrw_delay);

	ret = spi_bitbang_start(&sp->bitbang);
	if (ret)
		goto err_clk_disable;

	return 0;

err_clk_disable:
	clk_disable(sp->clk);
err_clk_put:
	clk_put(sp->clk);
err_unmap:
	iounmap(sp->base);
err_put_master:
	platform_set_drvdata(pdev, NULL);
	spi_master_put(sp->bitbang.master);

	return ret;
}

static int ath79_spi_remove(struct platform_device *pdev)
{
	struct ath79_spi *sp = platform_get_drvdata(pdev);

	spi_bitbang_stop(&sp->bitbang);
	clk_disable(sp->clk);
	clk_put(sp->clk);
	iounmap(sp->base);
	platform_set_drvdata(pdev, NULL);
	spi_master_put(sp->bitbang.master);

	return 0;
}

static struct platform_driver ath79_spi_driver = {
	.probe		= ath79_spi_probe,
	.remove		= ath79_spi_remove,
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
	},
};
module_platform_driver(ath79_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
8efaef4d GJ	1	/*
	2	* SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
	3	*
	4	* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
	5	*
	6	* This driver has been based on the spi-gpio.c:
	7	* Copyright (C) 2006,2008 David Brownell
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/kernel.h>
807cc4b1	16	#include <linux/module.h>
8efaef4d GJ	17	#include <linux/init.h>
	18	#include <linux/delay.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/workqueue.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
	23	#include <linux/spi/spi.h>
	24	#include <linux/spi/spi_bitbang.h>
	25	#include <linux/bitops.h>
	26	#include <linux/gpio.h>
440114fd GJ	27	#include <linux/clk.h>
440114fd GJ	28	#include <linux/err.h>
8efaef4d GJ	29
	30	#include <asm/mach-ath79/ar71xx_regs.h>
	31	#include <asm/mach-ath79/ath79_spi_platform.h>
	32
	33	#define DRV_NAME "ath79-spi"
	34
440114fd GJ	35	#define ATH79_SPI_RRW_DELAY_FACTOR 12000
	36	#define MHZ (1000 * 1000)
	37
8efaef4d GJ	38	struct ath79_spi {
	39	struct spi_bitbang bitbang;
	40	u32 ioc_base;
	41	u32 reg_ctrl;
	42	void __iomem *base;
440114fd GJ	43	struct clk *clk;
440114fd GJ	44	unsigned rrw_delay;
8efaef4d GJ	45	};
	46
	47	static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
	48	{
	49	return ioread32(sp->base + reg);
	50	}
	51
	52	static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
	53	{
	54	iowrite32(val, sp->base + reg);
	55	}
	56
	57	static inline struct ath79_spi ath79_spidev_to_sp(struct spi_device spi)
	58	{
	59	return spi_master_get_devdata(spi->master);
	60	}
	61
440114fd GJ	62	static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
	63	{
	64	if (nsecs > sp->rrw_delay)
	65	ndelay(nsecs - sp->rrw_delay);
	66	}
	67
8efaef4d GJ	68	static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
	69	{
	70	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	71	int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
	72
	73	if (is_active) {
	74	/* set initial clock polarity */
	75	if (spi->mode & SPI_CPOL)
	76	sp->ioc_base \|= AR71XX_SPI_IOC_CLK;
	77	else
	78	sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
	79
	80	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	81	}
	82
	83	if (spi->chip_select) {
	84	struct ath79_spi_controller_data *cdata = spi->controller_data;
	85
	86	/* SPI is normally active-low */
	87	gpio_set_value(cdata->gpio, cs_high);
	88	} else {
	89	if (cs_high)
	90	sp->ioc_base \|= AR71XX_SPI_IOC_CS0;
	91	else
	92	sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
	93
	94	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
	95	}
	96
	97	}
	98
	99	static int ath79_spi_setup_cs(struct spi_device *spi)
	100	{
	101	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
	102	struct ath79_spi_controller_data *cdata;
	103
	104	cdata = spi->controller_data;
	105	if (spi->chip_select && !cdata)
	106	return -EINVAL;
	107
	108	/* enable GPIO mode */
	109	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
	110
	111	/* save CTRL register */
	112	sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
	113	sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
	114
	115	/* TODO: setup speed? */
	116	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
	117
	118	if (spi->chip_select) {
	119	int status = 0;
	120
	121	status = gpio_request(cdata->gpio, dev_name(&spi->dev));
	122	if (status)
	123	return status;
	124
	125	status = gpio_direction_output(cdata->gpio,
	126	spi->mode & SPI_CS_HIGH);
	127	if (status) {
	128	gpio_free(cdata->gpio);
	129	return status;
	130	}
	131	} else {
132	if (spi->mode & SPI_CS_HIGH)
133	sp->ioc_base \|= AR71XX_SPI_IOC_CS0;
134	else
135	sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
136	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
137	}
138
139	return 0;
140	}
141
142	static void ath79_spi_cleanup_cs(struct spi_device *spi)
143	{
144	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
145
146	if (spi->chip_select) {
147	struct ath79_spi_controller_data *cdata = spi->controller_data;
148	gpio_free(cdata->gpio);
149	}
150
151	/* restore CTRL register */
152	ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
153	/* disable GPIO mode */
154	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
155	}
156
157	static int ath79_spi_setup(struct spi_device *spi)
158	{
159	int status = 0;
160
161	if (spi->bits_per_word > 32)
162	return -EINVAL;
163
164	if (!spi->controller_state) {
165	status = ath79_spi_setup_cs(spi);
166	if (status)
167	return status;
168	}
169
170	status = spi_bitbang_setup(spi);
171	if (status && !spi->controller_state)
172	ath79_spi_cleanup_cs(spi);
173
174	return status;
175	}
176
177	static void ath79_spi_cleanup(struct spi_device *spi)
178	{
179	ath79_spi_cleanup_cs(spi);
180	spi_bitbang_cleanup(spi);
181	}
182
183	static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
184	u32 word, u8 bits)
185	{
186	struct ath79_spi *sp = ath79_spidev_to_sp(spi);
187	u32 ioc = sp->ioc_base;
188
189	/* clock starts at inactive polarity */
190	for (word <<= (32 - bits); likely(bits); bits--) {
191	u32 out;
192
193	if (word & (1 << 31))
194	out = ioc \| AR71XX_SPI_IOC_DO;
195	else
196	out = ioc & ~AR71XX_SPI_IOC_DO;
197
198	/* setup MSB (to slave) on trailing edge */
199	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
440114fd	200	ath79_spi_delay(sp, nsecs);
8efaef4d	201	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out \| AR71XX_SPI_IOC_CLK);
440114fd	202	ath79_spi_delay(sp, nsecs);
8efaef4d GJ	203
	204	word <<= 1;
	205	}
	206
	207	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
	208	}
	209
fd4a319b	210	static int ath79_spi_probe(struct platform_device *pdev)
8efaef4d GJ	211	{
	212	struct spi_master *master;
	213	struct ath79_spi *sp;
	214	struct ath79_spi_platform_data *pdata;
	215	struct resource *r;
440114fd	216	unsigned long rate;
8efaef4d GJ	217	int ret;
	218
	219	master = spi_alloc_master(&pdev->dev, sizeof(*sp));
	220	if (master == NULL) {
	221	dev_err(&pdev->dev, "failed to allocate spi master\n");
	222	return -ENOMEM;
	223	}
	224
	225	sp = spi_master_get_devdata(master);
	226	platform_set_drvdata(pdev, sp);
	227
	228	pdata = pdev->dev.platform_data;
	229
	230	master->setup = ath79_spi_setup;
	231	master->cleanup = ath79_spi_cleanup;
	232	if (pdata) {
	233	master->bus_num = pdata->bus_num;
	234	master->num_chipselect = pdata->num_chipselect;
8efaef4d GJ	235	}
	236
	237	sp->bitbang.master = spi_master_get(master);
	238	sp->bitbang.chipselect = ath79_spi_chipselect;
	239	sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
	240	sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
	241	sp->bitbang.flags = SPI_CS_HIGH;
	242
	243	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	244	if (r == NULL) {
	245	ret = -ENOENT;
	246	goto err_put_master;
	247	}
	248
8e2943c0	249	sp->base = ioremap(r->start, resource_size(r));
8efaef4d GJ	250	if (!sp->base) {
	251	ret = -ENXIO;
	252	goto err_put_master;
	253	}
	254
440114fd GJ	255	sp->clk = clk_get(&pdev->dev, "ahb");
	256	if (IS_ERR(sp->clk)) {
	257	ret = PTR_ERR(sp->clk);
	258	goto err_unmap;
	259	}
	260
	261	ret = clk_enable(sp->clk);
	262	if (ret)
	263	goto err_clk_put;
	264
	265	rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
	266	if (!rate) {
	267	ret = -EINVAL;
	268	goto err_clk_disable;
	269	}
	270
	271	sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
	272	dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
	273	sp->rrw_delay);
	274
8efaef4d GJ	275	ret = spi_bitbang_start(&sp->bitbang);
8efaef4d GJ	276	if (ret)
440114fd	277	goto err_clk_disable;
8efaef4d GJ	278
	279	return 0;
	280
440114fd GJ	281	err_clk_disable:
	282	clk_disable(sp->clk);
	283	err_clk_put:
	284	clk_put(sp->clk);
8efaef4d GJ	285	err_unmap:
	286	iounmap(sp->base);
	287	err_put_master:
	288	platform_set_drvdata(pdev, NULL);
	289	spi_master_put(sp->bitbang.master);
	290
	291	return ret;
	292	}
	293
fd4a319b	294	static int ath79_spi_remove(struct platform_device *pdev)
8efaef4d GJ	295	{
	296	struct ath79_spi *sp = platform_get_drvdata(pdev);
	297
	298	spi_bitbang_stop(&sp->bitbang);
440114fd GJ	299	clk_disable(sp->clk);
440114fd GJ	300	clk_put(sp->clk);
8efaef4d GJ	301	iounmap(sp->base);
	302	platform_set_drvdata(pdev, NULL);
	303	spi_master_put(sp->bitbang.master);
	304
	305	return 0;
	306	}
	307
	308	static struct platform_driver ath79_spi_driver = {
	309	.probe = ath79_spi_probe,
fd4a319b	310	.remove = ath79_spi_remove,
8efaef4d GJ	311	.driver = {
	312	.name = DRV_NAME,
	313	.owner = THIS_MODULE,
	314	},
	315	};
940ab889	316	module_platform_driver(ath79_spi_driver);
8efaef4d GJ	317
	318	MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
	319	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
	320	MODULE_LICENSE("GPL v2");
	321	MODULE_ALIAS("platform:" DRV_NAME);