[deliverable/linux.git] / drivers / spi / spi-bcm2835.c

/*
 * Driver for Broadcom BCM2835 SPI Controllers
 *
 * Copyright (C) 2012 Chris Boot
 * Copyright (C) 2013 Stephen Warren
 *
 * This driver is inspired by:
 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_device.h>
#include <linux/spi/spi.h>

/* SPI register offsets */
#define BCM2835_SPI_CS			0x00
#define BCM2835_SPI_FIFO		0x04
#define BCM2835_SPI_CLK			0x08
#define BCM2835_SPI_DLEN		0x0c
#define BCM2835_SPI_LTOH		0x10
#define BCM2835_SPI_DC			0x14

/* Bitfields in CS */
#define BCM2835_SPI_CS_LEN_LONG		0x02000000
#define BCM2835_SPI_CS_DMA_LEN		0x01000000
#define BCM2835_SPI_CS_CSPOL2		0x00800000
#define BCM2835_SPI_CS_CSPOL1		0x00400000
#define BCM2835_SPI_CS_CSPOL0		0x00200000
#define BCM2835_SPI_CS_RXF		0x00100000
#define BCM2835_SPI_CS_RXR		0x00080000
#define BCM2835_SPI_CS_TXD		0x00040000
#define BCM2835_SPI_CS_RXD		0x00020000
#define BCM2835_SPI_CS_DONE		0x00010000
#define BCM2835_SPI_CS_LEN		0x00002000
#define BCM2835_SPI_CS_REN		0x00001000
#define BCM2835_SPI_CS_ADCS		0x00000800
#define BCM2835_SPI_CS_INTR		0x00000400
#define BCM2835_SPI_CS_INTD		0x00000200
#define BCM2835_SPI_CS_DMAEN		0x00000100
#define BCM2835_SPI_CS_TA		0x00000080
#define BCM2835_SPI_CS_CSPOL		0x00000040
#define BCM2835_SPI_CS_CLEAR_RX		0x00000020
#define BCM2835_SPI_CS_CLEAR_TX		0x00000010
#define BCM2835_SPI_CS_CPOL		0x00000008
#define BCM2835_SPI_CS_CPHA		0x00000004
#define BCM2835_SPI_CS_CS_10		0x00000002
#define BCM2835_SPI_CS_CS_01		0x00000001

#define BCM2835_SPI_TIMEOUT_MS	30000
#define BCM2835_SPI_MODE_BITS	(SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS)

#define DRV_NAME	"spi-bcm2835"

struct bcm2835_spi {
	void __iomem *regs;
	struct clk *clk;
	int irq;
	struct completion done;
	const u8 *tx_buf;
	u8 *rx_buf;
	int len;
};

static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
{
	return readl(bs->regs + reg);
}

static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
{
	writel(val, bs->regs + reg);
}

static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
{
	u8 byte;

	while (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD) {
		byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
		if (bs->rx_buf)
			*bs->rx_buf++ = byte;
	}
}

static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
{
	u8 byte;

	while ((bs->len) &&
	       (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
		byte = bs->tx_buf ? *bs->tx_buf++ : 0;
		bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
		bs->len--;
	}
}

static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = dev_id;
	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);

	/* Read as many bytes as possible from FIFO */
	bcm2835_rd_fifo(bs);

	if (bs->len) { /* there is more data to transmit */
		bcm2835_wr_fifo(bs);
	} else { /* Transfer complete */
		/* Disable SPI interrupts */
		cs &= ~(BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD);
		bcm2835_wr(bs, BCM2835_SPI_CS, cs);

		/*
		 * Wake up bcm2835_spi_transfer_one(), which will call
		 * bcm2835_spi_finish_transfer(), to drain the RX FIFO.
		 */
		complete(&bs->done);
	}

	return IRQ_HANDLED;
}

static int bcm2835_spi_start_transfer(struct spi_device *spi,
				      struct spi_transfer *tfr)
{
	struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
	unsigned long spi_hz, clk_hz, cdiv;
	u32 cs = BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;

	spi_hz = tfr->speed_hz;
	clk_hz = clk_get_rate(bs->clk);

	if (spi_hz >= clk_hz / 2) {
		cdiv = 2; /* clk_hz/2 is the fastest we can go */
	} else if (spi_hz) {
		/* CDIV must be a multiple of two */
		cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
		cdiv += (cdiv % 2);

		if (cdiv >= 65536)
			cdiv = 0; /* 0 is the slowest we can go */
	} else {
		cdiv = 0; /* 0 is the slowest we can go */
	}

	if (spi->mode & SPI_CPOL)
		cs |= BCM2835_SPI_CS_CPOL;
	if (spi->mode & SPI_CPHA)
		cs |= BCM2835_SPI_CS_CPHA;

	if (!(spi->mode & SPI_NO_CS)) {
		if (spi->mode & SPI_CS_HIGH) {
			cs |= BCM2835_SPI_CS_CSPOL;
			cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
		}

		cs |= spi->chip_select;
	}

	reinit_completion(&bs->done);
	bs->tx_buf = tfr->tx_buf;
	bs->rx_buf = tfr->rx_buf;
	bs->len = tfr->len;

	bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
	/*
	 * Enable the HW block. This will immediately trigger a DONE (TX
	 * empty) interrupt, upon which we will fill the TX FIFO with the
	 * first TX bytes. Pre-filling the TX FIFO here to avoid the
	 * interrupt doesn't work:-(
	 */
	bcm2835_wr(bs, BCM2835_SPI_CS, cs);

	return 0;
}

static int bcm2835_spi_finish_transfer(struct spi_device *spi,
				       struct spi_transfer *tfr,
				       bool cs_change)
{
	struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);

	if (tfr->delay_usecs)
		udelay(tfr->delay_usecs);

	if (cs_change)
		/* Clear TA flag */
		bcm2835_wr(bs, BCM2835_SPI_CS, cs & ~BCM2835_SPI_CS_TA);

	return 0;
}

static int bcm2835_spi_transfer_one(struct spi_master *master,
				    struct spi_message *mesg)
{
	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	struct spi_transfer *tfr;
	struct spi_device *spi = mesg->spi;
	int err = 0;
	unsigned int timeout;
	bool cs_change;

	list_for_each_entry(tfr, &mesg->transfers, transfer_list) {
		err = bcm2835_spi_start_transfer(spi, tfr);
		if (err)
			goto out;

		timeout = wait_for_completion_timeout(
			&bs->done,
			msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS)
			);
		if (!timeout) {
			err = -ETIMEDOUT;
			goto out;
		}

		cs_change = tfr->cs_change ||
			list_is_last(&tfr->transfer_list, &mesg->transfers);

		err = bcm2835_spi_finish_transfer(spi, tfr, cs_change);
		if (err)
			goto out;

		mesg->actual_length += (tfr->len - bs->len);
	}

out:
	/* Clear FIFOs, and disable the HW block */
	bcm2835_wr(bs, BCM2835_SPI_CS,
		   BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
	mesg->status = err;
	spi_finalize_current_message(master);

	return 0;
}

static int bcm2835_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct bcm2835_spi *bs;
	struct resource *res;
	int err;

	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	if (!master) {
		dev_err(&pdev->dev, "spi_alloc_master() failed\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, master);

	master->mode_bits = BCM2835_SPI_MODE_BITS;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->num_chipselect = 3;
	master->transfer_one_message = bcm2835_spi_transfer_one;
	master->dev.of_node = pdev->dev.of_node;

	bs = spi_master_get_devdata(master);

	init_completion(&bs->done);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(bs->regs)) {
		err = PTR_ERR(bs->regs);
		goto out_master_put;
	}

	bs->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(bs->clk)) {
		err = PTR_ERR(bs->clk);
		dev_err(&pdev->dev, "could not get clk: %d\n", err);
		goto out_master_put;
	}

	bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
	if (bs->irq <= 0) {
		dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
		err = bs->irq ? bs->irq : -ENODEV;
		goto out_master_put;
	}

	clk_prepare_enable(bs->clk);

	err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
			       dev_name(&pdev->dev), master);
	if (err) {
		dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
		goto out_clk_disable;
	}

	/* initialise the hardware */
	bcm2835_wr(bs, BCM2835_SPI_CS,
		   BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);

	err = devm_spi_register_master(&pdev->dev, master);
	if (err) {
		dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
		goto out_clk_disable;
	}

	return 0;

out_clk_disable:
	clk_disable_unprepare(bs->clk);
out_master_put:
	spi_master_put(master);
	return err;
}

static int bcm2835_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm2835_spi *bs = spi_master_get_devdata(master);

	/* Clear FIFOs, and disable the HW block */
	bcm2835_wr(bs, BCM2835_SPI_CS,
		   BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);

	clk_disable_unprepare(bs->clk);

	return 0;
}

static const struct of_device_id bcm2835_spi_match[] = {
	{ .compatible = "brcm,bcm2835-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, bcm2835_spi_match);

static struct platform_driver bcm2835_spi_driver = {
	.driver		= {
		.name		= DRV_NAME,
		.of_match_table	= bcm2835_spi_match,
	},
	.probe		= bcm2835_spi_probe,
	.remove		= bcm2835_spi_remove,
};
module_platform_driver(bcm2835_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f8043872 CB	1	/*
	2	* Driver for Broadcom BCM2835 SPI Controllers
	3	*
	4	* Copyright (C) 2012 Chris Boot
	5	* Copyright (C) 2013 Stephen Warren
	6	*
	7	* This driver is inspired by:
	8	* spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
	9	* spi-atmel.c, Copyright (C) 2006 Atmel Corporation
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
f8043872 CB	20	*/
	21
	22	#include <linux/clk.h>
	23	#include <linux/completion.h>
	24	#include <linux/delay.h>
	25	#include <linux/err.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/io.h>
	28	#include <linux/kernel.h>
	29	#include <linux/module.h>
	30	#include <linux/of.h>
	31	#include <linux/of_irq.h>
	32	#include <linux/of_device.h>
	33	#include <linux/spi/spi.h>
	34
	35	/* SPI register offsets */
	36	#define BCM2835_SPI_CS 0x00
	37	#define BCM2835_SPI_FIFO 0x04
	38	#define BCM2835_SPI_CLK 0x08
	39	#define BCM2835_SPI_DLEN 0x0c
	40	#define BCM2835_SPI_LTOH 0x10
	41	#define BCM2835_SPI_DC 0x14
	42
	43	/* Bitfields in CS */
	44	#define BCM2835_SPI_CS_LEN_LONG 0x02000000
	45	#define BCM2835_SPI_CS_DMA_LEN 0x01000000
	46	#define BCM2835_SPI_CS_CSPOL2 0x00800000
	47	#define BCM2835_SPI_CS_CSPOL1 0x00400000
	48	#define BCM2835_SPI_CS_CSPOL0 0x00200000
	49	#define BCM2835_SPI_CS_RXF 0x00100000
	50	#define BCM2835_SPI_CS_RXR 0x00080000
	51	#define BCM2835_SPI_CS_TXD 0x00040000
	52	#define BCM2835_SPI_CS_RXD 0x00020000
	53	#define BCM2835_SPI_CS_DONE 0x00010000
	54	#define BCM2835_SPI_CS_LEN 0x00002000
	55	#define BCM2835_SPI_CS_REN 0x00001000
	56	#define BCM2835_SPI_CS_ADCS 0x00000800
	57	#define BCM2835_SPI_CS_INTR 0x00000400
	58	#define BCM2835_SPI_CS_INTD 0x00000200
	59	#define BCM2835_SPI_CS_DMAEN 0x00000100
	60	#define BCM2835_SPI_CS_TA 0x00000080
	61	#define BCM2835_SPI_CS_CSPOL 0x00000040
	62	#define BCM2835_SPI_CS_CLEAR_RX 0x00000020
	63	#define BCM2835_SPI_CS_CLEAR_TX 0x00000010
	64	#define BCM2835_SPI_CS_CPOL 0x00000008
	65	#define BCM2835_SPI_CS_CPHA 0x00000004
	66	#define BCM2835_SPI_CS_CS_10 0x00000002
	67	#define BCM2835_SPI_CS_CS_01 0x00000001
	68
	69	#define BCM2835_SPI_TIMEOUT_MS 30000
	70	#define BCM2835_SPI_MODE_BITS (SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_NO_CS)
	71
	72	#define DRV_NAME "spi-bcm2835"
	73
	74	struct bcm2835_spi {
	75	void __iomem *regs;
	76	struct clk *clk;
	77	int irq;
	78	struct completion done;
	79	const u8 *tx_buf;
	80	u8 *rx_buf;
	81	int len;
	82	};
	83
84	static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
85	{
86	return readl(bs->regs + reg);
87	}
88
89	static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
90	{
91	writel(val, bs->regs + reg);
92	}
93
4adf3129	94	static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
f8043872 CB	95	{
	96	u8 byte;
	97
4adf3129	98	while (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD) {
f8043872 CB	99	byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
	100	if (bs->rx_buf)
	101	*bs->rx_buf++ = byte;
	102	}
	103	}
	104
4adf3129	105	static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
f8043872 CB	106	{
	107	u8 byte;
	108
4adf3129 MS	109	while ((bs->len) &&
4adf3129 MS	110	(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
f8043872 CB	111	byte = bs->tx_buf ? *bs->tx_buf++ : 0;
	112	bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
	113	bs->len--;
	114	}
	115	}
	116
	117	static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
	118	{
	119	struct spi_master *master = dev_id;
	120	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	121	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
	122
4adf3129 MS	123	/* Read as many bytes as possible from FIFO */
4adf3129 MS	124	bcm2835_rd_fifo(bs);
f8043872	125
4adf3129 MS	126	if (bs->len) { /* there is more data to transmit */
	127	bcm2835_wr_fifo(bs);
	128	} else { /* Transfer complete */
	129	/* Disable SPI interrupts */
	130	cs &= ~(BCM2835_SPI_CS_INTR \| BCM2835_SPI_CS_INTD);
	131	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
f8043872 CB	132
f8043872 CB	133	/*
4adf3129 MS	134	* Wake up bcm2835_spi_transfer_one(), which will call
4adf3129 MS	135	* bcm2835_spi_finish_transfer(), to drain the RX FIFO.
f8043872	136	*/
4adf3129	137	complete(&bs->done);
f8043872 CB	138	}
f8043872 CB	139
4adf3129	140	return IRQ_HANDLED;
f8043872 CB	141	}
f8043872 CB	142
f8043872	143	static int bcm2835_spi_start_transfer(struct spi_device *spi,
342f948a	144	struct spi_transfer *tfr)
f8043872 CB	145	{
	146	struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
	147	unsigned long spi_hz, clk_hz, cdiv;
	148	u32 cs = BCM2835_SPI_CS_INTR \| BCM2835_SPI_CS_INTD \| BCM2835_SPI_CS_TA;
	149
	150	spi_hz = tfr->speed_hz;
	151	clk_hz = clk_get_rate(bs->clk);
	152
	153	if (spi_hz >= clk_hz / 2) {
	154	cdiv = 2; /* clk_hz/2 is the fastest we can go */
	155	} else if (spi_hz) {
210b4923 MS	156	/* CDIV must be a multiple of two */
	157	cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
	158	cdiv += (cdiv % 2);
f8043872 CB	159
	160	if (cdiv >= 65536)
	161	cdiv = 0; /* 0 is the slowest we can go */
342f948a	162	} else {
f8043872	163	cdiv = 0; /* 0 is the slowest we can go */
342f948a	164	}
f8043872 CB	165
	166	if (spi->mode & SPI_CPOL)
	167	cs \|= BCM2835_SPI_CS_CPOL;
	168	if (spi->mode & SPI_CPHA)
	169	cs \|= BCM2835_SPI_CS_CPHA;
	170
	171	if (!(spi->mode & SPI_NO_CS)) {
	172	if (spi->mode & SPI_CS_HIGH) {
	173	cs \|= BCM2835_SPI_CS_CSPOL;
	174	cs \|= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
	175	}
	176
	177	cs \|= spi->chip_select;
	178	}
	179
16735d02	180	reinit_completion(&bs->done);
f8043872 CB	181	bs->tx_buf = tfr->tx_buf;
	182	bs->rx_buf = tfr->rx_buf;
	183	bs->len = tfr->len;
	184
	185	bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
	186	/*
	187	* Enable the HW block. This will immediately trigger a DONE (TX
	188	* empty) interrupt, upon which we will fill the TX FIFO with the
	189	* first TX bytes. Pre-filling the TX FIFO here to avoid the
	190	* interrupt doesn't work:-(
	191	*/
	192	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
	193
	194	return 0;
	195	}
	196
	197	static int bcm2835_spi_finish_transfer(struct spi_device *spi,
342f948a MS	198	struct spi_transfer *tfr,
342f948a MS	199	bool cs_change)
f8043872 CB	200	{
	201	struct bcm2835_spi *bs = spi_master_get_devdata(spi->master);
	202	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
	203
f8043872 CB	204	if (tfr->delay_usecs)
	205	udelay(tfr->delay_usecs);
	206
	207	if (cs_change)
	208	/* Clear TA flag */
	209	bcm2835_wr(bs, BCM2835_SPI_CS, cs & ~BCM2835_SPI_CS_TA);
	210
	211	return 0;
	212	}
	213
f8043872	214	static int bcm2835_spi_transfer_one(struct spi_master *master,
342f948a	215	struct spi_message *mesg)
f8043872 CB	216	{
	217	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	218	struct spi_transfer *tfr;
	219	struct spi_device *spi = mesg->spi;
	220	int err = 0;
	221	unsigned int timeout;
	222	bool cs_change;
	223
	224	list_for_each_entry(tfr, &mesg->transfers, transfer_list) {
f8043872 CB	225	err = bcm2835_spi_start_transfer(spi, tfr);
	226	if (err)
	227	goto out;
	228
342f948a MS	229	timeout = wait_for_completion_timeout(
	230	&bs->done,
	231	msecs_to_jiffies(BCM2835_SPI_TIMEOUT_MS)
	232	);
f8043872 CB	233	if (!timeout) {
	234	err = -ETIMEDOUT;
	235	goto out;
	236	}
	237
	238	cs_change = tfr->cs_change \|\|
	239	list_is_last(&tfr->transfer_list, &mesg->transfers);
	240
	241	err = bcm2835_spi_finish_transfer(spi, tfr, cs_change);
	242	if (err)
	243	goto out;
	244
	245	mesg->actual_length += (tfr->len - bs->len);
	246	}
	247
	248	out:
	249	/* Clear FIFOs, and disable the HW block */
	250	bcm2835_wr(bs, BCM2835_SPI_CS,
	251	BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX);
	252	mesg->status = err;
	253	spi_finalize_current_message(master);
	254
	255	return 0;
	256	}
	257
	258	static int bcm2835_spi_probe(struct platform_device *pdev)
	259	{
	260	struct spi_master *master;
	261	struct bcm2835_spi *bs;
	262	struct resource *res;
	263	int err;
	264
	265	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	266	if (!master) {
	267	dev_err(&pdev->dev, "spi_alloc_master() failed\n");
	268	return -ENOMEM;
	269	}
	270
	271	platform_set_drvdata(pdev, master);
	272
	273	master->mode_bits = BCM2835_SPI_MODE_BITS;
c2b6a3a8	274	master->bits_per_word_mask = SPI_BPW_MASK(8);
f8043872	275	master->num_chipselect = 3;
f8043872 CB	276	master->transfer_one_message = bcm2835_spi_transfer_one;
	277	master->dev.of_node = pdev->dev.of_node;
	278
	279	bs = spi_master_get_devdata(master);
	280
	281	init_completion(&bs->done);
	282
	283	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2d6e75e8 LN	284	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	285	if (IS_ERR(bs->regs)) {
	286	err = PTR_ERR(bs->regs);
f8043872 CB	287	goto out_master_put;
	288	}
	289
	290	bs->clk = devm_clk_get(&pdev->dev, NULL);
	291	if (IS_ERR(bs->clk)) {
	292	err = PTR_ERR(bs->clk);
	293	dev_err(&pdev->dev, "could not get clk: %d\n", err);
	294	goto out_master_put;
	295	}
	296
	297	bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
	298	if (bs->irq <= 0) {
	299	dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
	300	err = bs->irq ? bs->irq : -ENODEV;
	301	goto out_master_put;
	302	}
	303
	304	clk_prepare_enable(bs->clk);
	305
08bc0544	306	err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
342f948a	307	dev_name(&pdev->dev), master);
f8043872 CB	308	if (err) {
	309	dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
	310	goto out_clk_disable;
	311	}
	312
	313	/* initialise the hardware */
	314	bcm2835_wr(bs, BCM2835_SPI_CS,
	315	BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX);
	316
247263db	317	err = devm_spi_register_master(&pdev->dev, master);
f8043872 CB	318	if (err) {
f8043872 CB	319	dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
08bc0544	320	goto out_clk_disable;
f8043872 CB	321	}
	322
	323	return 0;
	324
f8043872 CB	325	out_clk_disable:
	326	clk_disable_unprepare(bs->clk);
	327	out_master_put:
	328	spi_master_put(master);
	329	return err;
	330	}
	331
	332	static int bcm2835_spi_remove(struct platform_device *pdev)
	333	{
e0b35b89	334	struct spi_master *master = platform_get_drvdata(pdev);
f8043872 CB	335	struct bcm2835_spi *bs = spi_master_get_devdata(master);
f8043872 CB	336
f8043872 CB	337	/* Clear FIFOs, and disable the HW block */
	338	bcm2835_wr(bs, BCM2835_SPI_CS,
	339	BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX);
	340
	341	clk_disable_unprepare(bs->clk);
f8043872 CB	342
	343	return 0;
	344	}
	345
	346	static const struct of_device_id bcm2835_spi_match[] = {
	347	{ .compatible = "brcm,bcm2835-spi", },
	348	{}
	349	};
	350	MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
	351
	352	static struct platform_driver bcm2835_spi_driver = {
	353	.driver = {
	354	.name = DRV_NAME,
f8043872 CB	355	.of_match_table = bcm2835_spi_match,
	356	},
	357	.probe = bcm2835_spi_probe,
	358	.remove = bcm2835_spi_remove,
	359	};
	360	module_platform_driver(bcm2835_spi_driver);
	361
	362	MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
	363	MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
	364	MODULE_LICENSE("GPL v2");