[deliverable/linux.git] / drivers / spi / spi-bcm2835.c

/*
 * Driver for Broadcom BCM2835 SPI Controllers
 *
 * Copyright (C) 2012 Chris Boot
 * Copyright (C) 2013 Stephen Warren
 * Copyright (C) 2015 Martin Sperl
 *
 * This driver is inspired by:
 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_gpio.h>
#include <linux/of_device.h>
#include <linux/spi/spi.h>

/* SPI register offsets */
#define BCM2835_SPI_CS			0x00
#define BCM2835_SPI_FIFO		0x04
#define BCM2835_SPI_CLK			0x08
#define BCM2835_SPI_DLEN		0x0c
#define BCM2835_SPI_LTOH		0x10
#define BCM2835_SPI_DC			0x14

/* Bitfields in CS */
#define BCM2835_SPI_CS_LEN_LONG		0x02000000
#define BCM2835_SPI_CS_DMA_LEN		0x01000000
#define BCM2835_SPI_CS_CSPOL2		0x00800000
#define BCM2835_SPI_CS_CSPOL1		0x00400000
#define BCM2835_SPI_CS_CSPOL0		0x00200000
#define BCM2835_SPI_CS_RXF		0x00100000
#define BCM2835_SPI_CS_RXR		0x00080000
#define BCM2835_SPI_CS_TXD		0x00040000
#define BCM2835_SPI_CS_RXD		0x00020000
#define BCM2835_SPI_CS_DONE		0x00010000
#define BCM2835_SPI_CS_LEN		0x00002000
#define BCM2835_SPI_CS_REN		0x00001000
#define BCM2835_SPI_CS_ADCS		0x00000800
#define BCM2835_SPI_CS_INTR		0x00000400
#define BCM2835_SPI_CS_INTD		0x00000200
#define BCM2835_SPI_CS_DMAEN		0x00000100
#define BCM2835_SPI_CS_TA		0x00000080
#define BCM2835_SPI_CS_CSPOL		0x00000040
#define BCM2835_SPI_CS_CLEAR_RX		0x00000020
#define BCM2835_SPI_CS_CLEAR_TX		0x00000010
#define BCM2835_SPI_CS_CPOL		0x00000008
#define BCM2835_SPI_CS_CPHA		0x00000004
#define BCM2835_SPI_CS_CS_10		0x00000002
#define BCM2835_SPI_CS_CS_01		0x00000001

#define BCM2835_SPI_TIMEOUT_MS	30000
#define BCM2835_SPI_MODE_BITS	(SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
				| SPI_NO_CS | SPI_3WIRE)

#define DRV_NAME	"spi-bcm2835"

struct bcm2835_spi {
	void __iomem *regs;
	struct clk *clk;
	int irq;
	const u8 *tx_buf;
	u8 *rx_buf;
	int tx_len;
	int rx_len;
};

static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
{
	return readl(bs->regs + reg);
}

static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
{
	writel(val, bs->regs + reg);
}

static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
{
	u8 byte;

	while ((bs->rx_len) &&
	       (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
		byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
		if (bs->rx_buf)
			*bs->rx_buf++ = byte;
		bs->rx_len--;
	}
}

static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
{
	u8 byte;

	while ((bs->tx_len) &&
	       (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
		byte = bs->tx_buf ? *bs->tx_buf++ : 0;
		bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
		bs->tx_len--;
	}
}

static void bcm2835_spi_reset_hw(struct spi_master *master)
{
	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);

	/* Disable SPI interrupts and transfer */
	cs &= ~(BCM2835_SPI_CS_INTR |
		BCM2835_SPI_CS_INTD |
		BCM2835_SPI_CS_TA);
	/* and reset RX/TX FIFOS */
	cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;

	/* and reset the SPI_HW */
	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
}

static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = dev_id;
	struct bcm2835_spi *bs = spi_master_get_devdata(master);

	/* Read as many bytes as possible from FIFO */
	bcm2835_rd_fifo(bs);
	/* Write as many bytes as possible to FIFO */
	bcm2835_wr_fifo(bs);

	/* based on flags decide if we can finish the transfer */
	if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
		/* Transfer complete - reset SPI HW */
		bcm2835_spi_reset_hw(master);
		/* wake up the framework */
		complete(&master->xfer_completion);
	}

	return IRQ_HANDLED;
}

static int bcm2835_spi_transfer_one(struct spi_master *master,
				    struct spi_device *spi,
				    struct spi_transfer *tfr)
{
	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	unsigned long spi_hz, clk_hz, cdiv;
	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);

	/* set clock */
	spi_hz = tfr->speed_hz;
	clk_hz = clk_get_rate(bs->clk);

	if (spi_hz >= clk_hz / 2) {
		cdiv = 2; /* clk_hz/2 is the fastest we can go */
	} else if (spi_hz) {
		/* CDIV must be a multiple of two */
		cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
		cdiv += (cdiv % 2);

		if (cdiv >= 65536)
			cdiv = 0; /* 0 is the slowest we can go */
	} else {
		cdiv = 0; /* 0 is the slowest we can go */
	}
	bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);

	/* handle all the modes */
	if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
		cs |= BCM2835_SPI_CS_REN;
	if (spi->mode & SPI_CPOL)
		cs |= BCM2835_SPI_CS_CPOL;
	if (spi->mode & SPI_CPHA)
		cs |= BCM2835_SPI_CS_CPHA;

	/* for gpio_cs set dummy CS so that no HW-CS get changed
	 * we can not run this in bcm2835_spi_set_cs, as it does
	 * not get called for cs_gpio cases, so we need to do it here
	 */
	if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS))
		cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;

	/* set transmit buffers and length */
	bs->tx_buf = tfr->tx_buf;
	bs->rx_buf = tfr->rx_buf;
	bs->tx_len = tfr->len;
	bs->rx_len = tfr->len;

	/*
	 * Enable the HW block. This will immediately trigger a DONE (TX
	 * empty) interrupt, upon which we will fill the TX FIFO with the
	 * first TX bytes. Pre-filling the TX FIFO here to avoid the
	 * interrupt doesn't work:-(
	 */
	cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
	bcm2835_wr(bs, BCM2835_SPI_CS, cs);

	/* signal that we need to wait for completion */
	return 1;
}

static void bcm2835_spi_handle_err(struct spi_master *master,
				   struct spi_message *msg)
{
	bcm2835_spi_reset_hw(master);
}

static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
{
	/*
	 * we can assume that we are "native" as per spi_set_cs
	 *   calling us ONLY when cs_gpio is not set
	 * we can also assume that we are CS < 3 as per bcm2835_spi_setup
	 *   we would not get called because of error handling there.
	 * the level passed is the electrical level not enabled/disabled
	 *   so it has to get translated back to enable/disable
	 *   see spi_set_cs in spi.c for the implementation
	 */

	struct spi_master *master = spi->master;
	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
	bool enable;

	/* calculate the enable flag from the passed gpio_level */
	enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;

	/* set flags for "reverse" polarity in the registers */
	if (spi->mode & SPI_CS_HIGH) {
		/* set the correct CS-bits */
		cs |= BCM2835_SPI_CS_CSPOL;
		cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
	} else {
		/* clean the CS-bits */
		cs &= ~BCM2835_SPI_CS_CSPOL;
		cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
	}

	/* select the correct chip_select depending on disabled/enabled */
	if (enable) {
		/* set cs correctly */
		if (spi->mode & SPI_NO_CS) {
			/* use the "undefined" chip-select */
			cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
		} else {
			/* set the chip select */
			cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01);
			cs |= spi->chip_select;
		}
	} else {
		/* disable CSPOL which puts HW-CS into deselected state */
		cs &= ~BCM2835_SPI_CS_CSPOL;
		/* use the "undefined" chip-select as precaution */
		cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
	}

	/* finally set the calculated flags in SPI_CS */
	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
}

static int bcm2835_spi_setup(struct spi_device *spi)
{
	/*
	 * sanity checking the native-chipselects
	 */
	if (spi->mode & SPI_NO_CS)
		return 0;
	if (gpio_is_valid(spi->cs_gpio))
		return 0;
	if (spi->chip_select < 3)
		return 0;

	/* error in the case of native CS requested with CS-id > 2 */
	dev_err(&spi->dev,
		"setup: only three native chip-selects are supported\n"
		);
	return -EINVAL;
}

static int bcm2835_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct bcm2835_spi *bs;
	struct resource *res;
	int err;

	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	if (!master) {
		dev_err(&pdev->dev, "spi_alloc_master() failed\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, master);

	master->mode_bits = BCM2835_SPI_MODE_BITS;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->num_chipselect = 3;
	master->setup = bcm2835_spi_setup;
	master->set_cs = bcm2835_spi_set_cs;
	master->transfer_one = bcm2835_spi_transfer_one;
	master->handle_err = bcm2835_spi_handle_err;
	master->dev.of_node = pdev->dev.of_node;

	bs = spi_master_get_devdata(master);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(bs->regs)) {
		err = PTR_ERR(bs->regs);
		goto out_master_put;
	}

	bs->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(bs->clk)) {
		err = PTR_ERR(bs->clk);
		dev_err(&pdev->dev, "could not get clk: %d\n", err);
		goto out_master_put;
	}

	bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
	if (bs->irq <= 0) {
		dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
		err = bs->irq ? bs->irq : -ENODEV;
		goto out_master_put;
	}

	clk_prepare_enable(bs->clk);

	err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
			       dev_name(&pdev->dev), master);
	if (err) {
		dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
		goto out_clk_disable;
	}

	/* initialise the hardware with the default polarities */
	bcm2835_wr(bs, BCM2835_SPI_CS,
		   BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);

	err = devm_spi_register_master(&pdev->dev, master);
	if (err) {
		dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
		goto out_clk_disable;
	}

	return 0;

out_clk_disable:
	clk_disable_unprepare(bs->clk);
out_master_put:
	spi_master_put(master);
	return err;
}

static int bcm2835_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm2835_spi *bs = spi_master_get_devdata(master);

	/* Clear FIFOs, and disable the HW block */
	bcm2835_wr(bs, BCM2835_SPI_CS,
		   BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);

	clk_disable_unprepare(bs->clk);

	return 0;
}

static const struct of_device_id bcm2835_spi_match[] = {
	{ .compatible = "brcm,bcm2835-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, bcm2835_spi_match);

static struct platform_driver bcm2835_spi_driver = {
	.driver		= {
		.name		= DRV_NAME,
		.of_match_table	= bcm2835_spi_match,
	},
	.probe		= bcm2835_spi_probe,
	.remove		= bcm2835_spi_remove,
};
module_platform_driver(bcm2835_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f8043872 CB	1	/*
	2	* Driver for Broadcom BCM2835 SPI Controllers
	3	*
	4	* Copyright (C) 2012 Chris Boot
	5	* Copyright (C) 2013 Stephen Warren
e34ff011	6	* Copyright (C) 2015 Martin Sperl
f8043872 CB	7	*
	8	* This driver is inspired by:
	9	* spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
	10	* spi-atmel.c, Copyright (C) 2006 Atmel Corporation
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2 of the License, or
	15	* (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
f8043872 CB	21	*/
	22
	23	#include <linux/clk.h>
	24	#include <linux/completion.h>
	25	#include <linux/delay.h>
	26	#include <linux/err.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/io.h>
	29	#include <linux/kernel.h>
	30	#include <linux/module.h>
	31	#include <linux/of.h>
	32	#include <linux/of_irq.h>
e34ff011	33	#include <linux/of_gpio.h>
f8043872 CB	34	#include <linux/of_device.h>
	35	#include <linux/spi/spi.h>
	36
	37	/* SPI register offsets */
	38	#define BCM2835_SPI_CS 0x00
	39	#define BCM2835_SPI_FIFO 0x04
	40	#define BCM2835_SPI_CLK 0x08
	41	#define BCM2835_SPI_DLEN 0x0c
	42	#define BCM2835_SPI_LTOH 0x10
	43	#define BCM2835_SPI_DC 0x14
	44
	45	/* Bitfields in CS */
	46	#define BCM2835_SPI_CS_LEN_LONG 0x02000000
	47	#define BCM2835_SPI_CS_DMA_LEN 0x01000000
	48	#define BCM2835_SPI_CS_CSPOL2 0x00800000
	49	#define BCM2835_SPI_CS_CSPOL1 0x00400000
	50	#define BCM2835_SPI_CS_CSPOL0 0x00200000
	51	#define BCM2835_SPI_CS_RXF 0x00100000
	52	#define BCM2835_SPI_CS_RXR 0x00080000
	53	#define BCM2835_SPI_CS_TXD 0x00040000
	54	#define BCM2835_SPI_CS_RXD 0x00020000
	55	#define BCM2835_SPI_CS_DONE 0x00010000
	56	#define BCM2835_SPI_CS_LEN 0x00002000
	57	#define BCM2835_SPI_CS_REN 0x00001000
	58	#define BCM2835_SPI_CS_ADCS 0x00000800
	59	#define BCM2835_SPI_CS_INTR 0x00000400
	60	#define BCM2835_SPI_CS_INTD 0x00000200
	61	#define BCM2835_SPI_CS_DMAEN 0x00000100
	62	#define BCM2835_SPI_CS_TA 0x00000080
	63	#define BCM2835_SPI_CS_CSPOL 0x00000040
	64	#define BCM2835_SPI_CS_CLEAR_RX 0x00000020
	65	#define BCM2835_SPI_CS_CLEAR_TX 0x00000010
	66	#define BCM2835_SPI_CS_CPOL 0x00000008
	67	#define BCM2835_SPI_CS_CPHA 0x00000004
	68	#define BCM2835_SPI_CS_CS_10 0x00000002
	69	#define BCM2835_SPI_CS_CS_01 0x00000001
	70
	71	#define BCM2835_SPI_TIMEOUT_MS 30000
6935224d MS	72	#define BCM2835_SPI_MODE_BITS (SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \
6935224d MS	73	\| SPI_NO_CS \| SPI_3WIRE)
f8043872 CB	74
	75	#define DRV_NAME "spi-bcm2835"
	76
	77	struct bcm2835_spi {
	78	void __iomem *regs;
	79	struct clk *clk;
	80	int irq;
f8043872 CB	81	const u8 *tx_buf;
f8043872 CB	82	u8 *rx_buf;
e34ff011 MS	83	int tx_len;
e34ff011 MS	84	int rx_len;
f8043872 CB	85	};
	86
	87	static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
	88	{
	89	return readl(bs->regs + reg);
	90	}
	91
	92	static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
	93	{
	94	writel(val, bs->regs + reg);
	95	}
	96
4adf3129	97	static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
f8043872 CB	98	{
	99	u8 byte;
	100
e34ff011 MS	101	while ((bs->rx_len) &&
e34ff011 MS	102	(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
f8043872 CB	103	byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
	104	if (bs->rx_buf)
	105	*bs->rx_buf++ = byte;
e34ff011	106	bs->rx_len--;
f8043872 CB	107	}
	108	}
	109
4adf3129	110	static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
f8043872 CB	111	{
	112	u8 byte;
	113
e34ff011	114	while ((bs->tx_len) &&
4adf3129	115	(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
f8043872 CB	116	byte = bs->tx_buf ? *bs->tx_buf++ : 0;
f8043872 CB	117	bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
e34ff011	118	bs->tx_len--;
f8043872 CB	119	}
	120	}
	121
e34ff011 MS	122	static void bcm2835_spi_reset_hw(struct spi_master *master)
	123	{
	124	struct bcm2835_spi *bs = spi_master_get_devdata(master);
	125	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
	126
	127	/* Disable SPI interrupts and transfer */
	128	cs &= ~(BCM2835_SPI_CS_INTR \|
	129	BCM2835_SPI_CS_INTD \|
	130	BCM2835_SPI_CS_TA);
	131	/* and reset RX/TX FIFOS */
	132	cs \|= BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX;
	133
	134	/* and reset the SPI_HW */
	135	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
	136	}
	137
f8043872 CB	138	static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
	139	{
	140	struct spi_master *master = dev_id;
	141	struct bcm2835_spi *bs = spi_master_get_devdata(master);
f8043872	142
4adf3129 MS	143	/* Read as many bytes as possible from FIFO */
4adf3129 MS	144	bcm2835_rd_fifo(bs);
e34ff011 MS	145	/* Write as many bytes as possible to FIFO */
	146	bcm2835_wr_fifo(bs);
	147
	148	/* based on flags decide if we can finish the transfer */
	149	if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
	150	/* Transfer complete - reset SPI HW */
	151	bcm2835_spi_reset_hw(master);
	152	/* wake up the framework */
	153	complete(&master->xfer_completion);
f8043872 CB	154	}
f8043872 CB	155
4adf3129	156	return IRQ_HANDLED;
f8043872 CB	157	}
f8043872 CB	158
e34ff011 MS	159	static int bcm2835_spi_transfer_one(struct spi_master *master,
	160	struct spi_device *spi,
	161	struct spi_transfer *tfr)
f8043872	162	{
e34ff011	163	struct bcm2835_spi *bs = spi_master_get_devdata(master);
f8043872	164	unsigned long spi_hz, clk_hz, cdiv;
e34ff011	165	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
f8043872	166
e34ff011	167	/* set clock */
f8043872 CB	168	spi_hz = tfr->speed_hz;
	169	clk_hz = clk_get_rate(bs->clk);
	170
	171	if (spi_hz >= clk_hz / 2) {
	172	cdiv = 2; /* clk_hz/2 is the fastest we can go */
	173	} else if (spi_hz) {
210b4923 MS	174	/* CDIV must be a multiple of two */
	175	cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
	176	cdiv += (cdiv % 2);
f8043872 CB	177
	178	if (cdiv >= 65536)
	179	cdiv = 0; /* 0 is the slowest we can go */
342f948a	180	} else {
f8043872	181	cdiv = 0; /* 0 is the slowest we can go */
342f948a	182	}
e34ff011	183	bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
f8043872	184
e34ff011	185	/* handle all the modes */
6935224d MS	186	if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
6935224d MS	187	cs \|= BCM2835_SPI_CS_REN;
f8043872 CB	188	if (spi->mode & SPI_CPOL)
	189	cs \|= BCM2835_SPI_CS_CPOL;
	190	if (spi->mode & SPI_CPHA)
	191	cs \|= BCM2835_SPI_CS_CPHA;
	192
e34ff011 MS	193	/* for gpio_cs set dummy CS so that no HW-CS get changed
	194	* we can not run this in bcm2835_spi_set_cs, as it does
	195	* not get called for cs_gpio cases, so we need to do it here
	196	*/
	197	if (gpio_is_valid(spi->cs_gpio) \|\| (spi->mode & SPI_NO_CS))
	198	cs \|= BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01;
f8043872	199
e34ff011	200	/* set transmit buffers and length */
f8043872 CB	201	bs->tx_buf = tfr->tx_buf;
f8043872 CB	202	bs->rx_buf = tfr->rx_buf;
e34ff011 MS	203	bs->tx_len = tfr->len;
e34ff011 MS	204	bs->rx_len = tfr->len;
f8043872	205
f8043872 CB	206	/*
	207	* Enable the HW block. This will immediately trigger a DONE (TX
	208	* empty) interrupt, upon which we will fill the TX FIFO with the
	209	* first TX bytes. Pre-filling the TX FIFO here to avoid the
	210	* interrupt doesn't work:-(
	211	*/
e34ff011	212	cs \|= BCM2835_SPI_CS_INTR \| BCM2835_SPI_CS_INTD \| BCM2835_SPI_CS_TA;
f8043872 CB	213	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
f8043872 CB	214
e34ff011 MS	215	/* signal that we need to wait for completion */
e34ff011 MS	216	return 1;
f8043872 CB	217	}
f8043872 CB	218
e34ff011 MS	219	static void bcm2835_spi_handle_err(struct spi_master *master,
e34ff011 MS	220	struct spi_message *msg)
f8043872	221	{
e34ff011	222	bcm2835_spi_reset_hw(master);
f8043872 CB	223	}
f8043872 CB	224
e34ff011	225	static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
f8043872	226	{
e34ff011 MS	227	/*
	228	* we can assume that we are "native" as per spi_set_cs
	229	* calling us ONLY when cs_gpio is not set
	230	* we can also assume that we are CS < 3 as per bcm2835_spi_setup
	231	* we would not get called because of error handling there.
	232	* the level passed is the electrical level not enabled/disabled
	233	* so it has to get translated back to enable/disable
	234	* see spi_set_cs in spi.c for the implementation
	235	*/
	236
	237	struct spi_master *master = spi->master;
f8043872	238	struct bcm2835_spi *bs = spi_master_get_devdata(master);
e34ff011 MS	239	u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
e34ff011 MS	240	bool enable;
f8043872	241
e34ff011 MS	242	/* calculate the enable flag from the passed gpio_level */
e34ff011 MS	243	enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;
f8043872	244
e34ff011 MS	245	/* set flags for "reverse" polarity in the registers */
	246	if (spi->mode & SPI_CS_HIGH) {
	247	/* set the correct CS-bits */
	248	cs \|= BCM2835_SPI_CS_CSPOL;
	249	cs \|= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
	250	} else {
	251	/* clean the CS-bits */
	252	cs &= ~BCM2835_SPI_CS_CSPOL;
	253	cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
	254	}
f8043872	255
e34ff011 MS	256	/* select the correct chip_select depending on disabled/enabled */
	257	if (enable) {
	258	/* set cs correctly */
	259	if (spi->mode & SPI_NO_CS) {
	260	/* use the "undefined" chip-select */
	261	cs \|= BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01;
	262	} else {
	263	/* set the chip select */
	264	cs &= ~(BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01);
	265	cs \|= spi->chip_select;
	266	}
	267	} else {
	268	/* disable CSPOL which puts HW-CS into deselected state */
	269	cs &= ~BCM2835_SPI_CS_CSPOL;
	270	/* use the "undefined" chip-select as precaution */
	271	cs \|= BCM2835_SPI_CS_CS_10 \| BCM2835_SPI_CS_CS_01;
f8043872 CB	272	}
f8043872 CB	273
e34ff011 MS	274	/* finally set the calculated flags in SPI_CS */
	275	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
	276	}
f8043872	277
e34ff011 MS	278	static int bcm2835_spi_setup(struct spi_device *spi)
	279	{
	280	/*
	281	* sanity checking the native-chipselects
	282	*/
	283	if (spi->mode & SPI_NO_CS)
	284	return 0;
	285	if (gpio_is_valid(spi->cs_gpio))
	286	return 0;
	287	if (spi->chip_select < 3)
	288	return 0;
	289
	290	/* error in the case of native CS requested with CS-id > 2 */
	291	dev_err(&spi->dev,
	292	"setup: only three native chip-selects are supported\n"
	293	);
	294	return -EINVAL;
f8043872 CB	295	}
	296
	297	static int bcm2835_spi_probe(struct platform_device *pdev)
	298	{
	299	struct spi_master *master;
	300	struct bcm2835_spi *bs;
	301	struct resource *res;
	302	int err;
	303
	304	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	305	if (!master) {
	306	dev_err(&pdev->dev, "spi_alloc_master() failed\n");
	307	return -ENOMEM;
	308	}
	309
	310	platform_set_drvdata(pdev, master);
	311
	312	master->mode_bits = BCM2835_SPI_MODE_BITS;
c2b6a3a8	313	master->bits_per_word_mask = SPI_BPW_MASK(8);
f8043872	314	master->num_chipselect = 3;
e34ff011 MS	315	master->setup = bcm2835_spi_setup;
	316	master->set_cs = bcm2835_spi_set_cs;
	317	master->transfer_one = bcm2835_spi_transfer_one;
	318	master->handle_err = bcm2835_spi_handle_err;
f8043872 CB	319	master->dev.of_node = pdev->dev.of_node;
	320
	321	bs = spi_master_get_devdata(master);
	322
f8043872	323	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2d6e75e8 LN	324	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	325	if (IS_ERR(bs->regs)) {
	326	err = PTR_ERR(bs->regs);
f8043872 CB	327	goto out_master_put;
	328	}
	329
	330	bs->clk = devm_clk_get(&pdev->dev, NULL);
	331	if (IS_ERR(bs->clk)) {
	332	err = PTR_ERR(bs->clk);
	333	dev_err(&pdev->dev, "could not get clk: %d\n", err);
	334	goto out_master_put;
	335	}
	336
	337	bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
	338	if (bs->irq <= 0) {
	339	dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
	340	err = bs->irq ? bs->irq : -ENODEV;
	341	goto out_master_put;
	342	}
	343
	344	clk_prepare_enable(bs->clk);
	345
08bc0544	346	err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
342f948a	347	dev_name(&pdev->dev), master);
f8043872 CB	348	if (err) {
	349	dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
	350	goto out_clk_disable;
	351	}
	352
e34ff011	353	/* initialise the hardware with the default polarities */
f8043872 CB	354	bcm2835_wr(bs, BCM2835_SPI_CS,
	355	BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX);
	356
247263db	357	err = devm_spi_register_master(&pdev->dev, master);
f8043872 CB	358	if (err) {
f8043872 CB	359	dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
08bc0544	360	goto out_clk_disable;
f8043872 CB	361	}
	362
	363	return 0;
	364
f8043872 CB	365	out_clk_disable:
	366	clk_disable_unprepare(bs->clk);
	367	out_master_put:
	368	spi_master_put(master);
	369	return err;
	370	}
	371
	372	static int bcm2835_spi_remove(struct platform_device *pdev)
	373	{
e0b35b89	374	struct spi_master *master = platform_get_drvdata(pdev);
f8043872 CB	375	struct bcm2835_spi *bs = spi_master_get_devdata(master);
f8043872 CB	376
f8043872 CB	377	/* Clear FIFOs, and disable the HW block */
	378	bcm2835_wr(bs, BCM2835_SPI_CS,
	379	BCM2835_SPI_CS_CLEAR_RX \| BCM2835_SPI_CS_CLEAR_TX);
	380
	381	clk_disable_unprepare(bs->clk);
f8043872 CB	382
	383	return 0;
	384	}
	385
	386	static const struct of_device_id bcm2835_spi_match[] = {
	387	{ .compatible = "brcm,bcm2835-spi", },
	388	{}
	389	};
	390	MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
	391
	392	static struct platform_driver bcm2835_spi_driver = {
	393	.driver = {
	394	.name = DRV_NAME,
f8043872 CB	395	.of_match_table = bcm2835_spi_match,
	396	},
	397	.probe = bcm2835_spi_probe,
	398	.remove = bcm2835_spi_remove,
	399	};
	400	module_platform_driver(bcm2835_spi_driver);
	401
	402	MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
	403	MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
	404	MODULE_LICENSE("GPL v2");