[deliverable/linux.git] / drivers / spi / spi-bcm2835aux.c

/*
 * Driver for Broadcom BCM2835 auxiliary SPI Controllers
 *
 * the driver does not rely on the native chipselects at all
 * but only uses the gpio type chipselects
 *
 * Based on: spi-bcm2835.c
 *
 * Copyright (C) 2015 Martin Sperl
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/spi/spi.h>
#include <linux/spinlock.h>

/*
 * spi register defines
 *
 * note there is garbage in the "official" documentation,
 * so some data is taken from the file:
 *   brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
 * inside of:
 *   http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
 */

/* SPI register offsets */
#define BCM2835_AUX_SPI_CNTL0	0x00
#define BCM2835_AUX_SPI_CNTL1	0x04
#define BCM2835_AUX_SPI_STAT	0x08
#define BCM2835_AUX_SPI_PEEK	0x0C
#define BCM2835_AUX_SPI_IO	0x20
#define BCM2835_AUX_SPI_TXHOLD	0x30

/* Bitfields in CNTL0 */
#define BCM2835_AUX_SPI_CNTL0_SPEED	0xFFF00000
#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX	0xFFF
#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT	20
#define BCM2835_AUX_SPI_CNTL0_CS	0x000E0000
#define BCM2835_AUX_SPI_CNTL0_POSTINPUT	0x00010000
#define BCM2835_AUX_SPI_CNTL0_VAR_CS	0x00008000
#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH	0x00004000
#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD	0x00003000
#define BCM2835_AUX_SPI_CNTL0_ENABLE	0x00000800
#define BCM2835_AUX_SPI_CNTL0_CPHA_IN	0x00000400
#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO	0x00000200
#define BCM2835_AUX_SPI_CNTL0_CPHA_OUT	0x00000100
#define BCM2835_AUX_SPI_CNTL0_CPOL	0x00000080
#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT	0x00000040
#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN	0x0000003F

/* Bitfields in CNTL1 */
#define BCM2835_AUX_SPI_CNTL1_CSHIGH	0x00000700
#define BCM2835_AUX_SPI_CNTL1_IDLE	0x00000080
#define BCM2835_AUX_SPI_CNTL1_TXEMPTY	0x00000040
#define BCM2835_AUX_SPI_CNTL1_MSBF_IN	0x00000002
#define BCM2835_AUX_SPI_CNTL1_KEEP_IN	0x00000001

/* Bitfields in STAT */
#define BCM2835_AUX_SPI_STAT_TX_LVL	0xFF000000
#define BCM2835_AUX_SPI_STAT_RX_LVL	0x00FF0000
#define BCM2835_AUX_SPI_STAT_TX_FULL	0x00000400
#define BCM2835_AUX_SPI_STAT_TX_EMPTY	0x00000200
#define BCM2835_AUX_SPI_STAT_RX_FULL	0x00000100
#define BCM2835_AUX_SPI_STAT_RX_EMPTY	0x00000080
#define BCM2835_AUX_SPI_STAT_BUSY	0x00000040
#define BCM2835_AUX_SPI_STAT_BITCOUNT	0x0000003F

/* timeout values */
#define BCM2835_AUX_SPI_POLLING_LIMIT_US	30
#define BCM2835_AUX_SPI_POLLING_JIFFIES		2

#define BCM2835_AUX_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
				  | SPI_NO_CS)

struct bcm2835aux_spi {
	void __iomem *regs;
	struct clk *clk;
	int irq;
	u32 cntl[2];
	const u8 *tx_buf;
	u8 *rx_buf;
	int tx_len;
	int rx_len;
	int pending;
};

static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
{
	return readl(bs->regs + reg);
}

static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
				 u32 val)
{
	writel(val, bs->regs + reg);
}

static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
{
	u32 data;
	int count = min(bs->rx_len, 3);

	data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
	if (bs->rx_buf) {
		switch (count) {
		case 4:
			*bs->rx_buf++ = (data >> 24) & 0xff;
			/* fallthrough */
		case 3:
			*bs->rx_buf++ = (data >> 16) & 0xff;
			/* fallthrough */
		case 2:
			*bs->rx_buf++ = (data >> 8) & 0xff;
			/* fallthrough */
		case 1:
			*bs->rx_buf++ = (data >> 0) & 0xff;
			/* fallthrough - no default */
		}
	}
	bs->rx_len -= count;
	bs->pending -= count;
}

static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
{
	u32 data;
	u8 byte;
	int count;
	int i;

	/* gather up to 3 bytes to write to the FIFO */
	count = min(bs->tx_len, 3);
	data = 0;
	for (i = 0; i < count; i++) {
		byte = bs->tx_buf ? *bs->tx_buf++ : 0;
		data |= byte << (8 * (2 - i));
	}

	/* and set the variable bit-length */
	data |= (count * 8) << 24;

	/* and decrement length */
	bs->tx_len -= count;
	bs->pending += count;

	/* write to the correct TX-register */
	if (bs->tx_len)
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
	else
		bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
}

static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
{
	/* disable spi clearing fifo and interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
		      BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
}

static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
{
	struct spi_master *master = dev_id;
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	irqreturn_t ret = IRQ_NONE;

	/* check if we have data to read */
	while (bs->rx_len &&
	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
		  BCM2835_AUX_SPI_STAT_RX_EMPTY))) {
		bcm2835aux_rd_fifo(bs);
		ret = IRQ_HANDLED;
	}

	/* check if we have data to write */
	while (bs->tx_len &&
	       (bs->pending < 12) &&
	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
		  BCM2835_AUX_SPI_STAT_TX_FULL))) {
		bcm2835aux_wr_fifo(bs);
		ret = IRQ_HANDLED;
	}

	/* and check if we have reached "done" */
	while (bs->rx_len &&
	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
		  BCM2835_AUX_SPI_STAT_BUSY))) {
		bcm2835aux_rd_fifo(bs);
		ret = IRQ_HANDLED;
	}

	/* and if rx_len is 0 then wake up completion and disable spi */
	if (!bs->rx_len) {
		bcm2835aux_spi_reset_hw(bs);
		complete(&master->xfer_completion);
	}

	/* and return */
	return ret;
}

static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
					     struct spi_device *spi,
					     struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	/* enable interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
		BCM2835_AUX_SPI_CNTL1_TXEMPTY |
		BCM2835_AUX_SPI_CNTL1_IDLE);

	/* and wait for finish... */
	return 1;
}

static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
					   struct spi_device *spi,
					   struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	/* fill in registers and fifos before enabling interrupts */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	/* fill in tx fifo with data before enabling interrupts */
	while ((bs->tx_len) &&
	       (bs->pending < 12) &&
	       (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
		  BCM2835_AUX_SPI_STAT_TX_FULL))) {
		bcm2835aux_wr_fifo(bs);
	}

	/* now run the interrupt mode */
	return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
}

static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
					    struct spi_device *spi,
					struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	unsigned long timeout;
	u32 stat;

	/* configure spi */
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

	/* set the timeout */
	timeout = jiffies + BCM2835_AUX_SPI_POLLING_JIFFIES;

	/* loop until finished the transfer */
	while (bs->rx_len) {
		/* read status */
		stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);

		/* fill in tx fifo with remaining data */
		if ((bs->tx_len) && (!(stat & BCM2835_AUX_SPI_STAT_TX_FULL))) {
			bcm2835aux_wr_fifo(bs);
			continue;
		}

		/* read data from fifo for both cases */
		if (!(stat & BCM2835_AUX_SPI_STAT_RX_EMPTY)) {
			bcm2835aux_rd_fifo(bs);
			continue;
		}
		if (!(stat & BCM2835_AUX_SPI_STAT_BUSY)) {
			bcm2835aux_rd_fifo(bs);
			continue;
		}

		/* there is still data pending to read check the timeout */
		if (bs->rx_len && time_after(jiffies, timeout)) {
			dev_dbg_ratelimited(&spi->dev,
					    "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
					    jiffies - timeout,
					    bs->tx_len, bs->rx_len);
			/* forward to interrupt handler */
			return __bcm2835aux_spi_transfer_one_irq(master,
							       spi, tfr);
		}
	}

	/* Transfer complete - reset SPI HW */
	bcm2835aux_spi_reset_hw(bs);

	/* and return without waiting for completion */
	return 0;
}

static int bcm2835aux_spi_transfer_one(struct spi_master *master,
				       struct spi_device *spi,
				       struct spi_transfer *tfr)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	unsigned long spi_hz, clk_hz, speed;
	unsigned long spi_used_hz;
	unsigned long long xfer_time_us;

	/* calculate the registers to handle
	 *
	 * note that we use the variable data mode, which
	 * is not optimal for longer transfers as we waste registers
	 * resulting (potentially) in more interrupts when transferring
	 * more than 12 bytes
	 */
	bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
		      BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
		      BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;

	/* set clock */
	spi_hz = tfr->speed_hz;
	clk_hz = clk_get_rate(bs->clk);

	if (spi_hz >= clk_hz / 2) {
		speed = 0;
	} else if (spi_hz) {
		speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
		if (speed >  BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
			speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	} else { /* the slowest we can go */
		speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	}
	bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;

	spi_used_hz = clk_hz / (2 * (speed + 1));

	/* handle all the modes */
	if (spi->mode & SPI_CPOL)
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
	if (spi->mode & SPI_CPHA)
		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT |
			       BCM2835_AUX_SPI_CNTL0_CPHA_IN;

	/* set transmit buffers and length */
	bs->tx_buf = tfr->tx_buf;
	bs->rx_buf = tfr->rx_buf;
	bs->tx_len = tfr->len;
	bs->rx_len = tfr->len;
	bs->pending = 0;

	/* calculate the estimated time in us the transfer runs
	 * note that there are are 2 idle clocks after each
	 * chunk getting transferred - in our case the chunk size
	 * is 3 bytes, so we approximate this by 9 bits/byte
	 */
	xfer_time_us = tfr->len * 9 * 1000000;
	do_div(xfer_time_us, spi_used_hz);

	/* run in polling mode for short transfers */
	if (xfer_time_us < BCM2835_AUX_SPI_POLLING_LIMIT_US)
		return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);

	/* run in interrupt mode for all others */
	return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
}

static void bcm2835aux_spi_handle_err(struct spi_master *master,
				      struct spi_message *msg)
{
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	bcm2835aux_spi_reset_hw(bs);
}

static int bcm2835aux_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct bcm2835aux_spi *bs;
	struct resource *res;
	unsigned long clk_hz;
	int err;

	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	if (!master) {
		dev_err(&pdev->dev, "spi_alloc_master() failed\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, master);
	master->mode_bits = BCM2835_AUX_SPI_MODE_BITS;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->num_chipselect = -1;
	master->transfer_one = bcm2835aux_spi_transfer_one;
	master->handle_err = bcm2835aux_spi_handle_err;
	master->dev.of_node = pdev->dev.of_node;

	bs = spi_master_get_devdata(master);

	/* the main area */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(bs->regs)) {
		err = PTR_ERR(bs->regs);
		goto out_master_put;
	}

	bs->clk = devm_clk_get(&pdev->dev, NULL);
	if ((!bs->clk) || (IS_ERR(bs->clk))) {
		err = PTR_ERR(bs->clk);
		dev_err(&pdev->dev, "could not get clk: %d\n", err);
		goto out_master_put;
	}

	bs->irq = platform_get_irq(pdev, 0);
	if (bs->irq <= 0) {
		dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
		err = bs->irq ? bs->irq : -ENODEV;
		goto out_master_put;
	}

	/* this also enables the HW block */
	err = clk_prepare_enable(bs->clk);
	if (err) {
		dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
		goto out_master_put;
	}

	/* just checking if the clock returns a sane value */
	clk_hz = clk_get_rate(bs->clk);
	if (!clk_hz) {
		dev_err(&pdev->dev, "clock returns 0 Hz\n");
		err = -ENODEV;
		goto out_clk_disable;
	}

	/* reset SPI-HW block */
	bcm2835aux_spi_reset_hw(bs);

	err = devm_request_irq(&pdev->dev, bs->irq,
			       bcm2835aux_spi_interrupt,
			       IRQF_SHARED,
			       dev_name(&pdev->dev), master);
	if (err) {
		dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
		goto out_clk_disable;
	}

	err = devm_spi_register_master(&pdev->dev, master);
	if (err) {
		dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
		goto out_clk_disable;
	}

	return 0;

out_clk_disable:
	clk_disable_unprepare(bs->clk);
out_master_put:
	spi_master_put(master);
	return err;
}

static int bcm2835aux_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);

	bcm2835aux_spi_reset_hw(bs);

	/* disable the HW block by releasing the clock */
	clk_disable_unprepare(bs->clk);

	return 0;
}

static const struct of_device_id bcm2835aux_spi_match[] = {
	{ .compatible = "brcm,bcm2835-aux-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);

static struct platform_driver bcm2835aux_spi_driver = {
	.driver		= {
		.name		= "spi-bcm2835aux",
		.of_match_table	= bcm2835aux_spi_match,
	},
	.probe		= bcm2835aux_spi_probe,
	.remove		= bcm2835aux_spi_remove,
};
module_platform_driver(bcm2835aux_spi_driver);

MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1ea29b39 MS	1	/*
	2	* Driver for Broadcom BCM2835 auxiliary SPI Controllers
	3	*
	4	* the driver does not rely on the native chipselects at all
	5	* but only uses the gpio type chipselects
	6	*
	7	* Based on: spi-bcm2835.c
	8	*
	9	* Copyright (C) 2015 Martin Sperl
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*/
	21
	22	#include <linux/clk.h>
	23	#include <linux/completion.h>
	24	#include <linux/delay.h>
	25	#include <linux/err.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/io.h>
	28	#include <linux/kernel.h>
	29	#include <linux/module.h>
	30	#include <linux/of.h>
	31	#include <linux/of_address.h>
	32	#include <linux/of_device.h>
	33	#include <linux/of_gpio.h>
	34	#include <linux/of_irq.h>
	35	#include <linux/regmap.h>
	36	#include <linux/spi/spi.h>
	37	#include <linux/spinlock.h>
	38
	39	/*
	40	* spi register defines
	41	*
	42	* note there is garbage in the "official" documentation,
	43	* so some data is taken from the file:
	44	* brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
	45	* inside of:
	46	* http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
	47	*/
	48
	49	/* SPI register offsets */
	50	#define BCM2835_AUX_SPI_CNTL0 0x00
	51	#define BCM2835_AUX_SPI_CNTL1 0x04
	52	#define BCM2835_AUX_SPI_STAT 0x08
	53	#define BCM2835_AUX_SPI_PEEK 0x0C
	54	#define BCM2835_AUX_SPI_IO 0x20
	55	#define BCM2835_AUX_SPI_TXHOLD 0x30
	56
	57	/* Bitfields in CNTL0 */
	58	#define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000
	59	#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
	60	#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20
	61	#define BCM2835_AUX_SPI_CNTL0_CS 0x000E0000
	62	#define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
	63	#define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000
	64	#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
65	#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000
66	#define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800
67	#define BCM2835_AUX_SPI_CNTL0_CPHA_IN 0x00000400
68	#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
69	#define BCM2835_AUX_SPI_CNTL0_CPHA_OUT 0x00000100
70	#define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080
71	#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040
72	#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F
73
74	/* Bitfields in CNTL1 */
75	#define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700
76	#define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000080
77	#define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000040
78	#define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002
79	#define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001
80
81	/* Bitfields in STAT */
82	#define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000
83	#define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000
84	#define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400
85	#define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200
86	#define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100
87	#define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080
88	#define BCM2835_AUX_SPI_STAT_BUSY 0x00000040
89	#define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F
90
91	/* timeout values */
92	#define BCM2835_AUX_SPI_POLLING_LIMIT_US 30
93	#define BCM2835_AUX_SPI_POLLING_JIFFIES 2
94
95	#define BCM2835_AUX_SPI_MODE_BITS (SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \
96	\| SPI_NO_CS)
97
98	struct bcm2835aux_spi {
99	void __iomem *regs;
100	struct clk *clk;
101	int irq;
102	u32 cntl[2];
103	const u8 *tx_buf;
104	u8 *rx_buf;
105	int tx_len;
106	int rx_len;
72aac02b	107	int pending;
1ea29b39 MS	108	};
	109
	110	static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
	111	{
	112	return readl(bs->regs + reg);
	113	}
	114
	115	static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
	116	u32 val)
	117	{
	118	writel(val, bs->regs + reg);
	119	}
	120
	121	static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
	122	{
	123	u32 data;
1ea29b39 MS	124	int count = min(bs->rx_len, 3);
	125
	126	data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
	127	if (bs->rx_buf) {
72aac02b MS	128	switch (count) {
	129	case 4:
	130	*bs->rx_buf++ = (data >> 24) & 0xff;
	131	/* fallthrough */
	132	case 3:
	133	*bs->rx_buf++ = (data >> 16) & 0xff;
	134	/* fallthrough */
	135	case 2:
	136	*bs->rx_buf++ = (data >> 8) & 0xff;
	137	/* fallthrough */
	138	case 1:
	139	*bs->rx_buf++ = (data >> 0) & 0xff;
	140	/* fallthrough - no default */
	141	}
1ea29b39 MS	142	}
1ea29b39 MS	143	bs->rx_len -= count;
72aac02b	144	bs->pending -= count;
1ea29b39 MS	145	}
	146
	147	static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
	148	{
	149	u32 data;
	150	u8 byte;
	151	int count;
	152	int i;
	153
	154	/* gather up to 3 bytes to write to the FIFO */
	155	count = min(bs->tx_len, 3);
	156	data = 0;
	157	for (i = 0; i < count; i++) {
	158	byte = bs->tx_buf ? *bs->tx_buf++ : 0;
	159	data \|= byte << (8 * (2 - i));
	160	}
	161
	162	/* and set the variable bit-length */
	163	data \|= (count * 8) << 24;
	164
	165	/* and decrement length */
	166	bs->tx_len -= count;
72aac02b	167	bs->pending += count;
1ea29b39 MS	168
	169	/* write to the correct TX-register */
	170	if (bs->tx_len)
	171	bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
	172	else
	173	bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
	174	}
	175
	176	static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
	177	{
	178	/* disable spi clearing fifo and interrupts */
	179	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
	180	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
	181	BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
	182	}
	183
	184	static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
	185	{
	186	struct spi_master *master = dev_id;
	187	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	188	irqreturn_t ret = IRQ_NONE;
	189
	190	/* check if we have data to read */
	191	while (bs->rx_len &&
	192	(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
	193	BCM2835_AUX_SPI_STAT_RX_EMPTY))) {
	194	bcm2835aux_rd_fifo(bs);
	195	ret = IRQ_HANDLED;
	196	}
	197
	198	/* check if we have data to write */
	199	while (bs->tx_len &&
72aac02b	200	(bs->pending < 12) &&
1ea29b39 MS	201	(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
	202	BCM2835_AUX_SPI_STAT_TX_FULL))) {
	203	bcm2835aux_wr_fifo(bs);
	204	ret = IRQ_HANDLED;
	205	}
	206
	207	/* and check if we have reached "done" */
	208	while (bs->rx_len &&
	209	(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
	210	BCM2835_AUX_SPI_STAT_BUSY))) {
	211	bcm2835aux_rd_fifo(bs);
	212	ret = IRQ_HANDLED;
	213	}
	214
	215	/* and if rx_len is 0 then wake up completion and disable spi */
	216	if (!bs->rx_len) {
	217	bcm2835aux_spi_reset_hw(bs);
	218	complete(&master->xfer_completion);
	219	}
	220
	221	/* and return */
	222	return ret;
	223	}
	224
	225	static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
	226	struct spi_device *spi,
	227	struct spi_transfer *tfr)
	228	{
	229	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	230
	231	/* enable interrupts */
	232	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] \|
	233	BCM2835_AUX_SPI_CNTL1_TXEMPTY \|
	234	BCM2835_AUX_SPI_CNTL1_IDLE);
	235
	236	/* and wait for finish... */
	237	return 1;
	238	}
	239
	240	static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
	241	struct spi_device *spi,
	242	struct spi_transfer *tfr)
	243	{
	244	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	245
	246	/* fill in registers and fifos before enabling interrupts */
	247	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	248	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	249
	250	/* fill in tx fifo with data before enabling interrupts */
	251	while ((bs->tx_len) &&
72aac02b	252	(bs->pending < 12) &&
1ea29b39 MS	253	(!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
	254	BCM2835_AUX_SPI_STAT_TX_FULL))) {
	255	bcm2835aux_wr_fifo(bs);
	256	}
	257
	258	/* now run the interrupt mode */
	259	return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
	260	}
	261
	262	static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
	263	struct spi_device *spi,
72aac02b	264	struct spi_transfer *tfr)
1ea29b39 MS	265	{
	266	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	267	unsigned long timeout;
	268	u32 stat;
	269
	270	/* configure spi */
	271	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	272	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
	273
	274	/* set the timeout */
	275	timeout = jiffies + BCM2835_AUX_SPI_POLLING_JIFFIES;
	276
	277	/* loop until finished the transfer */
	278	while (bs->rx_len) {
	279	/* read status */
	280	stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
	281
	282	/* fill in tx fifo with remaining data */
	283	if ((bs->tx_len) && (!(stat & BCM2835_AUX_SPI_STAT_TX_FULL))) {
	284	bcm2835aux_wr_fifo(bs);
	285	continue;
	286	}
	287
	288	/* read data from fifo for both cases */
	289	if (!(stat & BCM2835_AUX_SPI_STAT_RX_EMPTY)) {
	290	bcm2835aux_rd_fifo(bs);
	291	continue;
	292	}
	293	if (!(stat & BCM2835_AUX_SPI_STAT_BUSY)) {
	294	bcm2835aux_rd_fifo(bs);
	295	continue;
	296	}
	297
	298	/* there is still data pending to read check the timeout */
	299	if (bs->rx_len && time_after(jiffies, timeout)) {
	300	dev_dbg_ratelimited(&spi->dev,
	301	"timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
	302	jiffies - timeout,
	303	bs->tx_len, bs->rx_len);
	304	/* forward to interrupt handler */
	305	return __bcm2835aux_spi_transfer_one_irq(master,
	306	spi, tfr);
	307	}
	308	}
	309
	310	/* Transfer complete - reset SPI HW */
	311	bcm2835aux_spi_reset_hw(bs);
	312
	313	/* and return without waiting for completion */
	314	return 0;
	315	}
	316
	317	static int bcm2835aux_spi_transfer_one(struct spi_master *master,
	318	struct spi_device *spi,
	319	struct spi_transfer *tfr)
	320	{
	321	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	322	unsigned long spi_hz, clk_hz, speed;
72aac02b MS	323	unsigned long spi_used_hz;
72aac02b MS	324	unsigned long long xfer_time_us;
1ea29b39 MS	325
	326	/* calculate the registers to handle
	327	*
	328	* note that we use the variable data mode, which
	329	* is not optimal for longer transfers as we waste registers
	330	* resulting (potentially) in more interrupts when transferring
	331	* more than 12 bytes
	332	*/
	333	bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE \|
	334	BCM2835_AUX_SPI_CNTL0_VAR_WIDTH \|
	335	BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
	336	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
	337
	338	/* set clock */
	339	spi_hz = tfr->speed_hz;
	340	clk_hz = clk_get_rate(bs->clk);
	341
	342	if (spi_hz >= clk_hz / 2) {
	343	speed = 0;
	344	} else if (spi_hz) {
	345	speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
	346	if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
	347	speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	348	} else { /* the slowest we can go */
	349	speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
	350	}
	351	bs->cntl[0] \|= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
	352
	353	spi_used_hz = clk_hz / (2 * (speed + 1));
	354
	355	/* handle all the modes */
	356	if (spi->mode & SPI_CPOL)
	357	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_CPOL;
	358	if (spi->mode & SPI_CPHA)
	359	bs->cntl[0] \|= BCM2835_AUX_SPI_CNTL0_CPHA_OUT \|
	360	BCM2835_AUX_SPI_CNTL0_CPHA_IN;
	361
	362	/* set transmit buffers and length */
	363	bs->tx_buf = tfr->tx_buf;
	364	bs->rx_buf = tfr->rx_buf;
	365	bs->tx_len = tfr->len;
	366	bs->rx_len = tfr->len;
72aac02b	367	bs->pending = 0;
1ea29b39	368
72aac02b MS	369	/* calculate the estimated time in us the transfer runs
	370	* note that there are are 2 idle clocks after each
	371	* chunk getting transferred - in our case the chunk size
	372	* is 3 bytes, so we approximate this by 9 bits/byte
	373	*/
	374	xfer_time_us = tfr->len * 9 * 1000000;
	375	do_div(xfer_time_us, spi_used_hz);
1ea29b39 MS	376
	377	/* run in polling mode for short transfers */
	378	if (xfer_time_us < BCM2835_AUX_SPI_POLLING_LIMIT_US)
72aac02b	379	return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
1ea29b39 MS	380
	381	/* run in interrupt mode for all others */
	382	return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
	383	}
	384
	385	static void bcm2835aux_spi_handle_err(struct spi_master *master,
	386	struct spi_message *msg)
	387	{
	388	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	389
	390	bcm2835aux_spi_reset_hw(bs);
	391	}
	392
	393	static int bcm2835aux_spi_probe(struct platform_device *pdev)
	394	{
	395	struct spi_master *master;
	396	struct bcm2835aux_spi *bs;
	397	struct resource *res;
	398	unsigned long clk_hz;
	399	int err;
	400
	401	master = spi_alloc_master(&pdev->dev, sizeof(*bs));
	402	if (!master) {
	403	dev_err(&pdev->dev, "spi_alloc_master() failed\n");
	404	return -ENOMEM;
	405	}
	406
	407	platform_set_drvdata(pdev, master);
	408	master->mode_bits = BCM2835_AUX_SPI_MODE_BITS;
	409	master->bits_per_word_mask = SPI_BPW_MASK(8);
	410	master->num_chipselect = -1;
	411	master->transfer_one = bcm2835aux_spi_transfer_one;
	412	master->handle_err = bcm2835aux_spi_handle_err;
	413	master->dev.of_node = pdev->dev.of_node;
	414
	415	bs = spi_master_get_devdata(master);
	416
	417	/* the main area */
	418	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	419	bs->regs = devm_ioremap_resource(&pdev->dev, res);
	420	if (IS_ERR(bs->regs)) {
	421	err = PTR_ERR(bs->regs);
	422	goto out_master_put;
	423	}
	424
	425	bs->clk = devm_clk_get(&pdev->dev, NULL);
	426	if ((!bs->clk) \|\| (IS_ERR(bs->clk))) {
	427	err = PTR_ERR(bs->clk);
	428	dev_err(&pdev->dev, "could not get clk: %d\n", err);
	429	goto out_master_put;
	430	}
	431
07bce09e	432	bs->irq = platform_get_irq(pdev, 0);
1ea29b39 MS	433	if (bs->irq <= 0) {
	434	dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
	435	err = bs->irq ? bs->irq : -ENODEV;
	436	goto out_master_put;
	437	}
	438
	439	/* this also enables the HW block */
	440	err = clk_prepare_enable(bs->clk);
	441	if (err) {
	442	dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
	443	goto out_master_put;
	444	}
	445
	446	/* just checking if the clock returns a sane value */
	447	clk_hz = clk_get_rate(bs->clk);
	448	if (!clk_hz) {
	449	dev_err(&pdev->dev, "clock returns 0 Hz\n");
	450	err = -ENODEV;
	451	goto out_clk_disable;
	452	}
	453
07bce09e MS	454	/* reset SPI-HW block */
	455	bcm2835aux_spi_reset_hw(bs);
	456
1ea29b39 MS	457	err = devm_request_irq(&pdev->dev, bs->irq,
	458	bcm2835aux_spi_interrupt,
	459	IRQF_SHARED,
	460	dev_name(&pdev->dev), master);
	461	if (err) {
	462	dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
	463	goto out_clk_disable;
	464	}
	465
1ea29b39 MS	466	err = devm_spi_register_master(&pdev->dev, master);
	467	if (err) {
	468	dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
	469	goto out_clk_disable;
	470	}
	471
	472	return 0;
	473
	474	out_clk_disable:
	475	clk_disable_unprepare(bs->clk);
	476	out_master_put:
	477	spi_master_put(master);
	478	return err;
	479	}
	480
	481	static int bcm2835aux_spi_remove(struct platform_device *pdev)
	482	{
	483	struct spi_master *master = platform_get_drvdata(pdev);
	484	struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
	485
	486	bcm2835aux_spi_reset_hw(bs);
	487
	488	/* disable the HW block by releasing the clock */
	489	clk_disable_unprepare(bs->clk);
	490
	491	return 0;
	492	}
	493
	494	static const struct of_device_id bcm2835aux_spi_match[] = {
	495	{ .compatible = "brcm,bcm2835-aux-spi", },
	496	{}
	497	};
	498	MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
	499
	500	static struct platform_driver bcm2835aux_spi_driver = {
	501	.driver = {
	502	.name = "spi-bcm2835aux",
	503	.of_match_table = bcm2835aux_spi_match,
	504	},
	505	.probe = bcm2835aux_spi_probe,
	506	.remove = bcm2835aux_spi_remove,
	507	};
	508	module_platform_driver(bcm2835aux_spi_driver);
	509
	510	MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
	511	MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
	512	MODULE_LICENSE("GPL v2");